1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2005 Openedhand Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Richard Purdie <richard@openedhand.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ES8323_H 9*4882a593Smuzhiyun #define _ES8323_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define CONFIG_HHTECH_MINIPMP 1 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* ES8323 register space */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define ES8323_CONTROL1 0x00 16*4882a593Smuzhiyun #define ES8323_CONTROL2 0x01 17*4882a593Smuzhiyun #define ES8323_CHIPPOWER 0x02 18*4882a593Smuzhiyun #define ES8323_ADCPOWER 0x03 19*4882a593Smuzhiyun #define ES8323_DACPOWER 0x04 20*4882a593Smuzhiyun #define ES8323_CHIPLOPOW1 0x05 21*4882a593Smuzhiyun #define ES8323_CHIPLOPOW2 0x06 22*4882a593Smuzhiyun #define ES8323_ANAVOLMANAG 0x07 23*4882a593Smuzhiyun #define ES8323_MASTERMODE 0x08 24*4882a593Smuzhiyun #define ES8323_ADCCONTROL1 0x09 25*4882a593Smuzhiyun #define ES8323_ADCCONTROL2 0x0a 26*4882a593Smuzhiyun #define ES8323_ADCCONTROL3 0x0b 27*4882a593Smuzhiyun #define ES8323_ADCCONTROL4 0x0c 28*4882a593Smuzhiyun #define ES8323_ADCCONTROL5 0x0d 29*4882a593Smuzhiyun #define ES8323_ADCCONTROL6 0x0e 30*4882a593Smuzhiyun #define ES8323_ADCCONTROL7 0x0f 31*4882a593Smuzhiyun #define ES8323_ADCCONTROL8 0x10 32*4882a593Smuzhiyun #define ES8323_ADCCONTROL9 0x11 33*4882a593Smuzhiyun #define ES8323_ADCCONTROL10 0x12 34*4882a593Smuzhiyun #define ES8323_ADCCONTROL11 0x13 35*4882a593Smuzhiyun #define ES8323_ADCCONTROL12 0x14 36*4882a593Smuzhiyun #define ES8323_ADCCONTROL13 0x15 37*4882a593Smuzhiyun #define ES8323_ADCCONTROL14 0x16 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define ES8323_DACCONTROL1 0x17 40*4882a593Smuzhiyun #define ES8323_DACCONTROL2 0x18 41*4882a593Smuzhiyun #define ES8323_DACCONTROL3 0x19 42*4882a593Smuzhiyun #define ES8323_DACCONTROL4 0x1a 43*4882a593Smuzhiyun #define ES8323_DACCONTROL5 0x1b 44*4882a593Smuzhiyun #define ES8323_DACCONTROL6 0x1c 45*4882a593Smuzhiyun #define ES8323_DACCONTROL7 0x1d 46*4882a593Smuzhiyun #define ES8323_DACCONTROL8 0x1e 47*4882a593Smuzhiyun #define ES8323_DACCONTROL9 0x1f 48*4882a593Smuzhiyun #define ES8323_DACCONTROL10 0x20 49*4882a593Smuzhiyun #define ES8323_DACCONTROL11 0x21 50*4882a593Smuzhiyun #define ES8323_DACCONTROL12 0x22 51*4882a593Smuzhiyun #define ES8323_DACCONTROL13 0x23 52*4882a593Smuzhiyun #define ES8323_DACCONTROL14 0x24 53*4882a593Smuzhiyun #define ES8323_DACCONTROL15 0x25 54*4882a593Smuzhiyun #define ES8323_DACCONTROL16 0x26 55*4882a593Smuzhiyun #define ES8323_DACCONTROL17 0x27 56*4882a593Smuzhiyun #define ES8323_DACCONTROL18 0x28 57*4882a593Smuzhiyun #define ES8323_DACCONTROL19 0x29 58*4882a593Smuzhiyun #define ES8323_DACCONTROL20 0x2a 59*4882a593Smuzhiyun #define ES8323_DACCONTROL21 0x2b 60*4882a593Smuzhiyun #define ES8323_DACCONTROL22 0x2c 61*4882a593Smuzhiyun #define ES8323_DACCONTROL23 0x2d 62*4882a593Smuzhiyun #define ES8323_DACCONTROL24 0x2e 63*4882a593Smuzhiyun #define ES8323_DACCONTROL25 0x2f 64*4882a593Smuzhiyun #define ES8323_DACCONTROL26 0x30 65*4882a593Smuzhiyun #define ES8323_DACCONTROL27 0x31 66*4882a593Smuzhiyun #define ES8323_DACCONTROL28 0x32 67*4882a593Smuzhiyun #define ES8323_DACCONTROL29 0x33 68*4882a593Smuzhiyun #define ES8323_DACCONTROL30 0x34 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #define ES8323_LADC_VOL ES8323_ADCCONTROL8 71*4882a593Smuzhiyun #define ES8323_RADC_VOL ES8323_ADCCONTROL9 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define ES8323_LDAC_VOL ES8323_DACCONTROL4 74*4882a593Smuzhiyun #define ES8323_RDAC_VOL ES8323_DACCONTROL5 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define ES8323_LOUT1_VOL ES8323_DACCONTROL24 77*4882a593Smuzhiyun #define ES8323_ROUT1_VOL ES8323_DACCONTROL25 78*4882a593Smuzhiyun #define ES8323_LOUT2_VOL ES8323_DACCONTROL26 79*4882a593Smuzhiyun #define ES8323_ROUT2_VOL ES8323_DACCONTROL27 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define ES8323_ADC_MUTE ES8323_ADCCONTROL7 82*4882a593Smuzhiyun #define ES8323_DAC_MUTE ES8323_DACCONTROL3 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define ES8323_IFACE ES8323_MASTERMODE 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define ES8323_ADC_IFACE ES8323_ADCCONTROL4 89*4882a593Smuzhiyun #define ES8323_ADC_SRATE ES8323_ADCCONTROL5 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define ES8323_DAC_IFACE ES8323_DACCONTROL1 92*4882a593Smuzhiyun #define ES8323_DAC_SRATE ES8323_DACCONTROL2 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define ES8323_CACHEREGNUM 53 97*4882a593Smuzhiyun #define ES8323_SYSCLK 0 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun struct es8323_setup_data { 100*4882a593Smuzhiyun int i2c_bus; 101*4882a593Smuzhiyun unsigned short i2c_address; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #if 1 //lzcx 105*4882a593Smuzhiyun #define ES8323_PLL1 0 106*4882a593Smuzhiyun #define ES8323_PLL2 1 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* clock inputs */ 109*4882a593Smuzhiyun #define ES8323_MCLK 0 110*4882a593Smuzhiyun #define ES8323_PCMCLK 1 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun /* clock divider id's */ 113*4882a593Smuzhiyun #define ES8323_PCMDIV 0 114*4882a593Smuzhiyun #define ES8323_BCLKDIV 1 115*4882a593Smuzhiyun #define ES8323_VXCLKDIV 2 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun /* PCM clock dividers */ 118*4882a593Smuzhiyun #define ES8323_PCM_DIV_1 (0 << 6) 119*4882a593Smuzhiyun #define ES8323_PCM_DIV_3 (2 << 6) 120*4882a593Smuzhiyun #define ES8323_PCM_DIV_5_5 (3 << 6) 121*4882a593Smuzhiyun #define ES8323_PCM_DIV_2 (4 << 6) 122*4882a593Smuzhiyun #define ES8323_PCM_DIV_4 (5 << 6) 123*4882a593Smuzhiyun #define ES8323_PCM_DIV_6 (6 << 6) 124*4882a593Smuzhiyun #define ES8323_PCM_DIV_8 (7 << 6) 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* BCLK clock dividers */ 127*4882a593Smuzhiyun #define ES8323_BCLK_DIV_1 (0 << 7) 128*4882a593Smuzhiyun #define ES8323_BCLK_DIV_2 (1 << 7) 129*4882a593Smuzhiyun #define ES8323_BCLK_DIV_4 (2 << 7) 130*4882a593Smuzhiyun #define ES8323_BCLK_DIV_8 (3 << 7) 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* VXCLK clock dividers */ 133*4882a593Smuzhiyun #define ES8323_VXCLK_DIV_1 (0 << 6) 134*4882a593Smuzhiyun #define ES8323_VXCLK_DIV_2 (1 << 6) 135*4882a593Smuzhiyun #define ES8323_VXCLK_DIV_4 (2 << 6) 136*4882a593Smuzhiyun #define ES8323_VXCLK_DIV_8 (3 << 6) 137*4882a593Smuzhiyun #define ES8323_VXCLK_DIV_16 (4 << 6) 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun #define ES8323_DAI_HIFI 0 140*4882a593Smuzhiyun #define ES8323_DAI_VOICE 1 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define ES8323_1536FS 1536 143*4882a593Smuzhiyun #define ES8323_1024FS 1024 144*4882a593Smuzhiyun #define ES8323_768FS 768 145*4882a593Smuzhiyun #define ES8323_512FS 512 146*4882a593Smuzhiyun #define ES8323_384FS 384 147*4882a593Smuzhiyun #define ES8323_256FS 256 148*4882a593Smuzhiyun #define ES8323_128FS 128 149*4882a593Smuzhiyun #endif 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #endif 152