1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // es8323.c -- es8323 ALSA SoC audio driver
4 //
5 // Copyright (c) 2016 Rockchip Electronics Co. Ltd.
6 //
7 // Author: Mark Brown <will@everset-semi.com>
8 // Author: Jianqun Xu <jay.xu@rock-chips.com>
9 // Author: Nickey Yang <nickey.yang@rock-chips.com>
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/pm.h>
17 #include <linux/i2c.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/pcm.h>
22 #include <sound/pcm_params.h>
23 #include <sound/tlv.h>
24 #include <sound/soc.h>
25 #include <sound/soc-dapm.h>
26 #include <sound/initval.h>
27 #include <linux/proc_fs.h>
28 #include "es8323.h"
29
30 #define NR_SUPPORTED_MCLK_LRCK_RATIOS 5
31 static const unsigned int supported_mclk_lrck_ratios[NR_SUPPORTED_MCLK_LRCK_RATIOS] = {
32 256, 384, 512, 768, 1024
33 };
34
35 #define es8323_DEF_VOL 0x1b
36
37 static int es8323_set_bias_level(struct snd_soc_component *component,
38 enum snd_soc_bias_level level);
39
40 static struct reg_default es8323_reg_defaults[] = {
41 { 0x00, 0x06 },
42 { 0x01, 0x1c },
43 { 0x02, 0xc3 },
44 { 0x03, 0xfc },
45 { 0x04, 0xc0 },
46 { 0x05, 0x00 },
47 { 0x06, 0x00 },
48 { 0x07, 0x7c },
49 { 0x08, 0x80 },
50 { 0x09, 0x00 },
51 { 0x0a, 0x00 },
52 { 0x0b, 0x06 },
53 { 0x0c, 0x00 },
54 { 0x0d, 0x06 },
55 { 0x0e, 0x30 },
56 { 0x0f, 0x30 },
57 { 0x10, 0xc0 },
58 { 0x11, 0xc0 },
59 { 0x12, 0x38 },
60 { 0x13, 0xb0 },
61 { 0x14, 0x32 },
62 { 0x15, 0x06 },
63 { 0x16, 0x00 },
64 { 0x17, 0x00 },
65 { 0x18, 0x06 },
66 { 0x19, 0x30 },
67 { 0x1a, 0xc0 },
68 { 0x1b, 0xc0 },
69 { 0x1c, 0x08 },
70 { 0x1d, 0x06 },
71 { 0x1e, 0x1f },
72 { 0x1f, 0xf7 },
73 { 0x20, 0xfd },
74 { 0x21, 0xff },
75 { 0x22, 0x1f },
76 { 0x23, 0xf7 },
77 { 0x24, 0xfd },
78 { 0x25, 0xff },
79 { 0x26, 0x00 },
80 { 0x27, 0x38 },
81 { 0x28, 0x38 },
82 { 0x29, 0x38 },
83 { 0x2a, 0x38 },
84 { 0x2b, 0x38 },
85 { 0x2c, 0x38 },
86 };
87
88 /* codec private data */
89 struct es8323_priv {
90 unsigned int sysclk;
91 unsigned int allowed_rates[NR_SUPPORTED_MCLK_LRCK_RATIOS];
92 struct clk *mclk;
93 struct snd_pcm_hw_constraint_list sysclk_constraints;
94 struct snd_soc_component *component;
95 struct regmap *regmap;
96 };
97
es8323_reset(struct snd_soc_component * component)98 static int es8323_reset(struct snd_soc_component *component)
99 {
100 snd_soc_component_write(component, ES8323_CONTROL1, 0x80);
101 return snd_soc_component_write(component, ES8323_CONTROL1, 0x00);
102 }
103
104 static const char * const es8323_line_texts[] = {
105 "Line 1", "Line 2", "PGA"
106 };
107
108 static const unsigned int es8323_line_values[] = {
109 0, 1, 3
110 };
111
112 static const char * const es8323_pga_sell[] = {"Line 1L", "Line 2L", "DifferentialL"};
113 static const char * const es8323_pga_selr[] = {"Line 1R", "Line 2R", "DifferentialR"};
114 static const char * const es8323_lin_sell[] = {"Line 1L", "Line 2L", "NC", "MicL"};
115 static const char * const es8323_lin_selr[] = {"Line 1R", "Line 2R", "NC", "MicR"};
116
117 static const char * const stereo_3d_txt[] = {
118 "No 3D ", "Level 1", "Level 2",
119 "Level 3", "Level 4", "Level 5",
120 "Level 6", "Level 7"
121 };
122
123 static const char * const alc_func_txt[] = {
124 "Off", "Right", "Left", "Stereo"
125 };
126
127 static const char * const ng_type_txt[] = {
128 "Constant PGA Gain", "Mute ADC Output"
129 };
130
131 static const char * const deemph_txt[] = {
132 "None", "32Khz", "44.1Khz", "48Khz"
133 };
134
135 static const char * const adcpol_txt[] = {
136 "Normal", "L Invert", "R Invert", "L + R Invert"
137 };
138
139 static const char * const es8323_mono_mux[] = {
140 "Stereo", "Mono (Left)", "Mono (Right)"
141 };
142
143 static const char * const es8323_diff_sel[] = {
144 "Line 1", "Line 2"
145 };
146
147 SOC_VALUE_ENUM_SINGLE_DECL(es8323_left_dac_enum, ES8323_ADCCONTROL2, 6, 3, es8323_pga_sell, es8323_line_values);
148 SOC_VALUE_ENUM_SINGLE_DECL(es8323_right_dac_enum, ES8323_ADCCONTROL2, 4, 3, es8323_pga_selr, es8323_line_values);
149 static SOC_ENUM_SINGLE_DECL(es8323_diff_enum, ES8323_ADCCONTROL3, 7, es8323_diff_sel);
150 static SOC_ENUM_SINGLE_DECL(es8323_llin_enum, ES8323_DACCONTROL16, 3, es8323_lin_sell);
151 static SOC_ENUM_SINGLE_DECL(es8323_rlin_enum, ES8323_DACCONTROL16, 0, es8323_lin_selr);
152 static SOC_ENUM_SINGLE_DECL(es8323_mono_enum, ES8323_ADCCONTROL3, 3, es8323_mono_mux);
153
154 static const struct soc_enum es8323_enum[] = {
155 SOC_VALUE_ENUM_SINGLE(ES8323_DACCONTROL16, 3, 7, ARRAY_SIZE(es8323_line_texts), es8323_line_texts, es8323_line_values), /* LLINE */
156 SOC_VALUE_ENUM_SINGLE(ES8323_DACCONTROL16, 0, 7, ARRAY_SIZE(es8323_line_texts), es8323_line_texts, es8323_line_values), /* RLINE */
157 SOC_VALUE_ENUM_SINGLE(ES8323_ADCCONTROL2, 6, 3, ARRAY_SIZE(es8323_pga_sell), es8323_line_texts, es8323_line_values), /* Left PGA Mux */
158 SOC_VALUE_ENUM_SINGLE(ES8323_ADCCONTROL2, 4, 3, ARRAY_SIZE(es8323_pga_sell), es8323_line_texts, es8323_line_values), /* Right PGA Mux */
159 SOC_ENUM_SINGLE(ES8323_DACCONTROL7, 2, 8, stereo_3d_txt), /* stereo-3d */
160 SOC_ENUM_SINGLE(ES8323_ADCCONTROL10, 6, 4, alc_func_txt), /* alc func */
161 SOC_ENUM_SINGLE(ES8323_ADCCONTROL14, 1, 2, ng_type_txt), /* noise gate type */
162 SOC_ENUM_SINGLE(ES8323_DACCONTROL6, 6, 4, deemph_txt), /* Playback De-emphasis */
163 SOC_ENUM_SINGLE(ES8323_ADCCONTROL6, 6, 4, adcpol_txt),
164 SOC_ENUM_SINGLE(ES8323_ADCCONTROL3, 3, 3, es8323_mono_mux),
165 SOC_ENUM_SINGLE(ES8323_ADCCONTROL3, 7, 2, es8323_diff_sel),
166 };
167
168 static const DECLARE_TLV_DB_SCALE(adc_tlv, -9600, 50, 1);
169 static const DECLARE_TLV_DB_SCALE(dac_tlv, -9600, 50, 1);
170 static const DECLARE_TLV_DB_SCALE(out_tlv, -4500, 150, 0);
171 static const DECLARE_TLV_DB_SCALE(bypass_tlv, 0, 300, 0);
172 static const DECLARE_TLV_DB_SCALE(bypass_tlv2, -15, 300, 0);
173
174 static const struct snd_kcontrol_new es8323_left_dac_mux_controls = SOC_DAPM_ENUM("Route", es8323_left_dac_enum);
175 static const struct snd_kcontrol_new es8323_right_dac_mux_controls = SOC_DAPM_ENUM("Route", es8323_right_dac_enum);
176 static const struct snd_kcontrol_new es8323_diffmux_controls = SOC_DAPM_ENUM("Route2", es8323_diff_enum);
177
178 static const struct snd_kcontrol_new es8323_snd_controls[] = {
179 SOC_ENUM("3D Mode", es8323_enum[4]),
180 SOC_SINGLE("ALC Capture Target Volume", ES8323_ADCCONTROL11, 4, 15, 0),
181 SOC_SINGLE("ALC Capture Max PGA", ES8323_ADCCONTROL10, 3, 7, 0),
182 SOC_SINGLE("ALC Capture Min PGA", ES8323_ADCCONTROL10, 0, 7, 0),
183 SOC_ENUM("ALC Capture Function", es8323_enum[5]),
184 SOC_SINGLE("ALC Capture ZC Switch", ES8323_ADCCONTROL13, 6, 1, 0),
185 SOC_SINGLE("ALC Capture Hold Time", ES8323_ADCCONTROL11, 0, 15, 0),
186 SOC_SINGLE("ALC Capture Decay Time", ES8323_ADCCONTROL12, 4, 15, 0),
187 SOC_SINGLE("ALC Capture Attack Time", ES8323_ADCCONTROL12, 0, 15, 0),
188 SOC_SINGLE("ALC Capture NG Threshold", ES8323_ADCCONTROL14, 3, 31, 0),
189 SOC_ENUM("ALC Capture NG Type", es8323_enum[6]),
190 SOC_SINGLE("ALC Capture NG Switch", ES8323_ADCCONTROL14, 0, 1, 0),
191 SOC_SINGLE("ZC Timeout Switch", ES8323_ADCCONTROL13, 6, 1, 0),
192 SOC_DOUBLE_R_TLV("Capture Digital Volume", ES8323_ADCCONTROL8,
193 ES8323_ADCCONTROL9, 0, 192, 1, adc_tlv),
194 SOC_SINGLE("Capture Mute", ES8323_ADCCONTROL7, 2, 1, 0),
195 SOC_SINGLE_TLV("Left Channel Capture Volume", ES8323_ADCCONTROL1, 4, 8,
196 0, bypass_tlv),
197 SOC_SINGLE_TLV("Right Channel Capture Volume", ES8323_ADCCONTROL1, 0,
198 8, 0, bypass_tlv),
199 SOC_ENUM("Playback De-emphasis", es8323_enum[7]),
200 SOC_ENUM("Capture Polarity", es8323_enum[8]),
201 SOC_DOUBLE_R_TLV("PCM Volume", ES8323_DACCONTROL4, ES8323_DACCONTROL5,
202 0, 192, 1, dac_tlv),
203 SOC_SINGLE_TLV("Left Mixer Left Bypass Volume", ES8323_DACCONTROL17, 3,
204 7, 1, bypass_tlv2),
205 SOC_SINGLE_TLV("Right Mixer Right Bypass Volume", ES8323_DACCONTROL20,
206 3, 7, 1, bypass_tlv2),
207 SOC_DOUBLE_R_TLV("Output 1 Playback Volume", ES8323_DACCONTROL24,
208 ES8323_DACCONTROL25, 0, 33, 0, out_tlv),
209 SOC_DOUBLE_R_TLV("Output 2 Playback Volume", ES8323_DACCONTROL26,
210 ES8323_DACCONTROL27, 0, 33, 0, out_tlv),
211 };
212
213 static const struct snd_kcontrol_new es8323_left_line_controls =
214 SOC_DAPM_ENUM("LLIN Mux", es8323_llin_enum);
215
216 static const struct snd_kcontrol_new es8323_right_line_controls =
217 SOC_DAPM_ENUM("RLIN Mux", es8323_rlin_enum);
218 /* Mono ADC Mux */
219 static const struct snd_kcontrol_new es8323_monomux_controls =
220 SOC_DAPM_ENUM("Mono Mux", es8323_mono_enum);
221
222 /* Left Mixer */
223 static const struct snd_kcontrol_new es8323_left_mixer_controls[] = {
224 SOC_DAPM_SINGLE("Left Playback Switch", ES8323_DACCONTROL17, 7, 1, 0),
225 SOC_DAPM_SINGLE("Left Bypass Switch", ES8323_DACCONTROL17, 6, 1, 0),
226 };
227
228 /* Right Mixer */
229 static const struct snd_kcontrol_new es8323_right_mixer_controls[] = {
230 SOC_DAPM_SINGLE("Right Playback Switch", ES8323_DACCONTROL20, 7, 1, 0),
231 SOC_DAPM_SINGLE("Right Bypass Switch", ES8323_DACCONTROL20, 6, 1, 0),
232 };
233
234 static const struct snd_soc_dapm_widget es8323_dapm_widgets[] = {
235 SND_SOC_DAPM_INPUT("LINPUT1"),
236 SND_SOC_DAPM_INPUT("LINPUT2"),
237 SND_SOC_DAPM_INPUT("RINPUT1"),
238 SND_SOC_DAPM_INPUT("RINPUT2"),
239 SND_SOC_DAPM_MUX("Left PGA Mux", SND_SOC_NOPM, 0, 0,
240 &es8323_left_dac_mux_controls),
241 SND_SOC_DAPM_MUX("Right PGA Mux", SND_SOC_NOPM, 0, 0,
242 &es8323_right_dac_mux_controls),
243 SND_SOC_DAPM_MICBIAS("Mic Bias", ES8323_ADCPOWER, 3, 1),
244
245 SND_SOC_DAPM_MUX("Differential Mux", SND_SOC_NOPM, 0, 0,
246 &es8323_diffmux_controls),
247
248 SND_SOC_DAPM_MUX("Left ADC Mux", SND_SOC_NOPM, 0, 0,
249 &es8323_monomux_controls),
250 SND_SOC_DAPM_MUX("Right ADC Mux", SND_SOC_NOPM, 0, 0,
251 &es8323_monomux_controls),
252
253 SND_SOC_DAPM_MUX("Left Line Mux", SND_SOC_NOPM, 0, 0,
254 &es8323_left_line_controls),
255 SND_SOC_DAPM_MUX("Right Line Mux", SND_SOC_NOPM, 0, 0,
256 &es8323_right_line_controls),
257
258 SND_SOC_DAPM_ADC("Right ADC", "Right Capture", ES8323_ADCPOWER, 4, 1),
259 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", ES8323_ADCPOWER, 5, 1),
260
261 /* gModify.Cmmt Implement when suspend/startup */
262 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", ES8323_DACPOWER, 6, 1),
263 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", ES8323_DACPOWER, 7, 1),
264
265 SND_SOC_DAPM_AIF_OUT("I2S OUT", "Capture", 0, SND_SOC_NOPM, 0, 0),
266 SND_SOC_DAPM_AIF_IN("I2S IN", "Playback", 0, SND_SOC_NOPM, 0, 0),
267
268 SND_SOC_DAPM_MIXER("Left Mixer", SND_SOC_NOPM, 0, 0,
269 &es8323_left_mixer_controls[0],
270 ARRAY_SIZE(es8323_left_mixer_controls)),
271 SND_SOC_DAPM_MIXER("Right Mixer", SND_SOC_NOPM, 0, 0,
272 &es8323_right_mixer_controls[0],
273 ARRAY_SIZE(es8323_right_mixer_controls)),
274 SND_SOC_DAPM_PGA("Right ADC Power", ES8323_ADCPOWER, 6, 1, NULL, 0),
275 SND_SOC_DAPM_PGA("Left ADC Power", ES8323_ADCPOWER, 7, 1, NULL, 0),
276 SND_SOC_DAPM_PGA("Right Out 2", ES8323_DACPOWER, 2, 0, NULL, 0),
277 SND_SOC_DAPM_PGA("Left Out 2", ES8323_DACPOWER, 3, 0, NULL, 0),
278 SND_SOC_DAPM_PGA("Right Out 1", ES8323_DACPOWER, 4, 0, NULL, 0),
279 SND_SOC_DAPM_PGA("Left Out 1", ES8323_DACPOWER, 5, 0, NULL, 0),
280 SND_SOC_DAPM_PGA("LAMP", ES8323_ADCCONTROL1, 4, 0, NULL, 0),
281 SND_SOC_DAPM_PGA("RAMP", ES8323_ADCCONTROL1, 0, 0, NULL, 0),
282
283 SND_SOC_DAPM_OUTPUT("LOUT1"),
284 SND_SOC_DAPM_OUTPUT("ROUT1"),
285 SND_SOC_DAPM_OUTPUT("LOUT2"),
286 SND_SOC_DAPM_OUTPUT("ROUT2"),
287 SND_SOC_DAPM_OUTPUT("VREF"),
288 };
289
290 static const struct snd_soc_dapm_route audio_map[] = {
291 {"Left PGA Mux", "Line 1L", "LINPUT1"},
292 {"Left PGA Mux", "Line 2L", "LINPUT2"},
293 {"Left PGA Mux", "DifferentialL", "Differential Mux"},
294
295 {"Right PGA Mux", "Line 1R", "RINPUT1"},
296 {"Right PGA Mux", "Line 2R", "RINPUT2"},
297 {"Right PGA Mux", "DifferentialR", "Differential Mux"},
298
299 {"Differential Mux", "Line 1", "LINPUT1"},
300 {"Differential Mux", "Line 1", "RINPUT1"},
301 {"Differential Mux", "Line 2", "LINPUT2"},
302 {"Differential Mux", "Line 2", "RINPUT2"},
303
304 {"Left ADC Mux", "Stereo", "Right PGA Mux"},
305 {"Left ADC Mux", "Stereo", "Left PGA Mux"},
306 {"Left ADC Mux", "Mono (Left)", "Left PGA Mux"},
307
308 {"Right ADC Mux", "Stereo", "Left PGA Mux"},
309 {"Right ADC Mux", "Stereo", "Right PGA Mux"},
310 {"Right ADC Mux", "Mono (Right)", "Right PGA Mux"},
311
312 {"Left ADC Power", NULL, "Left ADC Mux"},
313 {"Right ADC Power", NULL, "Right ADC Mux"},
314 {"Left ADC", NULL, "Left ADC Power"},
315 {"Right ADC", NULL, "Right ADC Power"},
316
317 {"I2S OUT", NULL, "Left ADC"},
318 {"I2S OUT", NULL, "Right ADC"},
319
320 {"Left Line Mux", "Line 1L", "LINPUT1"},
321 {"Left Line Mux", "Line 2L", "LINPUT2"},
322 {"Left Line Mux", "MicL", "Left PGA Mux"},
323
324 {"Right Line Mux", "Line 1R", "RINPUT1"},
325 {"Right Line Mux", "Line 2R", "RINPUT2"},
326 {"Right Line Mux", "MicR", "Right PGA Mux"},
327
328 {"Right DAC", NULL, "I2S IN"},
329 {"Left DAC", NULL, "I2S IN"},
330
331 {"Left Mixer", "Left Playback Switch", "Left DAC"},
332 {"Left Mixer", "Left Bypass Switch", "Left Line Mux"},
333
334 {"Right Mixer", "Right Playback Switch", "Right DAC"},
335 {"Right Mixer", "Right Bypass Switch", "Right Line Mux"},
336
337 {"Left Out 1", NULL, "Left Mixer"},
338 {"LOUT1", NULL, "Left Out 1"},
339 {"Right Out 1", NULL, "Right Mixer"},
340 {"ROUT1", NULL, "Right Out 1"},
341
342 {"Left Out 2", NULL, "Left Mixer"},
343 {"LOUT2", NULL, "Left Out 2"},
344 {"Right Out 2", NULL, "Right Mixer"},
345 {"ROUT2", NULL, "Right Out 2"},
346 };
347
348 struct _coeff_div {
349 u32 mclk;
350 u32 rate;
351 u16 fs;
352 u8 sr:4;
353 u8 usb:1;
354 };
355
356 /* codec hifi mclk clock divider coefficients */
357 static const struct _coeff_div coeff_div[] = {
358 /* 8k */
359 {2048000, 8000, 256, 0x2, 0x0},
360 {4096000, 8000, 512, 0x4, 0x0},
361 {12288000, 8000, 1536, 0xa, 0x0},
362 {11289600, 8000, 1408, 0x9, 0x0},
363 {18432000, 8000, 2304, 0xc, 0x0},
364 {16934400, 8000, 2112, 0xb, 0x0},
365 {12000000, 8000, 1500, 0xb, 0x1},
366
367 /* 11.025k */
368 {11289600, 11025, 1024, 0x7, 0x0},
369 {16934400, 11025, 1536, 0xa, 0x0},
370 {12000000, 11025, 1088, 0x9, 0x1},
371
372 /* 16k */
373 {4096000, 16000, 256, 0x2, 0x0},
374 {8192000, 16000, 512, 0x4, 0x0},
375 {12288000, 16000, 768, 0x6, 0x0},
376 {18432000, 16000, 1152, 0x8, 0x0},
377 {12000000, 16000, 750, 0x7, 0x1},
378
379 /* 22.05k */
380 {11289600, 22050, 512, 0x4, 0x0},
381 {16934400, 22050, 768, 0x6, 0x0},
382 {12000000, 22050, 544, 0x6, 0x1},
383
384 /* 32k */
385 {8192000, 32000, 256, 0x2, 0x0},
386 {16384000, 32000, 512, 0x4, 0x0},
387 {12288000, 32000, 384, 0x3, 0x0},
388 {18432000, 32000, 576, 0x5, 0x0},
389 {12000000, 32000, 375, 0x4, 0x1},
390
391 /* 44.1k */
392 {11289600, 44100, 256, 0x2, 0x0},
393 {16934400, 44100, 384, 0x3, 0x0},
394 {12000000, 44100, 272, 0x3, 0x1},
395
396 /* 48k */
397 {12288000, 48000, 256, 0x2, 0x0},
398 {18432000, 48000, 384, 0x3, 0x0},
399 {12000000, 48000, 250, 0x2, 0x1},
400
401 /* 88.2k */
402 {11289600, 88200, 128, 0x0, 0x0},
403 {16934400, 88200, 192, 0x1, 0x0},
404 {12000000, 88200, 136, 0x1, 0x1},
405
406 /* 96k */
407 {12288000, 96000, 128, 0x0, 0x0},
408 {18432000, 96000, 192, 0x1, 0x0},
409 {12000000, 96000, 125, 0x0, 0x1},
410 };
411
get_coeff(int mclk,int rate)412 static inline int get_coeff(int mclk, int rate)
413 {
414 int i;
415
416 for (i = 0; i < ARRAY_SIZE(coeff_div); i++) {
417 if (coeff_div[i].rate == rate && coeff_div[i].mclk == mclk)
418 return i;
419 }
420
421 return -EINVAL;
422 }
423
424 /*
425 * Note that this should be called from init rather than from hw_params.
426 */
es8323_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)427 static int es8323_set_dai_sysclk(struct snd_soc_dai *codec_dai,
428 int clk_id, unsigned int freq, int dir)
429 {
430 struct snd_soc_component *component = codec_dai->component;
431 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
432 int i, ret;
433 int count = 0;
434
435 es8323->sysclk = freq;
436 if (freq == 0) {
437 es8323->sysclk_constraints.list = NULL;
438 es8323->sysclk_constraints.count = 0;
439
440 return 0;
441 }
442
443 ret = clk_set_rate(es8323->mclk, freq);
444 if (ret)
445 return ret;
446
447 /* Limit supported sample rates to ones that can be autodetected
448 * by the codec running in slave mode.
449 */
450 for (i = 0; i < NR_SUPPORTED_MCLK_LRCK_RATIOS; i++) {
451 const unsigned int ratio = supported_mclk_lrck_ratios[i];
452
453 if (freq % ratio == 0)
454 es8323->allowed_rates[count++] = freq / ratio;
455 }
456
457 es8323->sysclk_constraints.list = es8323->allowed_rates;
458 es8323->sysclk_constraints.count = count;
459
460 return 0;
461 }
462
es8323_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)463 static int es8323_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
464 {
465 struct snd_soc_component *component = codec_dai->component;
466 u8 iface = 0;
467 u8 adciface = 0;
468 u8 daciface = 0;
469
470 iface = snd_soc_component_read(component, ES8323_IFACE);
471 adciface = snd_soc_component_read(component, ES8323_ADC_IFACE);
472 daciface = snd_soc_component_read(component, ES8323_DAC_IFACE);
473
474 /* set master/slave audio interface */
475 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
476 case SND_SOC_DAIFMT_CBM_CFM: /* MASTER MODE */
477 iface |= 0x80;
478 break;
479 case SND_SOC_DAIFMT_CBS_CFS: /* SLAVE MODE */
480 iface &= 0x7F;
481 break;
482 default:
483 return -EINVAL;
484 }
485
486 /* interface format */
487 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
488 case SND_SOC_DAIFMT_I2S:
489 adciface &= 0xFC;
490 daciface &= 0xF9;
491 break;
492 case SND_SOC_DAIFMT_RIGHT_J:
493 break;
494 case SND_SOC_DAIFMT_LEFT_J:
495 break;
496 case SND_SOC_DAIFMT_DSP_A:
497 break;
498 case SND_SOC_DAIFMT_DSP_B:
499 break;
500 default:
501 return -EINVAL;
502 }
503
504 /* clock inversion */
505 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
506 case SND_SOC_DAIFMT_NB_NF:
507 iface &= 0xDF;
508 adciface &= 0xDF;
509 daciface &= 0xBF;
510 break;
511 case SND_SOC_DAIFMT_IB_IF:
512 iface |= 0x20;
513 adciface |= 0x20;
514 daciface |= 0x40;
515 break;
516 case SND_SOC_DAIFMT_IB_NF:
517 iface |= 0x20;
518 adciface &= 0xDF;
519 daciface &= 0xBF;
520 break;
521 case SND_SOC_DAIFMT_NB_IF:
522 iface &= 0xDF;
523 adciface |= 0x20;
524 daciface |= 0x40;
525 break;
526 default:
527 return -EINVAL;
528 }
529
530 snd_soc_component_write(component, ES8323_IFACE, iface);
531 snd_soc_component_write(component, ES8323_ADC_IFACE, adciface);
532 snd_soc_component_write(component, ES8323_DAC_IFACE, daciface);
533
534 return 0;
535 }
536
es8323_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)537 static int es8323_pcm_startup(struct snd_pcm_substream *substream,
538 struct snd_soc_dai *dai)
539 {
540 return 0;
541 }
542
es8323_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)543 static int es8323_pcm_hw_params(struct snd_pcm_substream *substream,
544 struct snd_pcm_hw_params *params,
545 struct snd_soc_dai *dai)
546 {
547 struct snd_soc_component *component = dai->component;
548 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
549 u16 srate = snd_soc_component_read(component, ES8323_IFACE) & 0x80;
550 u16 adciface = snd_soc_component_read(component, ES8323_ADC_IFACE) & 0xE3;
551 u16 daciface = snd_soc_component_read(component, ES8323_DAC_IFACE) & 0xC7;
552 int coeff;
553 int i;
554
555 /* Validate supported sample rates that are autodetected from MCLK */
556 for (i = 0; i < NR_SUPPORTED_MCLK_LRCK_RATIOS; i++) {
557 const unsigned int ratio = supported_mclk_lrck_ratios[i];
558
559 if (es8323->sysclk % ratio != 0)
560 continue;
561 if (es8323->sysclk / ratio == params_rate(params))
562 break;
563 }
564 if (i == NR_SUPPORTED_MCLK_LRCK_RATIOS) {
565 dev_err(component->dev,
566 "Unsupported sample rate %dHz with %dHz MCLK\n",
567 params_rate(params), es8323->sysclk);
568 return -EINVAL;
569 }
570 coeff = get_coeff(es8323->sysclk, params_rate(params));
571 if (coeff < 0) {
572 coeff = get_coeff(es8323->sysclk / 2, params_rate(params));
573 srate |= 0x40;
574 }
575 if (coeff < 0) {
576 dev_err(component->dev,
577 "Unable to configure sample rate %dHz with %dHz MCLK\n",
578 params_rate(params), es8323->sysclk);
579 return coeff;
580 }
581
582 /* bit size */
583 switch (params_format(params)) {
584 case SNDRV_PCM_FORMAT_S16_LE:
585 adciface |= 0x000C;
586 daciface |= 0x0018;
587 break;
588 case SNDRV_PCM_FORMAT_S20_3LE:
589 adciface |= 0x0004;
590 daciface |= 0x0008;
591 break;
592 case SNDRV_PCM_FORMAT_S24_LE:
593 break;
594 case SNDRV_PCM_FORMAT_S32_LE:
595 adciface |= 0x0010;
596 daciface |= 0x0020;
597 break;
598 }
599
600 /* set iface & srate */
601 snd_soc_component_write(component, ES8323_DAC_IFACE, daciface);
602 snd_soc_component_write(component, ES8323_ADC_IFACE, adciface);
603
604 if (coeff >= 0) {
605 snd_soc_component_write(component, ES8323_IFACE, srate);
606 snd_soc_component_write(component, ES8323_ADCCONTROL5,
607 coeff_div[coeff].sr |
608 coeff_div[coeff].usb << 4);
609 snd_soc_component_write(component, ES8323_DACCONTROL2,
610 coeff_div[coeff].sr |
611 coeff_div[coeff].usb << 4);
612 }
613
614 return 0;
615 }
616
es8323_mute(struct snd_soc_dai * dai,int mute,int stream)617 static int es8323_mute(struct snd_soc_dai *dai, int mute, int stream)
618 {
619 return 0;
620 }
621
es8323_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)622 static int es8323_set_bias_level(struct snd_soc_component *component,
623 enum snd_soc_bias_level level)
624 {
625 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
626 int ret;
627
628 switch (level) {
629 case SND_SOC_BIAS_ON:
630 dev_dbg(component->dev, "%s on\n", __func__);
631 break;
632 case SND_SOC_BIAS_PREPARE:
633 dev_dbg(component->dev, "%s prepare\n", __func__);
634 if (IS_ERR(es8323->mclk))
635 break;
636 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
637 clk_disable_unprepare(es8323->mclk);
638 } else {
639 ret = clk_prepare_enable(es8323->mclk);
640 if (ret)
641 return ret;
642 }
643 snd_soc_component_write(component, ES8323_ANAVOLMANAG, 0x7C);
644 snd_soc_component_write(component, ES8323_CHIPLOPOW1, 0x00);
645 snd_soc_component_write(component, ES8323_CHIPLOPOW2, 0x00);
646 snd_soc_component_write(component, ES8323_CHIPPOWER, 0x00);
647 snd_soc_component_write(component, ES8323_ADCPOWER, 0x59);
648 break;
649 case SND_SOC_BIAS_STANDBY:
650 dev_dbg(component->dev, "%s standby\n", __func__);
651 snd_soc_component_write(component, ES8323_ANAVOLMANAG, 0x7C);
652 snd_soc_component_write(component, ES8323_CHIPLOPOW1, 0x00);
653 snd_soc_component_write(component, ES8323_CHIPLOPOW2, 0x00);
654 snd_soc_component_write(component, ES8323_CHIPPOWER, 0x00);
655 snd_soc_component_write(component, ES8323_ADCPOWER, 0x59);
656 break;
657 case SND_SOC_BIAS_OFF:
658 dev_dbg(component->dev, "%s off\n", __func__);
659 snd_soc_component_write(component, ES8323_ADCPOWER, 0xFF);
660 snd_soc_component_write(component, ES8323_DACPOWER, 0xC0);
661 snd_soc_component_write(component, ES8323_CHIPLOPOW1, 0xFF);
662 snd_soc_component_write(component, ES8323_CHIPLOPOW2, 0xFF);
663 snd_soc_component_write(component, ES8323_CHIPPOWER, 0xFF);
664 snd_soc_component_write(component, ES8323_ANAVOLMANAG, 0x7B);
665 break;
666 }
667 return 0;
668 }
669
670 #define es8323_RATES SNDRV_PCM_RATE_8000_96000
671
672 #define es8323_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
673 SNDRV_PCM_FMTBIT_S24_LE)
674
675 static struct snd_soc_dai_ops es8323_ops = {
676 .startup = es8323_pcm_startup,
677 .hw_params = es8323_pcm_hw_params,
678 .set_fmt = es8323_set_dai_fmt,
679 .set_sysclk = es8323_set_dai_sysclk,
680 .mute_stream = es8323_mute,
681 .no_capture_mute = 1,
682 };
683
684 static struct snd_soc_dai_driver es8323_dai = {
685 .name = "ES8323 HiFi",
686 .playback = {
687 .stream_name = "Playback",
688 .channels_min = 1,
689 .channels_max = 2,
690 .rates = es8323_RATES,
691 .formats = es8323_FORMATS,
692 },
693 .capture = {
694 .stream_name = "Capture",
695 .channels_min = 1,
696 .channels_max = 2,
697 .rates = es8323_RATES,
698 .formats = es8323_FORMATS,
699 },
700 .ops = &es8323_ops,
701 .symmetric_rates = 1,
702 };
703
es8323_suspend(struct snd_soc_component * component)704 static int es8323_suspend(struct snd_soc_component *component)
705 {
706 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
707
708 snd_soc_component_write(component, 0x19, 0x06);
709 snd_soc_component_write(component, 0x30, 0x00);
710 snd_soc_component_write(component, 0x31, 0x00);
711 snd_soc_component_write(component, ES8323_ADCPOWER, 0xFF);
712 snd_soc_component_write(component, ES8323_DACPOWER, 0xc0);
713 snd_soc_component_write(component, ES8323_CHIPPOWER, 0xF3);
714 snd_soc_component_write(component, 0x00, 0x00);
715 snd_soc_component_write(component, 0x01, 0x58);
716 snd_soc_component_write(component, 0x2b, 0x9c);
717 usleep_range(18000, 20000);
718 regcache_cache_only(es8323->regmap, true);
719 regcache_mark_dirty(es8323->regmap);
720 return 0;
721 }
722
es8323_resume(struct snd_soc_component * component)723 static int es8323_resume(struct snd_soc_component *component)
724 {
725 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
726
727 regcache_cache_only(es8323->regmap, false);
728 snd_soc_component_cache_sync(component);
729 snd_soc_component_write(component, 0x2b, 0x80);
730 snd_soc_component_write(component, 0x01, 0x50);
731 snd_soc_component_write(component, 0x00, 0x32);
732 snd_soc_component_write(component, ES8323_CHIPPOWER, 0x00);
733 snd_soc_component_write(component, ES8323_DACPOWER, 0x0c);
734 snd_soc_component_write(component, ES8323_ADCPOWER, 0x59);
735 snd_soc_component_write(component, 0x31, es8323_DEF_VOL);
736 snd_soc_component_write(component, 0x30, es8323_DEF_VOL);
737 snd_soc_component_write(component, 0x19, 0x02);
738 return 0;
739 }
740
es8323_probe(struct snd_soc_component * component)741 static int es8323_probe(struct snd_soc_component *component)
742 {
743 struct es8323_priv *es8323 = snd_soc_component_get_drvdata(component);
744 int ret = 0;
745
746 es8323->mclk = devm_clk_get(component->dev, "mclk");
747 if (IS_ERR(es8323->mclk)) {
748 dev_err(component->dev, "%s mclk is missing or invalid\n", __func__);
749 return PTR_ERR(es8323->mclk);
750 }
751 ret = clk_prepare_enable(es8323->mclk);
752 if (ret)
753 return ret;
754 es8323->component = component;
755
756 ret = es8323_reset(component);
757 if (ret < 0) {
758 dev_err(component->dev, "Failed to issue reset\n");
759 clk_disable_unprepare(es8323->mclk);
760 return ret;
761 }
762
763 snd_soc_component_write(component, 0x01, 0x60);
764 snd_soc_component_write(component, 0x02, 0xF3);
765 snd_soc_component_write(component, 0x02, 0xF0);
766 snd_soc_component_write(component, 0x2B, 0x80);
767 snd_soc_component_write(component, 0x00, 0x36);
768 snd_soc_component_write(component, 0x08, 0x00);
769 snd_soc_component_write(component, 0x04, 0x00);
770 snd_soc_component_write(component, 0x06, 0xC3);
771 snd_soc_component_write(component, 0x19, 0x02);
772 snd_soc_component_write(component, 0x09, 0x00);
773 snd_soc_component_write(component, 0x0A, 0x00);
774 snd_soc_component_write(component, 0x0B, 0x02);
775 snd_soc_component_write(component, 0x0C, 0x4C);
776 snd_soc_component_write(component, 0x0D, 0x02);
777 snd_soc_component_write(component, 0x10, 0x00);
778 snd_soc_component_write(component, 0x11, 0x00);
779 snd_soc_component_write(component, 0x12, 0xea);
780 snd_soc_component_write(component, 0x13, 0xc0);
781 snd_soc_component_write(component, 0x14, 0x05);
782 snd_soc_component_write(component, 0x15, 0x06);
783 snd_soc_component_write(component, 0x16, 0x53);
784
785 snd_soc_component_write(component, 0x17, 0x18);
786 snd_soc_component_write(component, 0x18, 0x02);
787 snd_soc_component_write(component, 0x1A, 0x00);
788 snd_soc_component_write(component, 0x1B, 0x00);
789 snd_soc_component_write(component, 0x27, 0xB8);
790 snd_soc_component_write(component, 0x2A, 0xB8);
791 snd_soc_component_write(component, 0x35, 0xA0);
792 usleep_range(18000, 20000);
793 snd_soc_component_write(component, 0x2E, 0x1E);
794 snd_soc_component_write(component, 0x2F, 0x1E);
795 snd_soc_component_write(component, 0x30, 0x1E);
796 snd_soc_component_write(component, 0x31, 0x1E);
797 snd_soc_component_write(component, 0x03, 0x09);
798 snd_soc_component_write(component, 0x02, 0x00);
799 usleep_range(18000, 20000);
800 snd_soc_component_write(component, 0x04, 0x3C);
801
802 es8323_set_bias_level(component, SND_SOC_BIAS_STANDBY);
803 return 0;
804 }
805
es8323_remove(struct snd_soc_component * component)806 static void es8323_remove(struct snd_soc_component *component)
807 {
808 es8323_set_bias_level(component, SND_SOC_BIAS_OFF);
809 }
810
811 static const struct snd_soc_component_driver soc_codec_dev_es8323 = {
812 .probe = es8323_probe,
813 .remove = es8323_remove,
814 .suspend = es8323_suspend,
815 .resume = es8323_resume,
816 .set_bias_level = es8323_set_bias_level,
817 .dapm_widgets = es8323_dapm_widgets,
818 .num_dapm_widgets = ARRAY_SIZE(es8323_dapm_widgets),
819 .dapm_routes = audio_map,
820 .num_dapm_routes = ARRAY_SIZE(audio_map),
821 .controls = es8323_snd_controls,
822 .num_controls = ARRAY_SIZE(es8323_snd_controls),
823 };
824
825 static const struct regmap_config es8323_regmap_config = {
826 .reg_bits = 8,
827 .val_bits = 8,
828 .max_register = ES8323_DACCONTROL30,
829 .cache_type = REGCACHE_RBTREE,
830 .reg_defaults = es8323_reg_defaults,
831 .num_reg_defaults = ARRAY_SIZE(es8323_reg_defaults),
832 .use_single_read = true,
833 .use_single_write = true,
834 };
835
es8323_i2c_probe(struct i2c_client * i2c,const struct i2c_device_id * id)836 static int es8323_i2c_probe(struct i2c_client *i2c,
837 const struct i2c_device_id *id)
838 {
839 struct es8323_priv *es8323;
840 int ret = -1;
841 struct i2c_adapter *adapter = to_i2c_adapter(i2c->dev.parent);
842 char reg;
843
844 if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) {
845 dev_warn(&adapter->dev,
846 "I2C-Adapter doesn't support I2C_FUNC_I2C\n");
847 return -EIO;
848 }
849
850 es8323 = devm_kzalloc(&i2c->dev, sizeof(struct es8323_priv), GFP_KERNEL);
851 if (!es8323)
852 return -ENOMEM;
853
854 es8323->regmap = devm_regmap_init_i2c(i2c, &es8323_regmap_config);
855 if (IS_ERR(es8323->regmap))
856 return PTR_ERR(es8323->regmap);
857
858 i2c_set_clientdata(i2c, es8323);
859
860 reg = ES8323_DACCONTROL18;
861 ret = i2c_master_recv(i2c, ®, 1);
862 if (ret < 0) {
863 dev_err(&i2c->dev, "i2c recv Failed\n");
864 return ret;
865 }
866
867 ret = devm_snd_soc_register_component(&i2c->dev,
868 &soc_codec_dev_es8323,
869 &es8323_dai, 1);
870 return ret;
871 }
872
es8323_i2c_remove(struct i2c_client * client)873 static int es8323_i2c_remove(struct i2c_client *client)
874 {
875 snd_soc_unregister_component(&client->dev);
876 return 0;
877 }
878
879 static const struct i2c_device_id es8323_i2c_id[] = {
880 {"es8323", 0},
881 {}
882 };
883
884 MODULE_DEVICE_TABLE(i2c, es8323_i2c_id);
885
es8323_i2c_shutdown(struct i2c_client * client)886 static void es8323_i2c_shutdown(struct i2c_client *client)
887 {
888 struct es8323_priv *es8323 = i2c_get_clientdata(client);
889
890 regmap_write(es8323->regmap, ES8323_CONTROL2, 0x58);
891 regmap_write(es8323->regmap, ES8323_CONTROL1, 0x32);
892 regmap_write(es8323->regmap, ES8323_CHIPPOWER, 0xf3);
893 regmap_write(es8323->regmap, ES8323_DACPOWER, 0xc0);
894 mdelay(50);
895 regmap_write(es8323->regmap, ES8323_DACCONTROL26, 0x00);
896 regmap_write(es8323->regmap, ES8323_DACCONTROL27, 0x00);
897 mdelay(50);
898 regmap_write(es8323->regmap, ES8323_CONTROL1, 0x30);
899 regmap_write(es8323->regmap, ES8323_CONTROL1, 0x34);
900 }
901
902 static const struct of_device_id es8323_of_match[] = {
903 { .compatible = "everest,es8323", },
904 { }
905 };
906 MODULE_DEVICE_TABLE(of, es8323_of_match);
907
908 static struct i2c_driver es8323_i2c_driver = {
909 .driver = {
910 .name = "ES8323",
911 .of_match_table = of_match_ptr(es8323_of_match),
912 },
913 .shutdown = es8323_i2c_shutdown,
914 .probe = es8323_i2c_probe,
915 .remove = es8323_i2c_remove,
916 .id_table = es8323_i2c_id,
917 };
918 module_i2c_driver(es8323_i2c_driver);
919
920 MODULE_DESCRIPTION("ASoC es8323 driver");
921 MODULE_AUTHOR("Mark Brown <will@everset-semi.com>");
922 MODULE_LICENSE("GPL");
923