1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ES8311.h -- ES8311 ALSA SoC Audio Codec 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Authors: 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Based on ES8374.h by David Yang 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 10*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 11*4882a593Smuzhiyun * published by the Free Software Foundation. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _ES8311_H 15*4882a593Smuzhiyun #define _ES8311_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * ES8311_REGISTER NAME_REG_REGISTER ADDRESS 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun #define ES8311_RESET_REG00 0x00 /*reset digital,csm,clock manager etc.*/ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* 23*4882a593Smuzhiyun * Clock Scheme Register definition 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define ES8311_CLK_MANAGER_REG01 0x01 /* select clk src for mclk, enable clock for codec */ 26*4882a593Smuzhiyun #define ES8311_CLK_MANAGER_REG02 0x02 /* clk divider and clk multiplier */ 27*4882a593Smuzhiyun #define ES8311_CLK_MANAGER_REG03 0x03 /* adc fsmode and osr */ 28*4882a593Smuzhiyun #define ES8311_CLK_MANAGER_REG04 0x04 /* dac osr */ 29*4882a593Smuzhiyun #define ES8311_CLK_MANAGER_REG05 0x05 /* clk divier for adc and dac */ 30*4882a593Smuzhiyun #define ES8311_CLK_MANAGER_REG06 0x06 /* bclk inverter and divider */ 31*4882a593Smuzhiyun #define ES8311_CLK_MANAGER_REG07 0x07 /* tri-state, lrck divider */ 32*4882a593Smuzhiyun #define ES8311_CLK_MANAGER_REG08 0x08 /* lrck divider */ 33*4882a593Smuzhiyun #define ES8311_SDPIN_REG09 0x09 /* dac serial digital port */ 34*4882a593Smuzhiyun #define ES8311_SDPOUT_REG0A 0x0A /* adc serial digital port */ 35*4882a593Smuzhiyun #define ES8311_SYSTEM_REG0B 0x0B /* system */ 36*4882a593Smuzhiyun #define ES8311_SYSTEM_REG0C 0x0C /* system */ 37*4882a593Smuzhiyun #define ES8311_SYSTEM_REG0D 0x0D /* system, power up/down */ 38*4882a593Smuzhiyun #define ES8311_SYSTEM_REG0E 0x0E /* system, power up/down */ 39*4882a593Smuzhiyun #define ES8311_SYSTEM_REG0F 0x0F /* system, low power */ 40*4882a593Smuzhiyun #define ES8311_SYSTEM_REG10 0x10 /* system */ 41*4882a593Smuzhiyun #define ES8311_SYSTEM_REG11 0x11 /* system */ 42*4882a593Smuzhiyun #define ES8311_SYSTEM_REG12 0x12 /* system, Enable DAC */ 43*4882a593Smuzhiyun #define ES8311_SYSTEM_REG13 0x13 /* system */ 44*4882a593Smuzhiyun #define ES8311_SYSTEM_REG14 0x14 /* system, select DMIC, select analog pga gain */ 45*4882a593Smuzhiyun #define ES8311_ADC_REG15 0x15 /* ADC, adc ramp rate, dmic sense */ 46*4882a593Smuzhiyun #define ES8311_ADC_REG16 0x16 /* ADC */ 47*4882a593Smuzhiyun #define ES8311_ADC_REG17 0x17 /* ADC, volume */ 48*4882a593Smuzhiyun #define ES8311_ADC_REG18 0x18 /* ADC, alc enable and winsize */ 49*4882a593Smuzhiyun #define ES8311_ADC_REG19 0x19 /* ADC, alc maxlevel */ 50*4882a593Smuzhiyun #define ES8311_ADC_REG1A 0x1A /* ADC, alc automute */ 51*4882a593Smuzhiyun #define ES8311_ADC_REG1B 0x1B /* ADC, alc automute, adc hpf s1 */ 52*4882a593Smuzhiyun #define ES8311_ADC_REG1C 0x1C /* ADC, equalizer, hpf s2 */ 53*4882a593Smuzhiyun #define ES8311_DAC_REG31 0x31 /* DAC, mute */ 54*4882a593Smuzhiyun #define ES8311_DAC_REG32 0x32 /* DAC, volume */ 55*4882a593Smuzhiyun #define ES8311_DAC_REG33 0x33 /* DAC, offset */ 56*4882a593Smuzhiyun #define ES8311_DAC_REG34 0x34 /* DAC, drc enable, drc winsize */ 57*4882a593Smuzhiyun #define ES8311_DAC_REG35 0x35 /* DAC, drc maxlevel, minilevel */ 58*4882a593Smuzhiyun #define ES8311_DAC_REG37 0x37 /* DAC, ramprate */ 59*4882a593Smuzhiyun #define ES8311_GPIO_REG44 0x44 /* GPIO, dac2adc for test */ 60*4882a593Smuzhiyun #define ES8311_GP_REG45 0x45 /* GP CONTROL */ 61*4882a593Smuzhiyun #define ES8311_I2C_REGFA 0xFA /* I2C_RETIME and INI_REG */ 62*4882a593Smuzhiyun #define ES8311_CHD1_REGFD 0xFD /* CHIP ID1 */ 63*4882a593Smuzhiyun #define ES8311_CHD2_REGFE 0xFE /* CHIP ID2 */ 64*4882a593Smuzhiyun #define ES8311_CHVER_REGFF 0xFF /* VERSION */ 65*4882a593Smuzhiyun #define ES8311_CHD1_REGFD 0xFD /* CHIP ID1 */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define ES8311_MAX_REGISTER 0xFF 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif 70