1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * es8311.c -- ES8311/ES8312 ALSA SoC Audio Codec
4 *
5 * Copyright (C) 2018 Everest Semiconductor Co., Ltd
6 *
7 * Authors: David Yang(yangxiaohua@everest-semi.com)
8 *
9 *
10 * Based on es8374.c by David Yang(yangxiaohua@everest-semi.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17 #include <linux/clk.h>
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/of_gpio.h>
23 #include <linux/pm.h>
24 #include <linux/i2c.h>
25 #include <linux/slab.h>
26 #include <linux/regmap.h>
27 #include <linux/stddef.h>
28 #include <sound/core.h>
29 #include <sound/pcm.h>
30 #include <sound/pcm_params.h>
31 #include <sound/tlv.h>
32 #include <sound/soc.h>
33 #include <sound/initval.h>
34
35 #include "es8311.h"
36
37 /* codec private data */
38 struct es8311_priv {
39 struct snd_soc_component *component;
40 struct clk *mclk_in;
41 struct gpio_desc *spk_ctl_gpio;
42 struct regmap *regmap;
43 /* Optional properties: */
44 int adc_pga_gain;
45 int adc_volume;
46 int dac_volume;
47 int aec_mode;
48 int delay_pa_drv_ms;
49 };
50
51 static const DECLARE_TLV_DB_SCALE(vdac_tlv,
52 -9550, 50, true);
53 static const DECLARE_TLV_DB_SCALE(vadc_tlv,
54 -9550, 50, true);
55 static const DECLARE_TLV_DB_SCALE(mic_pga_tlv,
56 0, 300, true);
57 static const DECLARE_TLV_DB_SCALE(adc_scale_tlv,
58 0, 600, false);
59 static const DECLARE_TLV_DB_SCALE(alc_winsize_tlv,
60 0, 25, false);
61 static const DECLARE_TLV_DB_SCALE(alc_maxlevel_tlv,
62 -3600, 200, false);
63 static const DECLARE_TLV_DB_SCALE(alc_minlevel_tlv,
64 -3600, 200, false);
65 static const DECLARE_TLV_DB_SCALE(alc_noisegate_tlv,
66 -9600, 600, false);
67 static const DECLARE_TLV_DB_SCALE(alc_noisegate_winsize_tlv,
68 4200, 4200, false);
69 static const DECLARE_TLV_DB_SCALE(alc_automute_gain_tlv,
70 4200, 4200, false);
71 static const DECLARE_TLV_DB_SCALE(adc_ramprate_tlv,
72 0, 25, false);
73
74 static const char *const dmic_type_txt[] = {
75 "dmic at high level",
76 "dmic at low level"
77 };
78 static const struct soc_enum dmic_type =
79 SOC_ENUM_SINGLE(ES8311_ADC_REG15, 0, 1, dmic_type_txt);
80
81 static const char *const automute_type_txt[] = {
82 "automute disabled",
83 "automute enable"
84 };
85 static const struct soc_enum alc_automute_type =
86 SOC_ENUM_SINGLE(ES8311_ADC_REG18, 6, 1, automute_type_txt);
87
88 static const char *const dacdsm_mute_type_txt[] = {
89 "mute to 8",
90 "mute to 7/9"
91 };
92 static const struct soc_enum dacdsm_mute_type =
93 SOC_ENUM_SINGLE(ES8311_DAC_REG31, 7, 1, dacdsm_mute_type_txt);
94
95 static const char *const aec_type_txt[] = {
96 "adc left, adc right",
97 "adc left, null right",
98 "null left, adc right",
99 "null left, null right",
100 "dac left, adc right",
101 "adc left, dac right",
102 "dac left, dac right",
103 "N/A"
104 };
105 static const struct soc_enum aec_type =
106 SOC_ENUM_SINGLE(ES8311_GPIO_REG44, 4, 7, aec_type_txt);
107
108 static const char *const adc2dac_sel_txt[] = {
109 "disable",
110 "adc data to dac",
111 };
112 static const struct soc_enum adc2dac_sel =
113 SOC_ENUM_SINGLE(ES8311_GPIO_REG44, 7, 1, adc2dac_sel_txt);
114
115 static const char *const mclk_sel_txt[] = {
116 "from mclk pin",
117 "from bclk",
118 };
119 static const struct soc_enum mclk_src =
120 SOC_ENUM_SINGLE(ES8311_CLK_MANAGER_REG01, 7, 1, mclk_sel_txt);
121
122 /*
123 * es8311 Controls
124 */
125 static const struct snd_kcontrol_new es8311_snd_controls[] = {
126 SOC_SINGLE_TLV("MIC PGA GAIN", ES8311_SYSTEM_REG14,
127 0, 10, 0, mic_pga_tlv),
128 SOC_SINGLE_TLV("ADC SCALE", ES8311_ADC_REG16,
129 0, 7, 0, adc_scale_tlv),
130 SOC_ENUM("DMIC TYPE", dmic_type),
131 SOC_SINGLE_TLV("ADC RAMP RATE", ES8311_ADC_REG15,
132 4, 15, 0, adc_ramprate_tlv),
133 SOC_SINGLE("ADC SDP MUTE", ES8311_SDPOUT_REG0A, 6, 1, 0),
134 SOC_SINGLE("ADC INVERTED", ES8311_ADC_REG16, 4, 1, 0),
135 SOC_SINGLE("ADC SYNC", ES8311_ADC_REG16, 5, 1, 1),
136 SOC_SINGLE("ADC RAM CLR", ES8311_ADC_REG16, 3, 1, 0),
137 SOC_SINGLE_TLV("ADC VOLUME", ES8311_ADC_REG17,
138 0, 255, 0, vadc_tlv),
139 SOC_SINGLE("ALC ENABLE", ES8311_ADC_REG18, 7, 1, 0),
140 SOC_ENUM("ALC AUTOMUTE TYPE", alc_automute_type),
141 SOC_SINGLE_TLV("ALC WIN SIZE", ES8311_ADC_REG18,
142 0, 15, 0, alc_winsize_tlv),
143 SOC_SINGLE_TLV("ALC MAX LEVEL", ES8311_ADC_REG19,
144 4, 15, 0, alc_maxlevel_tlv),
145 SOC_SINGLE_TLV("ALC MIN LEVEL", ES8311_ADC_REG19,
146 0, 15, 0, alc_minlevel_tlv),
147 SOC_SINGLE_TLV("ALC AUTOMUTE WINSIZE", ES8311_ADC_REG1A,
148 4, 15, 0, alc_noisegate_winsize_tlv),
149 SOC_SINGLE_TLV("ALC AUTOMUTE GATE THRESHOLD", ES8311_ADC_REG1A,
150 0, 15, 0, alc_noisegate_tlv),
151 SOC_SINGLE_TLV("ALC AUTOMUTE VOLUME", ES8311_ADC_REG1B,
152 5, 7, 0, alc_automute_gain_tlv),
153 SOC_SINGLE("ADC FS MODE", ES8311_CLK_MANAGER_REG03, 6, 1, 0),
154 SOC_SINGLE("ADC OSR", ES8311_CLK_MANAGER_REG03, 0, 63, 0),
155 SOC_SINGLE("DAC SDP MUTE", ES8311_SDPIN_REG09, 6, 1, 0),
156 SOC_SINGLE("DAC DEM MUTE", ES8311_DAC_REG31, 5, 1, 0),
157 SOC_SINGLE("DAC INVERT", ES8311_DAC_REG31, 4, 1, 0),
158 SOC_SINGLE("DAC RAM CLR", ES8311_DAC_REG31, 3, 1, 0),
159 SOC_ENUM("DAC DSM MUTE", dacdsm_mute_type),
160 SOC_SINGLE("DAC OFFSET", ES8311_DAC_REG33, 0, 255, 0),
161 SOC_SINGLE_TLV("DAC VOLUME", ES8311_DAC_REG32,
162 0, 255, 0, vdac_tlv),
163 SOC_SINGLE("DRC ENABLE", ES8311_DAC_REG34, 7, 1, 0),
164 SOC_SINGLE_TLV("DRC WIN SIZE", ES8311_DAC_REG34,
165 0, 15, 0, alc_winsize_tlv),
166 SOC_SINGLE_TLV("DRC MAX LEVEL", ES8311_DAC_REG35,
167 4, 15, 0, alc_maxlevel_tlv),
168 SOC_SINGLE_TLV("DRC MIN LEVEL", ES8311_DAC_REG35,
169 0, 15, 0, alc_minlevel_tlv),
170 SOC_SINGLE_TLV("DAC RAMP RATE", ES8311_DAC_REG37,
171 4, 15, 0, adc_ramprate_tlv),
172 SOC_SINGLE("DAC OSR", ES8311_CLK_MANAGER_REG04, 0, 127, 0),
173 SOC_ENUM("AEC MODE", aec_type),
174 SOC_ENUM("ADC DATA TO DAC TEST MODE", adc2dac_sel),
175 SOC_SINGLE("MCLK INVERT", ES8311_CLK_MANAGER_REG01, 6, 1, 0),
176 SOC_SINGLE("BCLK INVERT", ES8311_CLK_MANAGER_REG06, 5, 1, 0),
177 SOC_ENUM("MCLK SOURCE", mclk_src),
178 };
179
180 /*
181 * DAPM Controls
182 */
183 static const char *const es8311_dmic_mux_txt[] = {
184 "DMIC DISABLE",
185 "DMIC ENABLE",
186 };
187 static const unsigned int es8311_dmic_mux_values[] = {
188 0, 1
189 };
190 static const struct soc_enum es8311_dmic_mux_enum =
191 SOC_VALUE_ENUM_SINGLE(ES8311_SYSTEM_REG14, 6, 1,
192 ARRAY_SIZE(es8311_dmic_mux_txt),
193 es8311_dmic_mux_txt,
194 es8311_dmic_mux_values);
195 static const struct snd_kcontrol_new es8311_dmic_mux_controls =
196 SOC_DAPM_ENUM("DMIC ROUTE", es8311_dmic_mux_enum);
197
198 static const char *const es8311_adc_sdp_mux_txt[] = {
199 "FROM ADC OUT",
200 "FROM EQUALIZER",
201 };
202 static const unsigned int es8311_adc_sdp_mux_values[] = {
203 0, 1
204 };
205 static const struct soc_enum es8311_adc_sdp_mux_enum =
206 SOC_VALUE_ENUM_SINGLE(ES8311_ADC_REG1C, 6, 1,
207 ARRAY_SIZE(es8311_adc_sdp_mux_txt),
208 es8311_adc_sdp_mux_txt,
209 es8311_adc_sdp_mux_values);
210 static const struct snd_kcontrol_new es8311_adc_sdp_mux_controls =
211 SOC_DAPM_ENUM("ADC SDP ROUTE", es8311_adc_sdp_mux_enum);
212
213 /*
214 * DAC data source
215 */
216 static const char *const es8311_dac_data_mux_txt[] = {
217 "SELECT SDP LEFT DATA",
218 "SELECT SDP RIGHT DATA",
219 };
220 static const unsigned int es8311_dac_data_mux_values[] = {
221 0, 1
222 };
223 static const struct soc_enum es8311_dac_data_mux_enum =
224 SOC_VALUE_ENUM_SINGLE(ES8311_SDPIN_REG09, 7, 1,
225 ARRAY_SIZE(es8311_dac_data_mux_txt),
226 es8311_dac_data_mux_txt,
227 es8311_dac_data_mux_values);
228 static const struct snd_kcontrol_new es8311_dac_data_mux_controls =
229 SOC_DAPM_ENUM("DAC SDP ROUTE", es8311_dac_data_mux_enum);
230
231 static const struct snd_soc_dapm_widget es8311_dapm_widgets[] = {
232 /* Input*/
233 SND_SOC_DAPM_INPUT("DMIC"),
234 SND_SOC_DAPM_INPUT("AMIC"),
235
236 SND_SOC_DAPM_PGA("INPUT PGA", ES8311_SYSTEM_REG0E,
237 6, 1, NULL, 0),
238 /* ADCs */
239 SND_SOC_DAPM_ADC("MONO ADC", NULL, ES8311_SYSTEM_REG0E, 5, 1),
240 /* Dmic MUX */
241 SND_SOC_DAPM_MUX("DMIC MUX", SND_SOC_NOPM, 0, 0,
242 &es8311_dmic_mux_controls),
243 /* sdp MUX */
244 SND_SOC_DAPM_MUX("SDP OUT MUX", SND_SOC_NOPM, 0, 0,
245 &es8311_adc_sdp_mux_controls),
246 /* Digital Interface */
247 SND_SOC_DAPM_AIF_OUT("I2S OUT", "I2S1 Capture", 1,
248 SND_SOC_NOPM, 0, 0),
249 /* Render path */
250 SND_SOC_DAPM_AIF_IN("I2S IN", "I2S1 Playback", 0,
251 SND_SOC_NOPM, 0, 0),
252 /*DACs SDP DATA SRC MUX */
253 SND_SOC_DAPM_MUX("DAC SDP SRC MUX", SND_SOC_NOPM, 0, 0,
254 &es8311_dac_data_mux_controls),
255 SND_SOC_DAPM_DAC("MONO DAC", NULL, SND_SOC_NOPM, 0, 0),
256
257 /* Output Lines */
258 SND_SOC_DAPM_OUTPUT("DIFFERENTIAL OUT"),
259 };
260
261 static const struct snd_soc_dapm_route es8311_dapm_routes[] = {
262 /* record route map */
263 {"INPUT PGA", NULL, "AMIC"},
264 {"MONO ADC", NULL, "INPUT PGA"},
265 {"DMIC MUX", "DMIC DISABLE", "MONO ADC"},
266 {"DMIC MUX", "DMIC ENABLE", "DMIC"},
267 {"SDP OUT MUX", "FROM ADC OUT", "DMIC MUX"},
268 {"SDP OUT MUX", "FROM EQUALIZER", "DMIC MUX"},
269 {"I2S OUT", NULL, "SDP OUT MUX"},
270 /* playback route map */
271 {"DAC SDP SRC MUX", "SELECT SDP LEFT DATA", "I2S IN"},
272 {"DAC SDP SRC MUX", "SELECT SDP RIGHT DATA", "I2S IN"},
273 {"MONO DAC", NULL, "DAC SDP SRC MUX"},
274 {"DIFFERENTIAL OUT", NULL, "MONO DAC"},
275 };
276
es8311_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)277 static int es8311_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
278 {
279 struct snd_soc_component *component = codec_dai->component;
280 u8 iface = 0;
281 u8 adciface = 0;
282 u8 daciface = 0;
283
284 iface = snd_soc_component_read(component, ES8311_RESET_REG00);
285 adciface = snd_soc_component_read(component, ES8311_SDPOUT_REG0A);
286 daciface = snd_soc_component_read(component, ES8311_SDPIN_REG09);
287
288 /* set master/slave audio interface */
289 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
290 case SND_SOC_DAIFMT_CBM_CFM: /* MASTER MODE */
291 iface |= 0x40;
292 break;
293 case SND_SOC_DAIFMT_CBS_CFS: /* SLAVE MODE */
294 iface &= 0xBF;
295 break;
296 default:
297 return -EINVAL;
298 }
299 snd_soc_component_write(component, ES8311_RESET_REG00, iface);
300
301 /* interface format */
302 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
303 case SND_SOC_DAIFMT_I2S:
304 adciface &= 0xFC;
305 daciface &= 0xFC;
306 break;
307 case SND_SOC_DAIFMT_LEFT_J:
308 adciface &= 0xFC;
309 daciface &= 0xFC;
310 adciface |= 0x01;
311 daciface |= 0x01;
312 break;
313 case SND_SOC_DAIFMT_DSP_A:
314 adciface &= 0xDC;
315 daciface &= 0xDC;
316 adciface |= 0x03;
317 daciface |= 0x03;
318 break;
319 case SND_SOC_DAIFMT_DSP_B:
320 adciface &= 0xDC;
321 daciface &= 0xDC;
322 adciface |= 0x23;
323 daciface |= 0x23;
324 break;
325 case SND_SOC_DAIFMT_RIGHT_J:
326 default:
327 return -EINVAL;
328 }
329
330 iface = snd_soc_component_read(component, ES8311_CLK_MANAGER_REG06);
331 /* clock inversion */
332 if (((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_I2S) ||
333 ((fmt & SND_SOC_DAIFMT_FORMAT_MASK) == SND_SOC_DAIFMT_LEFT_J)) {
334
335 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
336 case SND_SOC_DAIFMT_NB_NF:
337 iface &= 0xDF;
338 adciface &= 0xDF;
339 daciface &= 0xDF;
340 break;
341 case SND_SOC_DAIFMT_IB_IF:
342 iface |= 0x20;
343 adciface |= 0x20;
344 daciface |= 0x20;
345 break;
346 case SND_SOC_DAIFMT_IB_NF:
347 iface |= 0x20;
348 adciface &= 0xDF;
349 daciface &= 0xDF;
350 break;
351 case SND_SOC_DAIFMT_NB_IF:
352 iface &= 0xDF;
353 adciface |= 0x20;
354 daciface |= 0x20;
355 break;
356 default:
357 return -EINVAL;
358 }
359 }
360
361 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG06, iface);
362 snd_soc_component_write(component, ES8311_SDPOUT_REG0A, adciface);
363 snd_soc_component_write(component, ES8311_SDPIN_REG09, daciface);
364
365 return 0;
366 }
367
es8311_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)368 static int es8311_pcm_startup(struct snd_pcm_substream *substream,
369 struct snd_soc_dai *dai)
370 {
371 struct snd_soc_component *component = dai->component;
372 struct es8311_priv *es8311 = snd_soc_component_get_drvdata(component);
373
374 clk_prepare_enable(es8311->mclk_in);
375
376 return 0;
377 }
378
es8311_pcm_shutdown(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)379 static void es8311_pcm_shutdown(struct snd_pcm_substream *substream,
380 struct snd_soc_dai *dai)
381 {
382 struct snd_soc_component *component = dai->component;
383 struct es8311_priv *es8311 = snd_soc_component_get_drvdata(component);
384
385 clk_disable_unprepare(es8311->mclk_in);
386 }
387
es8311_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)388 static int es8311_pcm_hw_params(struct snd_pcm_substream *substream,
389 struct snd_pcm_hw_params *params,
390 struct snd_soc_dai *dai)
391 {
392 struct snd_soc_component *component = dai->component;
393 u16 iface;
394
395 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
396 iface = snd_soc_component_read(component, ES8311_SDPIN_REG09) & 0xE3;
397 /* bit size */
398 switch (params_format(params)) {
399 case SNDRV_PCM_FORMAT_S16_LE:
400 iface |= 0x0c;
401 break;
402 case SNDRV_PCM_FORMAT_S20_3LE:
403 iface |= 0x04;
404 break;
405 case SNDRV_PCM_FORMAT_S24_LE:
406 break;
407 case SNDRV_PCM_FORMAT_S32_LE:
408 iface |= 0x10;
409 break;
410 }
411 /* set iface */
412 snd_soc_component_write(component, ES8311_SDPIN_REG09, iface);
413 } else {
414 iface = snd_soc_component_read(component, ES8311_SDPOUT_REG0A) & 0xE3;
415 /* bit size */
416 switch (params_format(params)) {
417 case SNDRV_PCM_FORMAT_S16_LE:
418 iface |= 0x0c;
419 break;
420 case SNDRV_PCM_FORMAT_S20_3LE:
421 iface |= 0x04;
422 break;
423 case SNDRV_PCM_FORMAT_S24_LE:
424 break;
425 case SNDRV_PCM_FORMAT_S32_LE:
426 iface |= 0x10;
427 break;
428 }
429 /* set iface */
430 snd_soc_component_write(component, ES8311_SDPOUT_REG0A, iface);
431 }
432
433 return 0;
434 }
435
es8311_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)436 static int es8311_set_bias_level(struct snd_soc_component *component,
437 enum snd_soc_bias_level level)
438 {
439 struct es8311_priv *es8311 = snd_soc_component_get_drvdata(component);
440 int ret;
441
442 switch (level) {
443 case SND_SOC_BIAS_ON:
444 break;
445 case SND_SOC_BIAS_PREPARE:
446 if (IS_ERR(es8311->mclk_in))
447 break;
448
449 if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
450 clk_disable_unprepare(es8311->mclk_in);
451 } else {
452 ret = clk_prepare_enable(es8311->mclk_in);
453 if (ret)
454 return ret;
455 }
456 break;
457
458 case SND_SOC_BIAS_STANDBY:
459 break;
460
461 case SND_SOC_BIAS_OFF:
462 break;
463 }
464 return 0;
465 }
466
es8311_set_tristate(struct snd_soc_dai * dai,int tristate)467 static int es8311_set_tristate(struct snd_soc_dai *dai, int tristate)
468 {
469 struct snd_soc_component *component = dai->component;
470
471 if (tristate)
472 snd_soc_component_update_bits(component, ES8311_CLK_MANAGER_REG07,
473 0x30, 0x30);
474 else
475 snd_soc_component_update_bits(component, ES8311_CLK_MANAGER_REG07,
476 0x30, 0x00);
477 return 0;
478 }
479
es8311_mute(struct snd_soc_dai * dai,int mute,int stream)480 static int es8311_mute(struct snd_soc_dai *dai, int mute, int stream)
481 {
482 struct snd_soc_component *component = dai->component;
483 struct es8311_priv *es8311 = snd_soc_component_get_drvdata(component);
484
485 if (mute) {
486 snd_soc_component_write(component, ES8311_SYSTEM_REG12, 0x02);
487 snd_soc_component_update_bits(component, ES8311_DAC_REG31, 0x60, 0x60);
488 if (es8311->spk_ctl_gpio)
489 gpiod_direction_output(es8311->spk_ctl_gpio, 0);
490 } else {
491 snd_soc_component_update_bits(component, ES8311_DAC_REG31, 0x60, 0x00);
492 snd_soc_component_write(component, ES8311_SYSTEM_REG12, 0x00);
493 if (es8311->spk_ctl_gpio) {
494 gpiod_direction_output(es8311->spk_ctl_gpio, 1);
495 if (es8311->delay_pa_drv_ms)
496 msleep(es8311->delay_pa_drv_ms);
497 }
498 }
499 return 0;
500 }
501
502 #define ES8311_RATES SNDRV_PCM_RATE_8000_96000
503 #define ES8311_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE |\
504 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
505
506 static struct snd_soc_dai_ops es8311_ops = {
507 .startup = es8311_pcm_startup,
508 .shutdown = es8311_pcm_shutdown,
509 .hw_params = es8311_pcm_hw_params,
510 .set_fmt = es8311_set_dai_fmt,
511 .mute_stream = es8311_mute,
512 .set_tristate = es8311_set_tristate,
513 .no_capture_mute = 1,
514 };
515
516 static struct snd_soc_dai_driver es8311_dai = {
517 .name = "ES8311 HiFi",
518 .playback = {
519 .stream_name = "Playback",
520 .channels_min = 1,
521 .channels_max = 2,
522 .rates = ES8311_RATES,
523 .formats = ES8311_FORMATS,
524 },
525 .capture = {
526 .stream_name = "Capture",
527 .channels_min = 1,
528 .channels_max = 2,
529 .rates = ES8311_RATES,
530 .formats = ES8311_FORMATS,
531 },
532 .ops = &es8311_ops,
533 .symmetric_rates = 1,
534 };
535
es8311_regs_init(struct snd_soc_component * component)536 static int es8311_regs_init(struct snd_soc_component *component)
537 {
538 /* reset codec */
539 snd_soc_component_write(component, ES8311_I2C_REGFA, 0x01);
540 msleep(20);
541 snd_soc_component_write(component, ES8311_I2C_REGFA, 0x00);
542 snd_soc_component_write(component, ES8311_RESET_REG00, 0x1F);
543 snd_soc_component_write(component, ES8311_GP_REG45, 0x00);
544 /* set ADC/DAC CLK */
545 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x30);
546 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG02, 0x00);
547 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG03, 0x10);
548 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG04, 0x10);
549 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG05, 0x00);
550 /* set system power up */
551 snd_soc_component_write(component, ES8311_SYSTEM_REG0B, 0x00);
552 snd_soc_component_write(component, ES8311_SYSTEM_REG0C, 0x00);
553 snd_soc_component_write(component, ES8311_SYSTEM_REG10, 0x1F);
554 snd_soc_component_write(component, ES8311_SYSTEM_REG11, 0x7F);
555 /* chip powerup. slave mode */
556 snd_soc_component_write(component, ES8311_RESET_REG00, 0x80);
557 msleep(20);
558
559 /* power up analog */
560 snd_soc_component_write(component, ES8311_SYSTEM_REG0D, 0x01);
561 /* power up digital */
562 snd_soc_component_write(component, ES8311_CLK_MANAGER_REG01, 0x3F);
563 /* set adc hpf, ADC_EQ bypass */
564 snd_soc_component_write(component, ES8311_ADC_REG1C, 0x6A);
565 /* ensure select Mic1p-Mic1n by default. */
566 snd_soc_component_update_bits(component, ES8311_SYSTEM_REG14,
567 0x30, 0x10);
568
569 return 0;
570 }
571
es8311_probe(struct snd_soc_component * component)572 static int es8311_probe(struct snd_soc_component *component)
573 {
574 struct es8311_priv *es8311 = snd_soc_component_get_drvdata(component);
575
576 es8311->component = component;
577 es8311_regs_init(component);
578
579 /* Configure optional properties: */
580 if (es8311->aec_mode)
581 snd_soc_component_update_bits(component, ES8311_GPIO_REG44,
582 0x70, es8311->aec_mode << 4);
583 if (es8311->adc_pga_gain)
584 snd_soc_component_update_bits(component, ES8311_SYSTEM_REG14,
585 0x0f, es8311->adc_pga_gain);
586 if (es8311->adc_volume)
587 snd_soc_component_write(component, ES8311_ADC_REG17,
588 es8311->adc_volume);
589 if (es8311->dac_volume)
590 snd_soc_component_write(component, ES8311_DAC_REG32,
591 es8311->dac_volume);
592
593 return 0;
594 }
595
596 static const struct snd_soc_component_driver soc_component_dev_es8311 = {
597 .probe = es8311_probe,
598 .set_bias_level = es8311_set_bias_level,
599 .controls = es8311_snd_controls,
600 .num_controls = ARRAY_SIZE(es8311_snd_controls),
601 .dapm_widgets = es8311_dapm_widgets,
602 .num_dapm_widgets = ARRAY_SIZE(es8311_dapm_widgets),
603 .dapm_routes = es8311_dapm_routes,
604 .num_dapm_routes = ARRAY_SIZE(es8311_dapm_routes),
605 .use_pmdown_time = 1,
606 .endianness = 1,
607 .non_legacy_dai_naming = 1,
608 };
609
610 static struct regmap_config es8311_regmap = {
611 .reg_bits = 8,
612 .val_bits = 8,
613 .max_register = ES8311_MAX_REGISTER,
614 .cache_type = REGCACHE_RBTREE,
615 };
616
es8311_parse_dt(struct i2c_client * client,struct es8311_priv * es8311)617 static int es8311_parse_dt(struct i2c_client *client,
618 struct es8311_priv *es8311)
619 {
620 struct device_node *np;
621 const char *str;
622 u32 v;
623 int ret;
624
625 np = client->dev.of_node;
626 if (!np)
627 return -EINVAL;
628
629 es8311->delay_pa_drv_ms = 0;
630 es8311->spk_ctl_gpio = devm_gpiod_get_optional(&client->dev, "spk-ctl",
631 GPIOD_OUT_LOW);
632 if (!es8311->spk_ctl_gpio) {
633 dev_info(&client->dev, "Don't need spk-ctl gpio\n");
634 } else if (IS_ERR(es8311->spk_ctl_gpio)) {
635 ret = PTR_ERR(es8311->spk_ctl_gpio);
636 dev_err(&client->dev, "Unable to claim gpio spk-ctl\n");
637 return ret;
638 }
639 ret = of_property_read_s32(np, "delay-pa-drv-ms",
640 &es8311->delay_pa_drv_ms);
641 if (ret < 0 && ret != -EINVAL) {
642 dev_err(&client->dev,
643 "Failed to read 'rockchip,delay-pa-drv-ms': %d\n",
644 ret);
645 return ret;
646 }
647
648 es8311->adc_pga_gain = 0; /* ADC PGA Gain is 0dB by default reset. */
649 if (!of_property_read_u32(np, "adc-pga-gain", &v)) {
650 if (v >= 0 && v <= 10)
651 es8311->adc_pga_gain = v;
652 else
653 dev_warn(&client->dev,
654 "adc-pga-gain (%d) is out of range\n", v);
655 }
656
657 es8311->adc_volume = 0; /* ADC Volume is -95dB by default reset. */
658 if (!of_property_read_u32(np, "adc-volume", &v)) {
659 if (v >= 0 && v <= 0xff)
660 es8311->adc_volume = v;
661 else
662 dev_warn(&client->dev,
663 "adc-volume (0x%02x) is out of range\n", v);
664 }
665
666 es8311->dac_volume = 0; /* DAC Volume is -95dB by default reset. */
667 if (!of_property_read_u32(np, "dac-volume", &v)) {
668 if (v >= 0 && v <= 0xff)
669 es8311->dac_volume = v;
670 else
671 dev_warn(&client->dev,
672 "dac-volume (0x%02x) is out of range\n", v);
673 }
674
675 es8311->aec_mode = 0; /* ADCDAT: 0 is ADC + ADC (default) */
676 if (!of_property_read_string(np, "aec-mode", &str)) {
677 int i;
678
679 for (i = 0; i < ARRAY_SIZE(aec_type_txt); i++) {
680 if (strcmp(str, aec_type_txt[i]) == 0) {
681 es8311->aec_mode = i;
682 break;
683 }
684 }
685 }
686
687 return 0;
688 }
689
es8311_i2c_probe(struct i2c_client * i2c_client,const struct i2c_device_id * id)690 static int es8311_i2c_probe(struct i2c_client *i2c_client,
691 const struct i2c_device_id *id)
692 {
693 struct es8311_priv *es8311;
694 struct regmap *regmap;
695 int ret = 0;
696
697 es8311 = devm_kzalloc(&i2c_client->dev,
698 sizeof(*es8311), GFP_KERNEL);
699 if (es8311 == NULL)
700 return -ENOMEM;
701
702 i2c_set_clientdata(i2c_client, es8311);
703
704 regmap = devm_regmap_init_i2c(i2c_client, &es8311_regmap);
705 if (IS_ERR(regmap))
706 return PTR_ERR(regmap);
707
708 es8311->mclk_in = devm_clk_get(&i2c_client->dev, "mclk");
709 if (IS_ERR(es8311->mclk_in))
710 return PTR_ERR(es8311->mclk_in);
711
712 ret = es8311_parse_dt(i2c_client, es8311);
713 if (ret < 0) {
714 dev_err(&i2c_client->dev, "Parse DT failed: %d\n", ret);
715 return ret;
716 }
717
718 return devm_snd_soc_register_component(&i2c_client->dev,
719 &soc_component_dev_es8311,
720 &es8311_dai, 1);
721 }
722
es8311_i2c_shutdown(struct i2c_client * client)723 static void es8311_i2c_shutdown(struct i2c_client *client)
724 {
725 struct es8311_priv *es8311 = (struct es8311_priv *)i2c_get_clientdata(client);
726
727 /* Need to reset anc clear all registers for reboot */
728 snd_soc_component_write(es8311->component, ES8311_I2C_REGFA, 0x01);
729 }
730
731 static const struct i2c_device_id es8311_i2c_id[] = {
732 {"es8311", 0 },
733 {}
734 };
735 MODULE_DEVICE_TABLE(i2c, es8311_i2c_id);
736
737 static const struct of_device_id es8311_of_match[] = {
738 { .compatible = "everest,es8311", },
739 {},
740 };
741 MODULE_DEVICE_TABLE(of, es8311_of_match);
742
743 static struct i2c_driver es8311_i2c_driver = {
744 .driver = {
745 .name = "es8311",
746 .of_match_table = of_match_ptr(es8311_of_match),
747 },
748 .probe = es8311_i2c_probe,
749 .shutdown = es8311_i2c_shutdown,
750 .id_table = es8311_i2c_id,
751 };
752 module_i2c_driver(es8311_i2c_driver);
753
754 MODULE_DESCRIPTION("Everest Semi ES8311 ALSA SoC Codec Driver");
755 MODULE_AUTHOR("David Yang <yangxiaohua@everest-semi.com>");
756 MODULE_LICENSE("GPL");
757