1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * ALSA SoC ES7243E adc driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author: David Yang, <yangxiaohua@everest-semi.com> 5*4882a593Smuzhiyun * or 6*4882a593Smuzhiyun * <info@everest-semi.com> 7*4882a593Smuzhiyun * Copyright: (C) 2019 Everest Semiconductor Co Ltd., 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Based on sound/soc/codecs/es7243.c by DavidYang 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify 12*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as 13*4882a593Smuzhiyun * published by the Free Software Foundation. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * Notes: 16*4882a593Smuzhiyun * this is an important file, you need to check it before you use ES7243E. 17*4882a593Smuzhiyun * es7243e_usr_cfg.h is a user interface which is convenient for digital 18*4882a593Smuzhiyun * format, clock ratio, etc. 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define ENABLE 1 23*4882a593Smuzhiyun #define DISABLE 0 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * Here is the definition of ES7243E ADC Digital Format 26*4882a593Smuzhiyun * Users must select correct digital format for their systerm. 27*4882a593Smuzhiyun * 28*4882a593Smuzhiyun * ES7243E_WORK_MODE is used to select digital format, and user must update it for their system 29*4882a593Smuzhiyun * In ES7243E codec driver (es7243e.c), ES7243E_WORK_MODE will be used for digital format setting. 30*4882a593Smuzhiyun * 31*4882a593Smuzhiyun * In normal mode, ES7243E supports four digital formats including I2S, LJ, DSP-A and DSP-B, with 32*4882a593Smuzhiyun * resolution from 16bits to 32bits. 33*4882a593Smuzhiyun * In TDM mode, ES7243E only supports DSP-A TDM, doesn't support DSP-B TDM. 34*4882a593Smuzhiyun * In NFS mode, ES7243E only supports NFS I2S mode, doesn't support DSP or LJ NFS mode. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define ES7243E_NORMAL_I2S 0 37*4882a593Smuzhiyun #define ES7243E_NORMAL_LJ 1 38*4882a593Smuzhiyun #define ES7243E_NORMAL_DSPA 2 39*4882a593Smuzhiyun #define ES7243E_NORMAL_DSPB 3 40*4882a593Smuzhiyun #define ES7243E_TDM_A 4 41*4882a593Smuzhiyun #define ES7243E_NFS_I2S 5 42*4882a593Smuzhiyun #define ES7243E_NFS_DSPA 6 43*4882a593Smuzhiyun #define ES7243E_WORK_MODE ES7243E_NORMAL_I2S 44*4882a593Smuzhiyun /* 45*4882a593Smuzhiyun * Here is the definition of the common MCLK/LRCK rato. 46*4882a593Smuzhiyun * ES7243E will have different register configuration for each MCLK/LRCK ratio. 47*4882a593Smuzhiyun * Please check the MCLK/LRCK ratio in your system before you update ES7243E_MCLK_LRCK_RATIO. 48*4882a593Smuzhiyun * ES7243E codec driver will configure the clock registers according to the value of ES7243E_MCLK_LRCK_RATO. 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define RATIO_3072 3072 51*4882a593Smuzhiyun #define RATIO_2048 2048 52*4882a593Smuzhiyun #define RATIO_1536 1536 53*4882a593Smuzhiyun #define RATIO_1024 1024 54*4882a593Smuzhiyun #define RATIO_768 768 55*4882a593Smuzhiyun #define RATIO_512 512 56*4882a593Smuzhiyun #define RATIO_384 384 57*4882a593Smuzhiyun #define RATIO_256 256 58*4882a593Smuzhiyun #define RATIO_192 192 59*4882a593Smuzhiyun #define RATIO_128 128 60*4882a593Smuzhiyun #define RATIO_64 64 61*4882a593Smuzhiyun #define ES7243E_MCLK_LRCK_RATIO RATIO_64 62*4882a593Smuzhiyun /* 63*4882a593Smuzhiyun * To select the total analog input channel for microphone array 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun #define AIN_2_CH 2 66*4882a593Smuzhiyun #define AIN_4_CH 4 67*4882a593Smuzhiyun #define AIN_6_CH 6 68*4882a593Smuzhiyun #define AIN_8_CH 8 69*4882a593Smuzhiyun #define AIN_10_CH 10 70*4882a593Smuzhiyun #define AIN_12_CH 12 71*4882a593Smuzhiyun #define AIN_14_CH 14 72*4882a593Smuzhiyun #define AIN_16_CH 16 73*4882a593Smuzhiyun #define ES7243E_CHANNELS_MAX AIN_6_CH 74*4882a593Smuzhiyun /* 75*4882a593Smuzhiyun * to select the clock soure for internal MCLK clock 76*4882a593Smuzhiyun */ 77*4882a593Smuzhiyun #define FROM_MCLK_PIN 0 78*4882a593Smuzhiyun #define FROM_INTERNAL_BCLK 1 79*4882a593Smuzhiyun #define ES7243E_MCLK_SOURCE FROM_INTERNAL_BCLK 80*4882a593Smuzhiyun /* 81*4882a593Smuzhiyun * to select the data length or resolution 82*4882a593Smuzhiyun */ 83*4882a593Smuzhiyun #define DATA_16BITS 0 84*4882a593Smuzhiyun #define DATA_24BITS 1 85*4882a593Smuzhiyun #define DATA_32BITS 2 86*4882a593Smuzhiyun #define ES7243E_DATA_LENGTH DATA_16BITS 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * to select the pdm digital microphone interface 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun #define DMIC_INTERFACE_ON true 91*4882a593Smuzhiyun #define DMIC_INTERFACE_OFF false 92*4882a593Smuzhiyun #define DMIC_INTERFACE DMIC_INTERFACE_OFF 93*4882a593Smuzhiyun /* 94*4882a593Smuzhiyun * to select bclk inverted or not 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun #define BCLK_NORMAL false 97*4882a593Smuzhiyun #define BCLK_INVERTED true 98*4882a593Smuzhiyun #define BCLK_INVERTED_OR_NOT BCLK_NORMAL 99*4882a593Smuzhiyun /* 100*4882a593Smuzhiyun * to select mclk inverted or not 101*4882a593Smuzhiyun */ 102*4882a593Smuzhiyun #define MCLK_NORMAL false 103*4882a593Smuzhiyun #define MCLK_INVERTED true 104*4882a593Smuzhiyun #define MCLK_INVERTED_OR_NOT MCLK_NORMAL 105*4882a593Smuzhiyun /* 106*4882a593Smuzhiyun * to select PGA gain for different analog input channel 107*4882a593Smuzhiyun * user must allocate the PGA gain for each analog input channel 108*4882a593Smuzhiyun * ES7243E_MIC_ARRAY_AIN1_PGA to ES7243E_MIC_ARRAY_AIN16_PGA is used for PGA gain 109*4882a593Smuzhiyun */ 110*4882a593Smuzhiyun #define PGA_0DB 0 111*4882a593Smuzhiyun #define PGA_3DB 1 112*4882a593Smuzhiyun #define PGA_6DB 2 113*4882a593Smuzhiyun #define PGA_9DB 3 114*4882a593Smuzhiyun #define PGA_12DB 4 115*4882a593Smuzhiyun #define PGA_15DB 5 116*4882a593Smuzhiyun #define PGA_18DB 6 117*4882a593Smuzhiyun #define PGA_21DB 7 118*4882a593Smuzhiyun #define PGA_24DB 8 119*4882a593Smuzhiyun #define PGA_27DB 9 120*4882a593Smuzhiyun #define PGA_30DB 10 121*4882a593Smuzhiyun #define PGA_33DB 11 122*4882a593Smuzhiyun #define PGA_34DB 12 123*4882a593Smuzhiyun #define PGA_36DB 13 124*4882a593Smuzhiyun #define PGA_37DB 14 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 0 127*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN1_PGA PGA_27DB 128*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN2_PGA PGA_27DB 129*4882a593Smuzhiyun #endif 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 2 132*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN3_PGA PGA_33DB 133*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN4_PGA PGA_33DB 134*4882a593Smuzhiyun #endif 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 4 137*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN5_PGA PGA_33DB 138*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN6_PGA PGA_33DB 139*4882a593Smuzhiyun #endif 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 6 142*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN7_PGA PGA_0DB 143*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN8_PGA PGA_0DB 144*4882a593Smuzhiyun #endif 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 8 147*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN9_PGA PGA_33DB 148*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN10_PGA PGA_33DB 149*4882a593Smuzhiyun #endif 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 10 152*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN11_PGA PGA_33DB 153*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN12_PGA PGA_33DB 154*4882a593Smuzhiyun #endif 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 12 157*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN13_PGA PGA_33DB 158*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN14_PGA PGA_33DB 159*4882a593Smuzhiyun #endif 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 14 162*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN15_PGA PGA_33DB 163*4882a593Smuzhiyun #define ES7243E_MIC_ARRAY_AIN16_PGA PGA_33DB 164*4882a593Smuzhiyun #endif 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* 167*4882a593Smuzhiyun * here is the definition of digital volume. 168*4882a593Smuzhiyun * the digital volume is 0dB by default. User can update it 169*4882a593Smuzhiyun * ES7243E_DIGITAL_VOLUME_1 to ES7243E_DIGITAL_VOLUME_16 is used for digital volume 170*4882a593Smuzhiyun * digital volume is 0db default. 171*4882a593Smuzhiyun */ 172*4882a593Smuzhiyun 173*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 0 174*4882a593Smuzhiyun #define DIG_VOL_1 0 // DB 175*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_1 0xbf + (DIG_VOL_1 * 2) 176*4882a593Smuzhiyun #define DIG_VOL_2 0 // DB 177*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_2 0xbf + (DIG_VOL_2 * 2) 178*4882a593Smuzhiyun #endif 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 2 181*4882a593Smuzhiyun #define DIG_VOL_3 0 // DB 182*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_3 0xbf + (DIG_VOL_3 * 2) 183*4882a593Smuzhiyun #define DIG_VOL_4 0 // DB 184*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_4 0xbf + (DIG_VOL_4 * 2) 185*4882a593Smuzhiyun #endif 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 4 188*4882a593Smuzhiyun #define DIG_VOL_5 0 // DB 189*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_5 0xbf + (DIG_VOL_5 * 2) 190*4882a593Smuzhiyun #define DIG_VOL_6 0 // DB 191*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_6 0xbf + (DIG_VOL_6 * 2) 192*4882a593Smuzhiyun #endif 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 6 195*4882a593Smuzhiyun #define DIG_VOL_7 0 // DB 196*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_7 0xbf + (DIG_VOL_7 * 2) 197*4882a593Smuzhiyun #define DIG_VOL_8 0 // DB 198*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_8 0xbf + (DIG_VOL_8 * 2) 199*4882a593Smuzhiyun #endif 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 8 202*4882a593Smuzhiyun #define DIG_VOL_9 0 // DB 203*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_9 0xbf + (DIG_VOL_9 * 2) 204*4882a593Smuzhiyun #define DIG_VOL_10 0 // DB 205*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_10 0xbf + (DIG_VOL_10 * 2) 206*4882a593Smuzhiyun #endif 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 10 209*4882a593Smuzhiyun #define DIG_VOL_11 0 // DB 210*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_11 0xbf + (DIG_VOL_11 * 2) 211*4882a593Smuzhiyun #define DIG_VOL_12 0 // DB 212*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_12 0xbf + (DIG_VOL_12 * 2) 213*4882a593Smuzhiyun #endif 214*4882a593Smuzhiyun 215*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 12 216*4882a593Smuzhiyun #define DIG_VOL_13 0 // DB 217*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_13 0xbf + (DIG_VOL_13 * 2) 218*4882a593Smuzhiyun #define DIG_VOL_14 0 // DB 219*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_14 0xbf + (DIG_VOL_14 * 2) 220*4882a593Smuzhiyun #endif 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 14 223*4882a593Smuzhiyun #define DIG_VOL_15 0 // DB 224*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_15 0xbf + (DIG_VOL_15 * 2) 225*4882a593Smuzhiyun #define DIG_VOL_16 0 // DB 226*4882a593Smuzhiyun #define ES7243E_DIGITAL_VOLUME_16 0xbf + (DIG_VOL_16 * 2) 227*4882a593Smuzhiyun #endif 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun /* 230*4882a593Smuzhiyun * set the I2C chip address for each es7243e device in TDM linkloop 231*4882a593Smuzhiyun * user can update the chip address according their system circuit 232*4882a593Smuzhiyun */ 233*4882a593Smuzhiyun #define I2C_CHIP_ADDR_10H 0x10 // AD0 and AD1 pulled down, ASDOUT pulled down or float 234*4882a593Smuzhiyun #define I2C_CHIP_ADDR_11H 0x11 // AD0 pulled up, AD1 pulled down, ASDOUT pulled down or float 235*4882a593Smuzhiyun #define I2C_CHIP_ADDR_12H 0x12 // AD0 pulled down, AD1 pulled up, ASDOUT pulled down or float 236*4882a593Smuzhiyun #define I2C_CHIP_ADDR_13H 0x13 // AD0 and AD1 pulled up, ASDOUT pulled down or float 237*4882a593Smuzhiyun #define I2C_CHIP_ADDR_14H 0x14 // AD0 and AD1 pulled down, ASDOUT pulled up 238*4882a593Smuzhiyun #define I2C_CHIP_ADDR_15H 0x15 // AD0 pulled up, AD1 pulled down, ASDOUT pulled up 239*4882a593Smuzhiyun #define I2C_CHIP_ADDR_16H 0x16 // AD0 pulled down, AD1 pulled up, ASDOUT pulled up 240*4882a593Smuzhiyun #define I2C_CHIP_ADDR_17H 0x17 // AD0 and AD1 pulled up, ASDOUT pulled up 241*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 0 242*4882a593Smuzhiyun #define ES7243E_I2C_CHIP_ADDRESS_0 I2C_CHIP_ADDR_10H 243*4882a593Smuzhiyun #endif 244*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 2 245*4882a593Smuzhiyun #define ES7243E_I2C_CHIP_ADDRESS_1 I2C_CHIP_ADDR_13H 246*4882a593Smuzhiyun #endif 247*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 4 248*4882a593Smuzhiyun #define ES7243E_I2C_CHIP_ADDRESS_2 I2C_CHIP_ADDR_12H 249*4882a593Smuzhiyun #endif 250*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 6 251*4882a593Smuzhiyun #define ES7243E_I2C_CHIP_ADDRESS_3 I2C_CHIP_ADDR_11H 252*4882a593Smuzhiyun #endif 253*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 8 254*4882a593Smuzhiyun #define ES7243E_I2C_CHIP_ADDRESS_4 I2C_CHIP_ADDR_14H 255*4882a593Smuzhiyun #endif 256*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 10 257*4882a593Smuzhiyun #define ES7243E_I2C_CHIP_ADDRESS_5 I2C_CHIP_ADDR_15H 258*4882a593Smuzhiyun #endif 259*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 12 260*4882a593Smuzhiyun #define ES7243E_I2C_CHIP_ADDRESS_6 I2C_CHIP_ADDR_16H 261*4882a593Smuzhiyun #endif 262*4882a593Smuzhiyun #if ES7243E_CHANNELS_MAX > 14 263*4882a593Smuzhiyun #define ES7243E_I2C_CHIP_ADDRESS_7 I2C_CHIP_ADDR_17H 264*4882a593Smuzhiyun #endif 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun #define ES7243E_I2C_BUS_NUM 1 267*4882a593Smuzhiyun #define ES7243E_CODEC_RW_TEST_EN 0 268*4882a593Smuzhiyun #define ES7243E_IDLE_RESET_EN 1 //reset ES7243 when in idle time 269*4882a593Smuzhiyun #define ES7243E_MATCH_DTS_EN 1 //ES7243 match method select: 0: i2c_detect, 1:of_device_id 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun #define VDDA_1V8 0 272*4882a593Smuzhiyun #define VDDA_3V3 1 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun #define VDDA_VOLTAGE VDDA_3V3 275