1 /* 2 * ALSA SoC ES7243E adc driver 3 * 4 * Author: David Yang, <yangxiaohua@everest-semi.com> 5 * or 6 * <info@everest-semi.com> 7 * Copyright: (C) 2019 Everest Semiconductor Co Ltd., 8 * 9 * Based on sound/soc/codecs/es7243.c by DavidYang 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License version 2 as 13 * published by the Free Software Foundation. 14 * 15 * Notes: 16 * this is an important file, you need to check it before you use ES7243E. 17 * es7243e_usr_cfg.h is a user interface which is convenient for digital 18 * format, clock ratio, etc. 19 * 20 */ 21 22 #define ENABLE 1 23 #define DISABLE 0 24 /* 25 * Here is the definition of ES7243E ADC Digital Format 26 * Users must select correct digital format for their systerm. 27 * 28 * ES7243E_WORK_MODE is used to select digital format, and user must update it for their system 29 * In ES7243E codec driver (es7243e.c), ES7243E_WORK_MODE will be used for digital format setting. 30 * 31 * In normal mode, ES7243E supports four digital formats including I2S, LJ, DSP-A and DSP-B, with 32 * resolution from 16bits to 32bits. 33 * In TDM mode, ES7243E only supports DSP-A TDM, doesn't support DSP-B TDM. 34 * In NFS mode, ES7243E only supports NFS I2S mode, doesn't support DSP or LJ NFS mode. 35 */ 36 #define ES7243E_NORMAL_I2S 0 37 #define ES7243E_NORMAL_LJ 1 38 #define ES7243E_NORMAL_DSPA 2 39 #define ES7243E_NORMAL_DSPB 3 40 #define ES7243E_TDM_A 4 41 #define ES7243E_NFS_I2S 5 42 #define ES7243E_NFS_DSPA 6 43 #define ES7243E_WORK_MODE ES7243E_NORMAL_I2S 44 /* 45 * Here is the definition of the common MCLK/LRCK rato. 46 * ES7243E will have different register configuration for each MCLK/LRCK ratio. 47 * Please check the MCLK/LRCK ratio in your system before you update ES7243E_MCLK_LRCK_RATIO. 48 * ES7243E codec driver will configure the clock registers according to the value of ES7243E_MCLK_LRCK_RATO. 49 */ 50 #define RATIO_3072 3072 51 #define RATIO_2048 2048 52 #define RATIO_1536 1536 53 #define RATIO_1024 1024 54 #define RATIO_768 768 55 #define RATIO_512 512 56 #define RATIO_384 384 57 #define RATIO_256 256 58 #define RATIO_192 192 59 #define RATIO_128 128 60 #define RATIO_64 64 61 #define ES7243E_MCLK_LRCK_RATIO RATIO_64 62 /* 63 * To select the total analog input channel for microphone array 64 */ 65 #define AIN_2_CH 2 66 #define AIN_4_CH 4 67 #define AIN_6_CH 6 68 #define AIN_8_CH 8 69 #define AIN_10_CH 10 70 #define AIN_12_CH 12 71 #define AIN_14_CH 14 72 #define AIN_16_CH 16 73 #define ES7243E_CHANNELS_MAX AIN_6_CH 74 /* 75 * to select the clock soure for internal MCLK clock 76 */ 77 #define FROM_MCLK_PIN 0 78 #define FROM_INTERNAL_BCLK 1 79 #define ES7243E_MCLK_SOURCE FROM_INTERNAL_BCLK 80 /* 81 * to select the data length or resolution 82 */ 83 #define DATA_16BITS 0 84 #define DATA_24BITS 1 85 #define DATA_32BITS 2 86 #define ES7243E_DATA_LENGTH DATA_16BITS 87 /* 88 * to select the pdm digital microphone interface 89 */ 90 #define DMIC_INTERFACE_ON true 91 #define DMIC_INTERFACE_OFF false 92 #define DMIC_INTERFACE DMIC_INTERFACE_OFF 93 /* 94 * to select bclk inverted or not 95 */ 96 #define BCLK_NORMAL false 97 #define BCLK_INVERTED true 98 #define BCLK_INVERTED_OR_NOT BCLK_NORMAL 99 /* 100 * to select mclk inverted or not 101 */ 102 #define MCLK_NORMAL false 103 #define MCLK_INVERTED true 104 #define MCLK_INVERTED_OR_NOT MCLK_NORMAL 105 /* 106 * to select PGA gain for different analog input channel 107 * user must allocate the PGA gain for each analog input channel 108 * ES7243E_MIC_ARRAY_AIN1_PGA to ES7243E_MIC_ARRAY_AIN16_PGA is used for PGA gain 109 */ 110 #define PGA_0DB 0 111 #define PGA_3DB 1 112 #define PGA_6DB 2 113 #define PGA_9DB 3 114 #define PGA_12DB 4 115 #define PGA_15DB 5 116 #define PGA_18DB 6 117 #define PGA_21DB 7 118 #define PGA_24DB 8 119 #define PGA_27DB 9 120 #define PGA_30DB 10 121 #define PGA_33DB 11 122 #define PGA_34DB 12 123 #define PGA_36DB 13 124 #define PGA_37DB 14 125 126 #if ES7243E_CHANNELS_MAX > 0 127 #define ES7243E_MIC_ARRAY_AIN1_PGA PGA_27DB 128 #define ES7243E_MIC_ARRAY_AIN2_PGA PGA_27DB 129 #endif 130 131 #if ES7243E_CHANNELS_MAX > 2 132 #define ES7243E_MIC_ARRAY_AIN3_PGA PGA_33DB 133 #define ES7243E_MIC_ARRAY_AIN4_PGA PGA_33DB 134 #endif 135 136 #if ES7243E_CHANNELS_MAX > 4 137 #define ES7243E_MIC_ARRAY_AIN5_PGA PGA_33DB 138 #define ES7243E_MIC_ARRAY_AIN6_PGA PGA_33DB 139 #endif 140 141 #if ES7243E_CHANNELS_MAX > 6 142 #define ES7243E_MIC_ARRAY_AIN7_PGA PGA_0DB 143 #define ES7243E_MIC_ARRAY_AIN8_PGA PGA_0DB 144 #endif 145 146 #if ES7243E_CHANNELS_MAX > 8 147 #define ES7243E_MIC_ARRAY_AIN9_PGA PGA_33DB 148 #define ES7243E_MIC_ARRAY_AIN10_PGA PGA_33DB 149 #endif 150 151 #if ES7243E_CHANNELS_MAX > 10 152 #define ES7243E_MIC_ARRAY_AIN11_PGA PGA_33DB 153 #define ES7243E_MIC_ARRAY_AIN12_PGA PGA_33DB 154 #endif 155 156 #if ES7243E_CHANNELS_MAX > 12 157 #define ES7243E_MIC_ARRAY_AIN13_PGA PGA_33DB 158 #define ES7243E_MIC_ARRAY_AIN14_PGA PGA_33DB 159 #endif 160 161 #if ES7243E_CHANNELS_MAX > 14 162 #define ES7243E_MIC_ARRAY_AIN15_PGA PGA_33DB 163 #define ES7243E_MIC_ARRAY_AIN16_PGA PGA_33DB 164 #endif 165 166 /* 167 * here is the definition of digital volume. 168 * the digital volume is 0dB by default. User can update it 169 * ES7243E_DIGITAL_VOLUME_1 to ES7243E_DIGITAL_VOLUME_16 is used for digital volume 170 * digital volume is 0db default. 171 */ 172 173 #if ES7243E_CHANNELS_MAX > 0 174 #define DIG_VOL_1 0 // DB 175 #define ES7243E_DIGITAL_VOLUME_1 0xbf + (DIG_VOL_1 * 2) 176 #define DIG_VOL_2 0 // DB 177 #define ES7243E_DIGITAL_VOLUME_2 0xbf + (DIG_VOL_2 * 2) 178 #endif 179 180 #if ES7243E_CHANNELS_MAX > 2 181 #define DIG_VOL_3 0 // DB 182 #define ES7243E_DIGITAL_VOLUME_3 0xbf + (DIG_VOL_3 * 2) 183 #define DIG_VOL_4 0 // DB 184 #define ES7243E_DIGITAL_VOLUME_4 0xbf + (DIG_VOL_4 * 2) 185 #endif 186 187 #if ES7243E_CHANNELS_MAX > 4 188 #define DIG_VOL_5 0 // DB 189 #define ES7243E_DIGITAL_VOLUME_5 0xbf + (DIG_VOL_5 * 2) 190 #define DIG_VOL_6 0 // DB 191 #define ES7243E_DIGITAL_VOLUME_6 0xbf + (DIG_VOL_6 * 2) 192 #endif 193 194 #if ES7243E_CHANNELS_MAX > 6 195 #define DIG_VOL_7 0 // DB 196 #define ES7243E_DIGITAL_VOLUME_7 0xbf + (DIG_VOL_7 * 2) 197 #define DIG_VOL_8 0 // DB 198 #define ES7243E_DIGITAL_VOLUME_8 0xbf + (DIG_VOL_8 * 2) 199 #endif 200 201 #if ES7243E_CHANNELS_MAX > 8 202 #define DIG_VOL_9 0 // DB 203 #define ES7243E_DIGITAL_VOLUME_9 0xbf + (DIG_VOL_9 * 2) 204 #define DIG_VOL_10 0 // DB 205 #define ES7243E_DIGITAL_VOLUME_10 0xbf + (DIG_VOL_10 * 2) 206 #endif 207 208 #if ES7243E_CHANNELS_MAX > 10 209 #define DIG_VOL_11 0 // DB 210 #define ES7243E_DIGITAL_VOLUME_11 0xbf + (DIG_VOL_11 * 2) 211 #define DIG_VOL_12 0 // DB 212 #define ES7243E_DIGITAL_VOLUME_12 0xbf + (DIG_VOL_12 * 2) 213 #endif 214 215 #if ES7243E_CHANNELS_MAX > 12 216 #define DIG_VOL_13 0 // DB 217 #define ES7243E_DIGITAL_VOLUME_13 0xbf + (DIG_VOL_13 * 2) 218 #define DIG_VOL_14 0 // DB 219 #define ES7243E_DIGITAL_VOLUME_14 0xbf + (DIG_VOL_14 * 2) 220 #endif 221 222 #if ES7243E_CHANNELS_MAX > 14 223 #define DIG_VOL_15 0 // DB 224 #define ES7243E_DIGITAL_VOLUME_15 0xbf + (DIG_VOL_15 * 2) 225 #define DIG_VOL_16 0 // DB 226 #define ES7243E_DIGITAL_VOLUME_16 0xbf + (DIG_VOL_16 * 2) 227 #endif 228 229 /* 230 * set the I2C chip address for each es7243e device in TDM linkloop 231 * user can update the chip address according their system circuit 232 */ 233 #define I2C_CHIP_ADDR_10H 0x10 // AD0 and AD1 pulled down, ASDOUT pulled down or float 234 #define I2C_CHIP_ADDR_11H 0x11 // AD0 pulled up, AD1 pulled down, ASDOUT pulled down or float 235 #define I2C_CHIP_ADDR_12H 0x12 // AD0 pulled down, AD1 pulled up, ASDOUT pulled down or float 236 #define I2C_CHIP_ADDR_13H 0x13 // AD0 and AD1 pulled up, ASDOUT pulled down or float 237 #define I2C_CHIP_ADDR_14H 0x14 // AD0 and AD1 pulled down, ASDOUT pulled up 238 #define I2C_CHIP_ADDR_15H 0x15 // AD0 pulled up, AD1 pulled down, ASDOUT pulled up 239 #define I2C_CHIP_ADDR_16H 0x16 // AD0 pulled down, AD1 pulled up, ASDOUT pulled up 240 #define I2C_CHIP_ADDR_17H 0x17 // AD0 and AD1 pulled up, ASDOUT pulled up 241 #if ES7243E_CHANNELS_MAX > 0 242 #define ES7243E_I2C_CHIP_ADDRESS_0 I2C_CHIP_ADDR_10H 243 #endif 244 #if ES7243E_CHANNELS_MAX > 2 245 #define ES7243E_I2C_CHIP_ADDRESS_1 I2C_CHIP_ADDR_13H 246 #endif 247 #if ES7243E_CHANNELS_MAX > 4 248 #define ES7243E_I2C_CHIP_ADDRESS_2 I2C_CHIP_ADDR_12H 249 #endif 250 #if ES7243E_CHANNELS_MAX > 6 251 #define ES7243E_I2C_CHIP_ADDRESS_3 I2C_CHIP_ADDR_11H 252 #endif 253 #if ES7243E_CHANNELS_MAX > 8 254 #define ES7243E_I2C_CHIP_ADDRESS_4 I2C_CHIP_ADDR_14H 255 #endif 256 #if ES7243E_CHANNELS_MAX > 10 257 #define ES7243E_I2C_CHIP_ADDRESS_5 I2C_CHIP_ADDR_15H 258 #endif 259 #if ES7243E_CHANNELS_MAX > 12 260 #define ES7243E_I2C_CHIP_ADDRESS_6 I2C_CHIP_ADDR_16H 261 #endif 262 #if ES7243E_CHANNELS_MAX > 14 263 #define ES7243E_I2C_CHIP_ADDRESS_7 I2C_CHIP_ADDR_17H 264 #endif 265 266 #define ES7243E_I2C_BUS_NUM 1 267 #define ES7243E_CODEC_RW_TEST_EN 0 268 #define ES7243E_IDLE_RESET_EN 1 //reset ES7243 when in idle time 269 #define ES7243E_MATCH_DTS_EN 1 //ES7243 match method select: 0: i2c_detect, 1:of_device_id 270 271 #define VDDA_1V8 0 272 #define VDDA_3V3 1 273 274 #define VDDA_VOLTAGE VDDA_3V3 275