1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * ALSA SoC ES7210 adc driver
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Author: David Yang, <yangxiaohua@everest-semi.com>
5*4882a593Smuzhiyun * Copyright: (C) 2018 Everest Semiconductor Co Ltd.,
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Based on sound/soc/codecs/es7243.c by David Yang
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify
10*4882a593Smuzhiyun * it under the terms of the GNU General Public License version 2 as
11*4882a593Smuzhiyun * published by the Free Software Foundation.
12*4882a593Smuzhiyun *
13*4882a593Smuzhiyun * Notes:
14*4882a593Smuzhiyun * ES7210 is a 4-ch ADC of Everest
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun */
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include <linux/module.h>
19*4882a593Smuzhiyun #include <linux/moduleparam.h>
20*4882a593Smuzhiyun #include <linux/init.h>
21*4882a593Smuzhiyun #include <linux/clk.h>
22*4882a593Smuzhiyun #include <linux/delay.h>
23*4882a593Smuzhiyun #include <linux/pm.h>
24*4882a593Smuzhiyun #include <linux/i2c.h>
25*4882a593Smuzhiyun #include <linux/slab.h>
26*4882a593Smuzhiyun #include <sound/core.h>
27*4882a593Smuzhiyun #include <sound/pcm.h>
28*4882a593Smuzhiyun #include <sound/pcm_params.h>
29*4882a593Smuzhiyun #include <sound/soc.h>
30*4882a593Smuzhiyun #include <sound/soc-dapm.h>
31*4882a593Smuzhiyun #include <sound/tlv.h>
32*4882a593Smuzhiyun #include <sound/initval.h>
33*4882a593Smuzhiyun #include <linux/regmap.h>
34*4882a593Smuzhiyun #include "es7210.h"
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun #define ENABLE 1
37*4882a593Smuzhiyun #define DISABLE 0
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define MIC_CHN_16 16
40*4882a593Smuzhiyun #define MIC_CHN_14 14
41*4882a593Smuzhiyun #define MIC_CHN_12 12
42*4882a593Smuzhiyun #define MIC_CHN_10 10
43*4882a593Smuzhiyun #define MIC_CHN_8 8
44*4882a593Smuzhiyun #define MIC_CHN_6 6
45*4882a593Smuzhiyun #define MIC_CHN_4 4
46*4882a593Smuzhiyun #define MIC_CHN_2 2
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun #define ES7210_TDM_ENABLE DISABLE
49*4882a593Smuzhiyun #define ES7210_CHANNELS_MAX MIC_CHN_4
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX == MIC_CHN_2
52*4882a593Smuzhiyun #define ADC_DEV_MAXNUM 1
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX == MIC_CHN_4
55*4882a593Smuzhiyun #define ADC_DEV_MAXNUM 1
56*4882a593Smuzhiyun #endif
57*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX == MIC_CHN_6
58*4882a593Smuzhiyun #define ADC_DEV_MAXNUM 2
59*4882a593Smuzhiyun #endif
60*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX == MIC_CHN_8
61*4882a593Smuzhiyun #define ADC_DEV_MAXNUM 2
62*4882a593Smuzhiyun #endif
63*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX == MIC_CHN_10
64*4882a593Smuzhiyun #define ADC_DEV_MAXNUM 3
65*4882a593Smuzhiyun #endif
66*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX == MIC_CHN_12
67*4882a593Smuzhiyun #define ADC_DEV_MAXNUM 3
68*4882a593Smuzhiyun #endif
69*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX == MIC_CHN_14
70*4882a593Smuzhiyun #define ADC_DEV_MAXNUM 4
71*4882a593Smuzhiyun #endif
72*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX == MIC_CHN_16
73*4882a593Smuzhiyun #define ADC_DEV_MAXNUM 4
74*4882a593Smuzhiyun #endif
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define ES7210_TDM_1LRCK_DSPA 0
77*4882a593Smuzhiyun #define ES7210_TDM_1LRCK_DSPB 1
78*4882a593Smuzhiyun #define ES7210_TDM_1LRCK_I2S 2
79*4882a593Smuzhiyun #define ES7210_TDM_1LRCK_LJ 3
80*4882a593Smuzhiyun #define ES7210_TDM_NLRCK_DSPA 4
81*4882a593Smuzhiyun #define ES7210_TDM_NLRCK_DSPB 5
82*4882a593Smuzhiyun #define ES7210_TDM_NLRCK_I2S 6
83*4882a593Smuzhiyun #define ES7210_TDM_NLRCK_LJ 7
84*4882a593Smuzhiyun #define ES7210_NORMAL_I2S 8
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun #define ES7210_WORK_MODE ES7210_NORMAL_I2S
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun #define ES7210_I2C_BUS_NUM 1
90*4882a593Smuzhiyun #define ES7210_CODEC_RW_TEST_EN 0
91*4882a593Smuzhiyun #define ES7210_IDLE_RESET_EN 1 //reset ES7210 when in idle time
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun #define ES7210_MIC_GAIN 0x18 // need check hw design and channel
94*4882a593Smuzhiyun #define ES7210_AEC_GAIN 0x13 // need check hw design and channel
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* to set internal mclk and adclrclk ratio */
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #define RATIO_768 0xC3
99*4882a593Smuzhiyun #define RATIO_256 0xC1
100*4882a593Smuzhiyun #define RATIO_128 0x01
101*4882a593Smuzhiyun #define RATIO_64 0x41 /* mclk from bclk pin */
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun #define ES7210_MCLK_LRCK_RATIO RATIO_256
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun static struct i2c_client *i2c_clt1[ADC_DEV_MAXNUM];
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun static struct es7210_priv *resume_es7210 = NULL;
108*4882a593Smuzhiyun /* codec private data */
109*4882a593Smuzhiyun struct es7210_priv {
110*4882a593Smuzhiyun struct regmap *regmap;
111*4882a593Smuzhiyun struct i2c_client *i2c_client;
112*4882a593Smuzhiyun unsigned int dmic_enable;
113*4882a593Smuzhiyun unsigned int sysclk;
114*4882a593Smuzhiyun struct clk *mclk;
115*4882a593Smuzhiyun struct snd_pcm_hw_constraint_list *sysclk_constraints;
116*4882a593Smuzhiyun unsigned int tdm_mode;
117*4882a593Smuzhiyun struct delayed_work pcm_pop_work;
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun static struct snd_soc_component *tron_codec1[ADC_DEV_MAXNUM];
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun static int es7210_init_reg = 0;
123*4882a593Smuzhiyun static int es7210_codec_num = 0;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun static const struct regmap_config es7210_regmap_config = {
126*4882a593Smuzhiyun .reg_bits = 8, //Number of bits in a register address
127*4882a593Smuzhiyun .val_bits = 8, //Number of bits in a register value
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun /*
130*4882a593Smuzhiyun * ES7210 register cache
131*4882a593Smuzhiyun */
132*4882a593Smuzhiyun static const u8 es7210_reg[] = {
133*4882a593Smuzhiyun 0x32, 0x40, 0x02, 0x04, 0x01, 0x00, 0x00, 0x20, /* 0 - 7 */
134*4882a593Smuzhiyun 0x10, 0x40, 0x40, 0x00, 0x00, 0x09, 0x00, 0x00, /* 8 - F */
135*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 10 - 17 */
136*4882a593Smuzhiyun 0xf7, 0xf7, 0x00, 0xbf, 0xbf, 0xbf, 0xbf, 0x00, /* 18 - 1f */
137*4882a593Smuzhiyun 0x26, 0x26, 0x06, 0x26, 0x00, 0x00, 0x00, 0x00, /* 20 - 27 */
138*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 28 - 2f */
139*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 - 37 */
140*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x72, 0x10, 0x00, /* 38 - 3f */
141*4882a593Smuzhiyun 0x80, 0x71, 0x71, 0x00, 0x00, 0x00, 0x00, 0x00, /* 40 - 47 */
142*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0xff, 0xff, /* 48 - 4c */
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun struct es7210_reg_config {
146*4882a593Smuzhiyun unsigned char reg_addr;
147*4882a593Smuzhiyun unsigned char reg_v;
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun static const struct es7210_reg_config es7210_tdm_reg_common_cfg1[] = {
150*4882a593Smuzhiyun { 0x00, 0xFF },
151*4882a593Smuzhiyun { 0x00, 0x32 },
152*4882a593Smuzhiyun { 0x09, 0x30 },
153*4882a593Smuzhiyun { 0x0A, 0x30 },
154*4882a593Smuzhiyun { 0x23, 0x2a },
155*4882a593Smuzhiyun { 0x22, 0x0a },
156*4882a593Smuzhiyun { 0x21, 0x2a },
157*4882a593Smuzhiyun { 0x20, 0x0a },
158*4882a593Smuzhiyun };
159*4882a593Smuzhiyun static const struct es7210_reg_config es7210_tdm_reg_fmt_cfg[] = {
160*4882a593Smuzhiyun { 0x11, 0x63 },
161*4882a593Smuzhiyun { 0x12, 0x01 },
162*4882a593Smuzhiyun };
163*4882a593Smuzhiyun static const struct es7210_reg_config es7210_tdm_reg_common_cfg2[] = {
164*4882a593Smuzhiyun { 0x40, 0xC3 },
165*4882a593Smuzhiyun { 0x41, 0x70 },
166*4882a593Smuzhiyun { 0x42, 0x70 },
167*4882a593Smuzhiyun { 0x43, 0x1E },
168*4882a593Smuzhiyun { 0x44, 0x1E },
169*4882a593Smuzhiyun { 0x45, 0x1E },
170*4882a593Smuzhiyun { 0x46, 0x1E },
171*4882a593Smuzhiyun { 0x47, 0x08 },
172*4882a593Smuzhiyun { 0x48, 0x08 },
173*4882a593Smuzhiyun { 0x49, 0x08 },
174*4882a593Smuzhiyun { 0x4A, 0x08 },
175*4882a593Smuzhiyun { 0x07, 0x20 },
176*4882a593Smuzhiyun };
177*4882a593Smuzhiyun static const struct es7210_reg_config es7210_tdm_reg_mclk_cfg[] = {
178*4882a593Smuzhiyun { 0x02, 0xC1 },
179*4882a593Smuzhiyun };
180*4882a593Smuzhiyun static const struct es7210_reg_config es7210_tdm_reg_common_cfg3[] = {
181*4882a593Smuzhiyun { 0x06, 0x00 },
182*4882a593Smuzhiyun { 0x4B, 0x0F },
183*4882a593Smuzhiyun { 0x4C, 0x0F },
184*4882a593Smuzhiyun { 0x00, 0x71 },
185*4882a593Smuzhiyun { 0x00, 0x41 },
186*4882a593Smuzhiyun };
es7210_read(u8 reg,u8 * rt_value,struct i2c_client * client)187*4882a593Smuzhiyun static int es7210_read(u8 reg, u8 *rt_value, struct i2c_client *client)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun int ret;
190*4882a593Smuzhiyun u8 read_cmd[3] = {0};
191*4882a593Smuzhiyun u8 cmd_len = 0;
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun read_cmd[0] = reg;
194*4882a593Smuzhiyun cmd_len = 1;
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun if (client->adapter == NULL)
197*4882a593Smuzhiyun pr_err("es7210_read client->adapter==NULL\n");
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun ret = i2c_master_send(client, read_cmd, cmd_len);
200*4882a593Smuzhiyun if (ret != cmd_len) {
201*4882a593Smuzhiyun pr_err("es7210_read error1\n");
202*4882a593Smuzhiyun return -1;
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun ret = i2c_master_recv(client, rt_value, 1);
206*4882a593Smuzhiyun if (ret != 1) {
207*4882a593Smuzhiyun pr_err("es7210_read error2, ret = %d.\n", ret);
208*4882a593Smuzhiyun return -1;
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun return 0;
212*4882a593Smuzhiyun }
es7210_write(u8 reg,unsigned char value,struct i2c_client * client)213*4882a593Smuzhiyun static int es7210_write(u8 reg, unsigned char value, struct i2c_client *client)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun int ret;
216*4882a593Smuzhiyun u8 write_cmd[2] = {0};
217*4882a593Smuzhiyun write_cmd[0] = reg;
218*4882a593Smuzhiyun write_cmd[1] = value;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun ret = i2c_master_send(client, write_cmd, 2);
221*4882a593Smuzhiyun if (ret != 2) {
222*4882a593Smuzhiyun pr_err("es7210_write error->[REG-0x%02x,val-0x%02x]\n", reg, value);
223*4882a593Smuzhiyun return -1;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun return 0;
226*4882a593Smuzhiyun }
es7210_update_bits(u8 reg,u8 mask,u8 value,struct i2c_client * client)227*4882a593Smuzhiyun static int es7210_update_bits(u8 reg, u8 mask, u8 value, struct i2c_client *client)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun u8 val_old = 0, val_new = 0;
230*4882a593Smuzhiyun
231*4882a593Smuzhiyun es7210_read(reg, &val_old, client);
232*4882a593Smuzhiyun val_new = (val_old & ~mask) | (value & mask);
233*4882a593Smuzhiyun if (val_new != val_old) {
234*4882a593Smuzhiyun es7210_write(reg, val_new, client);
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun return 0;
238*4882a593Smuzhiyun }
239*4882a593Smuzhiyun /*
240*4882a593Smuzhiyun static int es7210_multi_chips_read(u8 reg, unsigned char *rt_value)
241*4882a593Smuzhiyun {
242*4882a593Smuzhiyun u8 i;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun for(i=0; i< ADC_DEV_MAXNUM; i++){
245*4882a593Smuzhiyun es7210_read(reg, rt_value++, i2c_clt1[i]);
246*4882a593Smuzhiyun }
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun return 0;
249*4882a593Smuzhiyun }
250*4882a593Smuzhiyun */
es7210_multi_chips_write(u8 reg,unsigned char value)251*4882a593Smuzhiyun static int es7210_multi_chips_write(u8 reg, unsigned char value)
252*4882a593Smuzhiyun {
253*4882a593Smuzhiyun u8 i;
254*4882a593Smuzhiyun for (i = 0; i < ADC_DEV_MAXNUM; i++) {
255*4882a593Smuzhiyun es7210_write(reg, value, i2c_clt1[i]);
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun return 0;
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
es7210_multi_chips_update_bits(u8 reg,u8 mask,u8 value)261*4882a593Smuzhiyun static int es7210_multi_chips_update_bits(u8 reg, u8 mask, u8 value)
262*4882a593Smuzhiyun {
263*4882a593Smuzhiyun u8 i;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun for (i = 0; i < ADC_DEV_MAXNUM; i++) {
266*4882a593Smuzhiyun es7210_update_bits(reg, mask, value, i2c_clt1[i]);
267*4882a593Smuzhiyun }
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun return 0;
270*4882a593Smuzhiyun }
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun /*
273*4882a593Smuzhiyun * Note that this should be called from init rather than from hw_params.
274*4882a593Smuzhiyun */
es7210_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)275*4882a593Smuzhiyun static int es7210_set_dai_sysclk(struct snd_soc_dai *codec_dai,
276*4882a593Smuzhiyun int clk_id, unsigned int freq, int dir)
277*4882a593Smuzhiyun {
278*4882a593Smuzhiyun return 0;
279*4882a593Smuzhiyun }
280*4882a593Smuzhiyun
es7210_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)281*4882a593Smuzhiyun static int es7210_set_dai_fmt(struct snd_soc_dai *codec_dai,
282*4882a593Smuzhiyun unsigned int fmt)
283*4882a593Smuzhiyun {
284*4882a593Smuzhiyun return 0;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun /*
287*4882a593Smuzhiyun * to initialize es7210 for tdm mode
288*4882a593Smuzhiyun */
es7210_tdm_init_codec(u8 mode)289*4882a593Smuzhiyun static void es7210_tdm_init_codec(u8 mode)
290*4882a593Smuzhiyun {
291*4882a593Smuzhiyun int cnt, channel, i;
292*4882a593Smuzhiyun printk("begin->>>>>>>>>>%s!\n", __func__);
293*4882a593Smuzhiyun for (cnt = 0;
294*4882a593Smuzhiyun cnt < sizeof(es7210_tdm_reg_common_cfg1) /
295*4882a593Smuzhiyun sizeof(es7210_tdm_reg_common_cfg1[0]);
296*4882a593Smuzhiyun cnt++) {
297*4882a593Smuzhiyun es7210_multi_chips_write(
298*4882a593Smuzhiyun es7210_tdm_reg_common_cfg1[cnt].reg_addr,
299*4882a593Smuzhiyun es7210_tdm_reg_common_cfg1[cnt].reg_v);
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun switch (mode) {
302*4882a593Smuzhiyun case ES7210_TDM_1LRCK_DSPA:
303*4882a593Smuzhiyun /*
304*4882a593Smuzhiyun * Here to set TDM format for DSP-A mode
305*4882a593Smuzhiyun */
306*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
307*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG1_REG11,
308*4882a593Smuzhiyun 0x63, i2c_clt1[cnt]);
309*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG2_REG12,
310*4882a593Smuzhiyun 0x01, i2c_clt1[cnt]);
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun break;
313*4882a593Smuzhiyun case ES7210_TDM_1LRCK_DSPB:
314*4882a593Smuzhiyun /*
315*4882a593Smuzhiyun * Here to set TDM format for DSP-B mode
316*4882a593Smuzhiyun */
317*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
318*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG1_REG11,
319*4882a593Smuzhiyun 0x73, i2c_clt1[cnt]);
320*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG2_REG12,
321*4882a593Smuzhiyun 0x01, i2c_clt1[cnt]);
322*4882a593Smuzhiyun }
323*4882a593Smuzhiyun break;
324*4882a593Smuzhiyun case ES7210_TDM_1LRCK_I2S:
325*4882a593Smuzhiyun /*
326*4882a593Smuzhiyun * Here to set TDM format for I2S mode
327*4882a593Smuzhiyun */
328*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
329*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG1_REG11,
330*4882a593Smuzhiyun 0x60, i2c_clt1[cnt]);
331*4882a593Smuzhiyun }
332*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
333*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG2_REG12,
334*4882a593Smuzhiyun 0x02, i2c_clt1[cnt]);
335*4882a593Smuzhiyun }
336*4882a593Smuzhiyun break;
337*4882a593Smuzhiyun case ES7210_TDM_1LRCK_LJ:
338*4882a593Smuzhiyun /*
339*4882a593Smuzhiyun * Here to set TDM format for Left Justified mode
340*4882a593Smuzhiyun */
341*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
342*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG1_REG11,
343*4882a593Smuzhiyun 0x61, i2c_clt1[cnt]);
344*4882a593Smuzhiyun }
345*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
346*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG2_REG12,
347*4882a593Smuzhiyun 0x02, i2c_clt1[cnt]);
348*4882a593Smuzhiyun }
349*4882a593Smuzhiyun break;
350*4882a593Smuzhiyun case ES7210_TDM_NLRCK_DSPA:
351*4882a593Smuzhiyun /*
352*4882a593Smuzhiyun * set format, dsp-a with multiple LRCK tdm mode
353*4882a593Smuzhiyun */
354*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
355*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG1_REG11,
356*4882a593Smuzhiyun 0x63, i2c_clt1[cnt]);
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
359*4882a593Smuzhiyun if (cnt == 0) {
360*4882a593Smuzhiyun /*
361*4882a593Smuzhiyun * set tdm flag in the interface
362*4882a593Smuzhiyun * chip
363*4882a593Smuzhiyun */
364*4882a593Smuzhiyun es7210_write(
365*4882a593Smuzhiyun ES7210_SDP_CFG2_REG12, 0x07,
366*4882a593Smuzhiyun i2c_clt1[cnt]);
367*4882a593Smuzhiyun } else {
368*4882a593Smuzhiyun es7210_write(
369*4882a593Smuzhiyun ES7210_SDP_CFG2_REG12, 0x03,
370*4882a593Smuzhiyun i2c_clt1[cnt]);
371*4882a593Smuzhiyun }
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun break;
374*4882a593Smuzhiyun case ES7210_TDM_NLRCK_DSPB:
375*4882a593Smuzhiyun /*
376*4882a593Smuzhiyun * set format, dsp-b with multiple LRCK tdm mode
377*4882a593Smuzhiyun */
378*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
379*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG1_REG11,
380*4882a593Smuzhiyun 0x73, i2c_clt1[cnt]);
381*4882a593Smuzhiyun }
382*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
383*4882a593Smuzhiyun if (cnt == 0) {
384*4882a593Smuzhiyun /*
385*4882a593Smuzhiyun * set tdm flag in the interface
386*4882a593Smuzhiyun * chip
387*4882a593Smuzhiyun */
388*4882a593Smuzhiyun es7210_write(
389*4882a593Smuzhiyun ES7210_SDP_CFG2_REG12, 0x07,
390*4882a593Smuzhiyun i2c_clt1[cnt]);
391*4882a593Smuzhiyun } else {
392*4882a593Smuzhiyun es7210_write(
393*4882a593Smuzhiyun ES7210_SDP_CFG2_REG12, 0x03,
394*4882a593Smuzhiyun i2c_clt1[cnt]);
395*4882a593Smuzhiyun }
396*4882a593Smuzhiyun }
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun break;
399*4882a593Smuzhiyun case ES7210_TDM_NLRCK_I2S:
400*4882a593Smuzhiyun /*
401*4882a593Smuzhiyun * set format, I2S with multiple LRCK tdm mode
402*4882a593Smuzhiyun */
403*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
404*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG1_REG11,
405*4882a593Smuzhiyun 0x60, i2c_clt1[cnt]);
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
408*4882a593Smuzhiyun if (cnt == 0) {
409*4882a593Smuzhiyun /*
410*4882a593Smuzhiyun * set tdm flag in the interface
411*4882a593Smuzhiyun * chip
412*4882a593Smuzhiyun */
413*4882a593Smuzhiyun es7210_write(
414*4882a593Smuzhiyun ES7210_SDP_CFG2_REG12, 0x07,
415*4882a593Smuzhiyun i2c_clt1[cnt]);
416*4882a593Smuzhiyun } else {
417*4882a593Smuzhiyun es7210_write(
418*4882a593Smuzhiyun ES7210_SDP_CFG2_REG12, 0x03,
419*4882a593Smuzhiyun i2c_clt1[cnt]);
420*4882a593Smuzhiyun }
421*4882a593Smuzhiyun }
422*4882a593Smuzhiyun
423*4882a593Smuzhiyun break;
424*4882a593Smuzhiyun case ES7210_TDM_NLRCK_LJ:
425*4882a593Smuzhiyun /*
426*4882a593Smuzhiyun * set format, left justified with multiple LRCK
427*4882a593Smuzhiyun * tdm mode
428*4882a593Smuzhiyun */
429*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
430*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG1_REG11,
431*4882a593Smuzhiyun 0x61, i2c_clt1[cnt]);
432*4882a593Smuzhiyun }
433*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
434*4882a593Smuzhiyun if (cnt == 0) {
435*4882a593Smuzhiyun /*
436*4882a593Smuzhiyun * set tdm flag in the interface
437*4882a593Smuzhiyun * chip
438*4882a593Smuzhiyun */
439*4882a593Smuzhiyun es7210_write(
440*4882a593Smuzhiyun ES7210_SDP_CFG2_REG12, 0x07,
441*4882a593Smuzhiyun i2c_clt1[cnt]);
442*4882a593Smuzhiyun } else {
443*4882a593Smuzhiyun es7210_write(
444*4882a593Smuzhiyun ES7210_SDP_CFG2_REG12, 0x03,
445*4882a593Smuzhiyun i2c_clt1[cnt]);
446*4882a593Smuzhiyun }
447*4882a593Smuzhiyun }
448*4882a593Smuzhiyun
449*4882a593Smuzhiyun break;
450*4882a593Smuzhiyun case ES7210_NORMAL_I2S:
451*4882a593Smuzhiyun /*
452*4882a593Smuzhiyun * Here to set Normal i2s mode format for SD1/SD2 output
453*4882a593Smuzhiyun */
454*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
455*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG1_REG11,
456*4882a593Smuzhiyun 0x60, i2c_clt1[cnt]);
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
459*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG2_REG12,
460*4882a593Smuzhiyun 0x00, i2c_clt1[cnt]);
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun break;
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun default:
466*4882a593Smuzhiyun /*
467*4882a593Smuzhiyun * here to disable tdm and set i2s-16bit for
468*4882a593Smuzhiyun * normal mode
469*4882a593Smuzhiyun */
470*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
471*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG1_REG11,
472*4882a593Smuzhiyun 0x60, i2c_clt1[cnt]);
473*4882a593Smuzhiyun es7210_write(ES7210_SDP_CFG2_REG12,
474*4882a593Smuzhiyun 0x00, i2c_clt1[cnt]);
475*4882a593Smuzhiyun }
476*4882a593Smuzhiyun break;
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun for (cnt = 0;
479*4882a593Smuzhiyun cnt < sizeof(es7210_tdm_reg_common_cfg2) /
480*4882a593Smuzhiyun sizeof(es7210_tdm_reg_common_cfg2[0]);
481*4882a593Smuzhiyun cnt++) {
482*4882a593Smuzhiyun es7210_multi_chips_write(
483*4882a593Smuzhiyun es7210_tdm_reg_common_cfg2[cnt].reg_addr,
484*4882a593Smuzhiyun es7210_tdm_reg_common_cfg2[cnt].reg_v);
485*4882a593Smuzhiyun }
486*4882a593Smuzhiyun switch (mode) {
487*4882a593Smuzhiyun case ES7210_TDM_1LRCK_DSPA:
488*4882a593Smuzhiyun case ES7210_TDM_1LRCK_DSPB:
489*4882a593Smuzhiyun case ES7210_TDM_1LRCK_I2S:
490*4882a593Smuzhiyun case ES7210_TDM_1LRCK_LJ:
491*4882a593Smuzhiyun case ES7210_NORMAL_I2S:
492*4882a593Smuzhiyun /*
493*4882a593Smuzhiyun * to set internal mclk
494*4882a593Smuzhiyun * here, we assume that cpu/soc always provides
495*4882a593Smuzhiyun * 256FS i2s clock
496*4882a593Smuzhiyun * to es7210.
497*4882a593Smuzhiyun * dll bypassed, use clock doubler to get double
498*4882a593Smuzhiyun * frequency for
499*4882a593Smuzhiyun * internal modem which need
500*4882a593Smuzhiyun * 512FS clock. the clk divider ratio is 1.
501*4882a593Smuzhiyun * user must modify the setting of register0x02
502*4882a593Smuzhiyun * according to FS
503*4882a593Smuzhiyun * ratio provided by CPU/SOC.
504*4882a593Smuzhiyun */
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
507*4882a593Smuzhiyun es7210_write(ES7210_MCLK_CTL_REG02,
508*4882a593Smuzhiyun ES7210_MCLK_LRCK_RATIO, i2c_clt1[cnt]);
509*4882a593Smuzhiyun }
510*4882a593Smuzhiyun // es7210_multi_chips_write(ES7210_MCLK_CTL_REG02,
511*4882a593Smuzhiyun // 0xc1);
512*4882a593Smuzhiyun break;
513*4882a593Smuzhiyun case ES7210_TDM_NLRCK_DSPA:
514*4882a593Smuzhiyun case ES7210_TDM_NLRCK_DSPB:
515*4882a593Smuzhiyun case ES7210_TDM_NLRCK_I2S:
516*4882a593Smuzhiyun case ES7210_TDM_NLRCK_LJ:
517*4882a593Smuzhiyun /*
518*4882a593Smuzhiyun * Here to set TDM format for DSP-A with
519*4882a593Smuzhiyun * multiple LRCK TDM mode
520*4882a593Smuzhiyun */
521*4882a593Smuzhiyun channel = ES7210_CHANNELS_MAX;
522*4882a593Smuzhiyun /*
523*4882a593Smuzhiyun * Set the microphone numbers in array
524*4882a593Smuzhiyun */
525*4882a593Smuzhiyun switch (channel) {
526*4882a593Smuzhiyun case 2:
527*4882a593Smuzhiyun /* ES7210_CHANNELS_MAX=2 */
528*4882a593Smuzhiyun es7210_multi_chips_write(
529*4882a593Smuzhiyun ES7210_MODE_CFG_REG08, 0x10);
530*4882a593Smuzhiyun break;
531*4882a593Smuzhiyun case 4:
532*4882a593Smuzhiyun /* ES7210_CHANNELS_MAX=4 */
533*4882a593Smuzhiyun es7210_multi_chips_write(
534*4882a593Smuzhiyun ES7210_MODE_CFG_REG08, 0x20);
535*4882a593Smuzhiyun break;
536*4882a593Smuzhiyun case 6:
537*4882a593Smuzhiyun /* ES7210_CHANNELS_MAX=6 */
538*4882a593Smuzhiyun es7210_multi_chips_write(
539*4882a593Smuzhiyun ES7210_MODE_CFG_REG08, 0x30);
540*4882a593Smuzhiyun break;
541*4882a593Smuzhiyun case 8:
542*4882a593Smuzhiyun /* ES7210_CHANNELS_MAX=8 */
543*4882a593Smuzhiyun es7210_multi_chips_write(
544*4882a593Smuzhiyun ES7210_MODE_CFG_REG08, 0x40);
545*4882a593Smuzhiyun break;
546*4882a593Smuzhiyun case 10:
547*4882a593Smuzhiyun /* ES7210_CHANNELS_MAX=10 */
548*4882a593Smuzhiyun es7210_multi_chips_write(
549*4882a593Smuzhiyun ES7210_MODE_CFG_REG08, 0x50);
550*4882a593Smuzhiyun break;
551*4882a593Smuzhiyun case 12:
552*4882a593Smuzhiyun /* ES7210_CHANNELS_MAX=12 */
553*4882a593Smuzhiyun es7210_multi_chips_write(
554*4882a593Smuzhiyun ES7210_MODE_CFG_REG08, 0x60);
555*4882a593Smuzhiyun break;
556*4882a593Smuzhiyun case 14:
557*4882a593Smuzhiyun /* ES7210_CHANNELS_MAX=14 */
558*4882a593Smuzhiyun es7210_multi_chips_write(
559*4882a593Smuzhiyun ES7210_MODE_CFG_REG08, 0x70);
560*4882a593Smuzhiyun break;
561*4882a593Smuzhiyun case 16:
562*4882a593Smuzhiyun /* ES7210_CHANNELS_MAX=16 */
563*4882a593Smuzhiyun es7210_multi_chips_write(
564*4882a593Smuzhiyun ES7210_MODE_CFG_REG08, 0x80);
565*4882a593Smuzhiyun break;
566*4882a593Smuzhiyun default:
567*4882a593Smuzhiyun break;
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun /*
570*4882a593Smuzhiyun * to set internal mclk
571*4882a593Smuzhiyun * here, we assume that cpu/soc always provides
572*4882a593Smuzhiyun * 256FS i2s clock
573*4882a593Smuzhiyun * to es7210 and there is four
574*4882a593Smuzhiyun * es7210 devices in tdm link. so the
575*4882a593Smuzhiyun * internal FS in es7210
576*4882a593Smuzhiyun * is only FS/4;
577*4882a593Smuzhiyun * dll bypassed, clock doubler bypassed. the clk
578*4882a593Smuzhiyun * divider ratio is
579*4882a593Smuzhiyun * 2. so the clock of internal
580*4882a593Smuzhiyun * modem equals to (256FS / (FS/4) / 2) * FS
581*4882a593Smuzhiyun * = 512FS
582*4882a593Smuzhiyun * user must modify the setting of register0x02
583*4882a593Smuzhiyun * according to FS
584*4882a593Smuzhiyun * ratio provided by CPU/SOC.
585*4882a593Smuzhiyun */
586*4882a593Smuzhiyun
587*4882a593Smuzhiyun es7210_multi_chips_write(ES7210_MCLK_CTL_REG02,
588*4882a593Smuzhiyun ES7210_MCLK_LRCK_RATIO);// NFS MODE:RATIO_768 ,12.288M/48K(16K 6 CH),12.288M/64K(16K 8 CH)
589*4882a593Smuzhiyun break;
590*4882a593Smuzhiyun default:
591*4882a593Smuzhiyun /*
592*4882a593Smuzhiyun * to set internal mclk for normal mode
593*4882a593Smuzhiyun * here, we assume that cpu/soc always provides
594*4882a593Smuzhiyun * 256FS i2s clock
595*4882a593Smuzhiyun * to es7210.
596*4882a593Smuzhiyun * dll bypassed, use clock doubler to get double
597*4882a593Smuzhiyun * frequency for
598*4882a593Smuzhiyun * internal modem which need
599*4882a593Smuzhiyun * 512FS clock. the clk divider ratio is 1.
600*4882a593Smuzhiyun * user must modify the setting of register0x02
601*4882a593Smuzhiyun * according to FS
602*4882a593Smuzhiyun * ratio provided by CPU/SOC.
603*4882a593Smuzhiyun */
604*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
605*4882a593Smuzhiyun es7210_write(ES7210_MCLK_CTL_REG02,
606*4882a593Smuzhiyun ES7210_MCLK_LRCK_RATIO, i2c_clt1[cnt]);
607*4882a593Smuzhiyun }
608*4882a593Smuzhiyun
609*4882a593Smuzhiyun break;
610*4882a593Smuzhiyun }
611*4882a593Smuzhiyun for (cnt = 0;
612*4882a593Smuzhiyun cnt < sizeof(es7210_tdm_reg_common_cfg3) /
613*4882a593Smuzhiyun sizeof(es7210_tdm_reg_common_cfg3[0]);
614*4882a593Smuzhiyun cnt++) {
615*4882a593Smuzhiyun es7210_multi_chips_write(
616*4882a593Smuzhiyun es7210_tdm_reg_common_cfg3[cnt].reg_addr,
617*4882a593Smuzhiyun es7210_tdm_reg_common_cfg3[cnt].reg_v);
618*4882a593Smuzhiyun }
619*4882a593Smuzhiyun /*
620*4882a593Smuzhiyun * Mute All ADC
621*4882a593Smuzhiyun */
622*4882a593Smuzhiyun printk("enter es7210_multi_chips_update_bits %s\n",
623*4882a593Smuzhiyun __func__);
624*4882a593Smuzhiyun for (cnt = 0; cnt < ADC_DEV_MAXNUM; cnt++) {
625*4882a593Smuzhiyun es7210_write(ES7210_ADC34_MUTE_REG14, 0x03,
626*4882a593Smuzhiyun i2c_clt1[cnt]);
627*4882a593Smuzhiyun es7210_write(ES7210_ADC12_MUTE_REG15, 0x03,
628*4882a593Smuzhiyun i2c_clt1[cnt]);
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun for (i = 0; i < ADC_DEV_MAXNUM; i++) {
631*4882a593Smuzhiyun if (i == 0) {
632*4882a593Smuzhiyun /* set first es7210 PGA GAIN */
633*4882a593Smuzhiyun es7210_write(ES7210_MIC1_GAIN_REG43, ES7210_MIC_GAIN,
634*4882a593Smuzhiyun i2c_clt1[i]);
635*4882a593Smuzhiyun es7210_write(ES7210_MIC2_GAIN_REG44, ES7210_MIC_GAIN,
636*4882a593Smuzhiyun i2c_clt1[i]);
637*4882a593Smuzhiyun es7210_write(ES7210_MIC3_GAIN_REG45, ES7210_MIC_GAIN,
638*4882a593Smuzhiyun i2c_clt1[i]);
639*4882a593Smuzhiyun es7210_write(ES7210_MIC4_GAIN_REG46, ES7210_MIC_GAIN,
640*4882a593Smuzhiyun i2c_clt1[i]);
641*4882a593Smuzhiyun }
642*4882a593Smuzhiyun if (i == 1) {
643*4882a593Smuzhiyun /* set second es7210 PGA GAIN */
644*4882a593Smuzhiyun es7210_write(ES7210_MIC1_GAIN_REG43, ES7210_AEC_GAIN,
645*4882a593Smuzhiyun i2c_clt1[i]);
646*4882a593Smuzhiyun es7210_write(ES7210_MIC2_GAIN_REG44, ES7210_AEC_GAIN,
647*4882a593Smuzhiyun i2c_clt1[i]);
648*4882a593Smuzhiyun es7210_write(ES7210_MIC3_GAIN_REG45, ES7210_AEC_GAIN,
649*4882a593Smuzhiyun i2c_clt1[i]);
650*4882a593Smuzhiyun es7210_write(ES7210_MIC4_GAIN_REG46, ES7210_AEC_GAIN,
651*4882a593Smuzhiyun i2c_clt1[i]);
652*4882a593Smuzhiyun }
653*4882a593Smuzhiyun if (i == 2) {
654*4882a593Smuzhiyun /* set third es7210 PGA GAIN */
655*4882a593Smuzhiyun es7210_write(ES7210_MIC1_GAIN_REG43, ES7210_AEC_GAIN,
656*4882a593Smuzhiyun i2c_clt1[i]);
657*4882a593Smuzhiyun es7210_write(ES7210_MIC2_GAIN_REG44, ES7210_AEC_GAIN,
658*4882a593Smuzhiyun i2c_clt1[i]);
659*4882a593Smuzhiyun es7210_write(ES7210_MIC3_GAIN_REG45, ES7210_AEC_GAIN,
660*4882a593Smuzhiyun i2c_clt1[i]);
661*4882a593Smuzhiyun es7210_write(ES7210_MIC4_GAIN_REG46, ES7210_AEC_GAIN,
662*4882a593Smuzhiyun i2c_clt1[i]);
663*4882a593Smuzhiyun }
664*4882a593Smuzhiyun
665*4882a593Smuzhiyun if (i == 3) {
666*4882a593Smuzhiyun /* set third es7210 PGA GAIN */
667*4882a593Smuzhiyun es7210_write(ES7210_MIC1_GAIN_REG43, ES7210_AEC_GAIN,
668*4882a593Smuzhiyun i2c_clt1[i]);
669*4882a593Smuzhiyun es7210_write(ES7210_MIC2_GAIN_REG44, ES7210_AEC_GAIN,
670*4882a593Smuzhiyun i2c_clt1[i]);
671*4882a593Smuzhiyun es7210_write(ES7210_MIC3_GAIN_REG45, ES7210_AEC_GAIN,
672*4882a593Smuzhiyun i2c_clt1[i]);
673*4882a593Smuzhiyun es7210_write(ES7210_MIC4_GAIN_REG46, ES7210_AEC_GAIN,
674*4882a593Smuzhiyun i2c_clt1[i]);
675*4882a593Smuzhiyun }
676*4882a593Smuzhiyun }
677*4882a593Smuzhiyun printk("exit->>>>>>>>>>%s!\n", __func__);
678*4882a593Smuzhiyun }
es7210_unmute(void)679*4882a593Smuzhiyun static void es7210_unmute(void)
680*4882a593Smuzhiyun {
681*4882a593Smuzhiyun printk("enter into %s\n", __func__);
682*4882a593Smuzhiyun es7210_multi_chips_update_bits(ES7210_ADC34_MUTE_REG14, 0x03, 0x00);
683*4882a593Smuzhiyun es7210_multi_chips_update_bits(ES7210_ADC12_MUTE_REG15, 0x03, 0x00);
684*4882a593Smuzhiyun }
685*4882a593Smuzhiyun
pcm_pop_work_events(struct work_struct * work)686*4882a593Smuzhiyun static void pcm_pop_work_events(struct work_struct *work)
687*4882a593Smuzhiyun {
688*4882a593Smuzhiyun printk("enter into %s\n", __func__);
689*4882a593Smuzhiyun es7210_unmute();
690*4882a593Smuzhiyun es7210_init_reg = 1;
691*4882a593Smuzhiyun }
es7210_mute(struct snd_soc_dai * dai,int mute,int stream)692*4882a593Smuzhiyun static int es7210_mute(struct snd_soc_dai *dai, int mute, int stream)
693*4882a593Smuzhiyun {
694*4882a593Smuzhiyun printk("enter into %s, mute = %d\n", __func__, mute);
695*4882a593Smuzhiyun if (stream == SNDRV_PCM_STREAM_PLAYBACK)
696*4882a593Smuzhiyun return 0;
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun if (mute) {
699*4882a593Smuzhiyun es7210_multi_chips_update_bits(ES7210_ADC34_MUTE_REG14, 0x03, 0x03);
700*4882a593Smuzhiyun es7210_multi_chips_update_bits(ES7210_ADC12_MUTE_REG15, 0x03, 0x03);
701*4882a593Smuzhiyun } else {
702*4882a593Smuzhiyun es7210_multi_chips_update_bits(ES7210_ADC34_MUTE_REG14, 0x03, 0x00);
703*4882a593Smuzhiyun es7210_multi_chips_update_bits(ES7210_ADC12_MUTE_REG15, 0x03, 0x00);
704*4882a593Smuzhiyun }
705*4882a593Smuzhiyun return 0;
706*4882a593Smuzhiyun }
707*4882a593Smuzhiyun
es7210_pcm_startup(struct snd_pcm_substream * substream,struct snd_soc_dai * dai)708*4882a593Smuzhiyun static int es7210_pcm_startup(struct snd_pcm_substream *substream,
709*4882a593Smuzhiyun struct snd_soc_dai *dai)
710*4882a593Smuzhiyun {
711*4882a593Smuzhiyun struct snd_soc_component *component = dai->component;
712*4882a593Smuzhiyun struct es7210_priv *es7210 = snd_soc_component_get_drvdata(component);
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun if (es7210_init_reg == 0) {
715*4882a593Smuzhiyun schedule_delayed_work(&es7210->pcm_pop_work, msecs_to_jiffies(100));
716*4882a593Smuzhiyun }
717*4882a593Smuzhiyun return 0;
718*4882a593Smuzhiyun }
es7210_pcm_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)719*4882a593Smuzhiyun static int es7210_pcm_hw_params(struct snd_pcm_substream *substream,
720*4882a593Smuzhiyun struct snd_pcm_hw_params *params,
721*4882a593Smuzhiyun struct snd_soc_dai *dai)
722*4882a593Smuzhiyun {
723*4882a593Smuzhiyun int i;
724*4882a593Smuzhiyun es7210_multi_chips_update_bits(ES7210_RESET_CTL_REG00, 0x30, 0x30);
725*4882a593Smuzhiyun for (i = 0; i < ADC_DEV_MAXNUM; i++) {
726*4882a593Smuzhiyun /* set es7210 bit size */
727*4882a593Smuzhiyun switch (params_format(params)) {
728*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S16_LE:
729*4882a593Smuzhiyun es7210_update_bits(0x11, 0xE0, 0x60,
730*4882a593Smuzhiyun i2c_clt1[i]);
731*4882a593Smuzhiyun break;
732*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S20_3LE:
733*4882a593Smuzhiyun es7210_update_bits(0x11, 0xE0, 0x20,
734*4882a593Smuzhiyun i2c_clt1[i]);
735*4882a593Smuzhiyun break;
736*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S24_3LE:
737*4882a593Smuzhiyun es7210_update_bits(0x11, 0xE0, 0x00,
738*4882a593Smuzhiyun i2c_clt1[i]);
739*4882a593Smuzhiyun break;
740*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S24_LE:
741*4882a593Smuzhiyun case SNDRV_PCM_FORMAT_S32_LE:
742*4882a593Smuzhiyun es7210_update_bits(0x11, 0xE0, 0x80,
743*4882a593Smuzhiyun i2c_clt1[i]);
744*4882a593Smuzhiyun break;
745*4882a593Smuzhiyun }
746*4882a593Smuzhiyun }
747*4882a593Smuzhiyun es7210_multi_chips_update_bits(ES7210_RESET_CTL_REG00, 0x30, 0x00);
748*4882a593Smuzhiyun switch (params_rate(params)) {
749*4882a593Smuzhiyun case 16000:
750*4882a593Smuzhiyun break;
751*4882a593Smuzhiyun case 32000:
752*4882a593Smuzhiyun break;
753*4882a593Smuzhiyun case 48000:
754*4882a593Smuzhiyun break;
755*4882a593Smuzhiyun case 64000:
756*4882a593Smuzhiyun break;
757*4882a593Smuzhiyun default:
758*4882a593Smuzhiyun break;
759*4882a593Smuzhiyun }
760*4882a593Smuzhiyun return 0;
761*4882a593Smuzhiyun }
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun #define es7210_RATES SNDRV_PCM_RATE_8000_96000
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun #define es7210_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE |\
766*4882a593Smuzhiyun SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun static struct snd_soc_dai_ops es7210_ops = {
769*4882a593Smuzhiyun .startup = es7210_pcm_startup,
770*4882a593Smuzhiyun .hw_params = es7210_pcm_hw_params,
771*4882a593Smuzhiyun .set_fmt = es7210_set_dai_fmt,
772*4882a593Smuzhiyun .set_sysclk = es7210_set_dai_sysclk,
773*4882a593Smuzhiyun .mute_stream = es7210_mute,
774*4882a593Smuzhiyun };
775*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 0
776*4882a593Smuzhiyun static struct snd_soc_dai_driver es7210_dai0 = {
777*4882a593Smuzhiyun .name = "ES7210 4CH ADC 0",
778*4882a593Smuzhiyun .capture = {
779*4882a593Smuzhiyun .stream_name = "Capture",
780*4882a593Smuzhiyun .channels_min = 1,
781*4882a593Smuzhiyun .channels_max = 8,
782*4882a593Smuzhiyun .rates = es7210_RATES,
783*4882a593Smuzhiyun .formats = es7210_FORMATS,
784*4882a593Smuzhiyun },
785*4882a593Smuzhiyun .ops = &es7210_ops,
786*4882a593Smuzhiyun .symmetric_rates = 1,
787*4882a593Smuzhiyun };
788*4882a593Smuzhiyun #endif
789*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 4
790*4882a593Smuzhiyun static struct snd_soc_dai_driver es7210_dai1 = {
791*4882a593Smuzhiyun .name = "ES7210 4CH ADC 1",
792*4882a593Smuzhiyun .capture = {
793*4882a593Smuzhiyun .stream_name = "Capture",
794*4882a593Smuzhiyun .channels_min = 1,
795*4882a593Smuzhiyun .channels_max = 8,
796*4882a593Smuzhiyun .rates = es7210_RATES,
797*4882a593Smuzhiyun .formats = es7210_FORMATS,
798*4882a593Smuzhiyun },
799*4882a593Smuzhiyun .ops = &es7210_ops,
800*4882a593Smuzhiyun .symmetric_rates = 1,
801*4882a593Smuzhiyun };
802*4882a593Smuzhiyun #endif
803*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 8
804*4882a593Smuzhiyun static struct snd_soc_dai_driver es7210_dai2 = {
805*4882a593Smuzhiyun .name = "ES7210 4CH ADC 2",
806*4882a593Smuzhiyun .capture = {
807*4882a593Smuzhiyun .stream_name = "Capture",
808*4882a593Smuzhiyun .channels_min = 1,
809*4882a593Smuzhiyun .channels_max = 4,
810*4882a593Smuzhiyun .rates = es7210_RATES,
811*4882a593Smuzhiyun .formats = es7210_FORMATS,
812*4882a593Smuzhiyun },
813*4882a593Smuzhiyun .ops = &es7210_ops,
814*4882a593Smuzhiyun .symmetric_rates = 1,
815*4882a593Smuzhiyun };
816*4882a593Smuzhiyun #endif
817*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 12
818*4882a593Smuzhiyun static struct snd_soc_dai_driver es7210_dai3 = {
819*4882a593Smuzhiyun .name = "ES7210 4CH ADC 3",
820*4882a593Smuzhiyun .capture = {
821*4882a593Smuzhiyun .stream_name = "Capture",
822*4882a593Smuzhiyun .channels_min = 1,
823*4882a593Smuzhiyun .channels_max = 4,
824*4882a593Smuzhiyun .rates = es7210_RATES,
825*4882a593Smuzhiyun .formats = es7210_FORMATS,
826*4882a593Smuzhiyun },
827*4882a593Smuzhiyun .ops = &es7210_ops,
828*4882a593Smuzhiyun .symmetric_rates = 1,
829*4882a593Smuzhiyun };
830*4882a593Smuzhiyun #endif
831*4882a593Smuzhiyun static struct snd_soc_dai_driver *es7210_dai[] = {
832*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 0
833*4882a593Smuzhiyun &es7210_dai0,
834*4882a593Smuzhiyun #endif
835*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 4
836*4882a593Smuzhiyun &es7210_dai1,
837*4882a593Smuzhiyun #endif
838*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 8
839*4882a593Smuzhiyun &es7210_dai2,
840*4882a593Smuzhiyun #endif
841*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 12
842*4882a593Smuzhiyun &es7210_dai3,
843*4882a593Smuzhiyun #endif
844*4882a593Smuzhiyun };
845*4882a593Smuzhiyun
es7210_suspend(struct snd_soc_component * component)846*4882a593Smuzhiyun static int es7210_suspend(struct snd_soc_component *component)
847*4882a593Smuzhiyun {
848*4882a593Smuzhiyun int i = 0;
849*4882a593Smuzhiyun
850*4882a593Smuzhiyun printk("jsl es7210_suspend enter\n");
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun for (i = 0; i < ADC_DEV_MAXNUM; i++) {
853*4882a593Smuzhiyun if (i == 1) {
854*4882a593Smuzhiyun es7210_write(0x06, 0x05, i2c_clt1[i]);
855*4882a593Smuzhiyun es7210_write(0x05, 0x1B, i2c_clt1[i]);
856*4882a593Smuzhiyun es7210_write(0x06, 0x5C, i2c_clt1[i]);
857*4882a593Smuzhiyun es7210_write(0x07, 0x3F, i2c_clt1[i]);
858*4882a593Smuzhiyun es7210_write(0x08, 0x4B, i2c_clt1[i]);
859*4882a593Smuzhiyun es7210_write(0x09, 0x9F, i2c_clt1[i]);
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun } else {
862*4882a593Smuzhiyun /*turn off mic3/4 */
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun es7210_write(0x4C, 0xFF, i2c_clt1[i]);
865*4882a593Smuzhiyun es7210_write(0x0B, 0xD0, i2c_clt1[i]);
866*4882a593Smuzhiyun es7210_write(0x40, 0x80, i2c_clt1[i]);
867*4882a593Smuzhiyun es7210_write(0x01, 0x34, i2c_clt1[i]);
868*4882a593Smuzhiyun es7210_write(0x06, 0x07, i2c_clt1[i]);
869*4882a593Smuzhiyun /*turn off mic 1/2/3/4 */
870*4882a593Smuzhiyun /*
871*4882a593Smuzhiyun es7210_write(0x4B, 0xFF, i2c_clt1[i]);
872*4882a593Smuzhiyun es7210_write(0x4C, 0xFF, i2c_clt1[i]);
873*4882a593Smuzhiyun es7210_write(0x0B, 0xD0, i2c_clt1[i]);
874*4882a593Smuzhiyun es7210_write(0x40, 0x80, i2c_clt1[i]);
875*4882a593Smuzhiyun es7210_write(0x01, 0x7F, i2c_clt1[i]);
876*4882a593Smuzhiyun es7210_write(0x06, 0x07, i2c_clt1[i]);
877*4882a593Smuzhiyun */
878*4882a593Smuzhiyun }
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun
881*4882a593Smuzhiyun es7210_init_reg = 0;
882*4882a593Smuzhiyun return 0;
883*4882a593Smuzhiyun }
884*4882a593Smuzhiyun
es7210_resume(struct snd_soc_component * component)885*4882a593Smuzhiyun static int es7210_resume(struct snd_soc_component *component)
886*4882a593Smuzhiyun {
887*4882a593Smuzhiyun //snd_soc_cache_sync(codec);
888*4882a593Smuzhiyun es7210_tdm_init_codec(resume_es7210->tdm_mode);
889*4882a593Smuzhiyun return 0;
890*4882a593Smuzhiyun }
891*4882a593Smuzhiyun
es7210_probe(struct snd_soc_component * component)892*4882a593Smuzhiyun static int es7210_probe(struct snd_soc_component *component)
893*4882a593Smuzhiyun {
894*4882a593Smuzhiyun struct es7210_priv *es7210 = snd_soc_component_get_drvdata(component);
895*4882a593Smuzhiyun int ret = 0;
896*4882a593Smuzhiyun printk("begin->>>>>>>>>>%s!\n", __func__);
897*4882a593Smuzhiyun es7210->mclk = devm_clk_get(component->dev, "mclk");
898*4882a593Smuzhiyun if (PTR_ERR(es7210->mclk) == -EPROBE_DEFER)
899*4882a593Smuzhiyun return -EPROBE_DEFER;
900*4882a593Smuzhiyun
901*4882a593Smuzhiyun ret = clk_prepare_enable(es7210->mclk);
902*4882a593Smuzhiyun if (ret)
903*4882a593Smuzhiyun return ret;
904*4882a593Smuzhiyun resume_es7210 = es7210;
905*4882a593Smuzhiyun #if !ES7210_CODEC_RW_TEST_EN
906*4882a593Smuzhiyun //ret = snd_soc_codec_set_cache_io(codec, 8, 8, SND_SOC_I2C);//8,8
907*4882a593Smuzhiyun #else
908*4882a593Smuzhiyun component->control_data = devm_regmap_init_i2c(es7210->i2c_client, &es7210_regmap_config);
909*4882a593Smuzhiyun ret = PTR_ERR_OR_ZERO(component->control_data);
910*4882a593Smuzhiyun #endif
911*4882a593Smuzhiyun
912*4882a593Smuzhiyun if (ret < 0) {
913*4882a593Smuzhiyun dev_err(component->dev, "Failed to set cache I/O: %d\n", ret);
914*4882a593Smuzhiyun return ret;
915*4882a593Smuzhiyun }
916*4882a593Smuzhiyun printk("begin->>>>>>>>>>%s!\n", __func__);
917*4882a593Smuzhiyun
918*4882a593Smuzhiyun tron_codec1[es7210_codec_num++] = component;
919*4882a593Smuzhiyun INIT_DELAYED_WORK(&es7210->pcm_pop_work, pcm_pop_work_events);
920*4882a593Smuzhiyun es7210_tdm_init_codec(es7210->tdm_mode);
921*4882a593Smuzhiyun return 0;
922*4882a593Smuzhiyun }
923*4882a593Smuzhiyun
es7210_remove(struct snd_soc_component * component)924*4882a593Smuzhiyun static void es7210_remove(struct snd_soc_component *component)
925*4882a593Smuzhiyun {
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun }
928*4882a593Smuzhiyun
es7210_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)929*4882a593Smuzhiyun static int es7210_set_bias_level(struct snd_soc_component *component,
930*4882a593Smuzhiyun enum snd_soc_bias_level level)
931*4882a593Smuzhiyun {
932*4882a593Smuzhiyun struct es7210_priv *es7210 = snd_soc_component_get_drvdata(component);
933*4882a593Smuzhiyun int ret;
934*4882a593Smuzhiyun
935*4882a593Smuzhiyun switch (level) {
936*4882a593Smuzhiyun case SND_SOC_BIAS_ON:
937*4882a593Smuzhiyun break;
938*4882a593Smuzhiyun case SND_SOC_BIAS_PREPARE:
939*4882a593Smuzhiyun if (IS_ERR(es7210->mclk))
940*4882a593Smuzhiyun break;
941*4882a593Smuzhiyun if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_ON) {
942*4882a593Smuzhiyun clk_disable_unprepare(es7210->mclk);
943*4882a593Smuzhiyun } else {
944*4882a593Smuzhiyun ret = clk_prepare_enable(es7210->mclk);
945*4882a593Smuzhiyun if (ret)
946*4882a593Smuzhiyun return ret;
947*4882a593Smuzhiyun }
948*4882a593Smuzhiyun break;
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun case SND_SOC_BIAS_STANDBY:
951*4882a593Smuzhiyun break;
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun case SND_SOC_BIAS_OFF:
954*4882a593Smuzhiyun break;
955*4882a593Smuzhiyun }
956*4882a593Smuzhiyun return 0;
957*4882a593Smuzhiyun }
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun static const DECLARE_TLV_DB_SCALE(mic_boost_tlv, 0, 300, 0);
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 0
es7210_micboost1_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)962*4882a593Smuzhiyun static int es7210_micboost1_setting_set(struct snd_kcontrol *kcontrol,
963*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
964*4882a593Smuzhiyun {
965*4882a593Smuzhiyun es7210_update_bits(0x43, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[0]);
966*4882a593Smuzhiyun return 0;
967*4882a593Smuzhiyun }
968*4882a593Smuzhiyun
es7210_micboost1_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)969*4882a593Smuzhiyun static int es7210_micboost1_setting_get(struct snd_kcontrol *kcontrol,
970*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
971*4882a593Smuzhiyun {
972*4882a593Smuzhiyun u8 val = 0;
973*4882a593Smuzhiyun es7210_read(0x43, &val, i2c_clt1[0]);
974*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
975*4882a593Smuzhiyun return 0;
976*4882a593Smuzhiyun }
977*4882a593Smuzhiyun
es7210_micboost2_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)978*4882a593Smuzhiyun static int es7210_micboost2_setting_set(struct snd_kcontrol *kcontrol,
979*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
980*4882a593Smuzhiyun {
981*4882a593Smuzhiyun es7210_update_bits(0x44, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[0]);
982*4882a593Smuzhiyun return 0;
983*4882a593Smuzhiyun }
984*4882a593Smuzhiyun
es7210_micboost2_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)985*4882a593Smuzhiyun static int es7210_micboost2_setting_get(struct snd_kcontrol *kcontrol,
986*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
987*4882a593Smuzhiyun {
988*4882a593Smuzhiyun u8 val = 0;
989*4882a593Smuzhiyun es7210_read(0x44, &val, i2c_clt1[0]);
990*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
991*4882a593Smuzhiyun return 0;
992*4882a593Smuzhiyun }
993*4882a593Smuzhiyun
es7210_micboost3_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)994*4882a593Smuzhiyun static int es7210_micboost3_setting_set(struct snd_kcontrol *kcontrol,
995*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
996*4882a593Smuzhiyun {
997*4882a593Smuzhiyun es7210_update_bits(0x45, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[0]);
998*4882a593Smuzhiyun return 0;
999*4882a593Smuzhiyun }
1000*4882a593Smuzhiyun
es7210_micboost3_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1001*4882a593Smuzhiyun static int es7210_micboost3_setting_get(struct snd_kcontrol *kcontrol,
1002*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1003*4882a593Smuzhiyun {
1004*4882a593Smuzhiyun u8 val = 0;
1005*4882a593Smuzhiyun es7210_read(0x45, &val, i2c_clt1[0]);
1006*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1007*4882a593Smuzhiyun return 0;
1008*4882a593Smuzhiyun }
es7210_micboost4_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1009*4882a593Smuzhiyun static int es7210_micboost4_setting_set(struct snd_kcontrol *kcontrol,
1010*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1011*4882a593Smuzhiyun {
1012*4882a593Smuzhiyun es7210_update_bits(0x46, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[0]);
1013*4882a593Smuzhiyun return 0;
1014*4882a593Smuzhiyun }
1015*4882a593Smuzhiyun
es7210_micboost4_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1016*4882a593Smuzhiyun static int es7210_micboost4_setting_get(struct snd_kcontrol *kcontrol,
1017*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1018*4882a593Smuzhiyun {
1019*4882a593Smuzhiyun u8 val = 0;
1020*4882a593Smuzhiyun es7210_read(0x46, &val, i2c_clt1[0]);
1021*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1022*4882a593Smuzhiyun return 0;
1023*4882a593Smuzhiyun }
1024*4882a593Smuzhiyun
es7210_adc1_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1025*4882a593Smuzhiyun static int es7210_adc1_mute_set(struct snd_kcontrol *kcontrol,
1026*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1027*4882a593Smuzhiyun {
1028*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC12_MUTE_REG15, 0x01,
1029*4882a593Smuzhiyun ucontrol->value.integer.value[0]&0x01, i2c_clt1[0]);
1030*4882a593Smuzhiyun return 0;
1031*4882a593Smuzhiyun }
1032*4882a593Smuzhiyun
es7210_adc1_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1033*4882a593Smuzhiyun static int es7210_adc1_mute_get(struct snd_kcontrol *kcontrol,
1034*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1035*4882a593Smuzhiyun {
1036*4882a593Smuzhiyun u8 val = 0;
1037*4882a593Smuzhiyun es7210_read(ES7210_ADC12_MUTE_REG15, &val, i2c_clt1[0]);
1038*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val & 0x01;
1039*4882a593Smuzhiyun return 0;
1040*4882a593Smuzhiyun }
1041*4882a593Smuzhiyun
es7210_adc2_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1042*4882a593Smuzhiyun static int es7210_adc2_mute_set(struct snd_kcontrol *kcontrol,
1043*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1044*4882a593Smuzhiyun {
1045*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC12_MUTE_REG15, 0x02,
1046*4882a593Smuzhiyun (ucontrol->value.integer.value[0] & 0x01) << 1, i2c_clt1[0]);
1047*4882a593Smuzhiyun return 0;
1048*4882a593Smuzhiyun }
1049*4882a593Smuzhiyun
es7210_adc2_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1050*4882a593Smuzhiyun static int es7210_adc2_mute_get(struct snd_kcontrol *kcontrol,
1051*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1052*4882a593Smuzhiyun {
1053*4882a593Smuzhiyun u8 val = 0;
1054*4882a593Smuzhiyun es7210_read(ES7210_ADC12_MUTE_REG15, &val, i2c_clt1[0]);
1055*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (val & 0x02) >> 1;
1056*4882a593Smuzhiyun return 0;
1057*4882a593Smuzhiyun }
1058*4882a593Smuzhiyun
es7210_adc3_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1059*4882a593Smuzhiyun static int es7210_adc3_mute_set(struct snd_kcontrol *kcontrol,
1060*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1061*4882a593Smuzhiyun {
1062*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC34_MUTE_REG14, 0x01,
1063*4882a593Smuzhiyun ucontrol->value.integer.value[0]&0x01, i2c_clt1[0]);
1064*4882a593Smuzhiyun return 0;
1065*4882a593Smuzhiyun }
1066*4882a593Smuzhiyun
es7210_adc3_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1067*4882a593Smuzhiyun static int es7210_adc3_mute_get(struct snd_kcontrol *kcontrol,
1068*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1069*4882a593Smuzhiyun {
1070*4882a593Smuzhiyun u8 val = 0;
1071*4882a593Smuzhiyun es7210_read(ES7210_ADC34_MUTE_REG14, &val, i2c_clt1[0]);
1072*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val & 0x01;
1073*4882a593Smuzhiyun return 0;
1074*4882a593Smuzhiyun }
es7210_adc4_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1075*4882a593Smuzhiyun static int es7210_adc4_mute_set(struct snd_kcontrol *kcontrol,
1076*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1077*4882a593Smuzhiyun {
1078*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC34_MUTE_REG14, 0x02,
1079*4882a593Smuzhiyun (ucontrol->value.integer.value[0] & 0x01) << 1, i2c_clt1[0]);
1080*4882a593Smuzhiyun return 0;
1081*4882a593Smuzhiyun }
1082*4882a593Smuzhiyun
es7210_adc4_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1083*4882a593Smuzhiyun static int es7210_adc4_mute_get(struct snd_kcontrol *kcontrol,
1084*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1085*4882a593Smuzhiyun {
1086*4882a593Smuzhiyun u8 val = 0;
1087*4882a593Smuzhiyun es7210_read(ES7210_ADC34_MUTE_REG14, &val, i2c_clt1[0]);
1088*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (val & 0x02) >> 1;
1089*4882a593Smuzhiyun return 0;
1090*4882a593Smuzhiyun }
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun #endif
1093*4882a593Smuzhiyun
1094*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 4
es7210_micboost5_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1095*4882a593Smuzhiyun static int es7210_micboost5_setting_set(struct snd_kcontrol *kcontrol,
1096*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1097*4882a593Smuzhiyun {
1098*4882a593Smuzhiyun es7210_update_bits(0x43, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[1]);
1099*4882a593Smuzhiyun return 0;
1100*4882a593Smuzhiyun }
1101*4882a593Smuzhiyun
es7210_micboost5_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1102*4882a593Smuzhiyun static int es7210_micboost5_setting_get(struct snd_kcontrol *kcontrol,
1103*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1104*4882a593Smuzhiyun {
1105*4882a593Smuzhiyun u8 val;
1106*4882a593Smuzhiyun es7210_read(0x43, &val, i2c_clt1[1]);
1107*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1108*4882a593Smuzhiyun return 0;
1109*4882a593Smuzhiyun }
es7210_micboost6_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1110*4882a593Smuzhiyun static int es7210_micboost6_setting_set(struct snd_kcontrol *kcontrol,
1111*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1112*4882a593Smuzhiyun {
1113*4882a593Smuzhiyun es7210_update_bits(0x44, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[1]);
1114*4882a593Smuzhiyun return 0;
1115*4882a593Smuzhiyun }
1116*4882a593Smuzhiyun
es7210_micboost6_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1117*4882a593Smuzhiyun static int es7210_micboost6_setting_get(struct snd_kcontrol *kcontrol,
1118*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1119*4882a593Smuzhiyun {
1120*4882a593Smuzhiyun u8 val;
1121*4882a593Smuzhiyun es7210_read(0x44, &val, i2c_clt1[1]);
1122*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1123*4882a593Smuzhiyun return 0;
1124*4882a593Smuzhiyun }
es7210_micboost7_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1125*4882a593Smuzhiyun static int es7210_micboost7_setting_set(struct snd_kcontrol *kcontrol,
1126*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1127*4882a593Smuzhiyun {
1128*4882a593Smuzhiyun es7210_update_bits(0x45, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[1]);
1129*4882a593Smuzhiyun return 0;
1130*4882a593Smuzhiyun }
1131*4882a593Smuzhiyun
es7210_micboost7_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1132*4882a593Smuzhiyun static int es7210_micboost7_setting_get(struct snd_kcontrol *kcontrol,
1133*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1134*4882a593Smuzhiyun {
1135*4882a593Smuzhiyun u8 val;
1136*4882a593Smuzhiyun es7210_read(0x45, &val, i2c_clt1[1]);
1137*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1138*4882a593Smuzhiyun return 0;
1139*4882a593Smuzhiyun }
es7210_micboost8_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1140*4882a593Smuzhiyun static int es7210_micboost8_setting_set(struct snd_kcontrol *kcontrol,
1141*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1142*4882a593Smuzhiyun {
1143*4882a593Smuzhiyun es7210_update_bits(0x46, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[1]);
1144*4882a593Smuzhiyun return 0;
1145*4882a593Smuzhiyun }
1146*4882a593Smuzhiyun
es7210_micboost8_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1147*4882a593Smuzhiyun static int es7210_micboost8_setting_get(struct snd_kcontrol *kcontrol,
1148*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1149*4882a593Smuzhiyun {
1150*4882a593Smuzhiyun u8 val;
1151*4882a593Smuzhiyun es7210_read(0x46, &val, i2c_clt1[1]);
1152*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1153*4882a593Smuzhiyun return 0;
1154*4882a593Smuzhiyun }
es7210_adc5_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1155*4882a593Smuzhiyun static int es7210_adc5_mute_set(struct snd_kcontrol *kcontrol,
1156*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1157*4882a593Smuzhiyun {
1158*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC12_MUTE_REG15, 0x01,
1159*4882a593Smuzhiyun ucontrol->value.integer.value[0]&0x01, i2c_clt1[1]);
1160*4882a593Smuzhiyun return 0;
1161*4882a593Smuzhiyun }
1162*4882a593Smuzhiyun
es7210_adc5_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1163*4882a593Smuzhiyun static int es7210_adc5_mute_get(struct snd_kcontrol *kcontrol,
1164*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1165*4882a593Smuzhiyun {
1166*4882a593Smuzhiyun u8 val;
1167*4882a593Smuzhiyun es7210_read(ES7210_ADC12_MUTE_REG15, &val, i2c_clt1[1]);
1168*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val & 0x01;
1169*4882a593Smuzhiyun return 0;
1170*4882a593Smuzhiyun }
1171*4882a593Smuzhiyun
es7210_adc6_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1172*4882a593Smuzhiyun static int es7210_adc6_mute_set(struct snd_kcontrol *kcontrol,
1173*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1174*4882a593Smuzhiyun {
1175*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC12_MUTE_REG15, 0x02,
1176*4882a593Smuzhiyun (ucontrol->value.integer.value[0] & 0x01) << 1, i2c_clt1[1]);
1177*4882a593Smuzhiyun return 0;
1178*4882a593Smuzhiyun }
1179*4882a593Smuzhiyun
es7210_adc6_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1180*4882a593Smuzhiyun static int es7210_adc6_mute_get(struct snd_kcontrol *kcontrol,
1181*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1182*4882a593Smuzhiyun {
1183*4882a593Smuzhiyun u8 val;
1184*4882a593Smuzhiyun es7210_read(ES7210_ADC12_MUTE_REG15, &val, i2c_clt1[1]);
1185*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (val & 0x02) >> 1;
1186*4882a593Smuzhiyun return 0;
1187*4882a593Smuzhiyun }
1188*4882a593Smuzhiyun
es7210_adc7_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1189*4882a593Smuzhiyun static int es7210_adc7_mute_set(struct snd_kcontrol *kcontrol,
1190*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1191*4882a593Smuzhiyun {
1192*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC34_MUTE_REG14, 0x01,
1193*4882a593Smuzhiyun ucontrol->value.integer.value[0]&0x01, i2c_clt1[1]);
1194*4882a593Smuzhiyun return 0;
1195*4882a593Smuzhiyun }
1196*4882a593Smuzhiyun
es7210_adc7_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1197*4882a593Smuzhiyun static int es7210_adc7_mute_get(struct snd_kcontrol *kcontrol,
1198*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1199*4882a593Smuzhiyun {
1200*4882a593Smuzhiyun u8 val;
1201*4882a593Smuzhiyun es7210_read(ES7210_ADC34_MUTE_REG14, &val, i2c_clt1[1]);
1202*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val & 0x01;
1203*4882a593Smuzhiyun return 0;
1204*4882a593Smuzhiyun }
es7210_adc8_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1205*4882a593Smuzhiyun static int es7210_adc8_mute_set(struct snd_kcontrol *kcontrol,
1206*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1207*4882a593Smuzhiyun {
1208*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC34_MUTE_REG14, 0x02,
1209*4882a593Smuzhiyun (ucontrol->value.integer.value[0] & 0x01) << 1, i2c_clt1[1]);
1210*4882a593Smuzhiyun return 0;
1211*4882a593Smuzhiyun }
1212*4882a593Smuzhiyun
es7210_adc8_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1213*4882a593Smuzhiyun static int es7210_adc8_mute_get(struct snd_kcontrol *kcontrol,
1214*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1215*4882a593Smuzhiyun {
1216*4882a593Smuzhiyun u8 val;
1217*4882a593Smuzhiyun es7210_read(ES7210_ADC34_MUTE_REG14, &val, i2c_clt1[1]);
1218*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (val & 0x02) >> 1;
1219*4882a593Smuzhiyun return 0;
1220*4882a593Smuzhiyun }
1221*4882a593Smuzhiyun
1222*4882a593Smuzhiyun #endif
1223*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 8
es7210_micboost9_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1224*4882a593Smuzhiyun static int es7210_micboost9_setting_set(struct snd_kcontrol *kcontrol,
1225*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1226*4882a593Smuzhiyun {
1227*4882a593Smuzhiyun es7210_update_bits(0x43, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[2]);
1228*4882a593Smuzhiyun return 0;
1229*4882a593Smuzhiyun }
1230*4882a593Smuzhiyun
es7210_micboost9_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1231*4882a593Smuzhiyun static int es7210_micboost9_setting_get(struct snd_kcontrol *kcontrol,
1232*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1233*4882a593Smuzhiyun {
1234*4882a593Smuzhiyun u8 val;
1235*4882a593Smuzhiyun es7210_read(0x43, &val, i2c_clt1[2]);
1236*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1237*4882a593Smuzhiyun return 0;
1238*4882a593Smuzhiyun }
es7210_micboost10_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1239*4882a593Smuzhiyun static int es7210_micboost10_setting_set(struct snd_kcontrol *kcontrol,
1240*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1241*4882a593Smuzhiyun {
1242*4882a593Smuzhiyun es7210_update_bits(0x44, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[2]);
1243*4882a593Smuzhiyun return 0;
1244*4882a593Smuzhiyun }
1245*4882a593Smuzhiyun
es7210_micboost10_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1246*4882a593Smuzhiyun static int es7210_micboost10_setting_get(struct snd_kcontrol *kcontrol,
1247*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1248*4882a593Smuzhiyun {
1249*4882a593Smuzhiyun u8 val;
1250*4882a593Smuzhiyun es7210_read(0x44, &val, i2c_clt1[2]);
1251*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1252*4882a593Smuzhiyun return 0;
1253*4882a593Smuzhiyun }
es7210_micboost11_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1254*4882a593Smuzhiyun static int es7210_micboost11_setting_set(struct snd_kcontrol *kcontrol,
1255*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1256*4882a593Smuzhiyun {
1257*4882a593Smuzhiyun es7210_update_bits(0x45, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[2]);
1258*4882a593Smuzhiyun return 0;
1259*4882a593Smuzhiyun }
1260*4882a593Smuzhiyun
es7210_micboost11_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1261*4882a593Smuzhiyun static int es7210_micboost11_setting_get(struct snd_kcontrol *kcontrol,
1262*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1263*4882a593Smuzhiyun {
1264*4882a593Smuzhiyun u8 val;
1265*4882a593Smuzhiyun es7210_read(0x45, &val, i2c_clt1[2]);
1266*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1267*4882a593Smuzhiyun return 0;
1268*4882a593Smuzhiyun }
es7210_micboost12_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1269*4882a593Smuzhiyun static int es7210_micboost12_setting_set(struct snd_kcontrol *kcontrol,
1270*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1271*4882a593Smuzhiyun {
1272*4882a593Smuzhiyun es7210_update_bits(0x46, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[2]);
1273*4882a593Smuzhiyun return 0;
1274*4882a593Smuzhiyun }
1275*4882a593Smuzhiyun
es7210_micboost12_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1276*4882a593Smuzhiyun static int es7210_micboost12_setting_get(struct snd_kcontrol *kcontrol,
1277*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1278*4882a593Smuzhiyun {
1279*4882a593Smuzhiyun u8 val;
1280*4882a593Smuzhiyun es7210_read(0x46, &val, i2c_clt1[2]);
1281*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1282*4882a593Smuzhiyun return 0;
1283*4882a593Smuzhiyun }
es7210_adc9_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1284*4882a593Smuzhiyun static int es7210_adc9_mute_set(struct snd_kcontrol *kcontrol,
1285*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1286*4882a593Smuzhiyun {
1287*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC12_MUTE_REG15, 0x01,
1288*4882a593Smuzhiyun ucontrol->value.integer.value[0]&0x01, i2c_clt1[2]);
1289*4882a593Smuzhiyun return 0;
1290*4882a593Smuzhiyun }
1291*4882a593Smuzhiyun
es7210_adc9_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1292*4882a593Smuzhiyun static int es7210_adc9_mute_get(struct snd_kcontrol *kcontrol,
1293*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1294*4882a593Smuzhiyun {
1295*4882a593Smuzhiyun u8 val;
1296*4882a593Smuzhiyun es7210_read(ES7210_ADC12_MUTE_REG15, &val, i2c_clt1[2]);
1297*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val & 0x01;
1298*4882a593Smuzhiyun return 0;
1299*4882a593Smuzhiyun }
1300*4882a593Smuzhiyun
es7210_adc10_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1301*4882a593Smuzhiyun static int es7210_adc10_mute_set(struct snd_kcontrol *kcontrol,
1302*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1303*4882a593Smuzhiyun {
1304*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC12_MUTE_REG15, 0x02,
1305*4882a593Smuzhiyun (ucontrol->value.integer.value[0] & 0x01) << 1, i2c_clt1[2]);
1306*4882a593Smuzhiyun return 0;
1307*4882a593Smuzhiyun }
1308*4882a593Smuzhiyun
es7210_adc10_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1309*4882a593Smuzhiyun static int es7210_adc10_mute_get(struct snd_kcontrol *kcontrol,
1310*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1311*4882a593Smuzhiyun {
1312*4882a593Smuzhiyun u8 val;
1313*4882a593Smuzhiyun es7210_read(ES7210_ADC12_MUTE_REG15, &val, i2c_clt1[2]);
1314*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (val & 0x02) >> 1;
1315*4882a593Smuzhiyun return 0;
1316*4882a593Smuzhiyun }
1317*4882a593Smuzhiyun
es7210_adc11_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1318*4882a593Smuzhiyun static int es7210_adc11_mute_set(struct snd_kcontrol *kcontrol,
1319*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1320*4882a593Smuzhiyun {
1321*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC34_MUTE_REG14, 0x01,
1322*4882a593Smuzhiyun ucontrol->value.integer.value[0]&0x01, i2c_clt1[2]);
1323*4882a593Smuzhiyun return 0;
1324*4882a593Smuzhiyun }
1325*4882a593Smuzhiyun
es7210_adc11_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1326*4882a593Smuzhiyun static int es7210_adc11_mute_get(struct snd_kcontrol *kcontrol,
1327*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1328*4882a593Smuzhiyun {
1329*4882a593Smuzhiyun u8 val;
1330*4882a593Smuzhiyun es7210_read(ES7210_ADC34_MUTE_REG14, &val, i2c_clt1[2]);
1331*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val & 0x01;
1332*4882a593Smuzhiyun return 0;
1333*4882a593Smuzhiyun }
es7210_adc12_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1334*4882a593Smuzhiyun static int es7210_adc12_mute_set(struct snd_kcontrol *kcontrol,
1335*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1336*4882a593Smuzhiyun {
1337*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC34_MUTE_REG14, 0x02,
1338*4882a593Smuzhiyun (ucontrol->value.integer.value[0] & 0x01) << 1, i2c_clt1[2]);
1339*4882a593Smuzhiyun return 0;
1340*4882a593Smuzhiyun }
1341*4882a593Smuzhiyun
es7210_adc12_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1342*4882a593Smuzhiyun static int es7210_adc12_mute_get(struct snd_kcontrol *kcontrol,
1343*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1344*4882a593Smuzhiyun {
1345*4882a593Smuzhiyun u8 val;
1346*4882a593Smuzhiyun es7210_read(ES7210_ADC34_MUTE_REG14, &val, i2c_clt1[2]);
1347*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (val & 0x02) >> 1;
1348*4882a593Smuzhiyun return 0;
1349*4882a593Smuzhiyun }
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun #endif
1352*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 12
es7210_micboost13_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1353*4882a593Smuzhiyun static int es7210_micboost13_setting_set(struct snd_kcontrol *kcontrol,
1354*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1355*4882a593Smuzhiyun {
1356*4882a593Smuzhiyun es7210_update_bits(0x43, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[3]);
1357*4882a593Smuzhiyun return 0;
1358*4882a593Smuzhiyun }
1359*4882a593Smuzhiyun
es7210_micboost13_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1360*4882a593Smuzhiyun static int es7210_micboost13_setting_get(struct snd_kcontrol *kcontrol,
1361*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1362*4882a593Smuzhiyun {
1363*4882a593Smuzhiyun u8 val;
1364*4882a593Smuzhiyun es7210_read(0x43, &val, i2c_clt1[3]);
1365*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1366*4882a593Smuzhiyun return 0;
1367*4882a593Smuzhiyun }
es7210_micboost14_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1368*4882a593Smuzhiyun static int es7210_micboost14_setting_set(struct snd_kcontrol *kcontrol,
1369*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1370*4882a593Smuzhiyun {
1371*4882a593Smuzhiyun es7210_update_bits(0x44, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[3]);
1372*4882a593Smuzhiyun return 0;
1373*4882a593Smuzhiyun }
1374*4882a593Smuzhiyun
es7210_micboost14_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1375*4882a593Smuzhiyun static int es7210_micboost14_setting_get(struct snd_kcontrol *kcontrol,
1376*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1377*4882a593Smuzhiyun {
1378*4882a593Smuzhiyun u8 val;
1379*4882a593Smuzhiyun es7210_read(0x44, &val, i2c_clt1[3]);
1380*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1381*4882a593Smuzhiyun return 0;
1382*4882a593Smuzhiyun }
es7210_micboost15_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1383*4882a593Smuzhiyun static int es7210_micboost15_setting_set(struct snd_kcontrol *kcontrol,
1384*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1385*4882a593Smuzhiyun {
1386*4882a593Smuzhiyun es7210_update_bits(0x45, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[3]);
1387*4882a593Smuzhiyun return 0;
1388*4882a593Smuzhiyun }
1389*4882a593Smuzhiyun
es7210_micboost15_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1390*4882a593Smuzhiyun static int es7210_micboost15_setting_get(struct snd_kcontrol *kcontrol,
1391*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1392*4882a593Smuzhiyun {
1393*4882a593Smuzhiyun u8 val;
1394*4882a593Smuzhiyun es7210_read(0x45, &val, i2c_clt1[3]);
1395*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1396*4882a593Smuzhiyun return 0;
1397*4882a593Smuzhiyun }
es7210_micboost16_setting_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1398*4882a593Smuzhiyun static int es7210_micboost16_setting_set(struct snd_kcontrol *kcontrol,
1399*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1400*4882a593Smuzhiyun {
1401*4882a593Smuzhiyun es7210_update_bits(0x46, 0x0F, ucontrol->value.integer.value[0], i2c_clt1[3]);
1402*4882a593Smuzhiyun return 0;
1403*4882a593Smuzhiyun }
1404*4882a593Smuzhiyun
es7210_micboost16_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1405*4882a593Smuzhiyun static int es7210_micboost16_setting_get(struct snd_kcontrol *kcontrol,
1406*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1407*4882a593Smuzhiyun {
1408*4882a593Smuzhiyun u8 val;
1409*4882a593Smuzhiyun es7210_read(0x46, &val, i2c_clt1[3]);
1410*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val;
1411*4882a593Smuzhiyun return 0;
1412*4882a593Smuzhiyun }
es7210_adc13_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1413*4882a593Smuzhiyun static int es7210_adc13_mute_set(struct snd_kcontrol *kcontrol,
1414*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1415*4882a593Smuzhiyun {
1416*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC12_MUTE_REG15, 0x01,
1417*4882a593Smuzhiyun ucontrol->value.integer.value[0]&0x01, i2c_clt1[3]);
1418*4882a593Smuzhiyun return 0;
1419*4882a593Smuzhiyun }
1420*4882a593Smuzhiyun
es7210_adc13_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1421*4882a593Smuzhiyun static int es7210_adc13_mute_get(struct snd_kcontrol *kcontrol,
1422*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1423*4882a593Smuzhiyun {
1424*4882a593Smuzhiyun u8 val;
1425*4882a593Smuzhiyun es7210_read(ES7210_ADC12_MUTE_REG15, &val, i2c_clt1[3]);
1426*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val & 0x01;
1427*4882a593Smuzhiyun return 0;
1428*4882a593Smuzhiyun }
1429*4882a593Smuzhiyun
es7210_adc14_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1430*4882a593Smuzhiyun static int es7210_adc14_mute_set(struct snd_kcontrol *kcontrol,
1431*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1432*4882a593Smuzhiyun {
1433*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC12_MUTE_REG15, 0x02,
1434*4882a593Smuzhiyun (ucontrol->value.integer.value[0] & 0x01) << 1, i2c_clt1[3]);
1435*4882a593Smuzhiyun return 0;
1436*4882a593Smuzhiyun }
1437*4882a593Smuzhiyun
es7210_adc14_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1438*4882a593Smuzhiyun static int es7210_adc14_mute_get(struct snd_kcontrol *kcontrol,
1439*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1440*4882a593Smuzhiyun {
1441*4882a593Smuzhiyun u8 val;
1442*4882a593Smuzhiyun es7210_read(ES7210_ADC12_MUTE_REG15, &val, i2c_clt1[3]);
1443*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (val & 0x02) >> 1;
1444*4882a593Smuzhiyun return 0;
1445*4882a593Smuzhiyun }
1446*4882a593Smuzhiyun
es7210_adc15_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1447*4882a593Smuzhiyun static int es7210_adc15_mute_set(struct snd_kcontrol *kcontrol,
1448*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1449*4882a593Smuzhiyun {
1450*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC34_MUTE_REG14, 0x01,
1451*4882a593Smuzhiyun ucontrol->value.integer.value[0]&0x01, i2c_clt1[3]);
1452*4882a593Smuzhiyun return 0;
1453*4882a593Smuzhiyun }
1454*4882a593Smuzhiyun
es7210_adc15_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1455*4882a593Smuzhiyun static int es7210_adc15_mute_get(struct snd_kcontrol *kcontrol,
1456*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1457*4882a593Smuzhiyun {
1458*4882a593Smuzhiyun u8 val;
1459*4882a593Smuzhiyun es7210_read(ES7210_ADC34_MUTE_REG14, &val, i2c_clt1[3]);
1460*4882a593Smuzhiyun ucontrol->value.integer.value[0] = val & 0x01;
1461*4882a593Smuzhiyun return 0;
1462*4882a593Smuzhiyun }
es7210_adc16_mute_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1463*4882a593Smuzhiyun static int es7210_adc16_mute_set(struct snd_kcontrol *kcontrol,
1464*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1465*4882a593Smuzhiyun {
1466*4882a593Smuzhiyun es7210_update_bits(ES7210_ADC34_MUTE_REG14, 0x02,
1467*4882a593Smuzhiyun (ucontrol->value.integer.value[0] & 0x01) << 1, i2c_clt1[3]);
1468*4882a593Smuzhiyun return 0;
1469*4882a593Smuzhiyun }
1470*4882a593Smuzhiyun
es7210_adc16_mute_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1471*4882a593Smuzhiyun static int es7210_adc16_mute_get(struct snd_kcontrol *kcontrol,
1472*4882a593Smuzhiyun struct snd_ctl_elem_value *ucontrol)
1473*4882a593Smuzhiyun {
1474*4882a593Smuzhiyun u8 val;
1475*4882a593Smuzhiyun es7210_read(ES7210_ADC34_MUTE_REG14, &val, i2c_clt1[3]);
1476*4882a593Smuzhiyun ucontrol->value.integer.value[0] = (val & 0x02) >> 1;
1477*4882a593Smuzhiyun return 0;
1478*4882a593Smuzhiyun }
1479*4882a593Smuzhiyun
1480*4882a593Smuzhiyun #endif
1481*4882a593Smuzhiyun static const struct snd_kcontrol_new es7210_snd_controls[] = {
1482*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 0
1483*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA1_setting",
1484*4882a593Smuzhiyun 0x43, 0, 0x0E, 0,
1485*4882a593Smuzhiyun es7210_micboost1_setting_get, es7210_micboost1_setting_set,
1486*4882a593Smuzhiyun mic_boost_tlv),
1487*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA2_setting",
1488*4882a593Smuzhiyun 0x44, 0, 0x0E, 0,
1489*4882a593Smuzhiyun es7210_micboost2_setting_get, es7210_micboost2_setting_set,
1490*4882a593Smuzhiyun mic_boost_tlv),
1491*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA3_setting",
1492*4882a593Smuzhiyun 0x45, 0, 0x0E, 0,
1493*4882a593Smuzhiyun es7210_micboost3_setting_get, es7210_micboost3_setting_set,
1494*4882a593Smuzhiyun mic_boost_tlv),
1495*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA4_setting",
1496*4882a593Smuzhiyun 0x46, 0, 0x0E, 0,
1497*4882a593Smuzhiyun es7210_micboost4_setting_get, es7210_micboost4_setting_set,
1498*4882a593Smuzhiyun mic_boost_tlv),
1499*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC1_MUTE", ES7210_ADC12_MUTE_REG15, 0, 1, 0,
1500*4882a593Smuzhiyun es7210_adc1_mute_get, es7210_adc1_mute_set),
1501*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC2_MUTE", ES7210_ADC12_MUTE_REG15, 1, 1, 0,
1502*4882a593Smuzhiyun es7210_adc2_mute_get, es7210_adc2_mute_set),
1503*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC3_MUTE", ES7210_ADC34_MUTE_REG14, 0, 1, 0,
1504*4882a593Smuzhiyun es7210_adc3_mute_get, es7210_adc3_mute_set),
1505*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC4_MUTE", ES7210_ADC34_MUTE_REG14, 1, 1, 0,
1506*4882a593Smuzhiyun es7210_adc4_mute_get, es7210_adc4_mute_set),
1507*4882a593Smuzhiyun #endif
1508*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 4
1509*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA5_setting",
1510*4882a593Smuzhiyun 0x43, 0, 0x0E, 0,
1511*4882a593Smuzhiyun es7210_micboost5_setting_get, es7210_micboost5_setting_set,
1512*4882a593Smuzhiyun mic_boost_tlv),
1513*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA6_setting",
1514*4882a593Smuzhiyun 0x44, 0, 0x0E, 0,
1515*4882a593Smuzhiyun es7210_micboost6_setting_get, es7210_micboost6_setting_set,
1516*4882a593Smuzhiyun mic_boost_tlv),
1517*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA7_setting",
1518*4882a593Smuzhiyun 0x45, 0, 0x0E, 0,
1519*4882a593Smuzhiyun es7210_micboost7_setting_get, es7210_micboost7_setting_set,
1520*4882a593Smuzhiyun mic_boost_tlv),
1521*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA8_setting",
1522*4882a593Smuzhiyun 0x46, 0, 0x0E, 0,
1523*4882a593Smuzhiyun es7210_micboost8_setting_get, es7210_micboost8_setting_set,
1524*4882a593Smuzhiyun mic_boost_tlv),
1525*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC5_MUTE", ES7210_ADC12_MUTE_REG15, 0, 1, 0,
1526*4882a593Smuzhiyun es7210_adc5_mute_get, es7210_adc5_mute_set),
1527*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC6_MUTE", ES7210_ADC12_MUTE_REG15, 1, 1, 0,
1528*4882a593Smuzhiyun es7210_adc6_mute_get, es7210_adc6_mute_set),
1529*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC7_MUTE", ES7210_ADC34_MUTE_REG14, 0, 1, 0,
1530*4882a593Smuzhiyun es7210_adc7_mute_get, es7210_adc7_mute_set),
1531*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC8_MUTE", ES7210_ADC34_MUTE_REG14, 1, 1, 0,
1532*4882a593Smuzhiyun es7210_adc8_mute_get, es7210_adc8_mute_set),
1533*4882a593Smuzhiyun
1534*4882a593Smuzhiyun #endif
1535*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 8
1536*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA9_setting",
1537*4882a593Smuzhiyun 0x43, 0, 0x0E, 0,
1538*4882a593Smuzhiyun es7210_micboost9_setting_get, es7210_micboost9_setting_set,
1539*4882a593Smuzhiyun mic_boost_tlv),
1540*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA10_setting",
1541*4882a593Smuzhiyun 0x44, 0, 0x0E, 0,
1542*4882a593Smuzhiyun es7210_micboost10_setting_get, es7210_micboost10_setting_set,
1543*4882a593Smuzhiyun mic_boost_tlv),
1544*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA11_setting",
1545*4882a593Smuzhiyun 0x45, 0, 0x0E, 0,
1546*4882a593Smuzhiyun es7210_micboost11_setting_get, es7210_micboost11_setting_set,
1547*4882a593Smuzhiyun mic_boost_tlv),
1548*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA12_setting",
1549*4882a593Smuzhiyun 0x46, 0, 0x0E, 0,
1550*4882a593Smuzhiyun es7210_micboost12_setting_get, es7210_micboost12_setting_set,
1551*4882a593Smuzhiyun mic_boost_tlv),
1552*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC9_MUTE", ES7210_ADC12_MUTE_REG15, 0, 1, 0,
1553*4882a593Smuzhiyun es7210_adc9_mute_get, es7210_adc9_mute_set),
1554*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC10_MUTE", ES7210_ADC12_MUTE_REG15, 1, 1, 0,
1555*4882a593Smuzhiyun es7210_adc10_mute_get, es7210_adc10_mute_set),
1556*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC11_MUTE", ES7210_ADC34_MUTE_REG14, 0, 1, 0,
1557*4882a593Smuzhiyun es7210_adc11_mute_get, es7210_adc11_mute_set),
1558*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC12_MUTE", ES7210_ADC34_MUTE_REG14, 1, 1, 0,
1559*4882a593Smuzhiyun es7210_adc12_mute_get, es7210_adc12_mute_set),
1560*4882a593Smuzhiyun
1561*4882a593Smuzhiyun #endif
1562*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 12
1563*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA13_setting",
1564*4882a593Smuzhiyun 0x43, 0, 0x0E, 0,
1565*4882a593Smuzhiyun es7210_micboost13_setting_get, es7210_micboost13_setting_set,
1566*4882a593Smuzhiyun mic_boost_tlv),
1567*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA14_setting",
1568*4882a593Smuzhiyun 0x44, 0, 0x0E, 0,
1569*4882a593Smuzhiyun es7210_micboost14_setting_get, es7210_micboost14_setting_set,
1570*4882a593Smuzhiyun mic_boost_tlv),
1571*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA15_setting",
1572*4882a593Smuzhiyun 0x45, 0, 0x0E, 0,
1573*4882a593Smuzhiyun es7210_micboost15_setting_get, es7210_micboost15_setting_set,
1574*4882a593Smuzhiyun mic_boost_tlv),
1575*4882a593Smuzhiyun SOC_SINGLE_EXT_TLV("PGA16_setting",
1576*4882a593Smuzhiyun 0x46, 0, 0x0E, 0,
1577*4882a593Smuzhiyun es7210_micboost16_setting_get, es7210_micboost16_setting_set,
1578*4882a593Smuzhiyun mic_boost_tlv),
1579*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC13_MUTE", ES7210_ADC12_MUTE_REG15, 0, 1, 0,
1580*4882a593Smuzhiyun es7210_adc13_mute_get, es7210_adc13_mute_set),
1581*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC14_MUTE", ES7210_ADC12_MUTE_REG15, 1, 1, 0,
1582*4882a593Smuzhiyun es7210_adc14_mute_get, es7210_adc14_mute_set),
1583*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC15_MUTE", ES7210_ADC34_MUTE_REG14, 0, 1, 0,
1584*4882a593Smuzhiyun es7210_adc15_mute_get, es7210_adc15_mute_set),
1585*4882a593Smuzhiyun SOC_SINGLE_EXT("ADC16_MUTE", ES7210_ADC34_MUTE_REG14, 1, 1, 0,
1586*4882a593Smuzhiyun es7210_adc16_mute_get, es7210_adc16_mute_set),
1587*4882a593Smuzhiyun
1588*4882a593Smuzhiyun #endif
1589*4882a593Smuzhiyun
1590*4882a593Smuzhiyun };
1591*4882a593Smuzhiyun
1592*4882a593Smuzhiyun static struct snd_soc_component_driver soc_codec_dev_es7210 = {
1593*4882a593Smuzhiyun .probe = es7210_probe,
1594*4882a593Smuzhiyun .remove = es7210_remove,
1595*4882a593Smuzhiyun .suspend = es7210_suspend,
1596*4882a593Smuzhiyun .resume = es7210_resume,
1597*4882a593Smuzhiyun .set_bias_level = es7210_set_bias_level,
1598*4882a593Smuzhiyun .controls = es7210_snd_controls,
1599*4882a593Smuzhiyun .num_controls = ARRAY_SIZE(es7210_snd_controls),
1600*4882a593Smuzhiyun };
1601*4882a593Smuzhiyun
es7210_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1602*4882a593Smuzhiyun static ssize_t es7210_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
1603*4882a593Smuzhiyun {
1604*4882a593Smuzhiyun int val = 0, flag = 0;
1605*4882a593Smuzhiyun u8 i = 0, reg, num, value_w, value_r;
1606*4882a593Smuzhiyun
1607*4882a593Smuzhiyun struct es7210_priv *es7210 = dev_get_drvdata(dev);
1608*4882a593Smuzhiyun val = simple_strtol(buf, NULL, 16);
1609*4882a593Smuzhiyun flag = (val >> 16) & 0xFF;
1610*4882a593Smuzhiyun
1611*4882a593Smuzhiyun if (flag) {
1612*4882a593Smuzhiyun reg = (val >> 8) & 0xFF;
1613*4882a593Smuzhiyun value_w = val & 0xFF;
1614*4882a593Smuzhiyun printk("\nWrite: start REG:0x%02x,val:0x%02x,count:0x%02x\n", reg, value_w, flag);
1615*4882a593Smuzhiyun while (flag--) {
1616*4882a593Smuzhiyun es7210_write(reg, value_w, es7210->i2c_client);
1617*4882a593Smuzhiyun printk("Write 0x%02x to REG:0x%02x\n", value_w, reg);
1618*4882a593Smuzhiyun reg++;
1619*4882a593Smuzhiyun }
1620*4882a593Smuzhiyun } else {
1621*4882a593Smuzhiyun reg = (val >> 8) & 0xFF;
1622*4882a593Smuzhiyun num = val & 0xff;
1623*4882a593Smuzhiyun printk("\nRead: start REG:0x%02x,count:0x%02x\n", reg, num);
1624*4882a593Smuzhiyun do {
1625*4882a593Smuzhiyun value_r = 0;
1626*4882a593Smuzhiyun es7210_read(reg, &value_r, es7210->i2c_client);
1627*4882a593Smuzhiyun printk("REG[0x%02x]: 0x%02x; ", reg, value_r);
1628*4882a593Smuzhiyun reg++;
1629*4882a593Smuzhiyun i++;
1630*4882a593Smuzhiyun if ((i == num) || (i % 4 == 0)) printk("\n");
1631*4882a593Smuzhiyun } while (i < num);
1632*4882a593Smuzhiyun }
1633*4882a593Smuzhiyun
1634*4882a593Smuzhiyun return count;
1635*4882a593Smuzhiyun }
1636*4882a593Smuzhiyun
es7210_show(struct device * dev,struct device_attribute * attr,char * buf)1637*4882a593Smuzhiyun static ssize_t es7210_show(struct device *dev, struct device_attribute *attr, char *buf)
1638*4882a593Smuzhiyun {
1639*4882a593Smuzhiyun printk("echo flag|reg|val > es7210\n");
1640*4882a593Smuzhiyun printk("eg read star address=0x06,count 0x10:echo 0610 >es7210\n");
1641*4882a593Smuzhiyun printk("eg write star address=0x90,value=0x3c,count=4:echo 4903c >es7210\n");
1642*4882a593Smuzhiyun return 0;
1643*4882a593Smuzhiyun }
1644*4882a593Smuzhiyun
1645*4882a593Smuzhiyun static DEVICE_ATTR(es7210, 0644, es7210_show, es7210_store);
1646*4882a593Smuzhiyun
1647*4882a593Smuzhiyun static struct attribute *es7210_debug_attrs[] = {
1648*4882a593Smuzhiyun &dev_attr_es7210.attr,
1649*4882a593Smuzhiyun NULL,
1650*4882a593Smuzhiyun };
1651*4882a593Smuzhiyun
1652*4882a593Smuzhiyun static struct attribute_group es7210_debug_attr_group = {
1653*4882a593Smuzhiyun .name = "es7210_debug",
1654*4882a593Smuzhiyun .attrs = es7210_debug_attrs,
1655*4882a593Smuzhiyun };
1656*4882a593Smuzhiyun
1657*4882a593Smuzhiyun /*
1658*4882a593Smuzhiyun * If the i2c layer weren't so broken, we could pass this kind of data
1659*4882a593Smuzhiyun * around
1660*4882a593Smuzhiyun */
es7210_i2c_probe(struct i2c_client * i2c_client,const struct i2c_device_id * i2c_id)1661*4882a593Smuzhiyun static int es7210_i2c_probe(struct i2c_client *i2c_client,
1662*4882a593Smuzhiyun const struct i2c_device_id *i2c_id)
1663*4882a593Smuzhiyun {
1664*4882a593Smuzhiyun struct es7210_priv *es7210;
1665*4882a593Smuzhiyun int ret;
1666*4882a593Smuzhiyun
1667*4882a593Smuzhiyun printk("begin->>>>>>>>>>%s!\n", __func__);
1668*4882a593Smuzhiyun
1669*4882a593Smuzhiyun es7210 = devm_kzalloc(&i2c_client->dev, sizeof(struct es7210_priv),
1670*4882a593Smuzhiyun GFP_KERNEL);
1671*4882a593Smuzhiyun if (es7210 == NULL)
1672*4882a593Smuzhiyun return -ENOMEM;
1673*4882a593Smuzhiyun es7210->i2c_client = i2c_client;
1674*4882a593Smuzhiyun es7210->tdm_mode = ES7210_WORK_MODE; //to set tdm mode or normal mode
1675*4882a593Smuzhiyun i2c_set_clientdata(i2c_client, es7210);
1676*4882a593Smuzhiyun if (i2c_id->driver_data < ADC_DEV_MAXNUM) {
1677*4882a593Smuzhiyun i2c_clt1[i2c_id->driver_data] = i2c_client;
1678*4882a593Smuzhiyun ret = devm_snd_soc_register_component(&i2c_client->dev, &soc_codec_dev_es7210,
1679*4882a593Smuzhiyun es7210_dai[i2c_id->driver_data], 1);
1680*4882a593Smuzhiyun if (ret < 0) {
1681*4882a593Smuzhiyun return ret;
1682*4882a593Smuzhiyun }
1683*4882a593Smuzhiyun }
1684*4882a593Smuzhiyun ret = sysfs_create_group(&i2c_client->dev.kobj, &es7210_debug_attr_group);
1685*4882a593Smuzhiyun if (ret) {
1686*4882a593Smuzhiyun pr_err("failed to create attr group\n");
1687*4882a593Smuzhiyun }
1688*4882a593Smuzhiyun printk("%s success!\n", __func__);
1689*4882a593Smuzhiyun return ret;
1690*4882a593Smuzhiyun }
1691*4882a593Smuzhiyun
es7210_i2c_remove(struct i2c_client * client)1692*4882a593Smuzhiyun static int es7210_i2c_remove(struct i2c_client *client)
1693*4882a593Smuzhiyun {
1694*4882a593Smuzhiyun sysfs_remove_group(&client->dev.kobj, &es7210_debug_attr_group);
1695*4882a593Smuzhiyun
1696*4882a593Smuzhiyun return 0;
1697*4882a593Smuzhiyun }
1698*4882a593Smuzhiyun
1699*4882a593Smuzhiyun static const struct i2c_device_id es7210_i2c_id[] = {
1700*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 0
1701*4882a593Smuzhiyun { "ES7210_MicArray_0", 0 },//es7210_0
1702*4882a593Smuzhiyun #endif
1703*4882a593Smuzhiyun
1704*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 4
1705*4882a593Smuzhiyun { "ES7210_MicArray_1", 1 },//es7210_1
1706*4882a593Smuzhiyun #endif
1707*4882a593Smuzhiyun
1708*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 8
1709*4882a593Smuzhiyun { "ES7210_MicArray_2", 2 },//es7210_2
1710*4882a593Smuzhiyun #endif
1711*4882a593Smuzhiyun
1712*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 12
1713*4882a593Smuzhiyun { "ES7210_MicArray_3", 3 },//es7210_3
1714*4882a593Smuzhiyun #endif
1715*4882a593Smuzhiyun { }
1716*4882a593Smuzhiyun };
1717*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c_client, es7210_i2c_id);
1718*4882a593Smuzhiyun
1719*4882a593Smuzhiyun static const struct of_device_id es7210_dt_ids[] = {
1720*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 0
1721*4882a593Smuzhiyun { .compatible = "ES7210_MicArray_0", },//es7210_0
1722*4882a593Smuzhiyun #endif
1723*4882a593Smuzhiyun
1724*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 4
1725*4882a593Smuzhiyun { .compatible = "ES7210_MicArray_1", },//es7210_1
1726*4882a593Smuzhiyun #endif
1727*4882a593Smuzhiyun
1728*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 8
1729*4882a593Smuzhiyun { .compatible = "ES7210_MicArray_2", },//es7210_2
1730*4882a593Smuzhiyun #endif
1731*4882a593Smuzhiyun
1732*4882a593Smuzhiyun #if ES7210_CHANNELS_MAX > 12
1733*4882a593Smuzhiyun { .compatible = "ES7210_MicArray_3", },//es7210_3
1734*4882a593Smuzhiyun #endif
1735*4882a593Smuzhiyun { }
1736*4882a593Smuzhiyun };
1737*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, es7210_dt_ids);
1738*4882a593Smuzhiyun
1739*4882a593Smuzhiyun static struct i2c_driver es7210_i2c_driver = {
1740*4882a593Smuzhiyun .driver = {
1741*4882a593Smuzhiyun .name = "es7210",
1742*4882a593Smuzhiyun .owner = THIS_MODULE,
1743*4882a593Smuzhiyun .of_match_table = es7210_dt_ids,
1744*4882a593Smuzhiyun },
1745*4882a593Smuzhiyun .probe = es7210_i2c_probe,
1746*4882a593Smuzhiyun .remove = es7210_i2c_remove,
1747*4882a593Smuzhiyun .id_table = es7210_i2c_id,
1748*4882a593Smuzhiyun
1749*4882a593Smuzhiyun };
1750*4882a593Smuzhiyun module_i2c_driver(es7210_i2c_driver);
1751*4882a593Smuzhiyun
1752*4882a593Smuzhiyun MODULE_DESCRIPTION("ASoC ES7210 audio adc driver");
1753*4882a593Smuzhiyun MODULE_AUTHOR("David Yang <yangxiaohua@everest-semi.com> / info@everest-semi.com");
1754*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1755