1 // SPDX-License-Identifier: GPL-2.0+
2
3 #include <linux/module.h>
4 #include <linux/i2c.h>
5 #include <sound/core.h>
6 #include <sound/pcm.h>
7 #include <sound/pcm_params.h>
8 #include <sound/soc.h>
9 #include <linux/of_gpio.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/firmware.h>
13 #include <linux/version.h>
14 #include <linux/workqueue.h>
15 #include <linux/syscalls.h>
16 #include <sound/control.h>
17 #include <linux/uaccess.h>
18 #include <linux/syscalls.h>
19
20 #include "aw883xx.h"
21 #include "aw_bin_parse.h"
22 #include "aw_pid_2049_reg.h"
23 #include "aw_log.h"
24
25 #define AW_FW_CHECK_PART (10)
26
aw883xx_dev_i2c_writes(struct aw_device * aw_dev,uint8_t reg_addr,uint8_t * buf,uint16_t len)27 static int aw883xx_dev_i2c_writes(struct aw_device *aw_dev,
28 uint8_t reg_addr, uint8_t *buf, uint16_t len)
29 {
30 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
31
32 return aw883xx_i2c_writes(aw883xx, reg_addr, buf, len);
33 }
34
aw883xx_dev_i2c_write(struct aw_device * aw_dev,uint8_t reg_addr,uint16_t reg_data)35 static int aw883xx_dev_i2c_write(struct aw_device *aw_dev,
36 uint8_t reg_addr, uint16_t reg_data)
37 {
38 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
39
40 return aw883xx_i2c_write(aw883xx, reg_addr, reg_data);
41 }
42
aw883xx_dev_i2c_read(struct aw_device * aw_dev,uint8_t reg_addr,uint16_t * reg_data)43 static int aw883xx_dev_i2c_read(struct aw_device *aw_dev,
44 uint8_t reg_addr, uint16_t *reg_data)
45 {
46 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
47
48 return aw883xx_i2c_read(aw883xx, reg_addr, reg_data);
49 }
50
51
aw883xx_dev_reg_read(struct aw_device * aw_dev,uint8_t reg_addr,uint16_t * reg_data)52 static int aw883xx_dev_reg_read(struct aw_device *aw_dev,
53 uint8_t reg_addr, uint16_t *reg_data)
54 {
55 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
56
57 return aw883xx_reg_read(aw883xx, reg_addr, reg_data);
58 }
59
aw883xx_dev_reg_write(struct aw_device * aw_dev,uint8_t reg_addr,uint16_t reg_data)60 static int aw883xx_dev_reg_write(struct aw_device *aw_dev,
61 uint8_t reg_addr, uint16_t reg_data)
62 {
63 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
64
65 return aw883xx_reg_write(aw883xx, reg_addr, reg_data);
66 }
67
aw883xx_dev_reg_write_bits(struct aw_device * aw_dev,uint8_t reg_addr,uint16_t mask,uint16_t reg_data)68 static int aw883xx_dev_reg_write_bits(struct aw_device *aw_dev,
69 uint8_t reg_addr, uint16_t mask, uint16_t reg_data)
70 {
71 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
72
73 return aw883xx_reg_write_bits(aw883xx, reg_addr, mask, reg_data);
74 }
75
aw883xx_dev_dsp_write(struct aw_device * aw_dev,uint16_t dsp_addr,uint32_t dsp_data,uint8_t data_type)76 static int aw883xx_dev_dsp_write(struct aw_device *aw_dev,
77 uint16_t dsp_addr, uint32_t dsp_data, uint8_t data_type)
78 {
79 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
80
81 return aw883xx_dsp_write(aw883xx, dsp_addr, dsp_data, data_type);
82 }
83
aw883xx_dev_dsp_read(struct aw_device * aw_dev,uint16_t dsp_addr,uint32_t * dsp_data,uint8_t data_type)84 static int aw883xx_dev_dsp_read(struct aw_device *aw_dev,
85 uint16_t dsp_addr, uint32_t *dsp_data, uint8_t data_type)
86 {
87 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
88
89 return aw883xx_dsp_read(aw883xx, dsp_addr, dsp_data, data_type);
90 }
91
92
93 /******************************************************
94 *
95 * aw883xx i2c write/read
96 *
97 ******************************************************/
98 /*[9 : 6]: -6DB ; [5 : 0]: -0.125DB real_value = value * 8 : 0.125db --> 1*/
aw_pid_2049_reg_val_to_db(unsigned int value)99 static unsigned int aw_pid_2049_reg_val_to_db(unsigned int value)
100 {
101 return (((value >> AW_PID_2049_VOL_6DB_START) * AW_PID_2049_VOLUME_STEP_DB) +
102 ((value & 0x3f) % AW_PID_2049_VOLUME_STEP_DB));
103 }
104
105 /*[9 : 6]: -6DB ; [5 : 0]: -0.125DB reg_value = value / step << 6 + value % step ; step = 6 * 8*/
aw883xx_db_val_to_reg(uint16_t value)106 static uint16_t aw883xx_db_val_to_reg(uint16_t value)
107 {
108 return (((value / AW_PID_2049_VOLUME_STEP_DB) << AW_PID_2049_VOL_6DB_START) +
109 (value % AW_PID_2049_VOLUME_STEP_DB));
110 }
111
aw883xx_set_volume(struct aw883xx * aw883xx,uint16_t value)112 static int aw883xx_set_volume(struct aw883xx *aw883xx, uint16_t value)
113 {
114 uint16_t reg_value = 0;
115 uint16_t real_value = aw883xx_db_val_to_reg(value);
116
117 /* cal real value */
118 aw883xx_reg_read(aw883xx, AW_PID_2049_SYSCTRL2_REG, ®_value);
119
120 aw_dev_dbg(aw883xx->dev, "value 0x%x , reg:0x%x", value, real_value);
121
122 /*[15 : 6] volume*/
123 real_value = (real_value << AW_PID_2049_VOL_START_BIT) | (reg_value & AW_PID_2049_VOL_MASK);
124
125 /* write value */
126 aw883xx_reg_write(aw883xx, AW_PID_2049_SYSCTRL2_REG, real_value);
127
128 return 0;
129 }
130
aw883xx_get_volume(struct aw883xx * aw883xx,uint16_t * value)131 static int aw883xx_get_volume(struct aw883xx *aw883xx, uint16_t *value)
132 {
133 uint16_t reg_value = 0;
134 uint16_t real_value = 0;
135
136 /* read value */
137 aw883xx_reg_read(aw883xx, AW_PID_2049_SYSCTRL2_REG, ®_value);
138
139 /*[15 : 6] volume*/
140 real_value = reg_value >> AW_PID_2049_VOL_START_BIT;
141
142 real_value = aw_pid_2049_reg_val_to_db(real_value);
143
144 *value = real_value;
145
146 return 0;
147 }
148
aw_pid_2049_set_volume(struct aw_device * aw_dev,uint16_t value)149 static int aw_pid_2049_set_volume(struct aw_device *aw_dev, uint16_t value)
150 {
151 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
152 return aw883xx_set_volume(aw883xx, value);
153 }
154
aw_pid_2049_get_volume(struct aw_device * aw_dev,uint16_t * value)155 static int aw_pid_2049_get_volume(struct aw_device *aw_dev, uint16_t *value)
156 {
157 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
158 return aw883xx_get_volume(aw883xx, value);
159 }
160
aw_pid_2049_i2s_tx_enable(struct aw_device * aw_dev,bool flag)161 static void aw_pid_2049_i2s_tx_enable(struct aw_device *aw_dev, bool flag)
162 {
163 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
164
165 aw_dev_dbg(aw883xx->dev, "enter");
166
167 if (flag) {
168 aw883xx_reg_write_bits(aw883xx, AW_PID_2049_I2SCFG1_REG,
169 AW_PID_2049_I2STXEN_MASK,
170 AW_PID_2049_I2STXEN_ENABLE_VALUE);
171 } else {
172 aw883xx_reg_write_bits(aw883xx, AW_PID_2049_I2SCFG1_REG,
173 AW_PID_2049_I2STXEN_MASK,
174 AW_PID_2049_I2STXEN_DISABLE_VALUE);
175 }
176 }
177
aw_pid_2049_set_cfg_f0_fs(struct aw_device * aw_dev,uint32_t * f0_fs)178 static void aw_pid_2049_set_cfg_f0_fs(struct aw_device *aw_dev, uint32_t *f0_fs)
179 {
180 uint16_t rate_data = 0;
181 uint32_t fs = 0;
182 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
183
184 aw_dev_dbg(aw883xx->dev, "enter");
185 aw883xx_reg_read(aw883xx, AW_PID_2049_I2SCTRL_REG, &rate_data);
186
187 switch (rate_data & (~AW_PID_2049_I2SSR_MASK)) {
188 case AW_PID_2049_I2SSR_8_KHZ_VALUE:
189 fs = 8000;
190 break;
191 case AW_PID_2049_I2SSR_16_KHZ_VALUE:
192 fs = 16000;
193 break;
194 case AW_PID_2049_I2SSR_32_KHZ_VALUE:
195 fs = 32000;
196 break;
197 case AW_PID_2049_I2SSR_44_KHZ_VALUE:
198 fs = 44000;
199 break;
200 case AW_PID_2049_I2SSR_48_KHZ_VALUE:
201 fs = 48000;
202 break;
203 case AW_PID_2049_I2SSR_96_KHZ_VALUE:
204 fs = 96000;
205 break;
206 case AW_PID_2049_I2SSR_192KHZ_VALUE:
207 fs = 192000;
208 break;
209 default:
210 fs = 48000;
211 aw_dev_err(aw883xx->dev,
212 "rate can not support, use default 48k");
213 break;
214 }
215
216 aw_dev_dbg(aw883xx->dev, "get i2s fs:%d", fs);
217 *f0_fs = fs / 8;
218
219 aw883xx_dsp_write(aw883xx,
220 AW_PID_2049_DSP_REG_CFGF0_FS, *f0_fs, AW_DSP_32_DATA);
221 }
222
aw_pid_2049_check_rd_access(int reg)223 static bool aw_pid_2049_check_rd_access(int reg)
224 {
225 if (reg >= AW_PID_2049_REG_MAX)
226 return false;
227
228 if (aw_pid_2049_reg_access[reg] & REG_RD_ACCESS)
229 return true;
230 else
231 return false;
232 }
233
aw_pid_2049_check_wr_access(int reg)234 static bool aw_pid_2049_check_wr_access(int reg)
235 {
236 if (reg >= AW_PID_2049_REG_MAX)
237 return false;
238
239 if (aw_pid_2049_reg_access[reg] & REG_WR_ACCESS)
240 return true;
241 else
242 return false;
243 }
244
aw_pid_2049_get_reg_num(void)245 static int aw_pid_2049_get_reg_num(void)
246 {
247 return AW_PID_2049_REG_MAX;
248 }
249
aw_pid_2049_get_hw_mon_st(struct aw_device * aw_dev,bool * is_enable,uint8_t * temp_flag)250 static int aw_pid_2049_get_hw_mon_st(struct aw_device *aw_dev,
251 bool *is_enable, uint8_t *temp_flag)
252 {
253 int ret = 0;
254 uint32_t vbat_en = 0;
255 uint32_t temp_en = 0;
256 uint32_t temp_switch = 0;
257 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
258
259 ret = aw883xx_dsp_read(aw883xx,
260 AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG, &vbat_en, AW_DSP_16_DATA);
261 if (ret < 0) {
262 aw_dev_err(aw883xx->dev, "read hardware monitor status failed");
263 return ret;
264 }
265
266 ret = aw883xx_dsp_read(aw883xx,
267 AW_PID_2049_DSP_REG_TEMP_SWITCH, &temp_en, AW_DSP_16_DATA);
268 if (ret < 0) {
269 aw_dev_err(aw883xx->dev, "read hardware temp switch failed");
270 return ret;
271 }
272
273 temp_switch = temp_en;
274 vbat_en &= (~AW_PID_2049_DSP_MONITOR_MASK);
275 temp_en &= (~AW_PID_2049_DSP_TEMP_PEAK_MASK);
276 temp_switch &= (~AW_PID_2049_DSP_TEMP_SEL_FLAG);
277
278 if (vbat_en || temp_en)
279 *is_enable = true;
280 else
281 *is_enable = false;
282
283 if (temp_switch)
284 *temp_flag = AW_EXTERNAL_TEMP;
285 else
286 *temp_flag = AW_INTERNAL_TEMP;
287
288 return 0;
289 }
290
aw_pid_2049_cali_get_iv_st(struct aw_device * aw_dev)291 static int aw_pid_2049_cali_get_iv_st(struct aw_device *aw_dev)
292 {
293 struct aw883xx *aw883xx = (struct aw883xx *)aw_dev->private_data;
294 int ret;
295 uint16_t reg_data = 0;
296 int i;
297
298 aw_dev_info(aw_dev->dev, "enter");
299
300 for (i = 0; i < AW_GET_IV_CNT_MAX; i++) {
301 ret = aw883xx_reg_read(aw883xx, AW_PID_2049_ASR1_REG, ®_data);
302 if (ret < 0) {
303 aw_dev_err(aw883xx->dev,
304 "read 0x%x failed", AW_PID_2049_ASR1_REG);
305 return ret;
306 }
307
308 reg_data &= (~AW_PID_2049_ReAbs_MASK);
309 if (!reg_data)
310 return 0;
311 msleep(30);
312 }
313
314 aw_dev_err(aw883xx->dev, "IV data abnormal, please check");
315
316 return -EINVAL;
317 }
318
aw_pid_2049_dsp_fw_check(struct aw_device * aw_dev)319 static int aw_pid_2049_dsp_fw_check(struct aw_device *aw_dev)
320 {
321 struct aw_prof_desc *set_prof_desc = NULL;
322 struct aw_sec_data_desc *dsp_fw_desc = NULL;
323 uint16_t base_addr = AW_PID_2049_DSP_FW_ADDR;
324 uint16_t addr = base_addr;
325 int ret, i;
326 uint32_t dsp_val;
327 uint16_t bin_val;
328
329 aw_dev_info(aw_dev->dev, "enter");
330
331 ret = aw_dev_get_prof_data(aw_dev, aw_dev->cur_prof, &set_prof_desc);
332 if (ret < 0)
333 return ret;
334
335 /*update reg*/
336 dsp_fw_desc = &set_prof_desc->sec_desc[AW_DATA_TYPE_DSP_FW];
337
338 for (i = 0; i < AW_FW_CHECK_PART; i++) {
339 ret = aw883xx_dev_dsp_read(aw_dev, addr, &dsp_val, AW_DSP_16_DATA);
340 if (ret < 0) {
341 aw_dev_err(aw_dev->dev, "dsp read failed");
342 return ret;
343 }
344
345 bin_val = AW_GET_16_DATA(dsp_fw_desc->data[2 * (addr - base_addr)],
346 dsp_fw_desc->data[2 * (addr - base_addr) + 1]);
347
348 if (dsp_val != bin_val) {
349 aw_dev_err(aw_dev->dev, "check failed, addr[0x%x], read[0x%x] != bindata[0x%x]",
350 addr, dsp_val, bin_val);
351 return -EINVAL;
352 }
353
354 addr += (dsp_fw_desc->len / 2) / AW_FW_CHECK_PART;
355 if ((addr - base_addr) > dsp_fw_desc->len) {
356 aw_dev_err(aw_dev->dev, "check failed, addr[0x%x] too large", addr);
357 return -EINVAL;
358 }
359 }
360
361 aw_dev_info(aw_dev->dev, "dsp fw check success");
362
363 return 0;
364 }
365
aw883xx_dev_init(struct aw883xx * aw883xx)366 static int aw883xx_dev_init(struct aw883xx *aw883xx)
367 {
368 struct aw_device *aw_pa = NULL;
369
370 aw_pa = devm_kzalloc(aw883xx->dev, sizeof(struct aw_device), GFP_KERNEL);
371 if (aw_pa == NULL) {
372 aw_dev_err(aw883xx->dev, "dev kalloc failed");
373 return -ENOMEM;
374 }
375
376 /*call aw device init func*/
377 aw_pa->acf = NULL;
378 aw_pa->prof_info.prof_desc = NULL;
379 aw_pa->prof_info.count = 0;
380 aw_pa->prof_info.prof_type = AW_DEV_NONE_TYPE_ID;
381 aw_pa->channel = 0;
382 aw_pa->i2c_lock = &aw883xx->i2c_lock;
383 aw_pa->i2c = aw883xx->i2c;
384 aw_pa->fw_status = AW_DEV_FW_FAILED;
385 aw_pa->fade_step = AW_PID_2049_VOLUME_STEP_DB;
386 aw_pa->re_range.re_min_default = AW_RE_MIN;
387 aw_pa->re_range.re_max_default = AW_RE_MAX;
388 aw_pa->monitor_desc.hw_monitor_delay = AW_HW_MONITOR_DELAY;
389
390 aw_pa->chip_id = aw883xx->chip_id;
391 aw_pa->private_data = (void *)aw883xx;
392 aw_pa->dev = aw883xx->dev;
393 aw_pa->ops.aw_get_version = aw883xx_get_version;
394 aw_pa->ops.aw_i2c_writes = aw883xx_dev_i2c_writes;
395 aw_pa->ops.aw_i2c_write = aw883xx_dev_i2c_write;
396 aw_pa->ops.aw_reg_write = aw883xx_dev_reg_write;
397 aw_pa->ops.aw_reg_write_bits = aw883xx_dev_reg_write_bits;
398 aw_pa->ops.aw_i2c_read = aw883xx_dev_i2c_read;
399 aw_pa->ops.aw_reg_read = aw883xx_dev_reg_read;
400 aw_pa->ops.aw_dsp_read = aw883xx_dev_dsp_read;
401 aw_pa->ops.aw_dsp_write = aw883xx_dev_dsp_write;
402 aw_pa->ops.aw_get_dev_num = aw883xx_get_dev_num;
403
404 aw_pa->ops.aw_get_volume = aw_pid_2049_get_volume;
405 aw_pa->ops.aw_set_volume = aw_pid_2049_set_volume;
406 aw_pa->ops.aw_reg_val_to_db = aw_pid_2049_reg_val_to_db;
407 aw_pa->ops.aw_check_rd_access = aw_pid_2049_check_rd_access;
408 aw_pa->ops.aw_check_wr_access = aw_pid_2049_check_wr_access;
409 aw_pa->ops.aw_get_reg_num = aw_pid_2049_get_reg_num;
410
411 aw_pa->ops.aw_i2s_tx_enable = aw_pid_2049_i2s_tx_enable;
412 aw_pa->ops.aw_get_hw_mon_st = aw_pid_2049_get_hw_mon_st;
413
414 aw_pa->ops.aw_cali_svc_get_iv_st = aw_pid_2049_cali_get_iv_st;
415 aw_pa->ops.aw_set_cfg_f0_fs = aw_pid_2049_set_cfg_f0_fs;
416 aw_pa->ops.aw_dsp_fw_check = aw_pid_2049_dsp_fw_check;
417
418 aw_pa->int_desc.mask_reg = AW_PID_2049_SYSINTM_REG;
419 aw_pa->int_desc.mask_default = AW_PID_2049_SYSINTM_DEFAULT;
420 aw_pa->int_desc.int_mask = AW_PID_2049_SYSINTM_DEFAULT;
421 aw_pa->int_desc.st_reg = AW_PID_2049_SYSINT_REG;
422 aw_pa->int_desc.intst_mask = AW_PID_2049_BIT_SYSINT_CHECK;
423
424 aw_pa->pwd_desc.reg = AW_PID_2049_SYSCTRL_REG;
425 aw_pa->pwd_desc.mask = AW_PID_2049_PWDN_MASK;
426 aw_pa->pwd_desc.enable = AW_PID_2049_PWDN_POWER_DOWN_VALUE;
427 aw_pa->pwd_desc.disable = AW_PID_2049_PWDN_WORKING_VALUE;
428
429 aw_pa->mute_desc.reg = AW_PID_2049_SYSCTRL_REG;
430 aw_pa->mute_desc.mask = AW_PID_2049_HMUTE_MASK;
431 aw_pa->mute_desc.enable = AW_PID_2049_HMUTE_ENABLE_VALUE;
432 aw_pa->mute_desc.disable = AW_PID_2049_HMUTE_DISABLE_VALUE;
433
434 aw_pa->vcalb_desc.vcalb_dsp_reg = AW_PID_2049_DSP_REG_VCALB;
435 aw_pa->vcalb_desc.data_type = AW_DSP_16_DATA;
436 aw_pa->vcalb_desc.vcal_factor = AW_PID_2049_VCAL_FACTOR;
437 aw_pa->vcalb_desc.cabl_base_value = AW_PID_2049_CABL_BASE_VALUE;
438 aw_pa->vcalb_desc.vscal_factor = AW_PID_2049_VSCAL_FACTOR;
439 aw_pa->vcalb_desc.iscal_factor = AW_PID_2049_ISCAL_FACTOR;
440
441 aw_pa->vcalb_desc.vcalb_adj_shift = AW_PID_2049_VCALB_ADJ_FACTOR;
442
443 aw_pa->vcalb_desc.icalk_value_factor = AW_PID_2049_ICABLK_FACTOR;
444 aw_pa->vcalb_desc.icalk_reg = AW_PID_2049_EFRM2_REG;
445 aw_pa->vcalb_desc.icalk_reg_mask = AW_PID_2049_EF_ISN_GESLP_MASK;
446 aw_pa->vcalb_desc.icalk_sign_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_MASK;
447 aw_pa->vcalb_desc.icalk_neg_mask = AW_PID_2049_EF_ISN_GESLP_SIGN_NEG;
448
449 aw_pa->vcalb_desc.vcalk_reg = AW_PID_2049_EFRH_REG;
450 aw_pa->vcalb_desc.vcalk_reg_mask = AW_PID_2049_EF_VSN_GESLP_MASK;
451 aw_pa->vcalb_desc.vcalk_sign_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_MASK;
452 aw_pa->vcalb_desc.vcalk_neg_mask = AW_PID_2049_EF_VSN_GESLP_SIGN_NEG;
453 aw_pa->vcalb_desc.vcalk_value_factor = AW_PID_2049_VCABLK_FACTOR;
454 aw_pa->vcalb_desc.vcalk_shift = AW_PID_2049_EF_VSENSE_GAIN_SHIFT;
455
456 aw_pa->vcalb_desc.vcalb_vsense_reg = AW_PID_2049_I2SCFG3_REG;
457 aw_pa->vcalb_desc.vcalk_vdsel_mask = AW_PID_2049_VDSEL_MASK;
458 aw_pa->vcalb_desc.vcalk_value_factor_vsense_in = AW_PID_2049_VCABLK_FACTOR_DAC;
459 aw_pa->vcalb_desc.vscal_factor_vsense_in = AW_PID_2049_VSCAL_FACTOR_DAC;
460 aw_pa->vcalb_desc.vcalk_dac_shift = AW_PID_2049_EF_DAC_GESLP_SHIFT;
461 aw_pa->vcalb_desc.vcalk_dac_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_MASK;
462 aw_pa->vcalb_desc.vcalk_dac_neg_mask = AW_PID_2049_EF_DAC_GESLP_SIGN_NEG;
463
464 aw_pa->sysst_desc.reg = AW_PID_2049_SYSST_REG;
465 aw_pa->sysst_desc.st_check = AW_PID_2049_BIT_SYSST_CHECK;
466 aw_pa->sysst_desc.st_mask = AW_PID_2049_BIT_SYSST_CHECK_MASK;
467 aw_pa->sysst_desc.pll_check = AW_PID_2049_BIT_PLL_CHECK;
468 aw_pa->sysst_desc.dsp_check = AW_PID_2049_DSPS_NORMAL_VALUE;
469 aw_pa->sysst_desc.dsp_mask = AW_PID_2049_DSPS_MASK;
470
471 aw_pa->profctrl_desc.reg = AW_PID_2049_SYSCTRL_REG;
472 aw_pa->profctrl_desc.mask = AW_PID_2049_RCV_MODE_MASK;
473 aw_pa->profctrl_desc.rcv_mode_val = AW_PID_2049_RCV_MODE_RECEIVER_VALUE;
474
475 aw_pa->volume_desc.reg = AW_PID_2049_SYSCTRL2_REG;
476 aw_pa->volume_desc.mask = AW_PID_2049_VOL_MASK;
477 aw_pa->volume_desc.shift = AW_PID_2049_VOL_START_BIT;
478 aw_pa->volume_desc.mute_volume = AW_PID_2049_MUTE_VOL;
479
480 aw_pa->dsp_en_desc.reg = AW_PID_2049_SYSCTRL_REG;
481 aw_pa->dsp_en_desc.mask = AW_PID_2049_DSPBY_MASK;
482 aw_pa->dsp_en_desc.enable = AW_PID_2049_DSPBY_WORKING_VALUE;
483 aw_pa->dsp_en_desc.disable = AW_PID_2049_DSPBY_BYPASS_VALUE;
484
485 aw_pa->memclk_desc.reg = AW_PID_2049_DBGCTRL_REG;
486 aw_pa->memclk_desc.mask = AW_PID_2049_MEM_CLKSEL_MASK;
487 aw_pa->memclk_desc.mcu_hclk = AW_PID_2049_MEM_CLKSEL_DAP_HCLK_VALUE;
488 aw_pa->memclk_desc.osc_clk = AW_PID_2049_MEM_CLKSEL_OSC_CLK_VALUE;
489
490 aw_pa->watch_dog_desc.reg = AW_PID_2049_WDT_REG;
491 aw_pa->watch_dog_desc.mask = AW_PID_2049_WDT_CNT_MASK;
492
493 aw_pa->dsp_mem_desc.dsp_madd_reg = AW_PID_2049_DSPMADD_REG;
494 aw_pa->dsp_mem_desc.dsp_mdat_reg = AW_PID_2049_DSPMDAT_REG;
495 aw_pa->dsp_mem_desc.dsp_cfg_base_addr = AW_PID_2049_DSP_CFG_ADDR;
496 aw_pa->dsp_mem_desc.dsp_fw_base_addr = AW_PID_2049_DSP_FW_ADDR;
497
498 aw_pa->voltage_desc.reg = AW_PID_2049_VBAT_REG;
499 aw_pa->voltage_desc.vbat_range = AW_PID_2049_VBAT_RANGE;
500 aw_pa->voltage_desc.int_bit = AW_PID_2049_INT_10BIT;
501
502 aw_pa->temp_desc.reg = AW_PID_2049_TEMP_REG;
503 aw_pa->temp_desc.sign_mask = AW_PID_2049_TEMP_SIGN_MASK;
504 aw_pa->temp_desc.neg_mask = AW_PID_2049_TEMP_NEG_MASK;
505
506 aw_pa->vmax_desc.dsp_reg = AW_PID_2049_DSP_REG_VMAX;
507 aw_pa->vmax_desc.data_type = AW_DSP_16_DATA;
508
509 aw_pa->ipeak_desc.reg = AW_PID_2049_SYSCTRL2_REG;
510 aw_pa->ipeak_desc.mask = AW_PID_2049_BST_IPEAK_MASK;
511
512 aw_pa->soft_rst.reg = AW_PID_2049_ID_REG;
513 aw_pa->soft_rst.reg_value = AW_PID_2049_SOFT_RESET_VALUE;
514
515 aw_pa->dsp_vol_desc.reg = AW_PID_2049_DSPCFG_REG;
516 aw_pa->dsp_vol_desc.mask = AW_PID_2049_DSP_VOL_MASK;
517 aw_pa->dsp_vol_desc.mute_st = AW_PID_2049_DSP_VOL_MUTE;
518 aw_pa->dsp_vol_desc.noise_st = AW_PID_2049_DSP_VOL_NOISE_ST;
519
520 aw_pa->amppd_desc.reg = AW_PID_2049_SYSCTRL_REG;
521 aw_pa->amppd_desc.mask = AW_PID_2049_AMPPD_MASK;
522 aw_pa->amppd_desc.enable = AW_PID_2049_AMPPD_POWER_DOWN_VALUE;
523 aw_pa->amppd_desc.disable = AW_PID_2049_AMPPD_WORKING_VALUE;
524
525 aw_pa->spkr_temp_desc.reg = AW_PID_2049_ASR2_REG;
526
527 /*32-bit data types need bypass dsp*/
528 aw_pa->ra_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RA;
529 aw_pa->ra_desc.data_type = AW_DSP_32_DATA;
530
531 /*32-bit data types need bypass dsp*/
532 aw_pa->cali_cfg_desc.actampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_ACTAMPTH;
533 aw_pa->cali_cfg_desc.actampth_data_type = AW_DSP_32_DATA;
534
535 /*32-bit data types need bypass dsp*/
536 aw_pa->cali_cfg_desc.noiseampth_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_NOISEAMPTH;
537 aw_pa->cali_cfg_desc.noiseampth_data_type = AW_DSP_32_DATA;
538
539 aw_pa->cali_cfg_desc.ustepn_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_USTEPN;
540 aw_pa->cali_cfg_desc.ustepn_data_type = AW_DSP_16_DATA;
541
542 aw_pa->cali_cfg_desc.alphan_reg = AW_PID_2049_DSP_REG_CFG_RE_ALPHA;
543 aw_pa->cali_cfg_desc.alphan_data_type = AW_DSP_16_DATA;
544
545 /*32-bit data types need bypass dsp*/
546 aw_pa->adpz_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_ADPZ_RE;
547 aw_pa->adpz_re_desc.data_type = AW_DSP_32_DATA;
548 aw_pa->adpz_re_desc.shift = AW_PID_2049_DSP_RE_SHIFT;
549
550 aw_pa->t0_desc.dsp_reg = AW_PID_2049_DSP_CFG_ADPZ_T0;
551 aw_pa->t0_desc.data_type = AW_DSP_16_DATA;
552 aw_pa->t0_desc.coilalpha_reg = AW_PID_2049_DSP_CFG_ADPZ_COILALPHA;
553 aw_pa->t0_desc.coil_type = AW_DSP_16_DATA;
554
555 aw_pa->ste_re_desc.shift = AW_PID_2049_DSP_REG_CALRE_SHIFT;
556 aw_pa->ste_re_desc.dsp_reg = AW_PID_2049_DSP_REG_CALRE;
557 aw_pa->ste_re_desc.data_type = AW_DSP_16_DATA;
558
559 aw_pa->noise_desc.dsp_reg = AW_PID_2049_DSP_REG_CFG_MBMEC_GLBCFG;
560 aw_pa->noise_desc.data_type = AW_DSP_16_DATA;
561 aw_pa->noise_desc.mask = AW_PID_2049_DSP_REG_NOISE_MASK;
562
563 aw_pa->f0_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_F0;
564 aw_pa->f0_desc.shift = AW_PID_2049_DSP_F0_SHIFT;
565 aw_pa->f0_desc.data_type = AW_DSP_16_DATA;
566
567 /*32-bit data types need bypass dsp*/
568 aw_pa->cfgf0_fs_desc.dsp_reg = AW_PID_2049_DSP_REG_CFGF0_FS;
569 aw_pa->cfgf0_fs_desc.data_type = AW_DSP_32_DATA;
570
571 aw_pa->q_desc.dsp_reg = AW_PID_2049_DSP_REG_RESULT_Q;
572 aw_pa->q_desc.shift = AW_PID_2049_DSP_Q_SHIFT;
573 aw_pa->q_desc.data_type = AW_DSP_16_DATA;
574
575 /*32-bit data types need bypass dsp*/
576 aw_pa->dsp_crc_desc.dsp_reg = AW_PID_2049_DSP_REG_CRC_ADDR;
577 aw_pa->dsp_crc_desc.data_type = AW_DSP_32_DATA;
578
579 aw_pa->dsp_crc_desc.ctl_reg = AW_PID_2049_HAGCCFG7_REG;
580 aw_pa->dsp_crc_desc.ctl_mask = AW_PID_2049_AGC_DSP_CTL_MASK;
581 aw_pa->dsp_crc_desc.ctl_enable = AW_PID_2049_AGC_DSP_CTL_ENABLE_VALUE;
582 aw_pa->dsp_crc_desc.ctl_disable = AW_PID_2049_AGC_DSP_CTL_DISABLE_VALUE;
583
584 aw_pa->cco_mux_desc.reg = AW_PID_2049_PLLCTRL1_REG;
585 aw_pa->cco_mux_desc.mask = AW_PID_2049_CCO_MUX_MASK;
586 aw_pa->cco_mux_desc.divider = AW_PID_2049_CCO_MUX_DIVIDED_VALUE;
587 aw_pa->cco_mux_desc.bypass = AW_PID_2049_CCO_MUX_BYPASS_VALUE;
588
589 /*hw monitor temp reg*/
590 aw_pa->hw_temp_desc.dsp_reg = AW_PID_2049_DSP_REG_TEMP_ADDR;
591 aw_pa->hw_temp_desc.data_type = AW_DSP_16_DATA;
592
593 aw_pa->chansel_desc.rxchan_reg = AW_PID_2049_I2SCTRL_REG;
594 aw_pa->chansel_desc.rxchan_mask = AW_PID_2049_CHSEL_MASK;
595 aw_pa->chansel_desc.txchan_reg = AW_PID_2049_I2SCFG1_REG;
596 aw_pa->chansel_desc.txchan_mask = AW_PID_2049_I2SCHS_MASK;
597
598 aw_pa->chansel_desc.rx_left = AW_PID_2049_CHSEL_LEFT_VALUE;
599 aw_pa->chansel_desc.rx_right = AW_PID_2049_CHSEL_RIGHT_VALUE;
600 aw_pa->chansel_desc.tx_left = AW_PID_2049_I2SCHS_LEFT_VALUE;
601 aw_pa->chansel_desc.tx_right = AW_PID_2049_I2SCHS_RIGHT_VALUE;
602
603 aw_pa->tx_en_desc.tx_en_mask = AW_PID_2049_I2STXEN_MASK;
604 aw_pa->tx_en_desc.tx_disable = AW_PID_2049_I2STXEN_DISABLE_VALUE;
605
606 aw_pa->cali_delay_desc.dsp_reg = AW_PID_2049_DSP_CALI_F0_DELAY;
607 aw_pa->cali_delay_desc.data_type = AW_DSP_16_DATA;
608
609 aw_pa->dsp_st_desc.dsp_reg_s1 = AW_PID_2049_DSP_ST_S1;
610 aw_pa->dsp_st_desc.dsp_reg_e1 = AW_PID_2049_DSP_ST_E1;
611 aw_pa->dsp_st_desc.dsp_reg_s2 = AW_PID_2049_DSP_ST_S2;
612 aw_pa->dsp_st_desc.dsp_reg_e2 = AW_PID_2049_DSP_ST_E2;
613
614 aw_device_probe(aw_pa);
615
616 aw883xx->aw_pa = aw_pa;
617
618 return 0;
619 }
620
aw883xx_init(struct aw883xx * aw883xx)621 int aw883xx_init(struct aw883xx *aw883xx)
622 {
623 if (aw883xx->chip_id == AW883XX_PID_2049) {
624 return aw883xx_dev_init(aw883xx);
625 } else {
626 aw_dev_err(aw883xx->dev, "unsupported device");
627 return -EINVAL;
628 }
629 }
630
631