1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef __AW_DEVICE_H__ 4*4882a593Smuzhiyun #define __AW_DEVICE_H__ 5*4882a593Smuzhiyun #include <linux/version.h> 6*4882a593Smuzhiyun #include <linux/kernel.h> 7*4882a593Smuzhiyun #include <sound/control.h> 8*4882a593Smuzhiyun #include <sound/soc.h> 9*4882a593Smuzhiyun #include "aw_acf_bin.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define AW87XXX_PID_9B_PRODUCT_MAX (1) 12*4882a593Smuzhiyun #define AW87XXX_PID_39_PRODUCT_MAX (3) 13*4882a593Smuzhiyun #define AW87XXX_PID_59_3X9_PRODUCT_MAX (2) 14*4882a593Smuzhiyun #define AW87XXX_PID_59_5X9_PRODUCT_MAX (4) 15*4882a593Smuzhiyun #define AW87XXX_PID_5A_PRODUCT_MAX (5) 16*4882a593Smuzhiyun #define AW87XXX_PID_76_PROFUCT_MAX (3) 17*4882a593Smuzhiyun #define AW_PRODUCT_NAME_LEN (8) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define AW_GPIO_HIGHT_LEVEL (1) 20*4882a593Smuzhiyun #define AW_GPIO_LOW_LEVEL (0) 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define AW_I2C_RETRIES (5) 23*4882a593Smuzhiyun #define AW_I2C_RETRY_DELAY (2) 24*4882a593Smuzhiyun #define AW_I2C_READ_MSG_NUM (2) 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define AW_READ_CHIPID_RETRIES (5) 27*4882a593Smuzhiyun #define AW_READ_CHIPID_RETRY_DELAY (2) 28*4882a593Smuzhiyun #define AW_DEV_REG_CHIPID (0x00) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define AW_DEV_REG_INVALID_MASK (0xff) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define AW_NO_RESET_GPIO (-1) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AW_PID_9B_BIN_REG_CFG_COUNT (10) 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /******************************************** 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * aw87xxx devices attributes 39*4882a593Smuzhiyun * 40*4882a593Smuzhiyun *******************************************/ 41*4882a593Smuzhiyun struct aw_device; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct aw_device_ops { 44*4882a593Smuzhiyun int (*pwr_on_func)(struct aw_device *aw_dev, struct aw_data_container *data); 45*4882a593Smuzhiyun int (*pwr_off_func)(struct aw_device *aw_dev, struct aw_data_container *data); 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun enum aw_dev_chipid { 49*4882a593Smuzhiyun AW_DEV_CHIPID_18 = 0x18, 50*4882a593Smuzhiyun AW_DEV_CHIPID_39 = 0x39, 51*4882a593Smuzhiyun AW_DEV_CHIPID_59 = 0x59, 52*4882a593Smuzhiyun AW_DEV_CHIPID_69 = 0x69, 53*4882a593Smuzhiyun AW_DEV_CHIPID_5A = 0x5A, 54*4882a593Smuzhiyun AW_DEV_CHIPID_9A = 0x9A, 55*4882a593Smuzhiyun AW_DEV_CHIPID_9B = 0x9B, 56*4882a593Smuzhiyun AW_DEV_CHIPID_76 = 0x76, 57*4882a593Smuzhiyun }; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun enum aw_dev_hw_status { 60*4882a593Smuzhiyun AW_DEV_HWEN_OFF = 0, 61*4882a593Smuzhiyun AW_DEV_HWEN_ON, 62*4882a593Smuzhiyun AW_DEV_HWEN_INVALID, 63*4882a593Smuzhiyun AW_DEV_HWEN_STATUS_MAX, 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun enum aw_dev_soft_off_enable { 67*4882a593Smuzhiyun AW_DEV_SOFT_OFF_DISENABLE = 0, 68*4882a593Smuzhiyun AW_DEV_SOFT_OFF_ENABLE = 1, 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun enum aw_dev_soft_rst_enable { 72*4882a593Smuzhiyun AW_DEV_SOFT_RST_DISENABLE = 0, 73*4882a593Smuzhiyun AW_DEV_SOFT_RST_ENABLE = 1, 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun enum aw_reg_receiver_mode { 77*4882a593Smuzhiyun AW_NOT_REC_MODE = 0, 78*4882a593Smuzhiyun AW_IS_REC_MODE = 1, 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct aw_mute_desc { 82*4882a593Smuzhiyun uint8_t addr; 83*4882a593Smuzhiyun uint8_t enable; 84*4882a593Smuzhiyun uint8_t disable; 85*4882a593Smuzhiyun uint16_t mask; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun struct aw_soft_rst_desc { 89*4882a593Smuzhiyun int len; 90*4882a593Smuzhiyun unsigned char *access; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct aw_esd_check_desc { 94*4882a593Smuzhiyun uint8_t first_update_reg_addr; 95*4882a593Smuzhiyun uint8_t first_update_reg_val; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct aw_rec_mode_desc { 99*4882a593Smuzhiyun uint8_t addr; 100*4882a593Smuzhiyun uint8_t enable; 101*4882a593Smuzhiyun uint8_t disable; 102*4882a593Smuzhiyun uint8_t mask; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun struct aw_device { 106*4882a593Smuzhiyun uint8_t i2c_addr; 107*4882a593Smuzhiyun uint8_t chipid; 108*4882a593Smuzhiyun uint8_t soft_rst_enable; 109*4882a593Smuzhiyun uint8_t soft_off_enable; 110*4882a593Smuzhiyun uint8_t is_rec_mode; 111*4882a593Smuzhiyun int hwen_status; 112*4882a593Smuzhiyun int i2c_bus; 113*4882a593Smuzhiyun int rst_gpio; 114*4882a593Smuzhiyun int rst_shared_gpio; 115*4882a593Smuzhiyun int reg_max_addr; 116*4882a593Smuzhiyun int product_cnt; 117*4882a593Smuzhiyun const char **product_tab; 118*4882a593Smuzhiyun const unsigned char *reg_access; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun struct device *dev; 121*4882a593Smuzhiyun struct i2c_client *i2c; 122*4882a593Smuzhiyun struct aw_mute_desc mute_desc; 123*4882a593Smuzhiyun struct aw_soft_rst_desc soft_rst_desc; 124*4882a593Smuzhiyun struct aw_esd_check_desc esd_desc; 125*4882a593Smuzhiyun struct aw_rec_mode_desc rec_desc; 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun struct aw_device_ops ops; 128*4882a593Smuzhiyun }; 129*4882a593Smuzhiyun 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun int aw_dev_i2c_write_byte(struct aw_device *aw_dev, 132*4882a593Smuzhiyun uint8_t reg_addr, uint8_t reg_data); 133*4882a593Smuzhiyun int aw_dev_i2c_read_byte(struct aw_device *aw_dev, 134*4882a593Smuzhiyun uint8_t reg_addr, uint8_t *reg_data); 135*4882a593Smuzhiyun int aw_dev_i2c_read_msg(struct aw_device *aw_dev, 136*4882a593Smuzhiyun uint8_t reg_addr, uint8_t *data_buf, uint32_t data_len); 137*4882a593Smuzhiyun int aw_dev_i2c_write_bits(struct aw_device *aw_dev, 138*4882a593Smuzhiyun uint8_t reg_addr, uint8_t mask, uint8_t reg_data); 139*4882a593Smuzhiyun void aw_dev_soft_reset(struct aw_device *aw_dev); 140*4882a593Smuzhiyun void aw_dev_hw_pwr_ctrl(struct aw_device *aw_dev, bool enable); 141*4882a593Smuzhiyun int aw_dev_default_profile_check(struct aw_device *aw_dev, 142*4882a593Smuzhiyun int profile, struct aw_data_container *profile_data); 143*4882a593Smuzhiyun int aw_dev_default_pwr_on(struct aw_device *aw_dev, 144*4882a593Smuzhiyun struct aw_data_container *profile_data); 145*4882a593Smuzhiyun int aw_dev_default_pwr_off(struct aw_device *aw_dev, 146*4882a593Smuzhiyun struct aw_data_container *profile_data); 147*4882a593Smuzhiyun int aw_dev_esd_reg_status_check(struct aw_device *aw_dev); 148*4882a593Smuzhiyun int aw_dev_check_reg_is_rec_mode(struct aw_device *aw_dev); 149*4882a593Smuzhiyun int aw_dev_init(struct aw_device *aw_dev); 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #endif 152