xref: /OK3568_Linux_fs/kernel/sound/soc/codecs/aw87xxx/aw_device.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * aw_device.c  aw87xxx pa module
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Copyright (c) 2021 AWINIC Technology CO., LTD
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Author: Barry <zhaozhongbo@awinic.com>
7*4882a593Smuzhiyun  *
8*4882a593Smuzhiyun  * This program is free software; you can redistribute  it and/or modify it
9*4882a593Smuzhiyun  * under  the terms of  the GNU General  Public License as published by the
10*4882a593Smuzhiyun  * Free Software Foundation;  either version 2 of the  License, or (at your
11*4882a593Smuzhiyun  * option) any later version.
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <linux/i2c.h>
16*4882a593Smuzhiyun #include <linux/gpio.h>
17*4882a593Smuzhiyun #include <linux/of_gpio.h>
18*4882a593Smuzhiyun #include <linux/interrupt.h>
19*4882a593Smuzhiyun #include <linux/delay.h>
20*4882a593Smuzhiyun #include <linux/kernel.h>
21*4882a593Smuzhiyun #include <linux/device.h>
22*4882a593Smuzhiyun #include <linux/irq.h>
23*4882a593Smuzhiyun #include <linux/io.h>
24*4882a593Smuzhiyun #include <linux/init.h>
25*4882a593Smuzhiyun #include <linux/timer.h>
26*4882a593Smuzhiyun #include "aw87xxx.h"
27*4882a593Smuzhiyun #include "aw_device.h"
28*4882a593Smuzhiyun #include "aw_log.h"
29*4882a593Smuzhiyun #include "aw87xxx_pid_9b_reg.h"
30*4882a593Smuzhiyun #include "aw87xxx_pid_18_reg.h"
31*4882a593Smuzhiyun #include "aw87xxx_pid_39_reg.h"
32*4882a593Smuzhiyun #include "aw87xxx_pid_59_3x9_reg.h"
33*4882a593Smuzhiyun #include "aw87xxx_pid_59_5x9_reg.h"
34*4882a593Smuzhiyun #include "aw87xxx_pid_5a_reg.h"
35*4882a593Smuzhiyun #include "aw87xxx_pid_76_reg.h"
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /*************************************************************************
38*4882a593Smuzhiyun  * aw87xxx variable
39*4882a593Smuzhiyun  ************************************************************************/
40*4882a593Smuzhiyun const char *g_aw_pid_9b_product[] = {
41*4882a593Smuzhiyun 	"aw87319",
42*4882a593Smuzhiyun };
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun const char *g_aw_pid_39_product[] = {
45*4882a593Smuzhiyun 	"aw87329",
46*4882a593Smuzhiyun 	"aw87339",
47*4882a593Smuzhiyun 	"aw87349",
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun const char *g_aw_pid_59_3x9_product[] = {
51*4882a593Smuzhiyun 	"aw87359",
52*4882a593Smuzhiyun 	"aw87389",
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun const char *g_aw_pid_59_5x9_product[] = {
56*4882a593Smuzhiyun 	"aw87509",
57*4882a593Smuzhiyun 	"aw87519",
58*4882a593Smuzhiyun 	"aw87529",
59*4882a593Smuzhiyun 	"aw87539",
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun 
62*4882a593Smuzhiyun const char *g_aw_pid_5a_product[] = {
63*4882a593Smuzhiyun 	"aw87549",
64*4882a593Smuzhiyun 	"aw87559",
65*4882a593Smuzhiyun 	"aw87569",
66*4882a593Smuzhiyun 	"aw87579",
67*4882a593Smuzhiyun 	"aw81509",
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun const char *g_aw_pid_76_product[] = {
71*4882a593Smuzhiyun 	"aw87390",
72*4882a593Smuzhiyun 	"aw87320",
73*4882a593Smuzhiyun 	"aw87401",
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun static int aw_dev_get_chipid(struct aw_device *aw_dev);
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun /***************************************************************************
79*4882a593Smuzhiyun  *
80*4882a593Smuzhiyun  * reading and writing of I2C bus
81*4882a593Smuzhiyun  *
82*4882a593Smuzhiyun  ***************************************************************************/
aw_dev_i2c_write_byte(struct aw_device * aw_dev,uint8_t reg_addr,uint8_t reg_data)83*4882a593Smuzhiyun int aw_dev_i2c_write_byte(struct aw_device *aw_dev,
84*4882a593Smuzhiyun 			uint8_t reg_addr, uint8_t reg_data)
85*4882a593Smuzhiyun {
86*4882a593Smuzhiyun 	int ret = -1;
87*4882a593Smuzhiyun 	unsigned char cnt = 0;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	while (cnt < AW_I2C_RETRIES) {
90*4882a593Smuzhiyun 		ret = i2c_smbus_write_byte_data(aw_dev->i2c, reg_addr, reg_data);
91*4882a593Smuzhiyun 		if (ret < 0)
92*4882a593Smuzhiyun 			AW_DEV_LOGE(aw_dev->dev, "i2c_write cnt=%d error=%d",
93*4882a593Smuzhiyun 				cnt, ret);
94*4882a593Smuzhiyun 		else
95*4882a593Smuzhiyun 			break;
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun 		cnt++;
98*4882a593Smuzhiyun 		msleep(AW_I2C_RETRY_DELAY);
99*4882a593Smuzhiyun 	}
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return ret;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
aw_dev_i2c_read_byte(struct aw_device * aw_dev,uint8_t reg_addr,uint8_t * reg_data)104*4882a593Smuzhiyun int aw_dev_i2c_read_byte(struct aw_device *aw_dev,
105*4882a593Smuzhiyun 			uint8_t reg_addr, uint8_t *reg_data)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun 	int ret = -1;
108*4882a593Smuzhiyun 	unsigned char cnt = 0;
109*4882a593Smuzhiyun 
110*4882a593Smuzhiyun 	while (cnt < AW_I2C_RETRIES) {
111*4882a593Smuzhiyun 		ret = i2c_smbus_read_byte_data(aw_dev->i2c, reg_addr);
112*4882a593Smuzhiyun 		if (ret < 0) {
113*4882a593Smuzhiyun 			AW_DEV_LOGE(aw_dev->dev, "i2c_read cnt=%d error=%d",
114*4882a593Smuzhiyun 				cnt, ret);
115*4882a593Smuzhiyun 		} else {
116*4882a593Smuzhiyun 			*reg_data = ret;
117*4882a593Smuzhiyun 			break;
118*4882a593Smuzhiyun 		}
119*4882a593Smuzhiyun 		cnt++;
120*4882a593Smuzhiyun 		msleep(AW_I2C_RETRY_DELAY);
121*4882a593Smuzhiyun 	}
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	return ret;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
aw_dev_i2c_read_msg(struct aw_device * aw_dev,uint8_t reg_addr,uint8_t * data_buf,uint32_t data_len)126*4882a593Smuzhiyun int aw_dev_i2c_read_msg(struct aw_device *aw_dev,
127*4882a593Smuzhiyun 	uint8_t reg_addr, uint8_t *data_buf, uint32_t data_len)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun 	int ret = -1;
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun 	struct i2c_msg msg[] = {
132*4882a593Smuzhiyun 	[0] = {
133*4882a593Smuzhiyun 		.addr = aw_dev->i2c_addr,
134*4882a593Smuzhiyun 		.flags = 0,
135*4882a593Smuzhiyun 		.len = sizeof(uint8_t),
136*4882a593Smuzhiyun 		.buf = &reg_addr,
137*4882a593Smuzhiyun 		},
138*4882a593Smuzhiyun 	[1] = {
139*4882a593Smuzhiyun 		.addr = aw_dev->i2c_addr,
140*4882a593Smuzhiyun 		.flags = I2C_M_RD,
141*4882a593Smuzhiyun 		.len = data_len,
142*4882a593Smuzhiyun 		.buf = data_buf,
143*4882a593Smuzhiyun 		},
144*4882a593Smuzhiyun 	};
145*4882a593Smuzhiyun 
146*4882a593Smuzhiyun 	ret = i2c_transfer(aw_dev->i2c->adapter, msg, ARRAY_SIZE(msg));
147*4882a593Smuzhiyun 	if (ret < 0) {
148*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "transfer failed");
149*4882a593Smuzhiyun 		return ret;
150*4882a593Smuzhiyun 	} else if (ret != AW_I2C_READ_MSG_NUM) {
151*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "transfer failed(size error)");
152*4882a593Smuzhiyun 		return -ENXIO;
153*4882a593Smuzhiyun 	}
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun 	return 0;
156*4882a593Smuzhiyun }
157*4882a593Smuzhiyun 
aw_dev_i2c_write_bits(struct aw_device * aw_dev,uint8_t reg_addr,uint8_t mask,uint8_t reg_data)158*4882a593Smuzhiyun int aw_dev_i2c_write_bits(struct aw_device *aw_dev,
159*4882a593Smuzhiyun 	uint8_t reg_addr, uint8_t mask, uint8_t reg_data)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun 	int ret = -1;
162*4882a593Smuzhiyun 	unsigned char reg_val = 0;
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	ret = aw_dev_i2c_read_byte(aw_dev, reg_addr, &reg_val);
165*4882a593Smuzhiyun 	if (ret < 0) {
166*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "i2c read error, ret=%d", ret);
167*4882a593Smuzhiyun 		return ret;
168*4882a593Smuzhiyun 	}
169*4882a593Smuzhiyun 	reg_val &= mask;
170*4882a593Smuzhiyun 	reg_val |= reg_data;
171*4882a593Smuzhiyun 	ret = aw_dev_i2c_write_byte(aw_dev, reg_addr, reg_val);
172*4882a593Smuzhiyun 	if (ret < 0) {
173*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "i2c write error, ret=%d", ret);
174*4882a593Smuzhiyun 		return ret;
175*4882a593Smuzhiyun 	}
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun 	return 0;
178*4882a593Smuzhiyun }
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /************************************************************************
181*4882a593Smuzhiyun  *
182*4882a593Smuzhiyun  * aw87xxx device update profile data to registers
183*4882a593Smuzhiyun  *
184*4882a593Smuzhiyun  ************************************************************************/
aw_dev_reg_update(struct aw_device * aw_dev,struct aw_data_container * profile_data)185*4882a593Smuzhiyun static int aw_dev_reg_update(struct aw_device *aw_dev,
186*4882a593Smuzhiyun 			struct aw_data_container *profile_data)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun 	int i = 0;
189*4882a593Smuzhiyun 	int ret = -1;
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	if (profile_data == NULL)
192*4882a593Smuzhiyun 		return -EINVAL;
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) {
195*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "dev is pwr_off,can not update reg");
196*4882a593Smuzhiyun 		return -EINVAL;
197*4882a593Smuzhiyun 	}
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	for (i = 0; i < profile_data->len; i = i + 2) {
200*4882a593Smuzhiyun 		AW_DEV_LOGI(aw_dev->dev, "reg=0x%02x, val = 0x%02x",
201*4882a593Smuzhiyun 			profile_data->data[i], profile_data->data[i + 1]);
202*4882a593Smuzhiyun 
203*4882a593Smuzhiyun 		ret = aw_dev_i2c_write_byte(aw_dev, profile_data->data[i],
204*4882a593Smuzhiyun 				profile_data->data[i + 1]);
205*4882a593Smuzhiyun 		if (ret < 0)
206*4882a593Smuzhiyun 			return ret;
207*4882a593Smuzhiyun 	}
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	return 0;
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun 
aw_dev_reg_mute_bits_set(struct aw_device * aw_dev,uint8_t * reg_val,bool enable)212*4882a593Smuzhiyun static void aw_dev_reg_mute_bits_set(struct aw_device *aw_dev,
213*4882a593Smuzhiyun 				uint8_t *reg_val, bool enable)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	if (enable) {
216*4882a593Smuzhiyun 		*reg_val &= aw_dev->mute_desc.mask;
217*4882a593Smuzhiyun 		*reg_val |= aw_dev->mute_desc.enable;
218*4882a593Smuzhiyun 	} else {
219*4882a593Smuzhiyun 		*reg_val &= aw_dev->mute_desc.mask;
220*4882a593Smuzhiyun 		*reg_val |= aw_dev->mute_desc.disable;
221*4882a593Smuzhiyun 	}
222*4882a593Smuzhiyun }
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun /************************************************************************
225*4882a593Smuzhiyun  *
226*4882a593Smuzhiyun  * aw87xxx device hadware and soft contols
227*4882a593Smuzhiyun  *
228*4882a593Smuzhiyun  ************************************************************************/
aw_dev_gpio_is_valid(struct aw_device * aw_dev)229*4882a593Smuzhiyun static bool aw_dev_gpio_is_valid(struct aw_device *aw_dev)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun 	if (gpio_is_valid(aw_dev->rst_gpio))
232*4882a593Smuzhiyun 		return true;
233*4882a593Smuzhiyun 	else
234*4882a593Smuzhiyun 		return false;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun 
aw_dev_hw_pwr_ctrl(struct aw_device * aw_dev,bool enable)237*4882a593Smuzhiyun void aw_dev_hw_pwr_ctrl(struct aw_device *aw_dev, bool enable)
238*4882a593Smuzhiyun {
239*4882a593Smuzhiyun 	if (aw_dev->hwen_status == AW_DEV_HWEN_INVALID) {
240*4882a593Smuzhiyun 		AW_DEV_LOGD(aw_dev->dev, "product not have reset-pin,hardware pwd control invalid");
241*4882a593Smuzhiyun 		return;
242*4882a593Smuzhiyun 	}
243*4882a593Smuzhiyun 	if (enable) {
244*4882a593Smuzhiyun 		if (aw_dev_gpio_is_valid(aw_dev)) {
245*4882a593Smuzhiyun 			gpio_set_value_cansleep(aw_dev->rst_gpio, AW_GPIO_LOW_LEVEL);
246*4882a593Smuzhiyun 			mdelay(2);
247*4882a593Smuzhiyun 			gpio_set_value_cansleep(aw_dev->rst_gpio, AW_GPIO_HIGHT_LEVEL);
248*4882a593Smuzhiyun 			mdelay(2);
249*4882a593Smuzhiyun 			aw_dev->hwen_status = AW_DEV_HWEN_ON;
250*4882a593Smuzhiyun 			AW_DEV_LOGI(aw_dev->dev, "hw power on");
251*4882a593Smuzhiyun 		} else {
252*4882a593Smuzhiyun 			AW_DEV_LOGI(aw_dev->dev, "hw already power on");
253*4882a593Smuzhiyun 		}
254*4882a593Smuzhiyun 	} else {
255*4882a593Smuzhiyun 		if (aw_dev_gpio_is_valid(aw_dev)) {
256*4882a593Smuzhiyun 			gpio_set_value_cansleep(aw_dev->rst_gpio, AW_GPIO_LOW_LEVEL);
257*4882a593Smuzhiyun 			mdelay(2);
258*4882a593Smuzhiyun 			aw_dev->hwen_status = AW_DEV_HWEN_OFF;
259*4882a593Smuzhiyun 			AW_DEV_LOGI(aw_dev->dev, "hw power off");
260*4882a593Smuzhiyun 		} else {
261*4882a593Smuzhiyun 			AW_DEV_LOGI(aw_dev->dev, "hw already power off");
262*4882a593Smuzhiyun 		}
263*4882a593Smuzhiyun 	}
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun 
aw_dev_mute_ctrl(struct aw_device * aw_dev,bool enable)266*4882a593Smuzhiyun int aw_dev_mute_ctrl(struct aw_device *aw_dev, bool enable)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun 	int ret = 0;
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	if (enable) {
271*4882a593Smuzhiyun 		ret = aw_dev_i2c_write_bits(aw_dev, aw_dev->mute_desc.addr,
272*4882a593Smuzhiyun 				aw_dev->mute_desc.mask, aw_dev->mute_desc.enable);
273*4882a593Smuzhiyun 		if (ret < 0)
274*4882a593Smuzhiyun 			return ret;
275*4882a593Smuzhiyun 		AW_DEV_LOGI(aw_dev->dev, "set mute down");
276*4882a593Smuzhiyun 	} else {
277*4882a593Smuzhiyun 		ret = aw_dev_i2c_write_bits(aw_dev, aw_dev->mute_desc.addr,
278*4882a593Smuzhiyun 				aw_dev->mute_desc.mask, aw_dev->mute_desc.disable);
279*4882a593Smuzhiyun 		if (ret < 0)
280*4882a593Smuzhiyun 			return ret;
281*4882a593Smuzhiyun 		AW_DEV_LOGI(aw_dev->dev, "close mute down");
282*4882a593Smuzhiyun 	}
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun 	return 0;
285*4882a593Smuzhiyun }
286*4882a593Smuzhiyun 
aw_dev_soft_reset(struct aw_device * aw_dev)287*4882a593Smuzhiyun void aw_dev_soft_reset(struct aw_device *aw_dev)
288*4882a593Smuzhiyun {
289*4882a593Smuzhiyun 	int i = 0;
290*4882a593Smuzhiyun 	int ret = -1;
291*4882a593Smuzhiyun 	struct aw_soft_rst_desc *soft_rst = &aw_dev->soft_rst_desc;
292*4882a593Smuzhiyun 
293*4882a593Smuzhiyun 	AW_DEV_LOGD(aw_dev->dev, "enter");
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) {
296*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "hw is off,can not softrst");
297*4882a593Smuzhiyun 		return;
298*4882a593Smuzhiyun 	}
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	if (aw_dev->soft_rst_enable == AW_DEV_SOFT_RST_DISENABLE) {
301*4882a593Smuzhiyun 		AW_DEV_LOGD(aw_dev->dev, "softrst is disenable");
302*4882a593Smuzhiyun 		return;
303*4882a593Smuzhiyun 	}
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	if (soft_rst->access == NULL || soft_rst->len == 0) {
306*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "softrst_info not init");
307*4882a593Smuzhiyun 		return;
308*4882a593Smuzhiyun 	}
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	if (soft_rst->len % 2) {
311*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "softrst data_len[%d] is odd number,data not available",
312*4882a593Smuzhiyun 			aw_dev->soft_rst_desc.len);
313*4882a593Smuzhiyun 		return;
314*4882a593Smuzhiyun 	}
315*4882a593Smuzhiyun 
316*4882a593Smuzhiyun 	for (i = 0; i < soft_rst->len / sizeof(uint8_t); i += 2) {
317*4882a593Smuzhiyun 		AW_DEV_LOGD(aw_dev->dev, "softrst_reg=0x%02x, val = 0x%02x",
318*4882a593Smuzhiyun 			soft_rst->access[i], soft_rst->access[i + 1]);
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun 		ret = aw_dev_i2c_write_byte(aw_dev, soft_rst->access[i],
321*4882a593Smuzhiyun 				soft_rst->access[i + 1]);
322*4882a593Smuzhiyun 		if (ret < 0) {
323*4882a593Smuzhiyun 			AW_DEV_LOGE(aw_dev->dev, "write failed,ret = %d,cnt=%d",
324*4882a593Smuzhiyun 				ret, i);
325*4882a593Smuzhiyun 			return;
326*4882a593Smuzhiyun 		}
327*4882a593Smuzhiyun 	}
328*4882a593Smuzhiyun 	AW_DEV_LOGD(aw_dev->dev, "down");
329*4882a593Smuzhiyun }
330*4882a593Smuzhiyun 
331*4882a593Smuzhiyun 
aw_dev_default_pwr_off(struct aw_device * aw_dev,struct aw_data_container * profile_data)332*4882a593Smuzhiyun int aw_dev_default_pwr_off(struct aw_device *aw_dev,
333*4882a593Smuzhiyun 		struct aw_data_container *profile_data)
334*4882a593Smuzhiyun {
335*4882a593Smuzhiyun 	int ret = 0;
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 	AW_DEV_LOGD(aw_dev->dev, "enter");
338*4882a593Smuzhiyun 	if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) {
339*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "hwen is already off");
340*4882a593Smuzhiyun 		return 0;
341*4882a593Smuzhiyun 	}
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	if (aw_dev->soft_off_enable && profile_data) {
344*4882a593Smuzhiyun 		ret = aw_dev_reg_update(aw_dev, profile_data);
345*4882a593Smuzhiyun 		if (ret < 0) {
346*4882a593Smuzhiyun 			AW_DEV_LOGE(aw_dev->dev, "update profile[Off] fw config failed");
347*4882a593Smuzhiyun 			goto reg_off_update_failed;
348*4882a593Smuzhiyun 		}
349*4882a593Smuzhiyun 	}
350*4882a593Smuzhiyun 
351*4882a593Smuzhiyun 	aw_dev_hw_pwr_ctrl(aw_dev, false);
352*4882a593Smuzhiyun 	AW_DEV_LOGD(aw_dev->dev, "down");
353*4882a593Smuzhiyun 	return 0;
354*4882a593Smuzhiyun 
355*4882a593Smuzhiyun reg_off_update_failed:
356*4882a593Smuzhiyun 	aw_dev_hw_pwr_ctrl(aw_dev, false);
357*4882a593Smuzhiyun 	return ret;
358*4882a593Smuzhiyun }
359*4882a593Smuzhiyun 
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun /************************************************************************
362*4882a593Smuzhiyun  *
363*4882a593Smuzhiyun  * aw87xxx device power on process function
364*4882a593Smuzhiyun  *
365*4882a593Smuzhiyun  ************************************************************************/
366*4882a593Smuzhiyun 
aw_dev_default_pwr_on(struct aw_device * aw_dev,struct aw_data_container * profile_data)367*4882a593Smuzhiyun int aw_dev_default_pwr_on(struct aw_device *aw_dev,
368*4882a593Smuzhiyun 			struct aw_data_container *profile_data)
369*4882a593Smuzhiyun {
370*4882a593Smuzhiyun 	int ret = 0;
371*4882a593Smuzhiyun 
372*4882a593Smuzhiyun 	/*hw power on*/
373*4882a593Smuzhiyun 	aw_dev_hw_pwr_ctrl(aw_dev, true);
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun 	ret = aw_dev_reg_update(aw_dev, profile_data);
376*4882a593Smuzhiyun 	if (ret < 0)
377*4882a593Smuzhiyun 		return ret;
378*4882a593Smuzhiyun 
379*4882a593Smuzhiyun 	return 0;
380*4882a593Smuzhiyun }
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun /****************************************************************************
383*4882a593Smuzhiyun  *
384*4882a593Smuzhiyun  * aw87xxx chip esd status check
385*4882a593Smuzhiyun  *
386*4882a593Smuzhiyun  ****************************************************************************/
aw_dev_esd_reg_status_check(struct aw_device * aw_dev)387*4882a593Smuzhiyun int aw_dev_esd_reg_status_check(struct aw_device *aw_dev)
388*4882a593Smuzhiyun {
389*4882a593Smuzhiyun 	int ret;
390*4882a593Smuzhiyun 	unsigned char reg_val = 0;
391*4882a593Smuzhiyun 	struct aw_esd_check_desc *esd_desc = &aw_dev->esd_desc;
392*4882a593Smuzhiyun 
393*4882a593Smuzhiyun 	AW_DEV_LOGD(aw_dev->dev, "enter");
394*4882a593Smuzhiyun 
395*4882a593Smuzhiyun 	if (!esd_desc->first_update_reg_addr) {
396*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "esd check info if not init,please check");
397*4882a593Smuzhiyun 		return -EINVAL;
398*4882a593Smuzhiyun 	}
399*4882a593Smuzhiyun 
400*4882a593Smuzhiyun 	ret = aw_dev_i2c_read_byte(aw_dev, esd_desc->first_update_reg_addr,
401*4882a593Smuzhiyun 			&reg_val);
402*4882a593Smuzhiyun 	if (ret < 0) {
403*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "read reg 0x%02x failed",
404*4882a593Smuzhiyun 			esd_desc->first_update_reg_addr);
405*4882a593Smuzhiyun 		return ret;
406*4882a593Smuzhiyun 	}
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun 	AW_DEV_LOGD(aw_dev->dev, "0x%02x:default val=0x%02x real val=0x%02x",
409*4882a593Smuzhiyun 		esd_desc->first_update_reg_addr,
410*4882a593Smuzhiyun 		esd_desc->first_update_reg_val, reg_val);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun 	if (reg_val == esd_desc->first_update_reg_val) {
413*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "reg status check failed");
414*4882a593Smuzhiyun 		return -EINVAL;
415*4882a593Smuzhiyun 	}
416*4882a593Smuzhiyun 	return 0;
417*4882a593Smuzhiyun }
418*4882a593Smuzhiyun 
aw_dev_check_reg_is_rec_mode(struct aw_device * aw_dev)419*4882a593Smuzhiyun int aw_dev_check_reg_is_rec_mode(struct aw_device *aw_dev)
420*4882a593Smuzhiyun {
421*4882a593Smuzhiyun 	int ret;
422*4882a593Smuzhiyun 	unsigned char reg_val = 0;
423*4882a593Smuzhiyun 	struct aw_rec_mode_desc *rec_desc = &aw_dev->rec_desc;
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	if (!rec_desc->addr) {
426*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "rec check info if not init,please check");
427*4882a593Smuzhiyun 		return -EINVAL;
428*4882a593Smuzhiyun 	}
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun 	ret = aw_dev_i2c_read_byte(aw_dev, rec_desc->addr, &reg_val);
431*4882a593Smuzhiyun 	if (ret < 0) {
432*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "read reg 0x%02x failed",
433*4882a593Smuzhiyun 			rec_desc->addr);
434*4882a593Smuzhiyun 		return ret;
435*4882a593Smuzhiyun 	}
436*4882a593Smuzhiyun 
437*4882a593Smuzhiyun 	if (rec_desc->enable) {
438*4882a593Smuzhiyun 		if (reg_val & ~(rec_desc->mask)) {
439*4882a593Smuzhiyun 			AW_DEV_LOGI(aw_dev->dev, "reg status is receiver mode");
440*4882a593Smuzhiyun 			aw_dev->is_rec_mode = AW_IS_REC_MODE;
441*4882a593Smuzhiyun 		} else {
442*4882a593Smuzhiyun 			aw_dev->is_rec_mode = AW_NOT_REC_MODE;
443*4882a593Smuzhiyun 		}
444*4882a593Smuzhiyun 	} else {
445*4882a593Smuzhiyun 		if (!(reg_val & ~(rec_desc->mask))) {
446*4882a593Smuzhiyun 			AW_DEV_LOGI(aw_dev->dev, "reg status is receiver mode");
447*4882a593Smuzhiyun 			aw_dev->is_rec_mode = AW_IS_REC_MODE;
448*4882a593Smuzhiyun 		} else {
449*4882a593Smuzhiyun 			aw_dev->is_rec_mode = AW_NOT_REC_MODE;
450*4882a593Smuzhiyun 		}
451*4882a593Smuzhiyun 	}
452*4882a593Smuzhiyun 	return 0;
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun 
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun /****************************************************************************
457*4882a593Smuzhiyun  *
458*4882a593Smuzhiyun  * aw87xxx product attributes init info
459*4882a593Smuzhiyun  *
460*4882a593Smuzhiyun  ****************************************************************************/
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun /********************** aw87xxx_pid_9A attributes ***************************/
463*4882a593Smuzhiyun 
aw_dev_pid_9b_reg_update(struct aw_device * aw_dev,struct aw_data_container * profile_data)464*4882a593Smuzhiyun static int aw_dev_pid_9b_reg_update(struct aw_device *aw_dev,
465*4882a593Smuzhiyun 			struct aw_data_container *profile_data)
466*4882a593Smuzhiyun {
467*4882a593Smuzhiyun 	int i = 0;
468*4882a593Smuzhiyun 	int ret = -1;
469*4882a593Smuzhiyun 	uint8_t reg_val = 0;
470*4882a593Smuzhiyun 
471*4882a593Smuzhiyun 	if (profile_data == NULL)
472*4882a593Smuzhiyun 		return -EINVAL;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) {
475*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "dev is pwr_off,can not update reg");
476*4882a593Smuzhiyun 		return -EINVAL;
477*4882a593Smuzhiyun 	}
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 	if (profile_data->len != AW_PID_9B_BIN_REG_CFG_COUNT) {
480*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "reg_config count of bin is error,can not update reg");
481*4882a593Smuzhiyun 		return -EINVAL;
482*4882a593Smuzhiyun 	}
483*4882a593Smuzhiyun 	ret = aw_dev_i2c_write_byte(aw_dev, AW87XXX_PID_9B_ENCRYPTION_REG,
484*4882a593Smuzhiyun 		AW87XXX_PID_9B_ENCRYPTION_BOOST_OUTPUT_SET);
485*4882a593Smuzhiyun 	if (ret < 0)
486*4882a593Smuzhiyun 		return ret;
487*4882a593Smuzhiyun 
488*4882a593Smuzhiyun 	for (i = 1; i < AW_PID_9B_BIN_REG_CFG_COUNT; i++) {
489*4882a593Smuzhiyun 		AW_DEV_LOGI(aw_dev->dev, "reg=0x%02x, val = 0x%02x",
490*4882a593Smuzhiyun 			i, profile_data->data[i]);
491*4882a593Smuzhiyun 		reg_val = profile_data->data[i];
492*4882a593Smuzhiyun 		if (i == AW87XXX_PID_9B_SYSCTRL_REG) {
493*4882a593Smuzhiyun 			aw_dev_reg_mute_bits_set(aw_dev, &reg_val, true);
494*4882a593Smuzhiyun 			AW_DEV_LOGD(aw_dev->dev, "change mute_mask, val = 0x%02x",
495*4882a593Smuzhiyun 				reg_val);
496*4882a593Smuzhiyun 		}
497*4882a593Smuzhiyun 
498*4882a593Smuzhiyun 		ret = aw_dev_i2c_write_byte(aw_dev, i, reg_val);
499*4882a593Smuzhiyun 		if (ret < 0)
500*4882a593Smuzhiyun 			return ret;
501*4882a593Smuzhiyun 	}
502*4882a593Smuzhiyun 
503*4882a593Smuzhiyun 	return 0;
504*4882a593Smuzhiyun }
505*4882a593Smuzhiyun 
aw_dev_pid_9b_pwr_on(struct aw_device * aw_dev,struct aw_data_container * data)506*4882a593Smuzhiyun int aw_dev_pid_9b_pwr_on(struct aw_device *aw_dev, struct aw_data_container *data)
507*4882a593Smuzhiyun {
508*4882a593Smuzhiyun 	int ret = 0;
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 	/*hw power on*/
511*4882a593Smuzhiyun 	aw_dev_hw_pwr_ctrl(aw_dev, true);
512*4882a593Smuzhiyun 
513*4882a593Smuzhiyun 	/* open the mute */
514*4882a593Smuzhiyun 	ret = aw_dev_mute_ctrl(aw_dev, true);
515*4882a593Smuzhiyun 	if (ret < 0)
516*4882a593Smuzhiyun 		return ret;
517*4882a593Smuzhiyun 
518*4882a593Smuzhiyun 	/* Update scene parameters in mute mode */
519*4882a593Smuzhiyun 	ret = aw_dev_pid_9b_reg_update(aw_dev, data);
520*4882a593Smuzhiyun 	if (ret < 0)
521*4882a593Smuzhiyun 		return ret;
522*4882a593Smuzhiyun 
523*4882a593Smuzhiyun 	/* close the mute */
524*4882a593Smuzhiyun 	aw_dev_mute_ctrl(aw_dev, false);
525*4882a593Smuzhiyun 	if (ret < 0)
526*4882a593Smuzhiyun 		return ret;
527*4882a593Smuzhiyun 
528*4882a593Smuzhiyun 	return 0;
529*4882a593Smuzhiyun }
530*4882a593Smuzhiyun 
aw_dev_pid_9b_init(struct aw_device * aw_dev)531*4882a593Smuzhiyun static void aw_dev_pid_9b_init(struct aw_device *aw_dev)
532*4882a593Smuzhiyun {
533*4882a593Smuzhiyun 	/* Product register permission info */
534*4882a593Smuzhiyun 	aw_dev->reg_max_addr = AW87XXX_PID_9B_REG_MAX;
535*4882a593Smuzhiyun 	aw_dev->reg_access = aw87xxx_pid_9b_reg_access;
536*4882a593Smuzhiyun 
537*4882a593Smuzhiyun 	aw_dev->mute_desc.addr = AW87XXX_PID_9B_SYSCTRL_REG;
538*4882a593Smuzhiyun 	aw_dev->mute_desc.mask = AW87XXX_PID_9B_REG_EN_SW_MASK;
539*4882a593Smuzhiyun 	aw_dev->mute_desc.enable = AW87XXX_PID_9B_REG_EN_SW_DISABLE_VALUE;
540*4882a593Smuzhiyun 	aw_dev->mute_desc.disable = AW87XXX_PID_9B_REG_EN_SW_ENABLE_VALUE;
541*4882a593Smuzhiyun 	aw_dev->ops.pwr_on_func = aw_dev_pid_9b_pwr_on;
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	/* software reset control info */
544*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_9b_softrst_access);
545*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.access = aw87xxx_pid_9b_softrst_access;
546*4882a593Smuzhiyun 	aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE;
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun 	/* Whether to allow register operation to power off */
549*4882a593Smuzhiyun 	aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_DISENABLE;
550*4882a593Smuzhiyun 
551*4882a593Smuzhiyun 	aw_dev->product_tab = g_aw_pid_9b_product;
552*4882a593Smuzhiyun 	aw_dev->product_cnt = AW87XXX_PID_9B_PRODUCT_MAX;
553*4882a593Smuzhiyun 
554*4882a593Smuzhiyun 	aw_dev->rec_desc.addr = AW87XXX_PID_9B_SYSCTRL_REG;
555*4882a593Smuzhiyun 	aw_dev->rec_desc.disable = AW87XXX_PID_9B_SPK_MODE_ENABLE;
556*4882a593Smuzhiyun 	aw_dev->rec_desc.enable = AW87XXX_PID_9B_SPK_MODE_DISABLE;
557*4882a593Smuzhiyun 	aw_dev->rec_desc.mask = AW87XXX_PID_9B_SPK_MODE_MASK;
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	/* esd reg info */
560*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_9B_SYSCTRL_REG;
561*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_9B_SYSCTRL_DEFAULT;
562*4882a593Smuzhiyun }
563*4882a593Smuzhiyun 
aw_dev_pid_9a_init(struct aw_device * aw_dev)564*4882a593Smuzhiyun static int aw_dev_pid_9a_init(struct aw_device *aw_dev)
565*4882a593Smuzhiyun {
566*4882a593Smuzhiyun 	int ret = 0;
567*4882a593Smuzhiyun 
568*4882a593Smuzhiyun 	ret = aw_dev_i2c_write_byte(aw_dev, AW87XXX_PID_9B_ENCRYPTION_REG,
569*4882a593Smuzhiyun 		AW87XXX_PID_9B_ENCRYPTION_BOOST_OUTPUT_SET);
570*4882a593Smuzhiyun 	if (ret < 0) {
571*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "write 0x64=0x2C error");
572*4882a593Smuzhiyun 		return -EINVAL;
573*4882a593Smuzhiyun 	}
574*4882a593Smuzhiyun 
575*4882a593Smuzhiyun 	ret = aw_dev_get_chipid(aw_dev);
576*4882a593Smuzhiyun 	if (ret < 0) {
577*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "read chipid is failed,ret=%d", ret);
578*4882a593Smuzhiyun 		return ret;
579*4882a593Smuzhiyun 	}
580*4882a593Smuzhiyun 
581*4882a593Smuzhiyun 	if (aw_dev->chipid == AW_DEV_CHIPID_9B) {
582*4882a593Smuzhiyun 		AW_DEV_LOGI(aw_dev->dev, "product is pid_9B class");
583*4882a593Smuzhiyun 		aw_dev_pid_9b_init(aw_dev);
584*4882a593Smuzhiyun 	} else {
585*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "product is not pid_9B class, not support");
586*4882a593Smuzhiyun 		return -EINVAL;
587*4882a593Smuzhiyun 	}
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	return 0;
590*4882a593Smuzhiyun }
591*4882a593Smuzhiyun 
592*4882a593Smuzhiyun /********************** aw87xxx_pid_9b attributes end ***********************/
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun /********************** aw87xxx_pid_39 attributes ***************************/
aw_dev_chipid_39_init(struct aw_device * aw_dev)595*4882a593Smuzhiyun static void aw_dev_chipid_39_init(struct aw_device *aw_dev)
596*4882a593Smuzhiyun {
597*4882a593Smuzhiyun 	/* Product register permission info */
598*4882a593Smuzhiyun 	aw_dev->reg_max_addr = AW87XXX_PID_39_REG_MAX;
599*4882a593Smuzhiyun 	aw_dev->reg_access = aw87xxx_pid_39_reg_access;
600*4882a593Smuzhiyun 
601*4882a593Smuzhiyun 	/* software reset control info */
602*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_39_softrst_access);
603*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.access = aw87xxx_pid_39_softrst_access;
604*4882a593Smuzhiyun 	aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE;
605*4882a593Smuzhiyun 
606*4882a593Smuzhiyun 	/* Whether to allow register operation to power off */
607*4882a593Smuzhiyun 	aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE;
608*4882a593Smuzhiyun 
609*4882a593Smuzhiyun 	aw_dev->product_tab = g_aw_pid_39_product;
610*4882a593Smuzhiyun 	aw_dev->product_cnt = AW87XXX_PID_39_PRODUCT_MAX;
611*4882a593Smuzhiyun 
612*4882a593Smuzhiyun 	aw_dev->rec_desc.addr = AW87XXX_PID_39_REG_MODECTRL;
613*4882a593Smuzhiyun 	aw_dev->rec_desc.disable = AW87XXX_PID_39_REC_MODE_DISABLE;
614*4882a593Smuzhiyun 	aw_dev->rec_desc.enable = AW87XXX_PID_39_REC_MODE_ENABLE;
615*4882a593Smuzhiyun 	aw_dev->rec_desc.mask = AW87XXX_PID_39_REC_MODE_MASK;
616*4882a593Smuzhiyun 
617*4882a593Smuzhiyun 	/* esd reg info */
618*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_39_REG_MODECTRL;
619*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_39_MODECTRL_DEFAULT;
620*4882a593Smuzhiyun }
621*4882a593Smuzhiyun /********************* aw87xxx_pid_39 attributes end *************************/
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 
624*4882a593Smuzhiyun /********************* aw87xxx_pid_59_5x9 attributes *************************/
aw_dev_chipid_59_5x9_init(struct aw_device * aw_dev)625*4882a593Smuzhiyun static void aw_dev_chipid_59_5x9_init(struct aw_device *aw_dev)
626*4882a593Smuzhiyun {
627*4882a593Smuzhiyun 	/* Product register permission info */
628*4882a593Smuzhiyun 	aw_dev->reg_max_addr = AW87XXX_PID_59_5X9_REG_MAX;
629*4882a593Smuzhiyun 	aw_dev->reg_access = aw87xxx_pid_59_5x9_reg_access;
630*4882a593Smuzhiyun 
631*4882a593Smuzhiyun 	/* software reset control info */
632*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_59_5x9_softrst_access);
633*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.access = aw87xxx_pid_59_5x9_softrst_access;
634*4882a593Smuzhiyun 	aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE;
635*4882a593Smuzhiyun 
636*4882a593Smuzhiyun 	/* Whether to allow register operation to power off */
637*4882a593Smuzhiyun 	aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE;
638*4882a593Smuzhiyun 
639*4882a593Smuzhiyun 	aw_dev->product_tab = g_aw_pid_59_5x9_product;
640*4882a593Smuzhiyun 	aw_dev->product_cnt = AW87XXX_PID_59_5X9_PRODUCT_MAX;
641*4882a593Smuzhiyun 
642*4882a593Smuzhiyun 	aw_dev->rec_desc.addr = AW87XXX_PID_59_5X9_REG_SYSCTRL;
643*4882a593Smuzhiyun 	aw_dev->rec_desc.disable = AW87XXX_PID_59_5X9_REC_MODE_DISABLE;
644*4882a593Smuzhiyun 	aw_dev->rec_desc.enable = AW87XXX_PID_59_5X9_REC_MODE_ENABLE;
645*4882a593Smuzhiyun 	aw_dev->rec_desc.mask = AW87XXX_PID_59_5X9_REC_MODE_MASK;
646*4882a593Smuzhiyun 
647*4882a593Smuzhiyun 	/* esd reg info */
648*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_59_5X9_REG_ENCR;
649*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_59_5X9_ENCRY_DEFAULT;
650*4882a593Smuzhiyun }
651*4882a593Smuzhiyun /******************* aw87xxx_pid_59_5x9 attributes end ***********************/
652*4882a593Smuzhiyun 
653*4882a593Smuzhiyun /********************* aw87xxx_pid_59_3x9 attributes *************************/
aw_dev_chipid_59_3x9_init(struct aw_device * aw_dev)654*4882a593Smuzhiyun static void aw_dev_chipid_59_3x9_init(struct aw_device *aw_dev)
655*4882a593Smuzhiyun {
656*4882a593Smuzhiyun 	/* Product register permission info */
657*4882a593Smuzhiyun 	aw_dev->reg_max_addr = AW87XXX_PID_59_3X9_REG_MAX;
658*4882a593Smuzhiyun 	aw_dev->reg_access = aw87xxx_pid_59_3x9_reg_access;
659*4882a593Smuzhiyun 
660*4882a593Smuzhiyun 	/* software reset control info */
661*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_59_3x9_softrst_access);
662*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.access = aw87xxx_pid_59_3x9_softrst_access;
663*4882a593Smuzhiyun 	aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE;
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	/* Whether to allow register operation to power off */
666*4882a593Smuzhiyun 	aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE;
667*4882a593Smuzhiyun 
668*4882a593Smuzhiyun 	aw_dev->product_tab = g_aw_pid_59_3x9_product;
669*4882a593Smuzhiyun 	aw_dev->product_cnt = AW87XXX_PID_59_3X9_PRODUCT_MAX;
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 	aw_dev->rec_desc.addr = AW87XXX_PID_59_3X9_REG_MDCRTL;
672*4882a593Smuzhiyun 	aw_dev->rec_desc.disable = AW87XXX_PID_59_3X9_SPK_MODE_ENABLE;
673*4882a593Smuzhiyun 	aw_dev->rec_desc.enable = AW87XXX_PID_59_3X9_SPK_MODE_DISABLE;
674*4882a593Smuzhiyun 	aw_dev->rec_desc.mask = AW87XXX_PID_59_3X9_SPK_MODE_MASK;
675*4882a593Smuzhiyun 
676*4882a593Smuzhiyun 	/* esd reg info */
677*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_59_3X9_REG_ENCR;
678*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_59_3X9_ENCR_DEFAULT;
679*4882a593Smuzhiyun }
680*4882a593Smuzhiyun /******************* aw87xxx_pid_59_3x9 attributes end ***********************/
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun /********************** aw87xxx_pid_5a attributes ****************************/
aw_dev_chipid_5a_init(struct aw_device * aw_dev)683*4882a593Smuzhiyun static void aw_dev_chipid_5a_init(struct aw_device *aw_dev)
684*4882a593Smuzhiyun {
685*4882a593Smuzhiyun 	/* Product register permission info */
686*4882a593Smuzhiyun 	aw_dev->reg_max_addr = AW87XXX_PID_5A_REG_MAX;
687*4882a593Smuzhiyun 	aw_dev->reg_access = aw87xxx_pid_5a_reg_access;
688*4882a593Smuzhiyun 
689*4882a593Smuzhiyun 	/* software reset control info */
690*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_5a_softrst_access);
691*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.access = aw87xxx_pid_5a_softrst_access;
692*4882a593Smuzhiyun 	aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE;
693*4882a593Smuzhiyun 
694*4882a593Smuzhiyun 	/* Whether to allow register operation to power off */
695*4882a593Smuzhiyun 	aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE;
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	aw_dev->product_tab = g_aw_pid_5a_product;
698*4882a593Smuzhiyun 	aw_dev->product_cnt = AW87XXX_PID_5A_PRODUCT_MAX;
699*4882a593Smuzhiyun 
700*4882a593Smuzhiyun 	aw_dev->rec_desc.addr = AW87XXX_PID_5A_REG_SYSCTRL_REG;
701*4882a593Smuzhiyun 	aw_dev->rec_desc.disable = AW87XXX_PID_5A_REG_RCV_MODE_DISABLE;
702*4882a593Smuzhiyun 	aw_dev->rec_desc.enable = AW87XXX_PID_5A_REG_RCV_MODE_ENABLE;
703*4882a593Smuzhiyun 	aw_dev->rec_desc.mask = AW87XXX_PID_5A_REG_RCV_MODE_MASK;
704*4882a593Smuzhiyun 
705*4882a593Smuzhiyun 	/* esd reg info */
706*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_5A_REG_DFT3R_REG;
707*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_5A_DFT3R_DEFAULT;
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun 
aw_dev_chipid_76_init(struct aw_device * aw_dev)710*4882a593Smuzhiyun static void aw_dev_chipid_76_init(struct aw_device *aw_dev)
711*4882a593Smuzhiyun {
712*4882a593Smuzhiyun 	/* Product register permission info */
713*4882a593Smuzhiyun 	aw_dev->reg_max_addr = AW87XXX_PID_76_REG_MAX;
714*4882a593Smuzhiyun 	aw_dev->reg_access = aw87xxx_pid_76_reg_access;
715*4882a593Smuzhiyun 
716*4882a593Smuzhiyun 	/* software reset control info */
717*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_76_softrst_access);
718*4882a593Smuzhiyun 	aw_dev->soft_rst_desc.access = aw87xxx_pid_76_softrst_access;
719*4882a593Smuzhiyun 	aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE;
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun 	/* software power off control info */
722*4882a593Smuzhiyun 	aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE;
723*4882a593Smuzhiyun 
724*4882a593Smuzhiyun 	aw_dev->product_tab = g_aw_pid_76_product;
725*4882a593Smuzhiyun 	aw_dev->product_cnt = AW87XXX_PID_76_PROFUCT_MAX;
726*4882a593Smuzhiyun 
727*4882a593Smuzhiyun 	aw_dev->rec_desc.addr = AW87XXX_PID_76_MDCTRL_REG;
728*4882a593Smuzhiyun 	aw_dev->rec_desc.disable = AW87XXX_PID_76_EN_SPK_ENABLE;
729*4882a593Smuzhiyun 	aw_dev->rec_desc.enable = AW87XXX_PID_76_EN_SPK_DISABLE;
730*4882a593Smuzhiyun 	aw_dev->rec_desc.mask = AW87XXX_PID_76_EN_SPK_MASK;
731*4882a593Smuzhiyun 
732*4882a593Smuzhiyun 	/* esd reg info */
733*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_76_DFT_ADP1_REG;
734*4882a593Smuzhiyun 	aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_76_DFT_ADP1_CHECK;
735*4882a593Smuzhiyun }
736*4882a593Smuzhiyun 
737*4882a593Smuzhiyun /********************** aw87xxx_pid_5a attributes end ************************/
738*4882a593Smuzhiyun 
aw_dev_chip_init(struct aw_device * aw_dev)739*4882a593Smuzhiyun static void aw_dev_chip_init(struct aw_device *aw_dev)
740*4882a593Smuzhiyun {
741*4882a593Smuzhiyun 	int ret  = 0;
742*4882a593Smuzhiyun 
743*4882a593Smuzhiyun 	/*get info by chipid*/
744*4882a593Smuzhiyun 	switch (aw_dev->chipid) {
745*4882a593Smuzhiyun 	case AW_DEV_CHIPID_9A:
746*4882a593Smuzhiyun 		ret = aw_dev_pid_9a_init(aw_dev);
747*4882a593Smuzhiyun 		if (ret < 0)
748*4882a593Smuzhiyun 			AW_DEV_LOGE(aw_dev->dev, "product is pid_9B init failed");
749*4882a593Smuzhiyun 		break;
750*4882a593Smuzhiyun 	case AW_DEV_CHIPID_9B:
751*4882a593Smuzhiyun 		aw_dev_pid_9b_init(aw_dev);
752*4882a593Smuzhiyun 		AW_DEV_LOGI(aw_dev->dev, "product is pid_9B class");
753*4882a593Smuzhiyun 		break;
754*4882a593Smuzhiyun 	case AW_DEV_CHIPID_39:
755*4882a593Smuzhiyun 		aw_dev_chipid_39_init(aw_dev);
756*4882a593Smuzhiyun 		AW_DEV_LOGI(aw_dev->dev, "product is pid_39 class");
757*4882a593Smuzhiyun 		break;
758*4882a593Smuzhiyun 	case AW_DEV_CHIPID_59:
759*4882a593Smuzhiyun 		if (aw_dev_gpio_is_valid(aw_dev)) {
760*4882a593Smuzhiyun 			aw_dev_chipid_59_5x9_init(aw_dev);
761*4882a593Smuzhiyun 			AW_DEV_LOGI(aw_dev->dev, "product is pid_59_5x9 class");
762*4882a593Smuzhiyun 		} else {
763*4882a593Smuzhiyun 			aw_dev_chipid_59_3x9_init(aw_dev);
764*4882a593Smuzhiyun 			AW_DEV_LOGI(aw_dev->dev, "product is pid_59_3x9 class");
765*4882a593Smuzhiyun 		}
766*4882a593Smuzhiyun 		break;
767*4882a593Smuzhiyun 	case AW_DEV_CHIPID_5A:
768*4882a593Smuzhiyun 		aw_dev_chipid_5a_init(aw_dev);
769*4882a593Smuzhiyun 		AW_DEV_LOGI(aw_dev->dev, "product is pid_5A class");
770*4882a593Smuzhiyun 		break;
771*4882a593Smuzhiyun 	case AW_DEV_CHIPID_76:
772*4882a593Smuzhiyun 		aw_dev_chipid_76_init(aw_dev);
773*4882a593Smuzhiyun 		AW_DEV_LOGI(aw_dev->dev, "product is pid_76 class");
774*4882a593Smuzhiyun 		break;
775*4882a593Smuzhiyun 	default:
776*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "unsupported device revision [0x%x]",
777*4882a593Smuzhiyun 			aw_dev->chipid);
778*4882a593Smuzhiyun 		return;
779*4882a593Smuzhiyun 	}
780*4882a593Smuzhiyun }
781*4882a593Smuzhiyun 
aw_dev_get_chipid(struct aw_device * aw_dev)782*4882a593Smuzhiyun static int aw_dev_get_chipid(struct aw_device *aw_dev)
783*4882a593Smuzhiyun {
784*4882a593Smuzhiyun 	int ret = -1;
785*4882a593Smuzhiyun 	unsigned int cnt = 0;
786*4882a593Smuzhiyun 	unsigned char reg_val = 0;
787*4882a593Smuzhiyun 
788*4882a593Smuzhiyun 	for (cnt = 0; cnt < AW_READ_CHIPID_RETRIES; cnt++) {
789*4882a593Smuzhiyun 		ret = aw_dev_i2c_read_byte(aw_dev, AW_DEV_REG_CHIPID, &reg_val);
790*4882a593Smuzhiyun 		if (ret < 0) {
791*4882a593Smuzhiyun 			AW_DEV_LOGE(aw_dev->dev, "[%d] read chip is failed, ret=%d",
792*4882a593Smuzhiyun 				cnt, ret);
793*4882a593Smuzhiyun 			continue;
794*4882a593Smuzhiyun 		}
795*4882a593Smuzhiyun 		break;
796*4882a593Smuzhiyun 	}
797*4882a593Smuzhiyun 
798*4882a593Smuzhiyun 
799*4882a593Smuzhiyun 	if (cnt == AW_READ_CHIPID_RETRIES) {
800*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "read chip is failed,cnt=%d", cnt);
801*4882a593Smuzhiyun 		return -EINVAL;
802*4882a593Smuzhiyun 	}
803*4882a593Smuzhiyun 
804*4882a593Smuzhiyun 	AW_DEV_LOGI(aw_dev->dev, "read chipid[0x%x] succeed", reg_val);
805*4882a593Smuzhiyun 	aw_dev->chipid = reg_val;
806*4882a593Smuzhiyun 
807*4882a593Smuzhiyun 	return 0;
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun 
aw_dev_init(struct aw_device * aw_dev)810*4882a593Smuzhiyun int aw_dev_init(struct aw_device *aw_dev)
811*4882a593Smuzhiyun {
812*4882a593Smuzhiyun 	int ret = -1;
813*4882a593Smuzhiyun 
814*4882a593Smuzhiyun 	ret = aw_dev_get_chipid(aw_dev);
815*4882a593Smuzhiyun 	if (ret < 0) {
816*4882a593Smuzhiyun 		AW_DEV_LOGE(aw_dev->dev, "read chipid is failed,ret=%d", ret);
817*4882a593Smuzhiyun 		return ret;
818*4882a593Smuzhiyun 	}
819*4882a593Smuzhiyun 
820*4882a593Smuzhiyun 	aw_dev_chip_init(aw_dev);
821*4882a593Smuzhiyun 
822*4882a593Smuzhiyun 	return 0;
823*4882a593Smuzhiyun }
824*4882a593Smuzhiyun 
825*4882a593Smuzhiyun 
826