1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * HD audio interface patch for Creative CA0132 chip
4 *
5 * Copyright (c) 2011, Creative Technology Ltd.
6 *
7 * Based on patch_ca0110.c
8 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
9 */
10
11 #include <linux/init.h>
12 #include <linux/delay.h>
13 #include <linux/slab.h>
14 #include <linux/mutex.h>
15 #include <linux/module.h>
16 #include <linux/firmware.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/io.h>
20 #include <linux/pci.h>
21 #include <asm/io.h>
22 #include <sound/core.h>
23 #include <sound/hda_codec.h>
24 #include "hda_local.h"
25 #include "hda_auto_parser.h"
26 #include "hda_jack.h"
27
28 #include "ca0132_regs.h"
29
30 /* Enable this to see controls for tuning purpose. */
31 /*#define ENABLE_TUNING_CONTROLS*/
32
33 #ifdef ENABLE_TUNING_CONTROLS
34 #include <sound/tlv.h>
35 #endif
36
37 #define FLOAT_ZERO 0x00000000
38 #define FLOAT_ONE 0x3f800000
39 #define FLOAT_TWO 0x40000000
40 #define FLOAT_THREE 0x40400000
41 #define FLOAT_FIVE 0x40a00000
42 #define FLOAT_SIX 0x40c00000
43 #define FLOAT_EIGHT 0x41000000
44 #define FLOAT_MINUS_5 0xc0a00000
45
46 #define UNSOL_TAG_DSP 0x16
47
48 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
49 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
50
51 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
52 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
53 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
54
55 #define MASTERCONTROL 0x80
56 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
57 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
58
59 #define WIDGET_CHIP_CTRL 0x15
60 #define WIDGET_DSP_CTRL 0x16
61
62 #define MEM_CONNID_MICIN1 3
63 #define MEM_CONNID_MICIN2 5
64 #define MEM_CONNID_MICOUT1 12
65 #define MEM_CONNID_MICOUT2 14
66 #define MEM_CONNID_WUH 10
67 #define MEM_CONNID_DSP 16
68 #define MEM_CONNID_DMIC 100
69
70 #define SCP_SET 0
71 #define SCP_GET 1
72
73 #define EFX_FILE "ctefx.bin"
74 #define DESKTOP_EFX_FILE "ctefx-desktop.bin"
75 #define R3DI_EFX_FILE "ctefx-r3di.bin"
76
77 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
78 MODULE_FIRMWARE(EFX_FILE);
79 MODULE_FIRMWARE(DESKTOP_EFX_FILE);
80 MODULE_FIRMWARE(R3DI_EFX_FILE);
81 #endif
82
83 static const char *const dirstr[2] = { "Playback", "Capture" };
84
85 #define NUM_OF_OUTPUTS 2
86 static const char *const out_type_str[2] = { "Speakers", "Headphone" };
87 enum {
88 SPEAKER_OUT,
89 HEADPHONE_OUT,
90 };
91
92 enum {
93 DIGITAL_MIC,
94 LINE_MIC_IN
95 };
96
97 /* Strings for Input Source Enum Control */
98 static const char *const in_src_str[3] = { "Microphone", "Line In", "Front Microphone" };
99 #define IN_SRC_NUM_OF_INPUTS 3
100 enum {
101 REAR_MIC,
102 REAR_LINE_IN,
103 FRONT_MIC,
104 };
105
106 enum {
107 #define VNODE_START_NID 0x80
108 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
109 VNID_MIC,
110 VNID_HP_SEL,
111 VNID_AMIC1_SEL,
112 VNID_HP_ASEL,
113 VNID_AMIC1_ASEL,
114 VNODE_END_NID,
115 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
116
117 #define EFFECT_START_NID 0x90
118 #define OUT_EFFECT_START_NID EFFECT_START_NID
119 SURROUND = OUT_EFFECT_START_NID,
120 CRYSTALIZER,
121 DIALOG_PLUS,
122 SMART_VOLUME,
123 X_BASS,
124 EQUALIZER,
125 OUT_EFFECT_END_NID,
126 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
127
128 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
129 ECHO_CANCELLATION = IN_EFFECT_START_NID,
130 VOICE_FOCUS,
131 MIC_SVM,
132 NOISE_REDUCTION,
133 IN_EFFECT_END_NID,
134 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
135
136 VOICEFX = IN_EFFECT_END_NID,
137 PLAY_ENHANCEMENT,
138 CRYSTAL_VOICE,
139 EFFECT_END_NID,
140 OUTPUT_SOURCE_ENUM,
141 INPUT_SOURCE_ENUM,
142 XBASS_XOVER,
143 EQ_PRESET_ENUM,
144 SMART_VOLUME_ENUM,
145 MIC_BOOST_ENUM,
146 AE5_HEADPHONE_GAIN_ENUM,
147 AE5_SOUND_FILTER_ENUM,
148 ZXR_HEADPHONE_GAIN,
149 SPEAKER_CHANNEL_CFG_ENUM,
150 SPEAKER_FULL_RANGE_FRONT,
151 SPEAKER_FULL_RANGE_REAR,
152 BASS_REDIRECTION,
153 BASS_REDIRECTION_XOVER,
154 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
155 };
156
157 /* Effects values size*/
158 #define EFFECT_VALS_MAX_COUNT 12
159
160 /*
161 * Default values for the effect slider controls, they are in order of their
162 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
163 * X-bass.
164 */
165 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
166 /* Amount of effect level sliders for ca0132_alt controls. */
167 #define EFFECT_LEVEL_SLIDERS 5
168
169 /* Latency introduced by DSP blocks in milliseconds. */
170 #define DSP_CAPTURE_INIT_LATENCY 0
171 #define DSP_CRYSTAL_VOICE_LATENCY 124
172 #define DSP_PLAYBACK_INIT_LATENCY 13
173 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
174 #define DSP_SPEAKER_OUT_LATENCY 7
175
176 struct ct_effect {
177 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
178 hda_nid_t nid;
179 int mid; /*effect module ID*/
180 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
181 int direct; /* 0:output; 1:input*/
182 int params; /* number of default non-on/off params */
183 /*effect default values, 1st is on/off. */
184 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
185 };
186
187 #define EFX_DIR_OUT 0
188 #define EFX_DIR_IN 1
189
190 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
191 { .name = "Surround",
192 .nid = SURROUND,
193 .mid = 0x96,
194 .reqs = {0, 1},
195 .direct = EFX_DIR_OUT,
196 .params = 1,
197 .def_vals = {0x3F800000, 0x3F2B851F}
198 },
199 { .name = "Crystalizer",
200 .nid = CRYSTALIZER,
201 .mid = 0x96,
202 .reqs = {7, 8},
203 .direct = EFX_DIR_OUT,
204 .params = 1,
205 .def_vals = {0x3F800000, 0x3F266666}
206 },
207 { .name = "Dialog Plus",
208 .nid = DIALOG_PLUS,
209 .mid = 0x96,
210 .reqs = {2, 3},
211 .direct = EFX_DIR_OUT,
212 .params = 1,
213 .def_vals = {0x00000000, 0x3F000000}
214 },
215 { .name = "Smart Volume",
216 .nid = SMART_VOLUME,
217 .mid = 0x96,
218 .reqs = {4, 5, 6},
219 .direct = EFX_DIR_OUT,
220 .params = 2,
221 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
222 },
223 { .name = "X-Bass",
224 .nid = X_BASS,
225 .mid = 0x96,
226 .reqs = {24, 23, 25},
227 .direct = EFX_DIR_OUT,
228 .params = 2,
229 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
230 },
231 { .name = "Equalizer",
232 .nid = EQUALIZER,
233 .mid = 0x96,
234 .reqs = {9, 10, 11, 12, 13, 14,
235 15, 16, 17, 18, 19, 20},
236 .direct = EFX_DIR_OUT,
237 .params = 11,
238 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
239 0x00000000, 0x00000000, 0x00000000, 0x00000000,
240 0x00000000, 0x00000000, 0x00000000, 0x00000000}
241 },
242 { .name = "Echo Cancellation",
243 .nid = ECHO_CANCELLATION,
244 .mid = 0x95,
245 .reqs = {0, 1, 2, 3},
246 .direct = EFX_DIR_IN,
247 .params = 3,
248 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
249 },
250 { .name = "Voice Focus",
251 .nid = VOICE_FOCUS,
252 .mid = 0x95,
253 .reqs = {6, 7, 8, 9},
254 .direct = EFX_DIR_IN,
255 .params = 3,
256 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
257 },
258 { .name = "Mic SVM",
259 .nid = MIC_SVM,
260 .mid = 0x95,
261 .reqs = {44, 45},
262 .direct = EFX_DIR_IN,
263 .params = 1,
264 .def_vals = {0x00000000, 0x3F3D70A4}
265 },
266 { .name = "Noise Reduction",
267 .nid = NOISE_REDUCTION,
268 .mid = 0x95,
269 .reqs = {4, 5},
270 .direct = EFX_DIR_IN,
271 .params = 1,
272 .def_vals = {0x3F800000, 0x3F000000}
273 },
274 { .name = "VoiceFX",
275 .nid = VOICEFX,
276 .mid = 0x95,
277 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
278 .direct = EFX_DIR_IN,
279 .params = 8,
280 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
281 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
282 0x00000000}
283 }
284 };
285
286 /* Tuning controls */
287 #ifdef ENABLE_TUNING_CONTROLS
288
289 enum {
290 #define TUNING_CTL_START_NID 0xC0
291 WEDGE_ANGLE = TUNING_CTL_START_NID,
292 SVM_LEVEL,
293 EQUALIZER_BAND_0,
294 EQUALIZER_BAND_1,
295 EQUALIZER_BAND_2,
296 EQUALIZER_BAND_3,
297 EQUALIZER_BAND_4,
298 EQUALIZER_BAND_5,
299 EQUALIZER_BAND_6,
300 EQUALIZER_BAND_7,
301 EQUALIZER_BAND_8,
302 EQUALIZER_BAND_9,
303 TUNING_CTL_END_NID
304 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
305 };
306
307 struct ct_tuning_ctl {
308 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
309 hda_nid_t parent_nid;
310 hda_nid_t nid;
311 int mid; /*effect module ID*/
312 int req; /*effect module request*/
313 int direct; /* 0:output; 1:input*/
314 unsigned int def_val;/*effect default values*/
315 };
316
317 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
318 { .name = "Wedge Angle",
319 .parent_nid = VOICE_FOCUS,
320 .nid = WEDGE_ANGLE,
321 .mid = 0x95,
322 .req = 8,
323 .direct = EFX_DIR_IN,
324 .def_val = 0x41F00000
325 },
326 { .name = "SVM Level",
327 .parent_nid = MIC_SVM,
328 .nid = SVM_LEVEL,
329 .mid = 0x95,
330 .req = 45,
331 .direct = EFX_DIR_IN,
332 .def_val = 0x3F3D70A4
333 },
334 { .name = "EQ Band0",
335 .parent_nid = EQUALIZER,
336 .nid = EQUALIZER_BAND_0,
337 .mid = 0x96,
338 .req = 11,
339 .direct = EFX_DIR_OUT,
340 .def_val = 0x00000000
341 },
342 { .name = "EQ Band1",
343 .parent_nid = EQUALIZER,
344 .nid = EQUALIZER_BAND_1,
345 .mid = 0x96,
346 .req = 12,
347 .direct = EFX_DIR_OUT,
348 .def_val = 0x00000000
349 },
350 { .name = "EQ Band2",
351 .parent_nid = EQUALIZER,
352 .nid = EQUALIZER_BAND_2,
353 .mid = 0x96,
354 .req = 13,
355 .direct = EFX_DIR_OUT,
356 .def_val = 0x00000000
357 },
358 { .name = "EQ Band3",
359 .parent_nid = EQUALIZER,
360 .nid = EQUALIZER_BAND_3,
361 .mid = 0x96,
362 .req = 14,
363 .direct = EFX_DIR_OUT,
364 .def_val = 0x00000000
365 },
366 { .name = "EQ Band4",
367 .parent_nid = EQUALIZER,
368 .nid = EQUALIZER_BAND_4,
369 .mid = 0x96,
370 .req = 15,
371 .direct = EFX_DIR_OUT,
372 .def_val = 0x00000000
373 },
374 { .name = "EQ Band5",
375 .parent_nid = EQUALIZER,
376 .nid = EQUALIZER_BAND_5,
377 .mid = 0x96,
378 .req = 16,
379 .direct = EFX_DIR_OUT,
380 .def_val = 0x00000000
381 },
382 { .name = "EQ Band6",
383 .parent_nid = EQUALIZER,
384 .nid = EQUALIZER_BAND_6,
385 .mid = 0x96,
386 .req = 17,
387 .direct = EFX_DIR_OUT,
388 .def_val = 0x00000000
389 },
390 { .name = "EQ Band7",
391 .parent_nid = EQUALIZER,
392 .nid = EQUALIZER_BAND_7,
393 .mid = 0x96,
394 .req = 18,
395 .direct = EFX_DIR_OUT,
396 .def_val = 0x00000000
397 },
398 { .name = "EQ Band8",
399 .parent_nid = EQUALIZER,
400 .nid = EQUALIZER_BAND_8,
401 .mid = 0x96,
402 .req = 19,
403 .direct = EFX_DIR_OUT,
404 .def_val = 0x00000000
405 },
406 { .name = "EQ Band9",
407 .parent_nid = EQUALIZER,
408 .nid = EQUALIZER_BAND_9,
409 .mid = 0x96,
410 .req = 20,
411 .direct = EFX_DIR_OUT,
412 .def_val = 0x00000000
413 }
414 };
415 #endif
416
417 /* Voice FX Presets */
418 #define VOICEFX_MAX_PARAM_COUNT 9
419
420 struct ct_voicefx {
421 char *name;
422 hda_nid_t nid;
423 int mid;
424 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
425 };
426
427 struct ct_voicefx_preset {
428 char *name; /*preset name*/
429 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
430 };
431
432 static const struct ct_voicefx ca0132_voicefx = {
433 .name = "VoiceFX Capture Switch",
434 .nid = VOICEFX,
435 .mid = 0x95,
436 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
437 };
438
439 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
440 { .name = "Neutral",
441 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
442 0x44FA0000, 0x3F800000, 0x3F800000,
443 0x3F800000, 0x00000000, 0x00000000 }
444 },
445 { .name = "Female2Male",
446 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
447 0x44FA0000, 0x3F19999A, 0x3F866666,
448 0x3F800000, 0x00000000, 0x00000000 }
449 },
450 { .name = "Male2Female",
451 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
452 0x450AC000, 0x4017AE14, 0x3F6B851F,
453 0x3F800000, 0x00000000, 0x00000000 }
454 },
455 { .name = "ScrappyKid",
456 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
457 0x44FA0000, 0x40400000, 0x3F28F5C3,
458 0x3F800000, 0x00000000, 0x00000000 }
459 },
460 { .name = "Elderly",
461 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
462 0x44E10000, 0x3FB33333, 0x3FB9999A,
463 0x3F800000, 0x3E3A2E43, 0x00000000 }
464 },
465 { .name = "Orc",
466 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
467 0x45098000, 0x3F266666, 0x3FC00000,
468 0x3F800000, 0x00000000, 0x00000000 }
469 },
470 { .name = "Elf",
471 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
472 0x45193000, 0x3F8E147B, 0x3F75C28F,
473 0x3F800000, 0x00000000, 0x00000000 }
474 },
475 { .name = "Dwarf",
476 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
477 0x45007000, 0x3F451EB8, 0x3F7851EC,
478 0x3F800000, 0x00000000, 0x00000000 }
479 },
480 { .name = "AlienBrute",
481 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
482 0x451F6000, 0x3F266666, 0x3FA7D945,
483 0x3F800000, 0x3CF5C28F, 0x00000000 }
484 },
485 { .name = "Robot",
486 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
487 0x44FA0000, 0x3FB2718B, 0x3F800000,
488 0xBC07010E, 0x00000000, 0x00000000 }
489 },
490 { .name = "Marine",
491 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
492 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
493 0x3F0A3D71, 0x00000000, 0x00000000 }
494 },
495 { .name = "Emo",
496 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
497 0x44FA0000, 0x3F800000, 0x3F800000,
498 0x3E4CCCCD, 0x00000000, 0x00000000 }
499 },
500 { .name = "DeepVoice",
501 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
502 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
503 0x3F800000, 0x00000000, 0x00000000 }
504 },
505 { .name = "Munchkin",
506 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
507 0x44FA0000, 0x3F800000, 0x3F1A043C,
508 0x3F800000, 0x00000000, 0x00000000 }
509 }
510 };
511
512 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
513
514 #define EQ_PRESET_MAX_PARAM_COUNT 11
515
516 struct ct_eq {
517 char *name;
518 hda_nid_t nid;
519 int mid;
520 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
521 };
522
523 struct ct_eq_preset {
524 char *name; /*preset name*/
525 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
526 };
527
528 static const struct ct_eq ca0132_alt_eq_enum = {
529 .name = "FX: Equalizer Preset Switch",
530 .nid = EQ_PRESET_ENUM,
531 .mid = 0x96,
532 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
533 };
534
535
536 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
537 { .name = "Flat",
538 .vals = { 0x00000000, 0x00000000, 0x00000000,
539 0x00000000, 0x00000000, 0x00000000,
540 0x00000000, 0x00000000, 0x00000000,
541 0x00000000, 0x00000000 }
542 },
543 { .name = "Acoustic",
544 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
545 0x40000000, 0x00000000, 0x00000000,
546 0x00000000, 0x00000000, 0x40000000,
547 0x40000000, 0x40000000 }
548 },
549 { .name = "Classical",
550 .vals = { 0x00000000, 0x00000000, 0x40C00000,
551 0x40C00000, 0x40466666, 0x00000000,
552 0x00000000, 0x00000000, 0x00000000,
553 0x40466666, 0x40466666 }
554 },
555 { .name = "Country",
556 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
557 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
558 0x00000000, 0x00000000, 0x40000000,
559 0x40466666, 0x40800000 }
560 },
561 { .name = "Dance",
562 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
563 0x40466666, 0x40866666, 0xBF99999A,
564 0xBF99999A, 0x00000000, 0x00000000,
565 0x40800000, 0x40800000 }
566 },
567 { .name = "Jazz",
568 .vals = { 0x00000000, 0x00000000, 0x00000000,
569 0x3F8CCCCD, 0x40800000, 0x40800000,
570 0x40800000, 0x00000000, 0x3F8CCCCD,
571 0x40466666, 0x40466666 }
572 },
573 { .name = "New Age",
574 .vals = { 0x00000000, 0x00000000, 0x40000000,
575 0x40000000, 0x00000000, 0x00000000,
576 0x00000000, 0x3F8CCCCD, 0x40000000,
577 0x40000000, 0x40000000 }
578 },
579 { .name = "Pop",
580 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
581 0x40000000, 0x40000000, 0x00000000,
582 0xBF99999A, 0xBF99999A, 0x00000000,
583 0x40466666, 0x40C00000 }
584 },
585 { .name = "Rock",
586 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
587 0x3F8CCCCD, 0x40000000, 0xBF99999A,
588 0xBF99999A, 0x00000000, 0x00000000,
589 0x40800000, 0x40800000 }
590 },
591 { .name = "Vocal",
592 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
593 0xBF99999A, 0x00000000, 0x40466666,
594 0x40800000, 0x40466666, 0x00000000,
595 0x00000000, 0x3F8CCCCD }
596 }
597 };
598
599 /*
600 * DSP reqs for handling full-range speakers/bass redirection. If a speaker is
601 * set as not being full range, and bass redirection is enabled, all
602 * frequencies below the crossover frequency are redirected to the LFE
603 * channel. If the surround configuration has no LFE channel, this can't be
604 * enabled. X-Bass must be disabled when using these.
605 */
606 enum speaker_range_reqs {
607 SPEAKER_BASS_REDIRECT = 0x15,
608 SPEAKER_BASS_REDIRECT_XOVER_FREQ = 0x16,
609 /* Between 0x16-0x1a are the X-Bass reqs. */
610 SPEAKER_FULL_RANGE_FRONT_L_R = 0x1a,
611 SPEAKER_FULL_RANGE_CENTER_LFE = 0x1b,
612 SPEAKER_FULL_RANGE_REAR_L_R = 0x1c,
613 SPEAKER_FULL_RANGE_SURROUND_L_R = 0x1d,
614 SPEAKER_BASS_REDIRECT_SUB_GAIN = 0x1e,
615 };
616
617 /*
618 * Definitions for the DSP req's to handle speaker tuning. These all belong to
619 * module ID 0x96, the output effects module.
620 */
621 enum speaker_tuning_reqs {
622 /*
623 * Currently, this value is always set to 0.0f. However, on Windows,
624 * when selecting certain headphone profiles on the new Sound Blaster
625 * connect software, the QUERY_SPEAKER_EQ_ADDRESS req on mid 0x80 is
626 * sent. This gets the speaker EQ address area, which is then used to
627 * send over (presumably) an equalizer profile for the specific
628 * headphone setup. It is sent using the same method the DSP
629 * firmware is uploaded with, which I believe is why the 'ctspeq.bin'
630 * file exists in linux firmware tree but goes unused. It would also
631 * explain why the QUERY_SPEAKER_EQ_ADDRESS req is defined but unused.
632 * Once this profile is sent over, SPEAKER_TUNING_USE_SPEAKER_EQ is
633 * set to 1.0f.
634 */
635 SPEAKER_TUNING_USE_SPEAKER_EQ = 0x1f,
636 SPEAKER_TUNING_ENABLE_CENTER_EQ = 0x20,
637 SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL = 0x21,
638 SPEAKER_TUNING_FRONT_RIGHT_VOL_LEVEL = 0x22,
639 SPEAKER_TUNING_CENTER_VOL_LEVEL = 0x23,
640 SPEAKER_TUNING_LFE_VOL_LEVEL = 0x24,
641 SPEAKER_TUNING_REAR_LEFT_VOL_LEVEL = 0x25,
642 SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL = 0x26,
643 SPEAKER_TUNING_SURROUND_LEFT_VOL_LEVEL = 0x27,
644 SPEAKER_TUNING_SURROUND_RIGHT_VOL_LEVEL = 0x28,
645 /*
646 * Inversion is used when setting headphone virtualization to line
647 * out. Not sure why this is, but it's the only place it's ever used.
648 */
649 SPEAKER_TUNING_FRONT_LEFT_INVERT = 0x29,
650 SPEAKER_TUNING_FRONT_RIGHT_INVERT = 0x2a,
651 SPEAKER_TUNING_CENTER_INVERT = 0x2b,
652 SPEAKER_TUNING_LFE_INVERT = 0x2c,
653 SPEAKER_TUNING_REAR_LEFT_INVERT = 0x2d,
654 SPEAKER_TUNING_REAR_RIGHT_INVERT = 0x2e,
655 SPEAKER_TUNING_SURROUND_LEFT_INVERT = 0x2f,
656 SPEAKER_TUNING_SURROUND_RIGHT_INVERT = 0x30,
657 /* Delay is used when setting surround speaker distance in Windows. */
658 SPEAKER_TUNING_FRONT_LEFT_DELAY = 0x31,
659 SPEAKER_TUNING_FRONT_RIGHT_DELAY = 0x32,
660 SPEAKER_TUNING_CENTER_DELAY = 0x33,
661 SPEAKER_TUNING_LFE_DELAY = 0x34,
662 SPEAKER_TUNING_REAR_LEFT_DELAY = 0x35,
663 SPEAKER_TUNING_REAR_RIGHT_DELAY = 0x36,
664 SPEAKER_TUNING_SURROUND_LEFT_DELAY = 0x37,
665 SPEAKER_TUNING_SURROUND_RIGHT_DELAY = 0x38,
666 /* Of these two, only mute seems to ever be used. */
667 SPEAKER_TUNING_MAIN_VOLUME = 0x39,
668 SPEAKER_TUNING_MUTE = 0x3a,
669 };
670
671 /* Surround output channel count configuration structures. */
672 #define SPEAKER_CHANNEL_CFG_COUNT 5
673 enum {
674 SPEAKER_CHANNELS_2_0,
675 SPEAKER_CHANNELS_2_1,
676 SPEAKER_CHANNELS_4_0,
677 SPEAKER_CHANNELS_4_1,
678 SPEAKER_CHANNELS_5_1,
679 };
680
681 struct ca0132_alt_speaker_channel_cfg {
682 char *name;
683 unsigned int val;
684 };
685
686 static const struct ca0132_alt_speaker_channel_cfg speaker_channel_cfgs[] = {
687 { .name = "2.0",
688 .val = FLOAT_ONE
689 },
690 { .name = "2.1",
691 .val = FLOAT_TWO
692 },
693 { .name = "4.0",
694 .val = FLOAT_FIVE
695 },
696 { .name = "4.1",
697 .val = FLOAT_SIX
698 },
699 { .name = "5.1",
700 .val = FLOAT_EIGHT
701 }
702 };
703
704 /*
705 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
706 * and I don't know what the third req is, but it's always zero. I assume it's
707 * some sort of update or set command to tell the DSP there's new volume info.
708 */
709 #define DSP_VOL_OUT 0
710 #define DSP_VOL_IN 1
711
712 struct ct_dsp_volume_ctl {
713 hda_nid_t vnid;
714 int mid; /* module ID*/
715 unsigned int reqs[3]; /* scp req ID */
716 };
717
718 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
719 { .vnid = VNID_SPK,
720 .mid = 0x32,
721 .reqs = {3, 4, 2}
722 },
723 { .vnid = VNID_MIC,
724 .mid = 0x37,
725 .reqs = {2, 3, 1}
726 }
727 };
728
729 /* Values for ca0113_mmio_command_set for selecting output. */
730 #define AE_CA0113_OUT_SET_COMMANDS 6
731 struct ae_ca0113_output_set {
732 unsigned int group[AE_CA0113_OUT_SET_COMMANDS];
733 unsigned int target[AE_CA0113_OUT_SET_COMMANDS];
734 unsigned int vals[NUM_OF_OUTPUTS][AE_CA0113_OUT_SET_COMMANDS];
735 };
736
737 static const struct ae_ca0113_output_set ae5_ca0113_output_presets = {
738 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
739 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
740 /* Speakers. */
741 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
742 /* Headphones. */
743 { 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00 } },
744 };
745
746 static const struct ae_ca0113_output_set ae7_ca0113_output_presets = {
747 .group = { 0x30, 0x30, 0x48, 0x48, 0x48, 0x30 },
748 .target = { 0x2e, 0x30, 0x0d, 0x17, 0x19, 0x32 },
749 /* Speakers. */
750 .vals = { { 0x00, 0x00, 0x40, 0x00, 0x00, 0x3f },
751 /* Headphones. */
752 { 0x3f, 0x3f, 0x00, 0x00, 0x02, 0x00 } },
753 };
754
755 /* ae5 ca0113 command sequences to set headphone gain levels. */
756 #define AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS 4
757 struct ae5_headphone_gain_set {
758 char *name;
759 unsigned int vals[AE5_HEADPHONE_GAIN_PRESET_MAX_COMMANDS];
760 };
761
762 static const struct ae5_headphone_gain_set ae5_headphone_gain_presets[] = {
763 { .name = "Low (16-31",
764 .vals = { 0xff, 0x2c, 0xf5, 0x32 }
765 },
766 { .name = "Medium (32-149",
767 .vals = { 0x38, 0xa8, 0x3e, 0x4c }
768 },
769 { .name = "High (150-600",
770 .vals = { 0xff, 0xff, 0xff, 0x7f }
771 }
772 };
773
774 struct ae5_filter_set {
775 char *name;
776 unsigned int val;
777 };
778
779 static const struct ae5_filter_set ae5_filter_presets[] = {
780 { .name = "Slow Roll Off",
781 .val = 0xa0
782 },
783 { .name = "Minimum Phase",
784 .val = 0xc0
785 },
786 { .name = "Fast Roll Off",
787 .val = 0x80
788 }
789 };
790
791 enum hda_cmd_vendor_io {
792 /* for DspIO node */
793 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
794 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
795
796 VENDOR_DSPIO_STATUS = 0xF01,
797 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
798 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
799 VENDOR_DSPIO_DSP_INIT = 0x703,
800 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
801 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
802
803 /* for ChipIO node */
804 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
805 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
806 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
807 VENDOR_CHIPIO_DATA_LOW = 0x300,
808 VENDOR_CHIPIO_DATA_HIGH = 0x400,
809
810 VENDOR_CHIPIO_8051_WRITE_DIRECT = 0x500,
811 VENDOR_CHIPIO_8051_READ_DIRECT = 0xD00,
812
813 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
814 VENDOR_CHIPIO_STATUS = 0xF01,
815 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
816 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
817
818 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
819 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
820 VENDOR_CHIPIO_8051_PMEM_READ = 0xF08,
821 VENDOR_CHIPIO_8051_IRAM_WRITE = 0x709,
822 VENDOR_CHIPIO_8051_IRAM_READ = 0xF09,
823
824 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
825 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
826
827 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
828 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
829 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
830 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
831 VENDOR_CHIPIO_FLAG_SET = 0x70F,
832 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
833 VENDOR_CHIPIO_PARAM_SET = 0x710,
834 VENDOR_CHIPIO_PARAM_GET = 0xF10,
835
836 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
837 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
838 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
839 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
840
841 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
842 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
843 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
844 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
845
846 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
847 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
848 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
849 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
850 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
851 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
852
853 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
854 };
855
856 /*
857 * Control flag IDs
858 */
859 enum control_flag_id {
860 /* Connection manager stream setup is bypassed/enabled */
861 CONTROL_FLAG_C_MGR = 0,
862 /* DSP DMA is bypassed/enabled */
863 CONTROL_FLAG_DMA = 1,
864 /* 8051 'idle' mode is disabled/enabled */
865 CONTROL_FLAG_IDLE_ENABLE = 2,
866 /* Tracker for the SPDIF-in path is bypassed/enabled */
867 CONTROL_FLAG_TRACKER = 3,
868 /* DigitalOut to Spdif2Out connection is disabled/enabled */
869 CONTROL_FLAG_SPDIF2OUT = 4,
870 /* Digital Microphone is disabled/enabled */
871 CONTROL_FLAG_DMIC = 5,
872 /* ADC_B rate is 48 kHz/96 kHz */
873 CONTROL_FLAG_ADC_B_96KHZ = 6,
874 /* ADC_C rate is 48 kHz/96 kHz */
875 CONTROL_FLAG_ADC_C_96KHZ = 7,
876 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
877 CONTROL_FLAG_DAC_96KHZ = 8,
878 /* DSP rate is 48 kHz/96 kHz */
879 CONTROL_FLAG_DSP_96KHZ = 9,
880 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
881 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
882 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
883 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
884 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
885 CONTROL_FLAG_DECODE_LOOP = 12,
886 /* De-emphasis filter on DAC-1 disabled/enabled */
887 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
888 /* De-emphasis filter on DAC-2 disabled/enabled */
889 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
890 /* De-emphasis filter on DAC-3 disabled/enabled */
891 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
892 /* High-pass filter on ADC_B disabled/enabled */
893 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
894 /* High-pass filter on ADC_C disabled/enabled */
895 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
896 /* Common mode on Port_A disabled/enabled */
897 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
898 /* Common mode on Port_D disabled/enabled */
899 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
900 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
901 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
902 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
903 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
904 /* ASI rate is 48kHz/96kHz */
905 CONTROL_FLAG_ASI_96KHZ = 22,
906 /* DAC power settings able to control attached ports no/yes */
907 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
908 /* Clock Stop OK reporting is disabled/enabled */
909 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
910 /* Number of control flags */
911 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
912 };
913
914 /*
915 * Control parameter IDs
916 */
917 enum control_param_id {
918 /* 0: None, 1: Mic1In*/
919 CONTROL_PARAM_VIP_SOURCE = 1,
920 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
921 CONTROL_PARAM_SPDIF1_SOURCE = 2,
922 /* Port A output stage gain setting to use when 16 Ohm output
923 * impedance is selected*/
924 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
925 /* Port D output stage gain setting to use when 16 Ohm output
926 * impedance is selected*/
927 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
928
929 /*
930 * This control param name was found in the 8051 memory, and makes
931 * sense given the fact the AE-5 uses it and has the ASI flag set.
932 */
933 CONTROL_PARAM_ASI = 23,
934
935 /* Stream Control */
936
937 /* Select stream with the given ID */
938 CONTROL_PARAM_STREAM_ID = 24,
939 /* Source connection point for the selected stream */
940 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
941 /* Destination connection point for the selected stream */
942 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
943 /* Number of audio channels in the selected stream */
944 CONTROL_PARAM_STREAMS_CHANNELS = 27,
945 /*Enable control for the selected stream */
946 CONTROL_PARAM_STREAM_CONTROL = 28,
947
948 /* Connection Point Control */
949
950 /* Select connection point with the given ID */
951 CONTROL_PARAM_CONN_POINT_ID = 29,
952 /* Connection point sample rate */
953 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
954
955 /* Node Control */
956
957 /* Select HDA node with the given ID */
958 CONTROL_PARAM_NODE_ID = 31
959 };
960
961 /*
962 * Dsp Io Status codes
963 */
964 enum hda_vendor_status_dspio {
965 /* Success */
966 VENDOR_STATUS_DSPIO_OK = 0x00,
967 /* Busy, unable to accept new command, the host must retry */
968 VENDOR_STATUS_DSPIO_BUSY = 0x01,
969 /* SCP command queue is full */
970 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
971 /* SCP response queue is empty */
972 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
973 };
974
975 /*
976 * Chip Io Status codes
977 */
978 enum hda_vendor_status_chipio {
979 /* Success */
980 VENDOR_STATUS_CHIPIO_OK = 0x00,
981 /* Busy, unable to accept new command, the host must retry */
982 VENDOR_STATUS_CHIPIO_BUSY = 0x01
983 };
984
985 /*
986 * CA0132 sample rate
987 */
988 enum ca0132_sample_rate {
989 SR_6_000 = 0x00,
990 SR_8_000 = 0x01,
991 SR_9_600 = 0x02,
992 SR_11_025 = 0x03,
993 SR_16_000 = 0x04,
994 SR_22_050 = 0x05,
995 SR_24_000 = 0x06,
996 SR_32_000 = 0x07,
997 SR_44_100 = 0x08,
998 SR_48_000 = 0x09,
999 SR_88_200 = 0x0A,
1000 SR_96_000 = 0x0B,
1001 SR_144_000 = 0x0C,
1002 SR_176_400 = 0x0D,
1003 SR_192_000 = 0x0E,
1004 SR_384_000 = 0x0F,
1005
1006 SR_COUNT = 0x10,
1007
1008 SR_RATE_UNKNOWN = 0x1F
1009 };
1010
1011 enum dsp_download_state {
1012 DSP_DOWNLOAD_FAILED = -1,
1013 DSP_DOWNLOAD_INIT = 0,
1014 DSP_DOWNLOADING = 1,
1015 DSP_DOWNLOADED = 2
1016 };
1017
1018 /* retrieve parameters from hda format */
1019 #define get_hdafmt_chs(fmt) (fmt & 0xf)
1020 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
1021 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
1022 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
1023
1024 /*
1025 * CA0132 specific
1026 */
1027
1028 struct ca0132_spec {
1029 const struct snd_kcontrol_new *mixers[5];
1030 unsigned int num_mixers;
1031 const struct hda_verb *base_init_verbs;
1032 const struct hda_verb *base_exit_verbs;
1033 const struct hda_verb *chip_init_verbs;
1034 const struct hda_verb *desktop_init_verbs;
1035 struct hda_verb *spec_init_verbs;
1036 struct auto_pin_cfg autocfg;
1037
1038 /* Nodes configurations */
1039 struct hda_multi_out multiout;
1040 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
1041 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
1042 unsigned int num_outputs;
1043 hda_nid_t input_pins[AUTO_PIN_LAST];
1044 hda_nid_t adcs[AUTO_PIN_LAST];
1045 hda_nid_t dig_out;
1046 hda_nid_t dig_in;
1047 unsigned int num_inputs;
1048 hda_nid_t shared_mic_nid;
1049 hda_nid_t shared_out_nid;
1050 hda_nid_t unsol_tag_hp;
1051 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
1052 hda_nid_t unsol_tag_amic1;
1053
1054 /* chip access */
1055 struct mutex chipio_mutex; /* chip access mutex */
1056 u32 curr_chip_addx;
1057
1058 /* DSP download related */
1059 enum dsp_download_state dsp_state;
1060 unsigned int dsp_stream_id;
1061 unsigned int wait_scp;
1062 unsigned int wait_scp_header;
1063 unsigned int wait_num_data;
1064 unsigned int scp_resp_header;
1065 unsigned int scp_resp_data[4];
1066 unsigned int scp_resp_count;
1067 bool startup_check_entered;
1068 bool dsp_reload;
1069
1070 /* mixer and effects related */
1071 unsigned char dmic_ctl;
1072 int cur_out_type;
1073 int cur_mic_type;
1074 long vnode_lvol[VNODES_COUNT];
1075 long vnode_rvol[VNODES_COUNT];
1076 long vnode_lswitch[VNODES_COUNT];
1077 long vnode_rswitch[VNODES_COUNT];
1078 long effects_switch[EFFECTS_COUNT];
1079 long voicefx_val;
1080 long cur_mic_boost;
1081 /* ca0132_alt control related values */
1082 unsigned char in_enum_val;
1083 unsigned char out_enum_val;
1084 unsigned char channel_cfg_val;
1085 unsigned char speaker_range_val[2];
1086 unsigned char mic_boost_enum_val;
1087 unsigned char smart_volume_setting;
1088 unsigned char bass_redirection_val;
1089 long bass_redirect_xover_freq;
1090 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
1091 long xbass_xover_freq;
1092 long eq_preset_val;
1093 unsigned int tlv[4];
1094 struct hda_vmaster_mute_hook vmaster_mute;
1095 /* AE-5 Control values */
1096 unsigned char ae5_headphone_gain_val;
1097 unsigned char ae5_filter_val;
1098 /* ZxR Control Values */
1099 unsigned char zxr_gain_set;
1100
1101 struct hda_codec *codec;
1102 struct delayed_work unsol_hp_work;
1103 int quirk;
1104
1105 #ifdef ENABLE_TUNING_CONTROLS
1106 long cur_ctl_vals[TUNING_CTLS_COUNT];
1107 #endif
1108 /*
1109 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
1110 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
1111 * things.
1112 */
1113 bool use_pci_mmio;
1114 void __iomem *mem_base;
1115
1116 /*
1117 * Whether or not to use the alt functions like alt_select_out,
1118 * alt_select_in, etc. Only used on desktop codecs for now, because of
1119 * surround sound support.
1120 */
1121 bool use_alt_functions;
1122
1123 /*
1124 * Whether or not to use alt controls: volume effect sliders, EQ
1125 * presets, smart volume presets, and new control names with FX prefix.
1126 * Renames PlayEnhancement and CrystalVoice too.
1127 */
1128 bool use_alt_controls;
1129 };
1130
1131 /*
1132 * CA0132 quirks table
1133 */
1134 enum {
1135 QUIRK_NONE,
1136 QUIRK_ALIENWARE,
1137 QUIRK_ALIENWARE_M17XR4,
1138 QUIRK_SBZ,
1139 QUIRK_ZXR,
1140 QUIRK_ZXR_DBPRO,
1141 QUIRK_R3DI,
1142 QUIRK_R3D,
1143 QUIRK_AE5,
1144 QUIRK_AE7,
1145 };
1146
1147 #ifdef CONFIG_PCI
1148 #define ca0132_quirk(spec) ((spec)->quirk)
1149 #define ca0132_use_pci_mmio(spec) ((spec)->use_pci_mmio)
1150 #define ca0132_use_alt_functions(spec) ((spec)->use_alt_functions)
1151 #define ca0132_use_alt_controls(spec) ((spec)->use_alt_controls)
1152 #else
1153 #define ca0132_quirk(spec) ({ (void)(spec); QUIRK_NONE; })
1154 #define ca0132_use_alt_functions(spec) ({ (void)(spec); false; })
1155 #define ca0132_use_pci_mmio(spec) ({ (void)(spec); false; })
1156 #define ca0132_use_alt_controls(spec) ({ (void)(spec); false; })
1157 #endif
1158
1159 static const struct hda_pintbl alienware_pincfgs[] = {
1160 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1161 { 0x0c, 0x411111f0 }, /* N/A */
1162 { 0x0d, 0x411111f0 }, /* N/A */
1163 { 0x0e, 0x411111f0 }, /* N/A */
1164 { 0x0f, 0x0321101f }, /* HP */
1165 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1166 { 0x11, 0x03a11021 }, /* Mic */
1167 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1168 { 0x13, 0x411111f0 }, /* N/A */
1169 { 0x18, 0x411111f0 }, /* N/A */
1170 {}
1171 };
1172
1173 /* Sound Blaster Z pin configs taken from Windows Driver */
1174 static const struct hda_pintbl sbz_pincfgs[] = {
1175 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1176 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1177 { 0x0d, 0x014510f0 }, /* Digital Out */
1178 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1179 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1180 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1181 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1182 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1183 { 0x13, 0x908700f0 }, /* What U Hear In*/
1184 { 0x18, 0x50d000f0 }, /* N/A */
1185 {}
1186 };
1187
1188 /* Sound Blaster ZxR pin configs taken from Windows Driver */
1189 static const struct hda_pintbl zxr_pincfgs[] = {
1190 { 0x0b, 0x01047110 }, /* Port G -- Lineout FRONT L/R */
1191 { 0x0c, 0x414510f0 }, /* SPDIF Out 1 - Disabled*/
1192 { 0x0d, 0x014510f0 }, /* Digital Out */
1193 { 0x0e, 0x41c520f0 }, /* SPDIF In - Disabled*/
1194 { 0x0f, 0x0122711f }, /* Port A -- BackPanel HP */
1195 { 0x10, 0x01017111 }, /* Port D -- Center/LFE */
1196 { 0x11, 0x01017114 }, /* Port B -- LineMicIn2 / Rear L/R */
1197 { 0x12, 0x01a271f0 }, /* Port C -- LineIn1 */
1198 { 0x13, 0x908700f0 }, /* What U Hear In*/
1199 { 0x18, 0x50d000f0 }, /* N/A */
1200 {}
1201 };
1202
1203 /* Recon3D pin configs taken from Windows Driver */
1204 static const struct hda_pintbl r3d_pincfgs[] = {
1205 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1206 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1207 { 0x0d, 0x014510f0 }, /* Digital Out */
1208 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1209 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1210 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1211 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1212 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1213 { 0x13, 0x908700f0 }, /* What U Hear In*/
1214 { 0x18, 0x50d000f0 }, /* N/A */
1215 {}
1216 };
1217
1218 /* Sound Blaster AE-5 pin configs taken from Windows Driver */
1219 static const struct hda_pintbl ae5_pincfgs[] = {
1220 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1221 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1222 { 0x0d, 0x014510f0 }, /* Digital Out */
1223 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1224 { 0x0f, 0x01017114 }, /* Port A -- Rear L/R. */
1225 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1226 { 0x11, 0x012170ff }, /* Port B -- LineMicIn2 / Rear Headphone */
1227 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1228 { 0x13, 0x908700f0 }, /* What U Hear In*/
1229 { 0x18, 0x50d000f0 }, /* N/A */
1230 {}
1231 };
1232
1233 /* Recon3D integrated pin configs taken from Windows Driver */
1234 static const struct hda_pintbl r3di_pincfgs[] = {
1235 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1236 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1237 { 0x0d, 0x014510f0 }, /* Digital Out */
1238 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1239 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1240 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1241 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1242 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1243 { 0x13, 0x908700f0 }, /* What U Hear In*/
1244 { 0x18, 0x500000f0 }, /* N/A */
1245 {}
1246 };
1247
1248 static const struct hda_pintbl ae7_pincfgs[] = {
1249 { 0x0b, 0x01017010 },
1250 { 0x0c, 0x014510f0 },
1251 { 0x0d, 0x414510f0 },
1252 { 0x0e, 0x01c520f0 },
1253 { 0x0f, 0x01017114 },
1254 { 0x10, 0x01017011 },
1255 { 0x11, 0x018170ff },
1256 { 0x12, 0x01a170f0 },
1257 { 0x13, 0x908700f0 },
1258 { 0x18, 0x500000f0 },
1259 {}
1260 };
1261
1262 static const struct snd_pci_quirk ca0132_quirks[] = {
1263 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1264 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1265 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1266 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1267 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1268 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1269 SND_PCI_QUIRK(0x1102, 0x0027, "Sound Blaster Z", QUIRK_SBZ),
1270 SND_PCI_QUIRK(0x1102, 0x0033, "Sound Blaster ZxR", QUIRK_SBZ),
1271 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1272 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1273 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1274 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1275 SND_PCI_QUIRK(0x3842, 0x1055, "EVGA Z390 DARK", QUIRK_R3DI),
1276 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1277 SND_PCI_QUIRK(0x1102, 0x0018, "Recon3D", QUIRK_R3D),
1278 SND_PCI_QUIRK(0x1102, 0x0051, "Sound Blaster AE-5", QUIRK_AE5),
1279 SND_PCI_QUIRK(0x1102, 0x0191, "Sound Blaster AE-5 Plus", QUIRK_AE5),
1280 SND_PCI_QUIRK(0x1102, 0x0081, "Sound Blaster AE-7", QUIRK_AE7),
1281 {}
1282 };
1283
1284 /* Output selection quirk info structures. */
1285 #define MAX_QUIRK_MMIO_GPIO_SET_VALS 3
1286 #define MAX_QUIRK_SCP_SET_VALS 2
1287 struct ca0132_alt_out_set_info {
1288 unsigned int dac2port; /* ParamID 0x0d value. */
1289
1290 bool has_hda_gpio;
1291 char hda_gpio_pin;
1292 char hda_gpio_set;
1293
1294 unsigned int mmio_gpio_count;
1295 char mmio_gpio_pin[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1296 char mmio_gpio_set[MAX_QUIRK_MMIO_GPIO_SET_VALS];
1297
1298 unsigned int scp_cmds_count;
1299 unsigned int scp_cmd_mid[MAX_QUIRK_SCP_SET_VALS];
1300 unsigned int scp_cmd_req[MAX_QUIRK_SCP_SET_VALS];
1301 unsigned int scp_cmd_val[MAX_QUIRK_SCP_SET_VALS];
1302
1303 bool has_chipio_write;
1304 unsigned int chipio_write_addr;
1305 unsigned int chipio_write_data;
1306 };
1307
1308 struct ca0132_alt_out_set_quirk_data {
1309 int quirk_id;
1310
1311 bool has_headphone_gain;
1312 bool is_ae_series;
1313
1314 struct ca0132_alt_out_set_info out_set_info[NUM_OF_OUTPUTS];
1315 };
1316
1317 static const struct ca0132_alt_out_set_quirk_data quirk_out_set_data[] = {
1318 { .quirk_id = QUIRK_R3DI,
1319 .has_headphone_gain = false,
1320 .is_ae_series = false,
1321 .out_set_info = {
1322 /* Speakers. */
1323 { .dac2port = 0x24,
1324 .has_hda_gpio = true,
1325 .hda_gpio_pin = 2,
1326 .hda_gpio_set = 1,
1327 .mmio_gpio_count = 0,
1328 .scp_cmds_count = 0,
1329 .has_chipio_write = false,
1330 },
1331 /* Headphones. */
1332 { .dac2port = 0x21,
1333 .has_hda_gpio = true,
1334 .hda_gpio_pin = 2,
1335 .hda_gpio_set = 0,
1336 .mmio_gpio_count = 0,
1337 .scp_cmds_count = 0,
1338 .has_chipio_write = false,
1339 } },
1340 },
1341 { .quirk_id = QUIRK_R3D,
1342 .has_headphone_gain = false,
1343 .is_ae_series = false,
1344 .out_set_info = {
1345 /* Speakers. */
1346 { .dac2port = 0x24,
1347 .has_hda_gpio = false,
1348 .mmio_gpio_count = 1,
1349 .mmio_gpio_pin = { 1 },
1350 .mmio_gpio_set = { 1 },
1351 .scp_cmds_count = 0,
1352 .has_chipio_write = false,
1353 },
1354 /* Headphones. */
1355 { .dac2port = 0x21,
1356 .has_hda_gpio = false,
1357 .mmio_gpio_count = 1,
1358 .mmio_gpio_pin = { 1 },
1359 .mmio_gpio_set = { 0 },
1360 .scp_cmds_count = 0,
1361 .has_chipio_write = false,
1362 } },
1363 },
1364 { .quirk_id = QUIRK_SBZ,
1365 .has_headphone_gain = false,
1366 .is_ae_series = false,
1367 .out_set_info = {
1368 /* Speakers. */
1369 { .dac2port = 0x18,
1370 .has_hda_gpio = false,
1371 .mmio_gpio_count = 3,
1372 .mmio_gpio_pin = { 7, 4, 1 },
1373 .mmio_gpio_set = { 0, 1, 1 },
1374 .scp_cmds_count = 0,
1375 .has_chipio_write = false, },
1376 /* Headphones. */
1377 { .dac2port = 0x12,
1378 .has_hda_gpio = false,
1379 .mmio_gpio_count = 3,
1380 .mmio_gpio_pin = { 7, 4, 1 },
1381 .mmio_gpio_set = { 1, 1, 0 },
1382 .scp_cmds_count = 0,
1383 .has_chipio_write = false,
1384 } },
1385 },
1386 { .quirk_id = QUIRK_ZXR,
1387 .has_headphone_gain = true,
1388 .is_ae_series = false,
1389 .out_set_info = {
1390 /* Speakers. */
1391 { .dac2port = 0x24,
1392 .has_hda_gpio = false,
1393 .mmio_gpio_count = 3,
1394 .mmio_gpio_pin = { 2, 3, 5 },
1395 .mmio_gpio_set = { 1, 1, 0 },
1396 .scp_cmds_count = 0,
1397 .has_chipio_write = false,
1398 },
1399 /* Headphones. */
1400 { .dac2port = 0x21,
1401 .has_hda_gpio = false,
1402 .mmio_gpio_count = 3,
1403 .mmio_gpio_pin = { 2, 3, 5 },
1404 .mmio_gpio_set = { 0, 1, 1 },
1405 .scp_cmds_count = 0,
1406 .has_chipio_write = false,
1407 } },
1408 },
1409 { .quirk_id = QUIRK_AE5,
1410 .has_headphone_gain = true,
1411 .is_ae_series = true,
1412 .out_set_info = {
1413 /* Speakers. */
1414 { .dac2port = 0xa4,
1415 .has_hda_gpio = false,
1416 .mmio_gpio_count = 0,
1417 .scp_cmds_count = 2,
1418 .scp_cmd_mid = { 0x96, 0x96 },
1419 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1420 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1421 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1422 .has_chipio_write = true,
1423 .chipio_write_addr = 0x0018b03c,
1424 .chipio_write_data = 0x00000012
1425 },
1426 /* Headphones. */
1427 { .dac2port = 0xa1,
1428 .has_hda_gpio = false,
1429 .mmio_gpio_count = 0,
1430 .scp_cmds_count = 2,
1431 .scp_cmd_mid = { 0x96, 0x96 },
1432 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1433 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1434 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1435 .has_chipio_write = true,
1436 .chipio_write_addr = 0x0018b03c,
1437 .chipio_write_data = 0x00000012
1438 } },
1439 },
1440 { .quirk_id = QUIRK_AE7,
1441 .has_headphone_gain = true,
1442 .is_ae_series = true,
1443 .out_set_info = {
1444 /* Speakers. */
1445 { .dac2port = 0x58,
1446 .has_hda_gpio = false,
1447 .mmio_gpio_count = 1,
1448 .mmio_gpio_pin = { 0 },
1449 .mmio_gpio_set = { 1 },
1450 .scp_cmds_count = 2,
1451 .scp_cmd_mid = { 0x96, 0x96 },
1452 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1453 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1454 .scp_cmd_val = { FLOAT_ZERO, FLOAT_ZERO },
1455 .has_chipio_write = true,
1456 .chipio_write_addr = 0x0018b03c,
1457 .chipio_write_data = 0x00000000
1458 },
1459 /* Headphones. */
1460 { .dac2port = 0x58,
1461 .has_hda_gpio = false,
1462 .mmio_gpio_count = 1,
1463 .mmio_gpio_pin = { 0 },
1464 .mmio_gpio_set = { 1 },
1465 .scp_cmds_count = 2,
1466 .scp_cmd_mid = { 0x96, 0x96 },
1467 .scp_cmd_req = { SPEAKER_TUNING_FRONT_LEFT_INVERT,
1468 SPEAKER_TUNING_FRONT_RIGHT_INVERT },
1469 .scp_cmd_val = { FLOAT_ONE, FLOAT_ONE },
1470 .has_chipio_write = true,
1471 .chipio_write_addr = 0x0018b03c,
1472 .chipio_write_data = 0x00000010
1473 } },
1474 }
1475 };
1476
1477 /*
1478 * CA0132 codec access
1479 */
codec_send_command(struct hda_codec * codec,hda_nid_t nid,unsigned int verb,unsigned int parm,unsigned int * res)1480 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1481 unsigned int verb, unsigned int parm, unsigned int *res)
1482 {
1483 unsigned int response;
1484 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1485 *res = response;
1486
1487 return ((response == -1) ? -1 : 0);
1488 }
1489
codec_set_converter_format(struct hda_codec * codec,hda_nid_t nid,unsigned short converter_format,unsigned int * res)1490 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1491 unsigned short converter_format, unsigned int *res)
1492 {
1493 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1494 converter_format & 0xffff, res);
1495 }
1496
codec_set_converter_stream_channel(struct hda_codec * codec,hda_nid_t nid,unsigned char stream,unsigned char channel,unsigned int * res)1497 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1498 hda_nid_t nid, unsigned char stream,
1499 unsigned char channel, unsigned int *res)
1500 {
1501 unsigned char converter_stream_channel = 0;
1502
1503 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1504 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1505 converter_stream_channel, res);
1506 }
1507
1508 /* Chip access helper function */
chipio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)1509 static int chipio_send(struct hda_codec *codec,
1510 unsigned int reg,
1511 unsigned int data)
1512 {
1513 unsigned int res;
1514 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1515
1516 /* send bits of data specified by reg */
1517 do {
1518 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1519 reg, data);
1520 if (res == VENDOR_STATUS_CHIPIO_OK)
1521 return 0;
1522 msleep(20);
1523 } while (time_before(jiffies, timeout));
1524
1525 return -EIO;
1526 }
1527
1528 /*
1529 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1530 */
chipio_write_address(struct hda_codec * codec,unsigned int chip_addx)1531 static int chipio_write_address(struct hda_codec *codec,
1532 unsigned int chip_addx)
1533 {
1534 struct ca0132_spec *spec = codec->spec;
1535 int res;
1536
1537 if (spec->curr_chip_addx == chip_addx)
1538 return 0;
1539
1540 /* send low 16 bits of the address */
1541 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1542 chip_addx & 0xffff);
1543
1544 if (res != -EIO) {
1545 /* send high 16 bits of the address */
1546 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1547 chip_addx >> 16);
1548 }
1549
1550 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1551
1552 return res;
1553 }
1554
1555 /*
1556 * Write data through the vendor widget -- NOT protected by the Mutex!
1557 */
chipio_write_data(struct hda_codec * codec,unsigned int data)1558 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1559 {
1560 struct ca0132_spec *spec = codec->spec;
1561 int res;
1562
1563 /* send low 16 bits of the data */
1564 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1565
1566 if (res != -EIO) {
1567 /* send high 16 bits of the data */
1568 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1569 data >> 16);
1570 }
1571
1572 /*If no error encountered, automatically increment the address
1573 as per chip behaviour*/
1574 spec->curr_chip_addx = (res != -EIO) ?
1575 (spec->curr_chip_addx + 4) : ~0U;
1576 return res;
1577 }
1578
1579 /*
1580 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1581 */
chipio_write_data_multiple(struct hda_codec * codec,const u32 * data,unsigned int count)1582 static int chipio_write_data_multiple(struct hda_codec *codec,
1583 const u32 *data,
1584 unsigned int count)
1585 {
1586 int status = 0;
1587
1588 if (data == NULL) {
1589 codec_dbg(codec, "chipio_write_data null ptr\n");
1590 return -EINVAL;
1591 }
1592
1593 while ((count-- != 0) && (status == 0))
1594 status = chipio_write_data(codec, *data++);
1595
1596 return status;
1597 }
1598
1599
1600 /*
1601 * Read data through the vendor widget -- NOT protected by the Mutex!
1602 */
chipio_read_data(struct hda_codec * codec,unsigned int * data)1603 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1604 {
1605 struct ca0132_spec *spec = codec->spec;
1606 int res;
1607
1608 /* post read */
1609 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1610
1611 if (res != -EIO) {
1612 /* read status */
1613 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1614 }
1615
1616 if (res != -EIO) {
1617 /* read data */
1618 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1619 VENDOR_CHIPIO_HIC_READ_DATA,
1620 0);
1621 }
1622
1623 /*If no error encountered, automatically increment the address
1624 as per chip behaviour*/
1625 spec->curr_chip_addx = (res != -EIO) ?
1626 (spec->curr_chip_addx + 4) : ~0U;
1627 return res;
1628 }
1629
1630 /*
1631 * Write given value to the given address through the chip I/O widget.
1632 * protected by the Mutex
1633 */
chipio_write(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1634 static int chipio_write(struct hda_codec *codec,
1635 unsigned int chip_addx, const unsigned int data)
1636 {
1637 struct ca0132_spec *spec = codec->spec;
1638 int err;
1639
1640 mutex_lock(&spec->chipio_mutex);
1641
1642 /* write the address, and if successful proceed to write data */
1643 err = chipio_write_address(codec, chip_addx);
1644 if (err < 0)
1645 goto exit;
1646
1647 err = chipio_write_data(codec, data);
1648 if (err < 0)
1649 goto exit;
1650
1651 exit:
1652 mutex_unlock(&spec->chipio_mutex);
1653 return err;
1654 }
1655
1656 /*
1657 * Write given value to the given address through the chip I/O widget.
1658 * not protected by the Mutex
1659 */
chipio_write_no_mutex(struct hda_codec * codec,unsigned int chip_addx,const unsigned int data)1660 static int chipio_write_no_mutex(struct hda_codec *codec,
1661 unsigned int chip_addx, const unsigned int data)
1662 {
1663 int err;
1664
1665
1666 /* write the address, and if successful proceed to write data */
1667 err = chipio_write_address(codec, chip_addx);
1668 if (err < 0)
1669 goto exit;
1670
1671 err = chipio_write_data(codec, data);
1672 if (err < 0)
1673 goto exit;
1674
1675 exit:
1676 return err;
1677 }
1678
1679 /*
1680 * Write multiple values to the given address through the chip I/O widget.
1681 * protected by the Mutex
1682 */
chipio_write_multiple(struct hda_codec * codec,u32 chip_addx,const u32 * data,unsigned int count)1683 static int chipio_write_multiple(struct hda_codec *codec,
1684 u32 chip_addx,
1685 const u32 *data,
1686 unsigned int count)
1687 {
1688 struct ca0132_spec *spec = codec->spec;
1689 int status;
1690
1691 mutex_lock(&spec->chipio_mutex);
1692 status = chipio_write_address(codec, chip_addx);
1693 if (status < 0)
1694 goto error;
1695
1696 status = chipio_write_data_multiple(codec, data, count);
1697 error:
1698 mutex_unlock(&spec->chipio_mutex);
1699
1700 return status;
1701 }
1702
1703 /*
1704 * Read the given address through the chip I/O widget
1705 * protected by the Mutex
1706 */
chipio_read(struct hda_codec * codec,unsigned int chip_addx,unsigned int * data)1707 static int chipio_read(struct hda_codec *codec,
1708 unsigned int chip_addx, unsigned int *data)
1709 {
1710 struct ca0132_spec *spec = codec->spec;
1711 int err;
1712
1713 mutex_lock(&spec->chipio_mutex);
1714
1715 /* write the address, and if successful proceed to write data */
1716 err = chipio_write_address(codec, chip_addx);
1717 if (err < 0)
1718 goto exit;
1719
1720 err = chipio_read_data(codec, data);
1721 if (err < 0)
1722 goto exit;
1723
1724 exit:
1725 mutex_unlock(&spec->chipio_mutex);
1726 return err;
1727 }
1728
1729 /*
1730 * Set chip control flags through the chip I/O widget.
1731 */
chipio_set_control_flag(struct hda_codec * codec,enum control_flag_id flag_id,bool flag_state)1732 static void chipio_set_control_flag(struct hda_codec *codec,
1733 enum control_flag_id flag_id,
1734 bool flag_state)
1735 {
1736 unsigned int val;
1737 unsigned int flag_bit;
1738
1739 flag_bit = (flag_state ? 1 : 0);
1740 val = (flag_bit << 7) | (flag_id);
1741 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1742 VENDOR_CHIPIO_FLAG_SET, val);
1743 }
1744
1745 /*
1746 * Set chip parameters through the chip I/O widget.
1747 */
chipio_set_control_param(struct hda_codec * codec,enum control_param_id param_id,int param_val)1748 static void chipio_set_control_param(struct hda_codec *codec,
1749 enum control_param_id param_id, int param_val)
1750 {
1751 struct ca0132_spec *spec = codec->spec;
1752 int val;
1753
1754 if ((param_id < 32) && (param_val < 8)) {
1755 val = (param_val << 5) | (param_id);
1756 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1757 VENDOR_CHIPIO_PARAM_SET, val);
1758 } else {
1759 mutex_lock(&spec->chipio_mutex);
1760 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1761 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1762 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1763 param_id);
1764 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1765 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1766 param_val);
1767 }
1768 mutex_unlock(&spec->chipio_mutex);
1769 }
1770 }
1771
1772 /*
1773 * Set chip parameters through the chip I/O widget. NO MUTEX.
1774 */
chipio_set_control_param_no_mutex(struct hda_codec * codec,enum control_param_id param_id,int param_val)1775 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1776 enum control_param_id param_id, int param_val)
1777 {
1778 int val;
1779
1780 if ((param_id < 32) && (param_val < 8)) {
1781 val = (param_val << 5) | (param_id);
1782 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1783 VENDOR_CHIPIO_PARAM_SET, val);
1784 } else {
1785 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1786 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1787 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1788 param_id);
1789 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1790 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1791 param_val);
1792 }
1793 }
1794 }
1795 /*
1796 * Connect stream to a source point, and then connect
1797 * that source point to a destination point.
1798 */
chipio_set_stream_source_dest(struct hda_codec * codec,int streamid,int source_point,int dest_point)1799 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1800 int streamid, int source_point, int dest_point)
1801 {
1802 chipio_set_control_param_no_mutex(codec,
1803 CONTROL_PARAM_STREAM_ID, streamid);
1804 chipio_set_control_param_no_mutex(codec,
1805 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1806 chipio_set_control_param_no_mutex(codec,
1807 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1808 }
1809
1810 /*
1811 * Set number of channels in the selected stream.
1812 */
chipio_set_stream_channels(struct hda_codec * codec,int streamid,unsigned int channels)1813 static void chipio_set_stream_channels(struct hda_codec *codec,
1814 int streamid, unsigned int channels)
1815 {
1816 chipio_set_control_param_no_mutex(codec,
1817 CONTROL_PARAM_STREAM_ID, streamid);
1818 chipio_set_control_param_no_mutex(codec,
1819 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1820 }
1821
1822 /*
1823 * Enable/Disable audio stream.
1824 */
chipio_set_stream_control(struct hda_codec * codec,int streamid,int enable)1825 static void chipio_set_stream_control(struct hda_codec *codec,
1826 int streamid, int enable)
1827 {
1828 chipio_set_control_param_no_mutex(codec,
1829 CONTROL_PARAM_STREAM_ID, streamid);
1830 chipio_set_control_param_no_mutex(codec,
1831 CONTROL_PARAM_STREAM_CONTROL, enable);
1832 }
1833
1834
1835 /*
1836 * Set sampling rate of the connection point. NO MUTEX.
1837 */
chipio_set_conn_rate_no_mutex(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1838 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1839 int connid, enum ca0132_sample_rate rate)
1840 {
1841 chipio_set_control_param_no_mutex(codec,
1842 CONTROL_PARAM_CONN_POINT_ID, connid);
1843 chipio_set_control_param_no_mutex(codec,
1844 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1845 }
1846
1847 /*
1848 * Set sampling rate of the connection point.
1849 */
chipio_set_conn_rate(struct hda_codec * codec,int connid,enum ca0132_sample_rate rate)1850 static void chipio_set_conn_rate(struct hda_codec *codec,
1851 int connid, enum ca0132_sample_rate rate)
1852 {
1853 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1854 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1855 rate);
1856 }
1857
1858 /*
1859 * Writes to the 8051's internal address space directly instead of indirectly,
1860 * giving access to the special function registers located at addresses
1861 * 0x80-0xFF.
1862 */
chipio_8051_write_direct(struct hda_codec * codec,unsigned int addr,unsigned int data)1863 static void chipio_8051_write_direct(struct hda_codec *codec,
1864 unsigned int addr, unsigned int data)
1865 {
1866 unsigned int verb;
1867
1868 verb = VENDOR_CHIPIO_8051_WRITE_DIRECT | data;
1869 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, verb, addr);
1870 }
1871
1872 /*
1873 * Enable clocks.
1874 */
chipio_enable_clocks(struct hda_codec * codec)1875 static void chipio_enable_clocks(struct hda_codec *codec)
1876 {
1877 struct ca0132_spec *spec = codec->spec;
1878
1879 mutex_lock(&spec->chipio_mutex);
1880 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1881 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1882 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1883 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1884 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1885 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1886 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1887 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1888 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1889 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1890 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1891 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1892 mutex_unlock(&spec->chipio_mutex);
1893 }
1894
1895 /*
1896 * CA0132 DSP IO stuffs
1897 */
dspio_send(struct hda_codec * codec,unsigned int reg,unsigned int data)1898 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1899 unsigned int data)
1900 {
1901 int res;
1902 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1903
1904 /* send bits of data specified by reg to dsp */
1905 do {
1906 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1907 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1908 return res;
1909 msleep(20);
1910 } while (time_before(jiffies, timeout));
1911
1912 return -EIO;
1913 }
1914
1915 /*
1916 * Wait for DSP to be ready for commands
1917 */
dspio_write_wait(struct hda_codec * codec)1918 static void dspio_write_wait(struct hda_codec *codec)
1919 {
1920 int status;
1921 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1922
1923 do {
1924 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1925 VENDOR_DSPIO_STATUS, 0);
1926 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1927 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1928 break;
1929 msleep(1);
1930 } while (time_before(jiffies, timeout));
1931 }
1932
1933 /*
1934 * Write SCP data to DSP
1935 */
dspio_write(struct hda_codec * codec,unsigned int scp_data)1936 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1937 {
1938 struct ca0132_spec *spec = codec->spec;
1939 int status;
1940
1941 dspio_write_wait(codec);
1942
1943 mutex_lock(&spec->chipio_mutex);
1944 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1945 scp_data & 0xffff);
1946 if (status < 0)
1947 goto error;
1948
1949 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1950 scp_data >> 16);
1951 if (status < 0)
1952 goto error;
1953
1954 /* OK, now check if the write itself has executed*/
1955 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1956 VENDOR_DSPIO_STATUS, 0);
1957 error:
1958 mutex_unlock(&spec->chipio_mutex);
1959
1960 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1961 -EIO : 0;
1962 }
1963
1964 /*
1965 * Write multiple SCP data to DSP
1966 */
dspio_write_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int size)1967 static int dspio_write_multiple(struct hda_codec *codec,
1968 unsigned int *buffer, unsigned int size)
1969 {
1970 int status = 0;
1971 unsigned int count;
1972
1973 if (buffer == NULL)
1974 return -EINVAL;
1975
1976 count = 0;
1977 while (count < size) {
1978 status = dspio_write(codec, *buffer++);
1979 if (status != 0)
1980 break;
1981 count++;
1982 }
1983
1984 return status;
1985 }
1986
dspio_read(struct hda_codec * codec,unsigned int * data)1987 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1988 {
1989 int status;
1990
1991 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1992 if (status == -EIO)
1993 return status;
1994
1995 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1996 if (status == -EIO ||
1997 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1998 return -EIO;
1999
2000 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
2001 VENDOR_DSPIO_SCP_READ_DATA, 0);
2002
2003 return 0;
2004 }
2005
dspio_read_multiple(struct hda_codec * codec,unsigned int * buffer,unsigned int * buf_size,unsigned int size_count)2006 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
2007 unsigned int *buf_size, unsigned int size_count)
2008 {
2009 int status = 0;
2010 unsigned int size = *buf_size;
2011 unsigned int count;
2012 unsigned int skip_count;
2013 unsigned int dummy;
2014
2015 if (buffer == NULL)
2016 return -1;
2017
2018 count = 0;
2019 while (count < size && count < size_count) {
2020 status = dspio_read(codec, buffer++);
2021 if (status != 0)
2022 break;
2023 count++;
2024 }
2025
2026 skip_count = count;
2027 if (status == 0) {
2028 while (skip_count < size) {
2029 status = dspio_read(codec, &dummy);
2030 if (status != 0)
2031 break;
2032 skip_count++;
2033 }
2034 }
2035 *buf_size = count;
2036
2037 return status;
2038 }
2039
2040 /*
2041 * Construct the SCP header using corresponding fields
2042 */
2043 static inline unsigned int
make_scp_header(unsigned int target_id,unsigned int source_id,unsigned int get_flag,unsigned int req,unsigned int device_flag,unsigned int resp_flag,unsigned int error_flag,unsigned int data_size)2044 make_scp_header(unsigned int target_id, unsigned int source_id,
2045 unsigned int get_flag, unsigned int req,
2046 unsigned int device_flag, unsigned int resp_flag,
2047 unsigned int error_flag, unsigned int data_size)
2048 {
2049 unsigned int header = 0;
2050
2051 header = (data_size & 0x1f) << 27;
2052 header |= (error_flag & 0x01) << 26;
2053 header |= (resp_flag & 0x01) << 25;
2054 header |= (device_flag & 0x01) << 24;
2055 header |= (req & 0x7f) << 17;
2056 header |= (get_flag & 0x01) << 16;
2057 header |= (source_id & 0xff) << 8;
2058 header |= target_id & 0xff;
2059
2060 return header;
2061 }
2062
2063 /*
2064 * Extract corresponding fields from SCP header
2065 */
2066 static inline void
extract_scp_header(unsigned int header,unsigned int * target_id,unsigned int * source_id,unsigned int * get_flag,unsigned int * req,unsigned int * device_flag,unsigned int * resp_flag,unsigned int * error_flag,unsigned int * data_size)2067 extract_scp_header(unsigned int header,
2068 unsigned int *target_id, unsigned int *source_id,
2069 unsigned int *get_flag, unsigned int *req,
2070 unsigned int *device_flag, unsigned int *resp_flag,
2071 unsigned int *error_flag, unsigned int *data_size)
2072 {
2073 if (data_size)
2074 *data_size = (header >> 27) & 0x1f;
2075 if (error_flag)
2076 *error_flag = (header >> 26) & 0x01;
2077 if (resp_flag)
2078 *resp_flag = (header >> 25) & 0x01;
2079 if (device_flag)
2080 *device_flag = (header >> 24) & 0x01;
2081 if (req)
2082 *req = (header >> 17) & 0x7f;
2083 if (get_flag)
2084 *get_flag = (header >> 16) & 0x01;
2085 if (source_id)
2086 *source_id = (header >> 8) & 0xff;
2087 if (target_id)
2088 *target_id = header & 0xff;
2089 }
2090
2091 #define SCP_MAX_DATA_WORDS (16)
2092
2093 /* Structure to contain any SCP message */
2094 struct scp_msg {
2095 unsigned int hdr;
2096 unsigned int data[SCP_MAX_DATA_WORDS];
2097 };
2098
dspio_clear_response_queue(struct hda_codec * codec)2099 static void dspio_clear_response_queue(struct hda_codec *codec)
2100 {
2101 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2102 unsigned int dummy = 0;
2103 int status;
2104
2105 /* clear all from the response queue */
2106 do {
2107 status = dspio_read(codec, &dummy);
2108 } while (status == 0 && time_before(jiffies, timeout));
2109 }
2110
dspio_get_response_data(struct hda_codec * codec)2111 static int dspio_get_response_data(struct hda_codec *codec)
2112 {
2113 struct ca0132_spec *spec = codec->spec;
2114 unsigned int data = 0;
2115 unsigned int count;
2116
2117 if (dspio_read(codec, &data) < 0)
2118 return -EIO;
2119
2120 if ((data & 0x00ffffff) == spec->wait_scp_header) {
2121 spec->scp_resp_header = data;
2122 spec->scp_resp_count = data >> 27;
2123 count = spec->wait_num_data;
2124 dspio_read_multiple(codec, spec->scp_resp_data,
2125 &spec->scp_resp_count, count);
2126 return 0;
2127 }
2128
2129 return -EIO;
2130 }
2131
2132 /*
2133 * Send SCP message to DSP
2134 */
dspio_send_scp_message(struct hda_codec * codec,unsigned char * send_buf,unsigned int send_buf_size,unsigned char * return_buf,unsigned int return_buf_size,unsigned int * bytes_returned)2135 static int dspio_send_scp_message(struct hda_codec *codec,
2136 unsigned char *send_buf,
2137 unsigned int send_buf_size,
2138 unsigned char *return_buf,
2139 unsigned int return_buf_size,
2140 unsigned int *bytes_returned)
2141 {
2142 struct ca0132_spec *spec = codec->spec;
2143 int status = -1;
2144 unsigned int scp_send_size = 0;
2145 unsigned int total_size;
2146 bool waiting_for_resp = false;
2147 unsigned int header;
2148 struct scp_msg *ret_msg;
2149 unsigned int resp_src_id, resp_target_id;
2150 unsigned int data_size, src_id, target_id, get_flag, device_flag;
2151
2152 if (bytes_returned)
2153 *bytes_returned = 0;
2154
2155 /* get scp header from buffer */
2156 header = *((unsigned int *)send_buf);
2157 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
2158 &device_flag, NULL, NULL, &data_size);
2159 scp_send_size = data_size + 1;
2160 total_size = (scp_send_size * 4);
2161
2162 if (send_buf_size < total_size)
2163 return -EINVAL;
2164
2165 if (get_flag || device_flag) {
2166 if (!return_buf || return_buf_size < 4 || !bytes_returned)
2167 return -EINVAL;
2168
2169 spec->wait_scp_header = *((unsigned int *)send_buf);
2170
2171 /* swap source id with target id */
2172 resp_target_id = src_id;
2173 resp_src_id = target_id;
2174 spec->wait_scp_header &= 0xffff0000;
2175 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
2176 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
2177 spec->wait_scp = 1;
2178 waiting_for_resp = true;
2179 }
2180
2181 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
2182 scp_send_size);
2183 if (status < 0) {
2184 spec->wait_scp = 0;
2185 return status;
2186 }
2187
2188 if (waiting_for_resp) {
2189 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
2190 memset(return_buf, 0, return_buf_size);
2191 do {
2192 msleep(20);
2193 } while (spec->wait_scp && time_before(jiffies, timeout));
2194 waiting_for_resp = false;
2195 if (!spec->wait_scp) {
2196 ret_msg = (struct scp_msg *)return_buf;
2197 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
2198 memcpy(&ret_msg->data, spec->scp_resp_data,
2199 spec->wait_num_data);
2200 *bytes_returned = (spec->scp_resp_count + 1) * 4;
2201 status = 0;
2202 } else {
2203 status = -EIO;
2204 }
2205 spec->wait_scp = 0;
2206 }
2207
2208 return status;
2209 }
2210
2211 /**
2212 * Prepare and send the SCP message to DSP
2213 * @codec: the HDA codec
2214 * @mod_id: ID of the DSP module to send the command
2215 * @src_id: ID of the source
2216 * @req: ID of request to send to the DSP module
2217 * @dir: SET or GET
2218 * @data: pointer to the data to send with the request, request specific
2219 * @len: length of the data, in bytes
2220 * @reply: point to the buffer to hold data returned for a reply
2221 * @reply_len: length of the reply buffer returned from GET
2222 *
2223 * Returns zero or a negative error code.
2224 */
dspio_scp(struct hda_codec * codec,int mod_id,int src_id,int req,int dir,const void * data,unsigned int len,void * reply,unsigned int * reply_len)2225 static int dspio_scp(struct hda_codec *codec,
2226 int mod_id, int src_id, int req, int dir, const void *data,
2227 unsigned int len, void *reply, unsigned int *reply_len)
2228 {
2229 int status = 0;
2230 struct scp_msg scp_send, scp_reply;
2231 unsigned int ret_bytes, send_size, ret_size;
2232 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
2233 unsigned int reply_data_size;
2234
2235 memset(&scp_send, 0, sizeof(scp_send));
2236 memset(&scp_reply, 0, sizeof(scp_reply));
2237
2238 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
2239 return -EINVAL;
2240
2241 if (dir == SCP_GET && reply == NULL) {
2242 codec_dbg(codec, "dspio_scp get but has no buffer\n");
2243 return -EINVAL;
2244 }
2245
2246 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
2247 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
2248 return -EINVAL;
2249 }
2250
2251 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
2252 0, 0, 0, len/sizeof(unsigned int));
2253 if (data != NULL && len > 0) {
2254 len = min((unsigned int)(sizeof(scp_send.data)), len);
2255 memcpy(scp_send.data, data, len);
2256 }
2257
2258 ret_bytes = 0;
2259 send_size = sizeof(unsigned int) + len;
2260 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
2261 send_size, (unsigned char *)&scp_reply,
2262 sizeof(scp_reply), &ret_bytes);
2263
2264 if (status < 0) {
2265 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
2266 return status;
2267 }
2268
2269 /* extract send and reply headers members */
2270 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
2271 NULL, NULL, NULL, NULL, NULL);
2272 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
2273 &reply_resp_flag, &reply_error_flag,
2274 &reply_data_size);
2275
2276 if (!send_get_flag)
2277 return 0;
2278
2279 if (reply_resp_flag && !reply_error_flag) {
2280 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
2281 / sizeof(unsigned int);
2282
2283 if (*reply_len < ret_size*sizeof(unsigned int)) {
2284 codec_dbg(codec, "reply too long for buf\n");
2285 return -EINVAL;
2286 } else if (ret_size != reply_data_size) {
2287 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
2288 return -EINVAL;
2289 } else if (!reply) {
2290 codec_dbg(codec, "NULL reply\n");
2291 return -EINVAL;
2292 } else {
2293 *reply_len = ret_size*sizeof(unsigned int);
2294 memcpy(reply, scp_reply.data, *reply_len);
2295 }
2296 } else {
2297 codec_dbg(codec, "reply ill-formed or errflag set\n");
2298 return -EIO;
2299 }
2300
2301 return status;
2302 }
2303
2304 /*
2305 * Set DSP parameters
2306 */
dspio_set_param(struct hda_codec * codec,int mod_id,int src_id,int req,const void * data,unsigned int len)2307 static int dspio_set_param(struct hda_codec *codec, int mod_id,
2308 int src_id, int req, const void *data, unsigned int len)
2309 {
2310 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
2311 NULL);
2312 }
2313
dspio_set_uint_param(struct hda_codec * codec,int mod_id,int req,const unsigned int data)2314 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
2315 int req, const unsigned int data)
2316 {
2317 return dspio_set_param(codec, mod_id, 0x20, req, &data,
2318 sizeof(unsigned int));
2319 }
2320
dspio_set_uint_param_no_source(struct hda_codec * codec,int mod_id,int req,const unsigned int data)2321 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
2322 int req, const unsigned int data)
2323 {
2324 return dspio_set_param(codec, mod_id, 0x00, req, &data,
2325 sizeof(unsigned int));
2326 }
2327
2328 /*
2329 * Allocate a DSP DMA channel via an SCP message
2330 */
dspio_alloc_dma_chan(struct hda_codec * codec,unsigned int * dma_chan)2331 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
2332 {
2333 int status = 0;
2334 unsigned int size = sizeof(dma_chan);
2335
2336 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
2337 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2338 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
2339 dma_chan, &size);
2340
2341 if (status < 0) {
2342 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
2343 return status;
2344 }
2345
2346 if ((*dma_chan + 1) == 0) {
2347 codec_dbg(codec, "no free dma channels to allocate\n");
2348 return -EBUSY;
2349 }
2350
2351 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
2352 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
2353
2354 return status;
2355 }
2356
2357 /*
2358 * Free a DSP DMA via an SCP message
2359 */
dspio_free_dma_chan(struct hda_codec * codec,unsigned int dma_chan)2360 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
2361 {
2362 int status = 0;
2363 unsigned int dummy = 0;
2364
2365 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
2366 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
2367
2368 status = dspio_scp(codec, MASTERCONTROL, 0x20,
2369 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
2370 sizeof(dma_chan), NULL, &dummy);
2371
2372 if (status < 0) {
2373 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
2374 return status;
2375 }
2376
2377 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
2378
2379 return status;
2380 }
2381
2382 /*
2383 * (Re)start the DSP
2384 */
dsp_set_run_state(struct hda_codec * codec)2385 static int dsp_set_run_state(struct hda_codec *codec)
2386 {
2387 unsigned int dbg_ctrl_reg;
2388 unsigned int halt_state;
2389 int err;
2390
2391 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
2392 if (err < 0)
2393 return err;
2394
2395 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
2396 DSP_DBGCNTL_STATE_LOBIT;
2397
2398 if (halt_state != 0) {
2399 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
2400 DSP_DBGCNTL_SS_MASK);
2401 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2402 dbg_ctrl_reg);
2403 if (err < 0)
2404 return err;
2405
2406 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
2407 DSP_DBGCNTL_EXEC_MASK;
2408 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
2409 dbg_ctrl_reg);
2410 if (err < 0)
2411 return err;
2412 }
2413
2414 return 0;
2415 }
2416
2417 /*
2418 * Reset the DSP
2419 */
dsp_reset(struct hda_codec * codec)2420 static int dsp_reset(struct hda_codec *codec)
2421 {
2422 unsigned int res;
2423 int retry = 20;
2424
2425 codec_dbg(codec, "dsp_reset\n");
2426 do {
2427 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2428 retry--;
2429 } while (res == -EIO && retry);
2430
2431 if (!retry) {
2432 codec_dbg(codec, "dsp_reset timeout\n");
2433 return -EIO;
2434 }
2435
2436 return 0;
2437 }
2438
2439 /*
2440 * Convert chip address to DSP address
2441 */
dsp_chip_to_dsp_addx(unsigned int chip_addx,bool * code,bool * yram)2442 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2443 bool *code, bool *yram)
2444 {
2445 *code = *yram = false;
2446
2447 if (UC_RANGE(chip_addx, 1)) {
2448 *code = true;
2449 return UC_OFF(chip_addx);
2450 } else if (X_RANGE_ALL(chip_addx, 1)) {
2451 return X_OFF(chip_addx);
2452 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2453 *yram = true;
2454 return Y_OFF(chip_addx);
2455 }
2456
2457 return INVALID_CHIP_ADDRESS;
2458 }
2459
2460 /*
2461 * Check if the DSP DMA is active
2462 */
dsp_is_dma_active(struct hda_codec * codec,unsigned int dma_chan)2463 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2464 {
2465 unsigned int dma_chnlstart_reg;
2466
2467 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2468
2469 return ((dma_chnlstart_reg & (1 <<
2470 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2471 }
2472
dsp_dma_setup_common(struct hda_codec * codec,unsigned int chip_addx,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)2473 static int dsp_dma_setup_common(struct hda_codec *codec,
2474 unsigned int chip_addx,
2475 unsigned int dma_chan,
2476 unsigned int port_map_mask,
2477 bool ovly)
2478 {
2479 int status = 0;
2480 unsigned int chnl_prop;
2481 unsigned int dsp_addx;
2482 unsigned int active;
2483 bool code, yram;
2484
2485 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2486
2487 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2488 codec_dbg(codec, "dma chan num invalid\n");
2489 return -EINVAL;
2490 }
2491
2492 if (dsp_is_dma_active(codec, dma_chan)) {
2493 codec_dbg(codec, "dma already active\n");
2494 return -EBUSY;
2495 }
2496
2497 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2498
2499 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2500 codec_dbg(codec, "invalid chip addr\n");
2501 return -ENXIO;
2502 }
2503
2504 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2505 active = 0;
2506
2507 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2508
2509 if (ovly) {
2510 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2511 &chnl_prop);
2512
2513 if (status < 0) {
2514 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2515 return status;
2516 }
2517 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2518 }
2519
2520 if (!code)
2521 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2522 else
2523 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2524
2525 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2526
2527 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2528 if (status < 0) {
2529 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2530 return status;
2531 }
2532 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2533
2534 if (ovly) {
2535 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2536 &active);
2537
2538 if (status < 0) {
2539 codec_dbg(codec, "read ACTIVE Reg fail\n");
2540 return status;
2541 }
2542 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2543 }
2544
2545 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2546 DSPDMAC_ACTIVE_AAR_MASK;
2547
2548 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2549 if (status < 0) {
2550 codec_dbg(codec, "write ACTIVE Reg fail\n");
2551 return status;
2552 }
2553
2554 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2555
2556 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2557 port_map_mask);
2558 if (status < 0) {
2559 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2560 return status;
2561 }
2562 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2563
2564 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2565 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2566 if (status < 0) {
2567 codec_dbg(codec, "write IRQCNT Reg fail\n");
2568 return status;
2569 }
2570 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2571
2572 codec_dbg(codec,
2573 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2574 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2575 chip_addx, dsp_addx, dma_chan,
2576 port_map_mask, chnl_prop, active);
2577
2578 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2579
2580 return 0;
2581 }
2582
2583 /*
2584 * Setup the DSP DMA per-transfer-specific registers
2585 */
dsp_dma_setup(struct hda_codec * codec,unsigned int chip_addx,unsigned int count,unsigned int dma_chan)2586 static int dsp_dma_setup(struct hda_codec *codec,
2587 unsigned int chip_addx,
2588 unsigned int count,
2589 unsigned int dma_chan)
2590 {
2591 int status = 0;
2592 bool code, yram;
2593 unsigned int dsp_addx;
2594 unsigned int addr_field;
2595 unsigned int incr_field;
2596 unsigned int base_cnt;
2597 unsigned int cur_cnt;
2598 unsigned int dma_cfg = 0;
2599 unsigned int adr_ofs = 0;
2600 unsigned int xfr_cnt = 0;
2601 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2602 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2603
2604 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2605
2606 if (count > max_dma_count) {
2607 codec_dbg(codec, "count too big\n");
2608 return -EINVAL;
2609 }
2610
2611 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2612 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2613 codec_dbg(codec, "invalid chip addr\n");
2614 return -ENXIO;
2615 }
2616
2617 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2618
2619 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2620 incr_field = 0;
2621
2622 if (!code) {
2623 addr_field <<= 1;
2624 if (yram)
2625 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2626
2627 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2628 }
2629
2630 dma_cfg = addr_field + incr_field;
2631 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2632 dma_cfg);
2633 if (status < 0) {
2634 codec_dbg(codec, "write DMACFG Reg fail\n");
2635 return status;
2636 }
2637 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2638
2639 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2640 (code ? 0 : 1));
2641
2642 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2643 adr_ofs);
2644 if (status < 0) {
2645 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2646 return status;
2647 }
2648 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2649
2650 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2651
2652 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2653
2654 xfr_cnt = base_cnt | cur_cnt;
2655
2656 status = chipio_write(codec,
2657 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2658 if (status < 0) {
2659 codec_dbg(codec, "write XFRCNT Reg fail\n");
2660 return status;
2661 }
2662 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2663
2664 codec_dbg(codec,
2665 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2666 "ADROFS=0x%x, XFRCNT=0x%x\n",
2667 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2668
2669 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2670
2671 return 0;
2672 }
2673
2674 /*
2675 * Start the DSP DMA
2676 */
dsp_dma_start(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2677 static int dsp_dma_start(struct hda_codec *codec,
2678 unsigned int dma_chan, bool ovly)
2679 {
2680 unsigned int reg = 0;
2681 int status = 0;
2682
2683 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2684
2685 if (ovly) {
2686 status = chipio_read(codec,
2687 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2688
2689 if (status < 0) {
2690 codec_dbg(codec, "read CHNLSTART reg fail\n");
2691 return status;
2692 }
2693 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2694
2695 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2696 DSPDMAC_CHNLSTART_DIS_MASK);
2697 }
2698
2699 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2700 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2701 if (status < 0) {
2702 codec_dbg(codec, "write CHNLSTART reg fail\n");
2703 return status;
2704 }
2705 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2706
2707 return status;
2708 }
2709
2710 /*
2711 * Stop the DSP DMA
2712 */
dsp_dma_stop(struct hda_codec * codec,unsigned int dma_chan,bool ovly)2713 static int dsp_dma_stop(struct hda_codec *codec,
2714 unsigned int dma_chan, bool ovly)
2715 {
2716 unsigned int reg = 0;
2717 int status = 0;
2718
2719 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2720
2721 if (ovly) {
2722 status = chipio_read(codec,
2723 DSPDMAC_CHNLSTART_INST_OFFSET, ®);
2724
2725 if (status < 0) {
2726 codec_dbg(codec, "read CHNLSTART reg fail\n");
2727 return status;
2728 }
2729 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2730 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2731 DSPDMAC_CHNLSTART_DIS_MASK);
2732 }
2733
2734 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2735 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2736 if (status < 0) {
2737 codec_dbg(codec, "write CHNLSTART reg fail\n");
2738 return status;
2739 }
2740 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2741
2742 return status;
2743 }
2744
2745 /**
2746 * Allocate router ports
2747 *
2748 * @codec: the HDA codec
2749 * @num_chans: number of channels in the stream
2750 * @ports_per_channel: number of ports per channel
2751 * @start_device: start device
2752 * @port_map: pointer to the port list to hold the allocated ports
2753 *
2754 * Returns zero or a negative error code.
2755 */
dsp_allocate_router_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int ports_per_channel,unsigned int start_device,unsigned int * port_map)2756 static int dsp_allocate_router_ports(struct hda_codec *codec,
2757 unsigned int num_chans,
2758 unsigned int ports_per_channel,
2759 unsigned int start_device,
2760 unsigned int *port_map)
2761 {
2762 int status = 0;
2763 int res;
2764 u8 val;
2765
2766 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2767 if (status < 0)
2768 return status;
2769
2770 val = start_device << 6;
2771 val |= (ports_per_channel - 1) << 4;
2772 val |= num_chans - 1;
2773
2774 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2775 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2776 val);
2777
2778 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2779 VENDOR_CHIPIO_PORT_ALLOC_SET,
2780 MEM_CONNID_DSP);
2781
2782 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2783 if (status < 0)
2784 return status;
2785
2786 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2787 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2788
2789 *port_map = res;
2790
2791 return (res < 0) ? res : 0;
2792 }
2793
2794 /*
2795 * Free router ports
2796 */
dsp_free_router_ports(struct hda_codec * codec)2797 static int dsp_free_router_ports(struct hda_codec *codec)
2798 {
2799 int status = 0;
2800
2801 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2802 if (status < 0)
2803 return status;
2804
2805 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2806 VENDOR_CHIPIO_PORT_FREE_SET,
2807 MEM_CONNID_DSP);
2808
2809 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2810
2811 return status;
2812 }
2813
2814 /*
2815 * Allocate DSP ports for the download stream
2816 */
dsp_allocate_ports(struct hda_codec * codec,unsigned int num_chans,unsigned int rate_multi,unsigned int * port_map)2817 static int dsp_allocate_ports(struct hda_codec *codec,
2818 unsigned int num_chans,
2819 unsigned int rate_multi, unsigned int *port_map)
2820 {
2821 int status;
2822
2823 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2824
2825 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2826 codec_dbg(codec, "bad rate multiple\n");
2827 return -EINVAL;
2828 }
2829
2830 status = dsp_allocate_router_ports(codec, num_chans,
2831 rate_multi, 0, port_map);
2832
2833 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2834
2835 return status;
2836 }
2837
dsp_allocate_ports_format(struct hda_codec * codec,const unsigned short fmt,unsigned int * port_map)2838 static int dsp_allocate_ports_format(struct hda_codec *codec,
2839 const unsigned short fmt,
2840 unsigned int *port_map)
2841 {
2842 int status;
2843 unsigned int num_chans;
2844
2845 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2846 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2847 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2848
2849 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2850 codec_dbg(codec, "bad rate multiple\n");
2851 return -EINVAL;
2852 }
2853
2854 num_chans = get_hdafmt_chs(fmt) + 1;
2855
2856 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2857
2858 return status;
2859 }
2860
2861 /*
2862 * free DSP ports
2863 */
dsp_free_ports(struct hda_codec * codec)2864 static int dsp_free_ports(struct hda_codec *codec)
2865 {
2866 int status;
2867
2868 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2869
2870 status = dsp_free_router_ports(codec);
2871 if (status < 0) {
2872 codec_dbg(codec, "free router ports fail\n");
2873 return status;
2874 }
2875 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2876
2877 return status;
2878 }
2879
2880 /*
2881 * HDA DMA engine stuffs for DSP code download
2882 */
2883 struct dma_engine {
2884 struct hda_codec *codec;
2885 unsigned short m_converter_format;
2886 struct snd_dma_buffer *dmab;
2887 unsigned int buf_size;
2888 };
2889
2890
2891 enum dma_state {
2892 DMA_STATE_STOP = 0,
2893 DMA_STATE_RUN = 1
2894 };
2895
dma_convert_to_hda_format(struct hda_codec * codec,unsigned int sample_rate,unsigned short channels,unsigned short * hda_format)2896 static int dma_convert_to_hda_format(struct hda_codec *codec,
2897 unsigned int sample_rate,
2898 unsigned short channels,
2899 unsigned short *hda_format)
2900 {
2901 unsigned int format_val;
2902
2903 format_val = snd_hdac_calc_stream_format(sample_rate,
2904 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2905
2906 if (hda_format)
2907 *hda_format = (unsigned short)format_val;
2908
2909 return 0;
2910 }
2911
2912 /*
2913 * Reset DMA for DSP download
2914 */
dma_reset(struct dma_engine * dma)2915 static int dma_reset(struct dma_engine *dma)
2916 {
2917 struct hda_codec *codec = dma->codec;
2918 struct ca0132_spec *spec = codec->spec;
2919 int status;
2920
2921 if (dma->dmab->area)
2922 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2923
2924 status = snd_hda_codec_load_dsp_prepare(codec,
2925 dma->m_converter_format,
2926 dma->buf_size,
2927 dma->dmab);
2928 if (status < 0)
2929 return status;
2930 spec->dsp_stream_id = status;
2931 return 0;
2932 }
2933
dma_set_state(struct dma_engine * dma,enum dma_state state)2934 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2935 {
2936 bool cmd;
2937
2938 switch (state) {
2939 case DMA_STATE_STOP:
2940 cmd = false;
2941 break;
2942 case DMA_STATE_RUN:
2943 cmd = true;
2944 break;
2945 default:
2946 return 0;
2947 }
2948
2949 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2950 return 0;
2951 }
2952
dma_get_buffer_size(struct dma_engine * dma)2953 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2954 {
2955 return dma->dmab->bytes;
2956 }
2957
dma_get_buffer_addr(struct dma_engine * dma)2958 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2959 {
2960 return dma->dmab->area;
2961 }
2962
dma_xfer(struct dma_engine * dma,const unsigned int * data,unsigned int count)2963 static int dma_xfer(struct dma_engine *dma,
2964 const unsigned int *data,
2965 unsigned int count)
2966 {
2967 memcpy(dma->dmab->area, data, count);
2968 return 0;
2969 }
2970
dma_get_converter_format(struct dma_engine * dma,unsigned short * format)2971 static void dma_get_converter_format(
2972 struct dma_engine *dma,
2973 unsigned short *format)
2974 {
2975 if (format)
2976 *format = dma->m_converter_format;
2977 }
2978
dma_get_stream_id(struct dma_engine * dma)2979 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2980 {
2981 struct ca0132_spec *spec = dma->codec->spec;
2982
2983 return spec->dsp_stream_id;
2984 }
2985
2986 struct dsp_image_seg {
2987 u32 magic;
2988 u32 chip_addr;
2989 u32 count;
2990 u32 data[];
2991 };
2992
2993 static const u32 g_magic_value = 0x4c46584d;
2994 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2995
is_valid(const struct dsp_image_seg * p)2996 static bool is_valid(const struct dsp_image_seg *p)
2997 {
2998 return p->magic == g_magic_value;
2999 }
3000
is_hci_prog_list_seg(const struct dsp_image_seg * p)3001 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
3002 {
3003 return g_chip_addr_magic_value == p->chip_addr;
3004 }
3005
is_last(const struct dsp_image_seg * p)3006 static bool is_last(const struct dsp_image_seg *p)
3007 {
3008 return p->count == 0;
3009 }
3010
dsp_sizeof(const struct dsp_image_seg * p)3011 static size_t dsp_sizeof(const struct dsp_image_seg *p)
3012 {
3013 return struct_size(p, data, p->count);
3014 }
3015
get_next_seg_ptr(const struct dsp_image_seg * p)3016 static const struct dsp_image_seg *get_next_seg_ptr(
3017 const struct dsp_image_seg *p)
3018 {
3019 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
3020 }
3021
3022 /*
3023 * CA0132 chip DSP transfer stuffs. For DSP download.
3024 */
3025 #define INVALID_DMA_CHANNEL (~0U)
3026
3027 /*
3028 * Program a list of address/data pairs via the ChipIO widget.
3029 * The segment data is in the format of successive pairs of words.
3030 * These are repeated as indicated by the segment's count field.
3031 */
dspxfr_hci_write(struct hda_codec * codec,const struct dsp_image_seg * fls)3032 static int dspxfr_hci_write(struct hda_codec *codec,
3033 const struct dsp_image_seg *fls)
3034 {
3035 int status;
3036 const u32 *data;
3037 unsigned int count;
3038
3039 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
3040 codec_dbg(codec, "hci_write invalid params\n");
3041 return -EINVAL;
3042 }
3043
3044 count = fls->count;
3045 data = (u32 *)(fls->data);
3046 while (count >= 2) {
3047 status = chipio_write(codec, data[0], data[1]);
3048 if (status < 0) {
3049 codec_dbg(codec, "hci_write chipio failed\n");
3050 return status;
3051 }
3052 count -= 2;
3053 data += 2;
3054 }
3055 return 0;
3056 }
3057
3058 /**
3059 * Write a block of data into DSP code or data RAM using pre-allocated
3060 * DMA engine.
3061 *
3062 * @codec: the HDA codec
3063 * @fls: pointer to a fast load image
3064 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3065 * no relocation
3066 * @dma_engine: pointer to DMA engine to be used for DSP download
3067 * @dma_chan: The number of DMA channels used for DSP download
3068 * @port_map_mask: port mapping
3069 * @ovly: TRUE if overlay format is required
3070 *
3071 * Returns zero or a negative error code.
3072 */
dspxfr_one_seg(struct hda_codec * codec,const struct dsp_image_seg * fls,unsigned int reloc,struct dma_engine * dma_engine,unsigned int dma_chan,unsigned int port_map_mask,bool ovly)3073 static int dspxfr_one_seg(struct hda_codec *codec,
3074 const struct dsp_image_seg *fls,
3075 unsigned int reloc,
3076 struct dma_engine *dma_engine,
3077 unsigned int dma_chan,
3078 unsigned int port_map_mask,
3079 bool ovly)
3080 {
3081 int status = 0;
3082 bool comm_dma_setup_done = false;
3083 const unsigned int *data;
3084 unsigned int chip_addx;
3085 unsigned int words_to_write;
3086 unsigned int buffer_size_words;
3087 unsigned char *buffer_addx;
3088 unsigned short hda_format;
3089 unsigned int sample_rate_div;
3090 unsigned int sample_rate_mul;
3091 unsigned int num_chans;
3092 unsigned int hda_frame_size_words;
3093 unsigned int remainder_words;
3094 const u32 *data_remainder;
3095 u32 chip_addx_remainder;
3096 unsigned int run_size_words;
3097 const struct dsp_image_seg *hci_write = NULL;
3098 unsigned long timeout;
3099 bool dma_active;
3100
3101 if (fls == NULL)
3102 return -EINVAL;
3103 if (is_hci_prog_list_seg(fls)) {
3104 hci_write = fls;
3105 fls = get_next_seg_ptr(fls);
3106 }
3107
3108 if (hci_write && (!fls || is_last(fls))) {
3109 codec_dbg(codec, "hci_write\n");
3110 return dspxfr_hci_write(codec, hci_write);
3111 }
3112
3113 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
3114 codec_dbg(codec, "Invalid Params\n");
3115 return -EINVAL;
3116 }
3117
3118 data = fls->data;
3119 chip_addx = fls->chip_addr;
3120 words_to_write = fls->count;
3121
3122 if (!words_to_write)
3123 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
3124 if (reloc)
3125 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
3126
3127 if (!UC_RANGE(chip_addx, words_to_write) &&
3128 !X_RANGE_ALL(chip_addx, words_to_write) &&
3129 !Y_RANGE_ALL(chip_addx, words_to_write)) {
3130 codec_dbg(codec, "Invalid chip_addx Params\n");
3131 return -EINVAL;
3132 }
3133
3134 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
3135 sizeof(u32);
3136
3137 buffer_addx = dma_get_buffer_addr(dma_engine);
3138
3139 if (buffer_addx == NULL) {
3140 codec_dbg(codec, "dma_engine buffer NULL\n");
3141 return -EINVAL;
3142 }
3143
3144 dma_get_converter_format(dma_engine, &hda_format);
3145 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
3146 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
3147 num_chans = get_hdafmt_chs(hda_format) + 1;
3148
3149 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
3150 (num_chans * sample_rate_mul / sample_rate_div));
3151
3152 if (hda_frame_size_words == 0) {
3153 codec_dbg(codec, "frmsz zero\n");
3154 return -EINVAL;
3155 }
3156
3157 buffer_size_words = min(buffer_size_words,
3158 (unsigned int)(UC_RANGE(chip_addx, 1) ?
3159 65536 : 32768));
3160 buffer_size_words -= buffer_size_words % hda_frame_size_words;
3161 codec_dbg(codec,
3162 "chpadr=0x%08x frmsz=%u nchan=%u "
3163 "rate_mul=%u div=%u bufsz=%u\n",
3164 chip_addx, hda_frame_size_words, num_chans,
3165 sample_rate_mul, sample_rate_div, buffer_size_words);
3166
3167 if (buffer_size_words < hda_frame_size_words) {
3168 codec_dbg(codec, "dspxfr_one_seg:failed\n");
3169 return -EINVAL;
3170 }
3171
3172 remainder_words = words_to_write % hda_frame_size_words;
3173 data_remainder = data;
3174 chip_addx_remainder = chip_addx;
3175
3176 data += remainder_words;
3177 chip_addx += remainder_words*sizeof(u32);
3178 words_to_write -= remainder_words;
3179
3180 while (words_to_write != 0) {
3181 run_size_words = min(buffer_size_words, words_to_write);
3182 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
3183 words_to_write, run_size_words, remainder_words);
3184 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
3185 if (!comm_dma_setup_done) {
3186 status = dsp_dma_stop(codec, dma_chan, ovly);
3187 if (status < 0)
3188 return status;
3189 status = dsp_dma_setup_common(codec, chip_addx,
3190 dma_chan, port_map_mask, ovly);
3191 if (status < 0)
3192 return status;
3193 comm_dma_setup_done = true;
3194 }
3195
3196 status = dsp_dma_setup(codec, chip_addx,
3197 run_size_words, dma_chan);
3198 if (status < 0)
3199 return status;
3200 status = dsp_dma_start(codec, dma_chan, ovly);
3201 if (status < 0)
3202 return status;
3203 if (!dsp_is_dma_active(codec, dma_chan)) {
3204 codec_dbg(codec, "dspxfr:DMA did not start\n");
3205 return -EIO;
3206 }
3207 status = dma_set_state(dma_engine, DMA_STATE_RUN);
3208 if (status < 0)
3209 return status;
3210 if (remainder_words != 0) {
3211 status = chipio_write_multiple(codec,
3212 chip_addx_remainder,
3213 data_remainder,
3214 remainder_words);
3215 if (status < 0)
3216 return status;
3217 remainder_words = 0;
3218 }
3219 if (hci_write) {
3220 status = dspxfr_hci_write(codec, hci_write);
3221 if (status < 0)
3222 return status;
3223 hci_write = NULL;
3224 }
3225
3226 timeout = jiffies + msecs_to_jiffies(2000);
3227 do {
3228 dma_active = dsp_is_dma_active(codec, dma_chan);
3229 if (!dma_active)
3230 break;
3231 msleep(20);
3232 } while (time_before(jiffies, timeout));
3233 if (dma_active)
3234 break;
3235
3236 codec_dbg(codec, "+++++ DMA complete\n");
3237 dma_set_state(dma_engine, DMA_STATE_STOP);
3238 status = dma_reset(dma_engine);
3239
3240 if (status < 0)
3241 return status;
3242
3243 data += run_size_words;
3244 chip_addx += run_size_words*sizeof(u32);
3245 words_to_write -= run_size_words;
3246 }
3247
3248 if (remainder_words != 0) {
3249 status = chipio_write_multiple(codec, chip_addx_remainder,
3250 data_remainder, remainder_words);
3251 }
3252
3253 return status;
3254 }
3255
3256 /**
3257 * Write the entire DSP image of a DSP code/data overlay to DSP memories
3258 *
3259 * @codec: the HDA codec
3260 * @fls_data: pointer to a fast load image
3261 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3262 * no relocation
3263 * @sample_rate: sampling rate of the stream used for DSP download
3264 * @channels: channels of the stream used for DSP download
3265 * @ovly: TRUE if overlay format is required
3266 *
3267 * Returns zero or a negative error code.
3268 */
dspxfr_image(struct hda_codec * codec,const struct dsp_image_seg * fls_data,unsigned int reloc,unsigned int sample_rate,unsigned short channels,bool ovly)3269 static int dspxfr_image(struct hda_codec *codec,
3270 const struct dsp_image_seg *fls_data,
3271 unsigned int reloc,
3272 unsigned int sample_rate,
3273 unsigned short channels,
3274 bool ovly)
3275 {
3276 struct ca0132_spec *spec = codec->spec;
3277 int status;
3278 unsigned short hda_format = 0;
3279 unsigned int response;
3280 unsigned char stream_id = 0;
3281 struct dma_engine *dma_engine;
3282 unsigned int dma_chan;
3283 unsigned int port_map_mask;
3284
3285 if (fls_data == NULL)
3286 return -EINVAL;
3287
3288 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
3289 if (!dma_engine)
3290 return -ENOMEM;
3291
3292 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
3293 if (!dma_engine->dmab) {
3294 kfree(dma_engine);
3295 return -ENOMEM;
3296 }
3297
3298 dma_engine->codec = codec;
3299 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
3300 dma_engine->m_converter_format = hda_format;
3301 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
3302 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
3303
3304 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
3305
3306 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
3307 hda_format, &response);
3308
3309 if (status < 0) {
3310 codec_dbg(codec, "set converter format fail\n");
3311 goto exit;
3312 }
3313
3314 status = snd_hda_codec_load_dsp_prepare(codec,
3315 dma_engine->m_converter_format,
3316 dma_engine->buf_size,
3317 dma_engine->dmab);
3318 if (status < 0)
3319 goto exit;
3320 spec->dsp_stream_id = status;
3321
3322 if (ovly) {
3323 status = dspio_alloc_dma_chan(codec, &dma_chan);
3324 if (status < 0) {
3325 codec_dbg(codec, "alloc dmachan fail\n");
3326 dma_chan = INVALID_DMA_CHANNEL;
3327 goto exit;
3328 }
3329 }
3330
3331 port_map_mask = 0;
3332 status = dsp_allocate_ports_format(codec, hda_format,
3333 &port_map_mask);
3334 if (status < 0) {
3335 codec_dbg(codec, "alloc ports fail\n");
3336 goto exit;
3337 }
3338
3339 stream_id = dma_get_stream_id(dma_engine);
3340 status = codec_set_converter_stream_channel(codec,
3341 WIDGET_CHIP_CTRL, stream_id, 0, &response);
3342 if (status < 0) {
3343 codec_dbg(codec, "set stream chan fail\n");
3344 goto exit;
3345 }
3346
3347 while ((fls_data != NULL) && !is_last(fls_data)) {
3348 if (!is_valid(fls_data)) {
3349 codec_dbg(codec, "FLS check fail\n");
3350 status = -EINVAL;
3351 goto exit;
3352 }
3353 status = dspxfr_one_seg(codec, fls_data, reloc,
3354 dma_engine, dma_chan,
3355 port_map_mask, ovly);
3356 if (status < 0)
3357 break;
3358
3359 if (is_hci_prog_list_seg(fls_data))
3360 fls_data = get_next_seg_ptr(fls_data);
3361
3362 if ((fls_data != NULL) && !is_last(fls_data))
3363 fls_data = get_next_seg_ptr(fls_data);
3364 }
3365
3366 if (port_map_mask != 0)
3367 status = dsp_free_ports(codec);
3368
3369 if (status < 0)
3370 goto exit;
3371
3372 status = codec_set_converter_stream_channel(codec,
3373 WIDGET_CHIP_CTRL, 0, 0, &response);
3374
3375 exit:
3376 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
3377 dspio_free_dma_chan(codec, dma_chan);
3378
3379 if (dma_engine->dmab->area)
3380 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
3381 kfree(dma_engine->dmab);
3382 kfree(dma_engine);
3383
3384 return status;
3385 }
3386
3387 /*
3388 * CA0132 DSP download stuffs.
3389 */
dspload_post_setup(struct hda_codec * codec)3390 static void dspload_post_setup(struct hda_codec *codec)
3391 {
3392 struct ca0132_spec *spec = codec->spec;
3393 codec_dbg(codec, "---- dspload_post_setup ------\n");
3394 if (!ca0132_use_alt_functions(spec)) {
3395 /*set DSP speaker to 2.0 configuration*/
3396 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
3397 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
3398
3399 /*update write pointer*/
3400 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
3401 }
3402 }
3403
3404 /**
3405 * dspload_image - Download DSP from a DSP Image Fast Load structure.
3406 *
3407 * @codec: the HDA codec
3408 * @fls: pointer to a fast load image
3409 * @ovly: TRUE if overlay format is required
3410 * @reloc: Relocation address for loading single-segment overlays, or 0 for
3411 * no relocation
3412 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
3413 * @router_chans: number of audio router channels to be allocated (0 means use
3414 * internal defaults; max is 32)
3415 *
3416 * Download DSP from a DSP Image Fast Load structure. This structure is a
3417 * linear, non-constant sized element array of structures, each of which
3418 * contain the count of the data to be loaded, the data itself, and the
3419 * corresponding starting chip address of the starting data location.
3420 * Returns zero or a negative error code.
3421 */
dspload_image(struct hda_codec * codec,const struct dsp_image_seg * fls,bool ovly,unsigned int reloc,bool autostart,int router_chans)3422 static int dspload_image(struct hda_codec *codec,
3423 const struct dsp_image_seg *fls,
3424 bool ovly,
3425 unsigned int reloc,
3426 bool autostart,
3427 int router_chans)
3428 {
3429 int status = 0;
3430 unsigned int sample_rate;
3431 unsigned short channels;
3432
3433 codec_dbg(codec, "---- dspload_image begin ------\n");
3434 if (router_chans == 0) {
3435 if (!ovly)
3436 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3437 else
3438 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3439 }
3440
3441 sample_rate = 48000;
3442 channels = (unsigned short)router_chans;
3443
3444 while (channels > 16) {
3445 sample_rate *= 2;
3446 channels /= 2;
3447 }
3448
3449 do {
3450 codec_dbg(codec, "Ready to program DMA\n");
3451 if (!ovly)
3452 status = dsp_reset(codec);
3453
3454 if (status < 0)
3455 break;
3456
3457 codec_dbg(codec, "dsp_reset() complete\n");
3458 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3459 ovly);
3460
3461 if (status < 0)
3462 break;
3463
3464 codec_dbg(codec, "dspxfr_image() complete\n");
3465 if (autostart && !ovly) {
3466 dspload_post_setup(codec);
3467 status = dsp_set_run_state(codec);
3468 }
3469
3470 codec_dbg(codec, "LOAD FINISHED\n");
3471 } while (0);
3472
3473 return status;
3474 }
3475
3476 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
dspload_is_loaded(struct hda_codec * codec)3477 static bool dspload_is_loaded(struct hda_codec *codec)
3478 {
3479 unsigned int data = 0;
3480 int status = 0;
3481
3482 status = chipio_read(codec, 0x40004, &data);
3483 if ((status < 0) || (data != 1))
3484 return false;
3485
3486 return true;
3487 }
3488 #else
3489 #define dspload_is_loaded(codec) false
3490 #endif
3491
dspload_wait_loaded(struct hda_codec * codec)3492 static bool dspload_wait_loaded(struct hda_codec *codec)
3493 {
3494 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3495
3496 do {
3497 if (dspload_is_loaded(codec)) {
3498 codec_info(codec, "ca0132 DSP downloaded and running\n");
3499 return true;
3500 }
3501 msleep(20);
3502 } while (time_before(jiffies, timeout));
3503
3504 codec_err(codec, "ca0132 failed to download DSP\n");
3505 return false;
3506 }
3507
3508 /*
3509 * ca0113 related functions. The ca0113 acts as the HDA bus for the pci-e
3510 * based cards, and has a second mmio region, region2, that's used for special
3511 * commands.
3512 */
3513
3514 /*
3515 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3516 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3517 * The first eight bits are just the number of the pin. So far, I've only seen
3518 * this number go to 7.
3519 * AE-5 note: The AE-5 seems to use pins 2 and 3 to somehow set the color value
3520 * of the on-card LED. It seems to use pin 2 for data, then toggles 3 to on and
3521 * then off to send that bit.
3522 */
ca0113_mmio_gpio_set(struct hda_codec * codec,unsigned int gpio_pin,bool enable)3523 static void ca0113_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3524 bool enable)
3525 {
3526 struct ca0132_spec *spec = codec->spec;
3527 unsigned short gpio_data;
3528
3529 gpio_data = gpio_pin & 0xF;
3530 gpio_data |= ((enable << 8) & 0x100);
3531
3532 writew(gpio_data, spec->mem_base + 0x320);
3533 }
3534
3535 /*
3536 * Special pci region2 commands that are only used by the AE-5. They follow
3537 * a set format, and require reads at certain points to seemingly 'clear'
3538 * the response data. My first tests didn't do these reads, and would cause
3539 * the card to get locked up until the memory was read. These commands
3540 * seem to work with three distinct values that I've taken to calling group,
3541 * target-id, and value.
3542 */
ca0113_mmio_command_set(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3543 static void ca0113_mmio_command_set(struct hda_codec *codec, unsigned int group,
3544 unsigned int target, unsigned int value)
3545 {
3546 struct ca0132_spec *spec = codec->spec;
3547 unsigned int write_val;
3548
3549 writel(0x0000007e, spec->mem_base + 0x210);
3550 readl(spec->mem_base + 0x210);
3551 writel(0x0000005a, spec->mem_base + 0x210);
3552 readl(spec->mem_base + 0x210);
3553 readl(spec->mem_base + 0x210);
3554
3555 writel(0x00800005, spec->mem_base + 0x20c);
3556 writel(group, spec->mem_base + 0x804);
3557
3558 writel(0x00800005, spec->mem_base + 0x20c);
3559 write_val = (target & 0xff);
3560 write_val |= (value << 8);
3561
3562
3563 writel(write_val, spec->mem_base + 0x204);
3564 /*
3565 * Need delay here or else it goes too fast and works inconsistently.
3566 */
3567 msleep(20);
3568
3569 readl(spec->mem_base + 0x860);
3570 readl(spec->mem_base + 0x854);
3571 readl(spec->mem_base + 0x840);
3572
3573 writel(0x00800004, spec->mem_base + 0x20c);
3574 writel(0x00000000, spec->mem_base + 0x210);
3575 readl(spec->mem_base + 0x210);
3576 readl(spec->mem_base + 0x210);
3577 }
3578
3579 /*
3580 * This second type of command is used for setting the sound filter type.
3581 */
ca0113_mmio_command_set_type2(struct hda_codec * codec,unsigned int group,unsigned int target,unsigned int value)3582 static void ca0113_mmio_command_set_type2(struct hda_codec *codec,
3583 unsigned int group, unsigned int target, unsigned int value)
3584 {
3585 struct ca0132_spec *spec = codec->spec;
3586 unsigned int write_val;
3587
3588 writel(0x0000007e, spec->mem_base + 0x210);
3589 readl(spec->mem_base + 0x210);
3590 writel(0x0000005a, spec->mem_base + 0x210);
3591 readl(spec->mem_base + 0x210);
3592 readl(spec->mem_base + 0x210);
3593
3594 writel(0x00800003, spec->mem_base + 0x20c);
3595 writel(group, spec->mem_base + 0x804);
3596
3597 writel(0x00800005, spec->mem_base + 0x20c);
3598 write_val = (target & 0xff);
3599 write_val |= (value << 8);
3600
3601
3602 writel(write_val, spec->mem_base + 0x204);
3603 msleep(20);
3604 readl(spec->mem_base + 0x860);
3605 readl(spec->mem_base + 0x854);
3606 readl(spec->mem_base + 0x840);
3607
3608 writel(0x00800004, spec->mem_base + 0x20c);
3609 writel(0x00000000, spec->mem_base + 0x210);
3610 readl(spec->mem_base + 0x210);
3611 readl(spec->mem_base + 0x210);
3612 }
3613
3614 /*
3615 * Setup GPIO for the other variants of Core3D.
3616 */
3617
3618 /*
3619 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3620 * the card shows as having no GPIO pins.
3621 */
ca0132_gpio_init(struct hda_codec * codec)3622 static void ca0132_gpio_init(struct hda_codec *codec)
3623 {
3624 struct ca0132_spec *spec = codec->spec;
3625
3626 switch (ca0132_quirk(spec)) {
3627 case QUIRK_SBZ:
3628 case QUIRK_AE5:
3629 case QUIRK_AE7:
3630 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3631 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3632 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3633 break;
3634 case QUIRK_R3DI:
3635 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3636 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3637 break;
3638 default:
3639 break;
3640 }
3641
3642 }
3643
3644 /* Sets the GPIO for audio output. */
ca0132_gpio_setup(struct hda_codec * codec)3645 static void ca0132_gpio_setup(struct hda_codec *codec)
3646 {
3647 struct ca0132_spec *spec = codec->spec;
3648
3649 switch (ca0132_quirk(spec)) {
3650 case QUIRK_SBZ:
3651 snd_hda_codec_write(codec, 0x01, 0,
3652 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3653 snd_hda_codec_write(codec, 0x01, 0,
3654 AC_VERB_SET_GPIO_MASK, 0x07);
3655 snd_hda_codec_write(codec, 0x01, 0,
3656 AC_VERB_SET_GPIO_DATA, 0x04);
3657 snd_hda_codec_write(codec, 0x01, 0,
3658 AC_VERB_SET_GPIO_DATA, 0x06);
3659 break;
3660 case QUIRK_R3DI:
3661 snd_hda_codec_write(codec, 0x01, 0,
3662 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3663 snd_hda_codec_write(codec, 0x01, 0,
3664 AC_VERB_SET_GPIO_MASK, 0x1F);
3665 snd_hda_codec_write(codec, 0x01, 0,
3666 AC_VERB_SET_GPIO_DATA, 0x0C);
3667 break;
3668 default:
3669 break;
3670 }
3671 }
3672
3673 /*
3674 * GPIO control functions for the Recon3D integrated.
3675 */
3676
3677 enum r3di_gpio_bit {
3678 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3679 R3DI_MIC_SELECT_BIT = 1,
3680 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3681 R3DI_OUT_SELECT_BIT = 2,
3682 /*
3683 * I dunno what this actually does, but it stays on until the dsp
3684 * is downloaded.
3685 */
3686 R3DI_GPIO_DSP_DOWNLOADING = 3,
3687 /*
3688 * Same as above, no clue what it does, but it comes on after the dsp
3689 * is downloaded.
3690 */
3691 R3DI_GPIO_DSP_DOWNLOADED = 4
3692 };
3693
3694 enum r3di_mic_select {
3695 /* Set GPIO bit 1 to 0 for rear mic */
3696 R3DI_REAR_MIC = 0,
3697 /* Set GPIO bit 1 to 1 for front microphone*/
3698 R3DI_FRONT_MIC = 1
3699 };
3700
3701 enum r3di_out_select {
3702 /* Set GPIO bit 2 to 0 for headphone */
3703 R3DI_HEADPHONE_OUT = 0,
3704 /* Set GPIO bit 2 to 1 for speaker */
3705 R3DI_LINE_OUT = 1
3706 };
3707 enum r3di_dsp_status {
3708 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3709 R3DI_DSP_DOWNLOADING = 0,
3710 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3711 R3DI_DSP_DOWNLOADED = 1
3712 };
3713
3714
r3di_gpio_mic_set(struct hda_codec * codec,enum r3di_mic_select cur_mic)3715 static void r3di_gpio_mic_set(struct hda_codec *codec,
3716 enum r3di_mic_select cur_mic)
3717 {
3718 unsigned int cur_gpio;
3719
3720 /* Get the current GPIO Data setup */
3721 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3722
3723 switch (cur_mic) {
3724 case R3DI_REAR_MIC:
3725 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3726 break;
3727 case R3DI_FRONT_MIC:
3728 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3729 break;
3730 }
3731 snd_hda_codec_write(codec, codec->core.afg, 0,
3732 AC_VERB_SET_GPIO_DATA, cur_gpio);
3733 }
3734
r3di_gpio_dsp_status_set(struct hda_codec * codec,enum r3di_dsp_status dsp_status)3735 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3736 enum r3di_dsp_status dsp_status)
3737 {
3738 unsigned int cur_gpio;
3739
3740 /* Get the current GPIO Data setup */
3741 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3742
3743 switch (dsp_status) {
3744 case R3DI_DSP_DOWNLOADING:
3745 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3746 snd_hda_codec_write(codec, codec->core.afg, 0,
3747 AC_VERB_SET_GPIO_DATA, cur_gpio);
3748 break;
3749 case R3DI_DSP_DOWNLOADED:
3750 /* Set DOWNLOADING bit to 0. */
3751 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3752
3753 snd_hda_codec_write(codec, codec->core.afg, 0,
3754 AC_VERB_SET_GPIO_DATA, cur_gpio);
3755
3756 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3757 break;
3758 }
3759
3760 snd_hda_codec_write(codec, codec->core.afg, 0,
3761 AC_VERB_SET_GPIO_DATA, cur_gpio);
3762 }
3763
3764 /*
3765 * PCM callbacks
3766 */
ca0132_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3767 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3768 struct hda_codec *codec,
3769 unsigned int stream_tag,
3770 unsigned int format,
3771 struct snd_pcm_substream *substream)
3772 {
3773 struct ca0132_spec *spec = codec->spec;
3774
3775 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3776
3777 return 0;
3778 }
3779
ca0132_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3780 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3781 struct hda_codec *codec,
3782 struct snd_pcm_substream *substream)
3783 {
3784 struct ca0132_spec *spec = codec->spec;
3785
3786 if (spec->dsp_state == DSP_DOWNLOADING)
3787 return 0;
3788
3789 /*If Playback effects are on, allow stream some time to flush
3790 *effects tail*/
3791 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3792 msleep(50);
3793
3794 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3795
3796 return 0;
3797 }
3798
ca0132_playback_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)3799 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3800 struct hda_codec *codec,
3801 struct snd_pcm_substream *substream)
3802 {
3803 struct ca0132_spec *spec = codec->spec;
3804 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3805 struct snd_pcm_runtime *runtime = substream->runtime;
3806
3807 if (spec->dsp_state != DSP_DOWNLOADED)
3808 return 0;
3809
3810 /* Add latency if playback enhancement and either effect is enabled. */
3811 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3812 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3813 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3814 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3815 }
3816
3817 /* Applying Speaker EQ adds latency as well. */
3818 if (spec->cur_out_type == SPEAKER_OUT)
3819 latency += DSP_SPEAKER_OUT_LATENCY;
3820
3821 return (latency * runtime->rate) / 1000;
3822 }
3823
3824 /*
3825 * Digital out
3826 */
ca0132_dig_playback_pcm_open(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3827 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3828 struct hda_codec *codec,
3829 struct snd_pcm_substream *substream)
3830 {
3831 struct ca0132_spec *spec = codec->spec;
3832 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3833 }
3834
ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3835 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3836 struct hda_codec *codec,
3837 unsigned int stream_tag,
3838 unsigned int format,
3839 struct snd_pcm_substream *substream)
3840 {
3841 struct ca0132_spec *spec = codec->spec;
3842 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3843 stream_tag, format, substream);
3844 }
3845
ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3846 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3847 struct hda_codec *codec,
3848 struct snd_pcm_substream *substream)
3849 {
3850 struct ca0132_spec *spec = codec->spec;
3851 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3852 }
3853
ca0132_dig_playback_pcm_close(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3854 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3855 struct hda_codec *codec,
3856 struct snd_pcm_substream *substream)
3857 {
3858 struct ca0132_spec *spec = codec->spec;
3859 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3860 }
3861
3862 /*
3863 * Analog capture
3864 */
ca0132_capture_pcm_prepare(struct hda_pcm_stream * hinfo,struct hda_codec * codec,unsigned int stream_tag,unsigned int format,struct snd_pcm_substream * substream)3865 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3866 struct hda_codec *codec,
3867 unsigned int stream_tag,
3868 unsigned int format,
3869 struct snd_pcm_substream *substream)
3870 {
3871 snd_hda_codec_setup_stream(codec, hinfo->nid,
3872 stream_tag, 0, format);
3873
3874 return 0;
3875 }
3876
ca0132_capture_pcm_cleanup(struct hda_pcm_stream * hinfo,struct hda_codec * codec,struct snd_pcm_substream * substream)3877 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3878 struct hda_codec *codec,
3879 struct snd_pcm_substream *substream)
3880 {
3881 struct ca0132_spec *spec = codec->spec;
3882
3883 if (spec->dsp_state == DSP_DOWNLOADING)
3884 return 0;
3885
3886 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3887 return 0;
3888 }
3889
ca0132_capture_pcm_delay(struct hda_pcm_stream * info,struct hda_codec * codec,struct snd_pcm_substream * substream)3890 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3891 struct hda_codec *codec,
3892 struct snd_pcm_substream *substream)
3893 {
3894 struct ca0132_spec *spec = codec->spec;
3895 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3896 struct snd_pcm_runtime *runtime = substream->runtime;
3897
3898 if (spec->dsp_state != DSP_DOWNLOADED)
3899 return 0;
3900
3901 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3902 latency += DSP_CRYSTAL_VOICE_LATENCY;
3903
3904 return (latency * runtime->rate) / 1000;
3905 }
3906
3907 /*
3908 * Controls stuffs.
3909 */
3910
3911 /*
3912 * Mixer controls helpers.
3913 */
3914 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3915 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3916 .name = xname, \
3917 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3918 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3919 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3920 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3921 .info = ca0132_volume_info, \
3922 .get = ca0132_volume_get, \
3923 .put = ca0132_volume_put, \
3924 .tlv = { .c = ca0132_volume_tlv }, \
3925 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3926
3927 /*
3928 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3929 * volume put, which is used for setting the DSP volume. This was done because
3930 * the ca0132 functions were taking too much time and causing lag.
3931 */
3932 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3933 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3934 .name = xname, \
3935 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3936 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3937 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3938 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3939 .info = snd_hda_mixer_amp_volume_info, \
3940 .get = snd_hda_mixer_amp_volume_get, \
3941 .put = ca0132_alt_volume_put, \
3942 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3943 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3944
3945 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3946 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3947 .name = xname, \
3948 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3949 .info = snd_hda_mixer_amp_switch_info, \
3950 .get = ca0132_switch_get, \
3951 .put = ca0132_switch_put, \
3952 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3953
3954 /* stereo */
3955 #define CA0132_CODEC_VOL(xname, nid, dir) \
3956 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3957 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3958 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3959 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3960 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3961
3962 /* lookup tables */
3963 /*
3964 * Lookup table with decibel values for the DSP. When volume is changed in
3965 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3966 * these values have decimal points, probably because the Windows driver
3967 * actually uses floating point. We can't here, so I made a lookup table of
3968 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3969 * DAC's, and 9 is the maximum.
3970 */
3971 static const unsigned int float_vol_db_lookup[] = {
3972 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3973 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3974 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3975 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3976 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3977 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3978 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3979 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3980 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3981 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3982 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3983 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3984 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3985 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3986 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3987 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3988 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3989 };
3990
3991 /*
3992 * This table counts from float 0 to 1 in increments of .01, which is
3993 * useful for a few different sliders.
3994 */
3995 static const unsigned int float_zero_to_one_lookup[] = {
3996 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3997 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3998 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3999 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4000 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4001 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4002 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4003 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4004 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4005 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4006 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4007 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4008 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4009 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4010 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4011 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4012 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4013 };
4014
4015 /*
4016 * This table counts from float 10 to 1000, which is the range of the x-bass
4017 * crossover slider in Windows.
4018 */
4019 static const unsigned int float_xbass_xover_lookup[] = {
4020 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
4021 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
4022 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
4023 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
4024 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
4025 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
4026 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
4027 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
4028 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
4029 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
4030 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
4031 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
4032 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
4033 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
4034 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
4035 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
4036 0x44728000, 0x44750000, 0x44778000, 0x447A0000
4037 };
4038
4039 /* The following are for tuning of products */
4040 #ifdef ENABLE_TUNING_CONTROLS
4041
4042 static const unsigned int voice_focus_vals_lookup[] = {
4043 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
4044 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
4045 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
4046 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
4047 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
4048 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
4049 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
4050 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
4051 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
4052 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
4053 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
4054 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
4055 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
4056 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
4057 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
4058 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
4059 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
4060 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
4061 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
4062 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
4063 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
4064 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
4065 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
4066 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
4067 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
4068 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
4069 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
4070 };
4071
4072 static const unsigned int mic_svm_vals_lookup[] = {
4073 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
4074 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
4075 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
4076 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
4077 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
4078 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
4079 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
4080 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
4081 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
4082 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
4083 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
4084 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
4085 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
4086 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
4087 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
4088 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
4089 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
4090 };
4091
4092 static const unsigned int equalizer_vals_lookup[] = {
4093 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
4094 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
4095 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
4096 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
4097 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
4098 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
4099 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
4100 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
4101 0x41C00000
4102 };
4103
tuning_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)4104 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4105 const unsigned int *lookup, int idx)
4106 {
4107 int i = 0;
4108
4109 for (i = 0; i < TUNING_CTLS_COUNT; i++)
4110 if (nid == ca0132_tuning_ctls[i].nid)
4111 break;
4112
4113 snd_hda_power_up(codec);
4114 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
4115 ca0132_tuning_ctls[i].req,
4116 &(lookup[idx]), sizeof(unsigned int));
4117 snd_hda_power_down(codec);
4118
4119 return 1;
4120 }
4121
tuning_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4122 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
4123 struct snd_ctl_elem_value *ucontrol)
4124 {
4125 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4126 struct ca0132_spec *spec = codec->spec;
4127 hda_nid_t nid = get_amp_nid(kcontrol);
4128 long *valp = ucontrol->value.integer.value;
4129 int idx = nid - TUNING_CTL_START_NID;
4130
4131 *valp = spec->cur_ctl_vals[idx];
4132 return 0;
4133 }
4134
voice_focus_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4135 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
4136 struct snd_ctl_elem_info *uinfo)
4137 {
4138 int chs = get_amp_channels(kcontrol);
4139 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4140 uinfo->count = chs == 3 ? 2 : 1;
4141 uinfo->value.integer.min = 20;
4142 uinfo->value.integer.max = 180;
4143 uinfo->value.integer.step = 1;
4144
4145 return 0;
4146 }
4147
voice_focus_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4148 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
4149 struct snd_ctl_elem_value *ucontrol)
4150 {
4151 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4152 struct ca0132_spec *spec = codec->spec;
4153 hda_nid_t nid = get_amp_nid(kcontrol);
4154 long *valp = ucontrol->value.integer.value;
4155 int idx;
4156
4157 idx = nid - TUNING_CTL_START_NID;
4158 /* any change? */
4159 if (spec->cur_ctl_vals[idx] == *valp)
4160 return 0;
4161
4162 spec->cur_ctl_vals[idx] = *valp;
4163
4164 idx = *valp - 20;
4165 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
4166
4167 return 1;
4168 }
4169
mic_svm_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4170 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
4171 struct snd_ctl_elem_info *uinfo)
4172 {
4173 int chs = get_amp_channels(kcontrol);
4174 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4175 uinfo->count = chs == 3 ? 2 : 1;
4176 uinfo->value.integer.min = 0;
4177 uinfo->value.integer.max = 100;
4178 uinfo->value.integer.step = 1;
4179
4180 return 0;
4181 }
4182
mic_svm_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4183 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
4184 struct snd_ctl_elem_value *ucontrol)
4185 {
4186 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4187 struct ca0132_spec *spec = codec->spec;
4188 hda_nid_t nid = get_amp_nid(kcontrol);
4189 long *valp = ucontrol->value.integer.value;
4190 int idx;
4191
4192 idx = nid - TUNING_CTL_START_NID;
4193 /* any change? */
4194 if (spec->cur_ctl_vals[idx] == *valp)
4195 return 0;
4196
4197 spec->cur_ctl_vals[idx] = *valp;
4198
4199 idx = *valp;
4200 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
4201
4202 return 0;
4203 }
4204
equalizer_ctl_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)4205 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
4206 struct snd_ctl_elem_info *uinfo)
4207 {
4208 int chs = get_amp_channels(kcontrol);
4209 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4210 uinfo->count = chs == 3 ? 2 : 1;
4211 uinfo->value.integer.min = 0;
4212 uinfo->value.integer.max = 48;
4213 uinfo->value.integer.step = 1;
4214
4215 return 0;
4216 }
4217
equalizer_ctl_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)4218 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
4219 struct snd_ctl_elem_value *ucontrol)
4220 {
4221 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4222 struct ca0132_spec *spec = codec->spec;
4223 hda_nid_t nid = get_amp_nid(kcontrol);
4224 long *valp = ucontrol->value.integer.value;
4225 int idx;
4226
4227 idx = nid - TUNING_CTL_START_NID;
4228 /* any change? */
4229 if (spec->cur_ctl_vals[idx] == *valp)
4230 return 0;
4231
4232 spec->cur_ctl_vals[idx] = *valp;
4233
4234 idx = *valp;
4235 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
4236
4237 return 1;
4238 }
4239
4240 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
4241 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
4242
add_tuning_control(struct hda_codec * codec,hda_nid_t pnid,hda_nid_t nid,const char * name,int dir)4243 static int add_tuning_control(struct hda_codec *codec,
4244 hda_nid_t pnid, hda_nid_t nid,
4245 const char *name, int dir)
4246 {
4247 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4248 int type = dir ? HDA_INPUT : HDA_OUTPUT;
4249 struct snd_kcontrol_new knew =
4250 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
4251
4252 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
4253 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
4254 knew.tlv.c = 0;
4255 knew.tlv.p = 0;
4256 switch (pnid) {
4257 case VOICE_FOCUS:
4258 knew.info = voice_focus_ctl_info;
4259 knew.get = tuning_ctl_get;
4260 knew.put = voice_focus_ctl_put;
4261 knew.tlv.p = voice_focus_db_scale;
4262 break;
4263 case MIC_SVM:
4264 knew.info = mic_svm_ctl_info;
4265 knew.get = tuning_ctl_get;
4266 knew.put = mic_svm_ctl_put;
4267 break;
4268 case EQUALIZER:
4269 knew.info = equalizer_ctl_info;
4270 knew.get = tuning_ctl_get;
4271 knew.put = equalizer_ctl_put;
4272 knew.tlv.p = eq_db_scale;
4273 break;
4274 default:
4275 return 0;
4276 }
4277 knew.private_value =
4278 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
4279 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
4280 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
4281 }
4282
add_tuning_ctls(struct hda_codec * codec)4283 static int add_tuning_ctls(struct hda_codec *codec)
4284 {
4285 int i;
4286 int err;
4287
4288 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
4289 err = add_tuning_control(codec,
4290 ca0132_tuning_ctls[i].parent_nid,
4291 ca0132_tuning_ctls[i].nid,
4292 ca0132_tuning_ctls[i].name,
4293 ca0132_tuning_ctls[i].direct);
4294 if (err < 0)
4295 return err;
4296 }
4297
4298 return 0;
4299 }
4300
ca0132_init_tuning_defaults(struct hda_codec * codec)4301 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
4302 {
4303 struct ca0132_spec *spec = codec->spec;
4304 int i;
4305
4306 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
4307 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
4308 /* SVM level defaults to 0.74. */
4309 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
4310
4311 /* EQ defaults to 0dB. */
4312 for (i = 2; i < TUNING_CTLS_COUNT; i++)
4313 spec->cur_ctl_vals[i] = 24;
4314 }
4315 #endif /*ENABLE_TUNING_CONTROLS*/
4316
4317 /*
4318 * Select the active output.
4319 * If autodetect is enabled, output will be selected based on jack detection.
4320 * If jack inserted, headphone will be selected, else built-in speakers
4321 * If autodetect is disabled, output will be selected based on selection.
4322 */
ca0132_select_out(struct hda_codec * codec)4323 static int ca0132_select_out(struct hda_codec *codec)
4324 {
4325 struct ca0132_spec *spec = codec->spec;
4326 unsigned int pin_ctl;
4327 int jack_present;
4328 int auto_jack;
4329 unsigned int tmp;
4330 int err;
4331
4332 codec_dbg(codec, "ca0132_select_out\n");
4333
4334 snd_hda_power_up_pm(codec);
4335
4336 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4337
4338 if (auto_jack)
4339 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
4340 else
4341 jack_present =
4342 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
4343
4344 if (jack_present)
4345 spec->cur_out_type = HEADPHONE_OUT;
4346 else
4347 spec->cur_out_type = SPEAKER_OUT;
4348
4349 if (spec->cur_out_type == SPEAKER_OUT) {
4350 codec_dbg(codec, "ca0132_select_out speaker\n");
4351 /*speaker out config*/
4352 tmp = FLOAT_ONE;
4353 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4354 if (err < 0)
4355 goto exit;
4356 /*enable speaker EQ*/
4357 tmp = FLOAT_ONE;
4358 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4359 if (err < 0)
4360 goto exit;
4361
4362 /* Setup EAPD */
4363 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4364 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4365 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4366 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4367 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4368 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4369 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4370 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4371
4372 /* disable headphone node */
4373 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4374 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4375 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4376 pin_ctl & ~PIN_HP);
4377 /* enable speaker node */
4378 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4379 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4380 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4381 pin_ctl | PIN_OUT);
4382 } else {
4383 codec_dbg(codec, "ca0132_select_out hp\n");
4384 /*headphone out config*/
4385 tmp = FLOAT_ZERO;
4386 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4387 if (err < 0)
4388 goto exit;
4389 /*disable speaker EQ*/
4390 tmp = FLOAT_ZERO;
4391 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
4392 if (err < 0)
4393 goto exit;
4394
4395 /* Setup EAPD */
4396 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4397 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
4398 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4399 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4400 snd_hda_codec_write(codec, spec->out_pins[1], 0,
4401 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
4402 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4403 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
4404
4405 /* disable speaker*/
4406 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4407 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4408 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4409 pin_ctl & ~PIN_HP);
4410 /* enable headphone*/
4411 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4412 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4413 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4414 pin_ctl | PIN_HP);
4415 }
4416
4417 exit:
4418 snd_hda_power_down_pm(codec);
4419
4420 return err < 0 ? err : 0;
4421 }
4422
4423 static int ae5_headphone_gain_set(struct hda_codec *codec, long val);
4424 static int zxr_headphone_gain_set(struct hda_codec *codec, long val);
4425 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4426
ae5_mmio_select_out(struct hda_codec * codec)4427 static void ae5_mmio_select_out(struct hda_codec *codec)
4428 {
4429 struct ca0132_spec *spec = codec->spec;
4430 const struct ae_ca0113_output_set *out_cmds;
4431 unsigned int i;
4432
4433 if (ca0132_quirk(spec) == QUIRK_AE5)
4434 out_cmds = &ae5_ca0113_output_presets;
4435 else
4436 out_cmds = &ae7_ca0113_output_presets;
4437
4438 for (i = 0; i < AE_CA0113_OUT_SET_COMMANDS; i++)
4439 ca0113_mmio_command_set(codec, out_cmds->group[i],
4440 out_cmds->target[i],
4441 out_cmds->vals[spec->cur_out_type][i]);
4442 }
4443
ca0132_alt_set_full_range_speaker(struct hda_codec * codec)4444 static int ca0132_alt_set_full_range_speaker(struct hda_codec *codec)
4445 {
4446 struct ca0132_spec *spec = codec->spec;
4447 int quirk = ca0132_quirk(spec);
4448 unsigned int tmp;
4449 int err;
4450
4451 /* 2.0/4.0 setup has no LFE channel, so setting full-range does nothing. */
4452 if (spec->channel_cfg_val == SPEAKER_CHANNELS_4_0
4453 || spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4454 return 0;
4455
4456 /* Set front L/R full range. Zero for full-range, one for redirection. */
4457 tmp = spec->speaker_range_val[0] ? FLOAT_ZERO : FLOAT_ONE;
4458 err = dspio_set_uint_param(codec, 0x96,
4459 SPEAKER_FULL_RANGE_FRONT_L_R, tmp);
4460 if (err < 0)
4461 return err;
4462
4463 /* When setting full-range rear, both rear and center/lfe are set. */
4464 tmp = spec->speaker_range_val[1] ? FLOAT_ZERO : FLOAT_ONE;
4465 err = dspio_set_uint_param(codec, 0x96,
4466 SPEAKER_FULL_RANGE_CENTER_LFE, tmp);
4467 if (err < 0)
4468 return err;
4469
4470 err = dspio_set_uint_param(codec, 0x96,
4471 SPEAKER_FULL_RANGE_REAR_L_R, tmp);
4472 if (err < 0)
4473 return err;
4474
4475 /*
4476 * Only the AE series cards set this value when setting full-range,
4477 * and it's always 1.0f.
4478 */
4479 if (quirk == QUIRK_AE5 || quirk == QUIRK_AE7) {
4480 err = dspio_set_uint_param(codec, 0x96,
4481 SPEAKER_FULL_RANGE_SURROUND_L_R, FLOAT_ONE);
4482 if (err < 0)
4483 return err;
4484 }
4485
4486 return 0;
4487 }
4488
ca0132_alt_surround_set_bass_redirection(struct hda_codec * codec,bool val)4489 static int ca0132_alt_surround_set_bass_redirection(struct hda_codec *codec,
4490 bool val)
4491 {
4492 struct ca0132_spec *spec = codec->spec;
4493 unsigned int tmp;
4494 int err;
4495
4496 if (val && spec->channel_cfg_val != SPEAKER_CHANNELS_4_0 &&
4497 spec->channel_cfg_val != SPEAKER_CHANNELS_2_0)
4498 tmp = FLOAT_ONE;
4499 else
4500 tmp = FLOAT_ZERO;
4501
4502 err = dspio_set_uint_param(codec, 0x96, SPEAKER_BASS_REDIRECT, tmp);
4503 if (err < 0)
4504 return err;
4505
4506 /* If it is enabled, make sure to set the crossover frequency. */
4507 if (tmp) {
4508 tmp = float_xbass_xover_lookup[spec->xbass_xover_freq];
4509 err = dspio_set_uint_param(codec, 0x96,
4510 SPEAKER_BASS_REDIRECT_XOVER_FREQ, tmp);
4511 if (err < 0)
4512 return err;
4513 }
4514
4515 return 0;
4516 }
4517
4518 /*
4519 * These are the commands needed to setup output on each of the different card
4520 * types.
4521 */
ca0132_alt_select_out_get_quirk_data(struct hda_codec * codec,const struct ca0132_alt_out_set_quirk_data ** quirk_data)4522 static void ca0132_alt_select_out_get_quirk_data(struct hda_codec *codec,
4523 const struct ca0132_alt_out_set_quirk_data **quirk_data)
4524 {
4525 struct ca0132_spec *spec = codec->spec;
4526 int quirk = ca0132_quirk(spec);
4527 unsigned int i;
4528
4529 *quirk_data = NULL;
4530 for (i = 0; i < ARRAY_SIZE(quirk_out_set_data); i++) {
4531 if (quirk_out_set_data[i].quirk_id == quirk) {
4532 *quirk_data = &quirk_out_set_data[i];
4533 return;
4534 }
4535 }
4536 }
4537
ca0132_alt_select_out_quirk_set(struct hda_codec * codec)4538 static int ca0132_alt_select_out_quirk_set(struct hda_codec *codec)
4539 {
4540 const struct ca0132_alt_out_set_quirk_data *quirk_data;
4541 const struct ca0132_alt_out_set_info *out_info;
4542 struct ca0132_spec *spec = codec->spec;
4543 unsigned int i, gpio_data;
4544 int err;
4545
4546 ca0132_alt_select_out_get_quirk_data(codec, &quirk_data);
4547 if (!quirk_data)
4548 return 0;
4549
4550 out_info = &quirk_data->out_set_info[spec->cur_out_type];
4551 if (quirk_data->is_ae_series)
4552 ae5_mmio_select_out(codec);
4553
4554 if (out_info->has_hda_gpio) {
4555 gpio_data = snd_hda_codec_read(codec, codec->core.afg, 0,
4556 AC_VERB_GET_GPIO_DATA, 0);
4557
4558 if (out_info->hda_gpio_set)
4559 gpio_data |= (1 << out_info->hda_gpio_pin);
4560 else
4561 gpio_data &= ~(1 << out_info->hda_gpio_pin);
4562
4563 snd_hda_codec_write(codec, codec->core.afg, 0,
4564 AC_VERB_SET_GPIO_DATA, gpio_data);
4565 }
4566
4567 if (out_info->mmio_gpio_count) {
4568 for (i = 0; i < out_info->mmio_gpio_count; i++) {
4569 ca0113_mmio_gpio_set(codec, out_info->mmio_gpio_pin[i],
4570 out_info->mmio_gpio_set[i]);
4571 }
4572 }
4573
4574 if (out_info->scp_cmds_count) {
4575 for (i = 0; i < out_info->scp_cmds_count; i++) {
4576 err = dspio_set_uint_param(codec,
4577 out_info->scp_cmd_mid[i],
4578 out_info->scp_cmd_req[i],
4579 out_info->scp_cmd_val[i]);
4580 if (err < 0)
4581 return err;
4582 }
4583 }
4584
4585 chipio_set_control_param(codec, 0x0d, out_info->dac2port);
4586
4587 if (out_info->has_chipio_write) {
4588 chipio_write(codec, out_info->chipio_write_addr,
4589 out_info->chipio_write_data);
4590 }
4591
4592 if (quirk_data->has_headphone_gain) {
4593 if (spec->cur_out_type != HEADPHONE_OUT) {
4594 if (quirk_data->is_ae_series)
4595 ae5_headphone_gain_set(codec, 2);
4596 else
4597 zxr_headphone_gain_set(codec, 0);
4598 } else {
4599 if (quirk_data->is_ae_series)
4600 ae5_headphone_gain_set(codec,
4601 spec->ae5_headphone_gain_val);
4602 else
4603 zxr_headphone_gain_set(codec,
4604 spec->zxr_gain_set);
4605 }
4606 }
4607
4608 return 0;
4609 }
4610
ca0132_set_out_node_pincfg(struct hda_codec * codec,hda_nid_t nid,bool out_enable,bool hp_enable)4611 static void ca0132_set_out_node_pincfg(struct hda_codec *codec, hda_nid_t nid,
4612 bool out_enable, bool hp_enable)
4613 {
4614 unsigned int pin_ctl;
4615
4616 pin_ctl = snd_hda_codec_read(codec, nid, 0,
4617 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4618
4619 pin_ctl = hp_enable ? pin_ctl | PIN_HP_AMP : pin_ctl & ~PIN_HP_AMP;
4620 pin_ctl = out_enable ? pin_ctl | PIN_OUT : pin_ctl & ~PIN_OUT;
4621 snd_hda_set_pin_ctl(codec, nid, pin_ctl);
4622 }
4623
4624 /*
4625 * This function behaves similarly to the ca0132_select_out funciton above,
4626 * except with a few differences. It adds the ability to select the current
4627 * output with an enumerated control "output source" if the auto detect
4628 * mute switch is set to off. If the auto detect mute switch is enabled, it
4629 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
4630 * It also adds the ability to auto-detect the front headphone port.
4631 */
ca0132_alt_select_out(struct hda_codec * codec)4632 static int ca0132_alt_select_out(struct hda_codec *codec)
4633 {
4634 struct ca0132_spec *spec = codec->spec;
4635 unsigned int tmp, outfx_set;
4636 int jack_present;
4637 int auto_jack;
4638 int err;
4639 /* Default Headphone is rear headphone */
4640 hda_nid_t headphone_nid = spec->out_pins[1];
4641
4642 codec_dbg(codec, "%s\n", __func__);
4643
4644 snd_hda_power_up_pm(codec);
4645
4646 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4647
4648 /*
4649 * If headphone rear or front is plugged in, set to headphone.
4650 * If neither is plugged in, set to rear line out. Only if
4651 * hp/speaker auto detect is enabled.
4652 */
4653 if (auto_jack) {
4654 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
4655 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
4656
4657 if (jack_present)
4658 spec->cur_out_type = HEADPHONE_OUT;
4659 else
4660 spec->cur_out_type = SPEAKER_OUT;
4661 } else
4662 spec->cur_out_type = spec->out_enum_val;
4663
4664 outfx_set = spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID];
4665
4666 /* Begin DSP output switch, mute DSP volume. */
4667 err = dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_MUTE, FLOAT_ONE);
4668 if (err < 0)
4669 goto exit;
4670
4671 if (ca0132_alt_select_out_quirk_set(codec) < 0)
4672 goto exit;
4673
4674 switch (spec->cur_out_type) {
4675 case SPEAKER_OUT:
4676 codec_dbg(codec, "%s speaker\n", __func__);
4677
4678 /* Enable EAPD */
4679 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4680 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4681
4682 /* Disable headphone node. */
4683 ca0132_set_out_node_pincfg(codec, spec->out_pins[1], 0, 0);
4684 /* Set front L-R to output. */
4685 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 1, 0);
4686 /* Set Center/LFE to output. */
4687 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 1, 0);
4688 /* Set rear surround to output. */
4689 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 1, 0);
4690
4691 /*
4692 * Without PlayEnhancement being enabled, if we've got a 2.0
4693 * setup, set it to floating point eight to disable any DSP
4694 * processing effects.
4695 */
4696 if (!outfx_set && spec->channel_cfg_val == SPEAKER_CHANNELS_2_0)
4697 tmp = FLOAT_EIGHT;
4698 else
4699 tmp = speaker_channel_cfgs[spec->channel_cfg_val].val;
4700
4701 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
4702 if (err < 0)
4703 goto exit;
4704
4705 break;
4706 case HEADPHONE_OUT:
4707 codec_dbg(codec, "%s hp\n", __func__);
4708 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4709 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4710
4711 /* Disable all speaker nodes. */
4712 ca0132_set_out_node_pincfg(codec, spec->out_pins[0], 0, 0);
4713 ca0132_set_out_node_pincfg(codec, spec->out_pins[2], 0, 0);
4714 ca0132_set_out_node_pincfg(codec, spec->out_pins[3], 0, 0);
4715
4716 /* enable headphone, either front or rear */
4717 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4718 headphone_nid = spec->out_pins[2];
4719 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4720 headphone_nid = spec->out_pins[1];
4721
4722 ca0132_set_out_node_pincfg(codec, headphone_nid, 1, 1);
4723
4724 if (outfx_set)
4725 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4726 else
4727 err = dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4728
4729 if (err < 0)
4730 goto exit;
4731 break;
4732 }
4733 /*
4734 * If output effects are enabled, set the X-Bass effect value again to
4735 * make sure that it's properly enabled/disabled for speaker
4736 * configurations with an LFE channel.
4737 */
4738 if (outfx_set)
4739 ca0132_effects_set(codec, X_BASS,
4740 spec->effects_switch[X_BASS - EFFECT_START_NID]);
4741
4742 /* Set speaker EQ bypass attenuation to 0. */
4743 err = dspio_set_uint_param(codec, 0x8f, 0x01, FLOAT_ZERO);
4744 if (err < 0)
4745 goto exit;
4746
4747 /*
4748 * Although unused on all cards but the AE series, this is always set
4749 * to zero when setting the output.
4750 */
4751 err = dspio_set_uint_param(codec, 0x96,
4752 SPEAKER_TUNING_USE_SPEAKER_EQ, FLOAT_ZERO);
4753 if (err < 0)
4754 goto exit;
4755
4756 if (spec->cur_out_type == SPEAKER_OUT)
4757 err = ca0132_alt_surround_set_bass_redirection(codec,
4758 spec->bass_redirection_val);
4759 else
4760 err = ca0132_alt_surround_set_bass_redirection(codec, 0);
4761
4762 /* Unmute DSP now that we're done with output selection. */
4763 err = dspio_set_uint_param(codec, 0x96,
4764 SPEAKER_TUNING_MUTE, FLOAT_ZERO);
4765 if (err < 0)
4766 goto exit;
4767
4768 if (spec->cur_out_type == SPEAKER_OUT) {
4769 err = ca0132_alt_set_full_range_speaker(codec);
4770 if (err < 0)
4771 goto exit;
4772 }
4773
4774 exit:
4775 snd_hda_power_down_pm(codec);
4776
4777 return err < 0 ? err : 0;
4778 }
4779
ca0132_unsol_hp_delayed(struct work_struct * work)4780 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4781 {
4782 struct ca0132_spec *spec = container_of(
4783 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4784 struct hda_jack_tbl *jack;
4785
4786 if (ca0132_use_alt_functions(spec))
4787 ca0132_alt_select_out(spec->codec);
4788 else
4789 ca0132_select_out(spec->codec);
4790
4791 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4792 if (jack) {
4793 jack->block_report = 0;
4794 snd_hda_jack_report_sync(spec->codec);
4795 }
4796 }
4797
4798 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4799 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4800 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4801 static int stop_mic1(struct hda_codec *codec);
4802 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4803 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4804
4805 /*
4806 * Select the active VIP source
4807 */
ca0132_set_vipsource(struct hda_codec * codec,int val)4808 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4809 {
4810 struct ca0132_spec *spec = codec->spec;
4811 unsigned int tmp;
4812
4813 if (spec->dsp_state != DSP_DOWNLOADED)
4814 return 0;
4815
4816 /* if CrystalVoice if off, vipsource should be 0 */
4817 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4818 (val == 0)) {
4819 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4820 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4821 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4822 if (spec->cur_mic_type == DIGITAL_MIC)
4823 tmp = FLOAT_TWO;
4824 else
4825 tmp = FLOAT_ONE;
4826 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4827 tmp = FLOAT_ZERO;
4828 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4829 } else {
4830 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4831 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4832 if (spec->cur_mic_type == DIGITAL_MIC)
4833 tmp = FLOAT_TWO;
4834 else
4835 tmp = FLOAT_ONE;
4836 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4837 tmp = FLOAT_ONE;
4838 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4839 msleep(20);
4840 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4841 }
4842
4843 return 1;
4844 }
4845
ca0132_alt_set_vipsource(struct hda_codec * codec,int val)4846 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4847 {
4848 struct ca0132_spec *spec = codec->spec;
4849 unsigned int tmp;
4850
4851 if (spec->dsp_state != DSP_DOWNLOADED)
4852 return 0;
4853
4854 codec_dbg(codec, "%s\n", __func__);
4855
4856 chipio_set_stream_control(codec, 0x03, 0);
4857 chipio_set_stream_control(codec, 0x04, 0);
4858
4859 /* if CrystalVoice is off, vipsource should be 0 */
4860 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4861 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4862 codec_dbg(codec, "%s: off.", __func__);
4863 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4864
4865 tmp = FLOAT_ZERO;
4866 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4867
4868 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4869 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4870 if (ca0132_quirk(spec) == QUIRK_R3DI)
4871 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4872
4873
4874 if (spec->in_enum_val == REAR_LINE_IN)
4875 tmp = FLOAT_ZERO;
4876 else {
4877 if (ca0132_quirk(spec) == QUIRK_SBZ)
4878 tmp = FLOAT_THREE;
4879 else
4880 tmp = FLOAT_ONE;
4881 }
4882
4883 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4884
4885 } else {
4886 codec_dbg(codec, "%s: on.", __func__);
4887 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4888 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4889 if (ca0132_quirk(spec) == QUIRK_R3DI)
4890 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4891
4892 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4893 tmp = FLOAT_TWO;
4894 else
4895 tmp = FLOAT_ONE;
4896 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4897
4898 tmp = FLOAT_ONE;
4899 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4900
4901 msleep(20);
4902 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4903 }
4904
4905 chipio_set_stream_control(codec, 0x03, 1);
4906 chipio_set_stream_control(codec, 0x04, 1);
4907
4908 return 1;
4909 }
4910
4911 /*
4912 * Select the active microphone.
4913 * If autodetect is enabled, mic will be selected based on jack detection.
4914 * If jack inserted, ext.mic will be selected, else built-in mic
4915 * If autodetect is disabled, mic will be selected based on selection.
4916 */
ca0132_select_mic(struct hda_codec * codec)4917 static int ca0132_select_mic(struct hda_codec *codec)
4918 {
4919 struct ca0132_spec *spec = codec->spec;
4920 int jack_present;
4921 int auto_jack;
4922
4923 codec_dbg(codec, "ca0132_select_mic\n");
4924
4925 snd_hda_power_up_pm(codec);
4926
4927 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4928
4929 if (auto_jack)
4930 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4931 else
4932 jack_present =
4933 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4934
4935 if (jack_present)
4936 spec->cur_mic_type = LINE_MIC_IN;
4937 else
4938 spec->cur_mic_type = DIGITAL_MIC;
4939
4940 if (spec->cur_mic_type == DIGITAL_MIC) {
4941 /* enable digital Mic */
4942 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4943 ca0132_set_dmic(codec, 1);
4944 ca0132_mic_boost_set(codec, 0);
4945 /* set voice focus */
4946 ca0132_effects_set(codec, VOICE_FOCUS,
4947 spec->effects_switch
4948 [VOICE_FOCUS - EFFECT_START_NID]);
4949 } else {
4950 /* disable digital Mic */
4951 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4952 ca0132_set_dmic(codec, 0);
4953 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4954 /* disable voice focus */
4955 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4956 }
4957
4958 snd_hda_power_down_pm(codec);
4959
4960 return 0;
4961 }
4962
4963 /*
4964 * Select the active input.
4965 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4966 * The front mic has no jack-detection, so the only way to switch to it
4967 * is to do it manually in alsamixer.
4968 */
ca0132_alt_select_in(struct hda_codec * codec)4969 static int ca0132_alt_select_in(struct hda_codec *codec)
4970 {
4971 struct ca0132_spec *spec = codec->spec;
4972 unsigned int tmp;
4973
4974 codec_dbg(codec, "%s\n", __func__);
4975
4976 snd_hda_power_up_pm(codec);
4977
4978 chipio_set_stream_control(codec, 0x03, 0);
4979 chipio_set_stream_control(codec, 0x04, 0);
4980
4981 spec->cur_mic_type = spec->in_enum_val;
4982
4983 switch (spec->cur_mic_type) {
4984 case REAR_MIC:
4985 switch (ca0132_quirk(spec)) {
4986 case QUIRK_SBZ:
4987 case QUIRK_R3D:
4988 ca0113_mmio_gpio_set(codec, 0, false);
4989 tmp = FLOAT_THREE;
4990 break;
4991 case QUIRK_ZXR:
4992 tmp = FLOAT_THREE;
4993 break;
4994 case QUIRK_R3DI:
4995 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4996 tmp = FLOAT_ONE;
4997 break;
4998 case QUIRK_AE5:
4999 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5000 tmp = FLOAT_THREE;
5001 break;
5002 case QUIRK_AE7:
5003 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5004 tmp = FLOAT_THREE;
5005 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5006 SR_96_000);
5007 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5008 SR_96_000);
5009 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5010 break;
5011 default:
5012 tmp = FLOAT_ONE;
5013 break;
5014 }
5015
5016 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5017 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5018 if (ca0132_quirk(spec) == QUIRK_R3DI)
5019 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5020
5021 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5022
5023 chipio_set_stream_control(codec, 0x03, 1);
5024 chipio_set_stream_control(codec, 0x04, 1);
5025 switch (ca0132_quirk(spec)) {
5026 case QUIRK_SBZ:
5027 chipio_write(codec, 0x18B098, 0x0000000C);
5028 chipio_write(codec, 0x18B09C, 0x0000000C);
5029 break;
5030 case QUIRK_ZXR:
5031 chipio_write(codec, 0x18B098, 0x0000000C);
5032 chipio_write(codec, 0x18B09C, 0x000000CC);
5033 break;
5034 case QUIRK_AE5:
5035 chipio_write(codec, 0x18B098, 0x0000000C);
5036 chipio_write(codec, 0x18B09C, 0x0000004C);
5037 break;
5038 default:
5039 break;
5040 }
5041 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5042 break;
5043 case REAR_LINE_IN:
5044 ca0132_mic_boost_set(codec, 0);
5045 switch (ca0132_quirk(spec)) {
5046 case QUIRK_SBZ:
5047 case QUIRK_R3D:
5048 ca0113_mmio_gpio_set(codec, 0, false);
5049 break;
5050 case QUIRK_R3DI:
5051 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
5052 break;
5053 case QUIRK_AE5:
5054 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
5055 break;
5056 case QUIRK_AE7:
5057 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5058 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2,
5059 SR_96_000);
5060 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2,
5061 SR_96_000);
5062 dspio_set_uint_param(codec, 0x80, 0x01, FLOAT_ZERO);
5063 break;
5064 default:
5065 break;
5066 }
5067
5068 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5069 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5070 if (ca0132_quirk(spec) == QUIRK_R3DI)
5071 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5072
5073 if (ca0132_quirk(spec) == QUIRK_AE7)
5074 tmp = FLOAT_THREE;
5075 else
5076 tmp = FLOAT_ZERO;
5077 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5078
5079 switch (ca0132_quirk(spec)) {
5080 case QUIRK_SBZ:
5081 case QUIRK_AE5:
5082 chipio_write(codec, 0x18B098, 0x00000000);
5083 chipio_write(codec, 0x18B09C, 0x00000000);
5084 break;
5085 default:
5086 break;
5087 }
5088 chipio_set_stream_control(codec, 0x03, 1);
5089 chipio_set_stream_control(codec, 0x04, 1);
5090 break;
5091 case FRONT_MIC:
5092 switch (ca0132_quirk(spec)) {
5093 case QUIRK_SBZ:
5094 case QUIRK_R3D:
5095 ca0113_mmio_gpio_set(codec, 0, true);
5096 ca0113_mmio_gpio_set(codec, 5, false);
5097 tmp = FLOAT_THREE;
5098 break;
5099 case QUIRK_R3DI:
5100 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
5101 tmp = FLOAT_ONE;
5102 break;
5103 case QUIRK_AE5:
5104 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x3f);
5105 tmp = FLOAT_THREE;
5106 break;
5107 default:
5108 tmp = FLOAT_ONE;
5109 break;
5110 }
5111
5112 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
5113 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
5114 if (ca0132_quirk(spec) == QUIRK_R3DI)
5115 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
5116
5117 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5118
5119 chipio_set_stream_control(codec, 0x03, 1);
5120 chipio_set_stream_control(codec, 0x04, 1);
5121
5122 switch (ca0132_quirk(spec)) {
5123 case QUIRK_SBZ:
5124 chipio_write(codec, 0x18B098, 0x0000000C);
5125 chipio_write(codec, 0x18B09C, 0x000000CC);
5126 break;
5127 case QUIRK_AE5:
5128 chipio_write(codec, 0x18B098, 0x0000000C);
5129 chipio_write(codec, 0x18B09C, 0x0000004C);
5130 break;
5131 default:
5132 break;
5133 }
5134 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5135 break;
5136 }
5137 ca0132_cvoice_switch_set(codec);
5138
5139 snd_hda_power_down_pm(codec);
5140 return 0;
5141 }
5142
5143 /*
5144 * Check if VNODE settings take effect immediately.
5145 */
ca0132_is_vnode_effective(struct hda_codec * codec,hda_nid_t vnid,hda_nid_t * shared_nid)5146 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
5147 hda_nid_t vnid,
5148 hda_nid_t *shared_nid)
5149 {
5150 struct ca0132_spec *spec = codec->spec;
5151 hda_nid_t nid;
5152
5153 switch (vnid) {
5154 case VNID_SPK:
5155 nid = spec->shared_out_nid;
5156 break;
5157 case VNID_MIC:
5158 nid = spec->shared_mic_nid;
5159 break;
5160 default:
5161 return false;
5162 }
5163
5164 if (shared_nid)
5165 *shared_nid = nid;
5166
5167 return true;
5168 }
5169
5170 /*
5171 * The following functions are control change helpers.
5172 * They return 0 if no changed. Return 1 if changed.
5173 */
ca0132_voicefx_set(struct hda_codec * codec,int enable)5174 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
5175 {
5176 struct ca0132_spec *spec = codec->spec;
5177 unsigned int tmp;
5178
5179 /* based on CrystalVoice state to enable VoiceFX. */
5180 if (enable) {
5181 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
5182 FLOAT_ONE : FLOAT_ZERO;
5183 } else {
5184 tmp = FLOAT_ZERO;
5185 }
5186
5187 dspio_set_uint_param(codec, ca0132_voicefx.mid,
5188 ca0132_voicefx.reqs[0], tmp);
5189
5190 return 1;
5191 }
5192
5193 /*
5194 * Set the effects parameters
5195 */
ca0132_effects_set(struct hda_codec * codec,hda_nid_t nid,long val)5196 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
5197 {
5198 struct ca0132_spec *spec = codec->spec;
5199 unsigned int on, tmp, channel_cfg;
5200 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5201 int err = 0;
5202 int idx = nid - EFFECT_START_NID;
5203
5204 if ((idx < 0) || (idx >= num_fx))
5205 return 0; /* no changed */
5206
5207 /* for out effect, qualify with PE */
5208 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
5209 /* if PE if off, turn off out effects. */
5210 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
5211 val = 0;
5212 if (spec->cur_out_type == SPEAKER_OUT && nid == X_BASS) {
5213 channel_cfg = spec->channel_cfg_val;
5214 if (channel_cfg != SPEAKER_CHANNELS_2_0 &&
5215 channel_cfg != SPEAKER_CHANNELS_4_0)
5216 val = 0;
5217 }
5218 }
5219
5220 /* for in effect, qualify with CrystalVoice */
5221 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
5222 /* if CrystalVoice if off, turn off in effects. */
5223 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
5224 val = 0;
5225
5226 /* Voice Focus applies to 2-ch Mic, Digital Mic */
5227 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
5228 val = 0;
5229
5230 /* If Voice Focus on SBZ, set to two channel. */
5231 if ((nid == VOICE_FOCUS) && ca0132_use_pci_mmio(spec)
5232 && (spec->cur_mic_type != REAR_LINE_IN)) {
5233 if (spec->effects_switch[CRYSTAL_VOICE -
5234 EFFECT_START_NID]) {
5235
5236 if (spec->effects_switch[VOICE_FOCUS -
5237 EFFECT_START_NID]) {
5238 tmp = FLOAT_TWO;
5239 val = 1;
5240 } else
5241 tmp = FLOAT_ONE;
5242
5243 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
5244 }
5245 }
5246 /*
5247 * For SBZ noise reduction, there's an extra command
5248 * to module ID 0x47. No clue why.
5249 */
5250 if ((nid == NOISE_REDUCTION) && ca0132_use_pci_mmio(spec)
5251 && (spec->cur_mic_type != REAR_LINE_IN)) {
5252 if (spec->effects_switch[CRYSTAL_VOICE -
5253 EFFECT_START_NID]) {
5254 if (spec->effects_switch[NOISE_REDUCTION -
5255 EFFECT_START_NID])
5256 tmp = FLOAT_ONE;
5257 else
5258 tmp = FLOAT_ZERO;
5259 } else
5260 tmp = FLOAT_ZERO;
5261
5262 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
5263 }
5264
5265 /* If rear line in disable effects. */
5266 if (ca0132_use_alt_functions(spec) &&
5267 spec->in_enum_val == REAR_LINE_IN)
5268 val = 0;
5269 }
5270
5271 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
5272 nid, val);
5273
5274 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
5275 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5276 ca0132_effects[idx].reqs[0], on);
5277
5278 if (err < 0)
5279 return 0; /* no changed */
5280
5281 return 1;
5282 }
5283
5284 /*
5285 * Turn on/off Playback Enhancements
5286 */
ca0132_pe_switch_set(struct hda_codec * codec)5287 static int ca0132_pe_switch_set(struct hda_codec *codec)
5288 {
5289 struct ca0132_spec *spec = codec->spec;
5290 hda_nid_t nid;
5291 int i, ret = 0;
5292
5293 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
5294 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
5295
5296 if (ca0132_use_alt_functions(spec))
5297 ca0132_alt_select_out(codec);
5298
5299 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
5300 nid = OUT_EFFECT_START_NID;
5301 /* PE affects all out effects */
5302 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
5303 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5304
5305 return ret;
5306 }
5307
5308 /* Check if Mic1 is streaming, if so, stop streaming */
stop_mic1(struct hda_codec * codec)5309 static int stop_mic1(struct hda_codec *codec)
5310 {
5311 struct ca0132_spec *spec = codec->spec;
5312 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
5313 AC_VERB_GET_CONV, 0);
5314 if (oldval != 0)
5315 snd_hda_codec_write(codec, spec->adcs[0], 0,
5316 AC_VERB_SET_CHANNEL_STREAMID,
5317 0);
5318 return oldval;
5319 }
5320
5321 /* Resume Mic1 streaming if it was stopped. */
resume_mic1(struct hda_codec * codec,unsigned int oldval)5322 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
5323 {
5324 struct ca0132_spec *spec = codec->spec;
5325 /* Restore the previous stream and channel */
5326 if (oldval != 0)
5327 snd_hda_codec_write(codec, spec->adcs[0], 0,
5328 AC_VERB_SET_CHANNEL_STREAMID,
5329 oldval);
5330 }
5331
5332 /*
5333 * Turn on/off CrystalVoice
5334 */
ca0132_cvoice_switch_set(struct hda_codec * codec)5335 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
5336 {
5337 struct ca0132_spec *spec = codec->spec;
5338 hda_nid_t nid;
5339 int i, ret = 0;
5340 unsigned int oldval;
5341
5342 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
5343 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
5344
5345 i = IN_EFFECT_START_NID - EFFECT_START_NID;
5346 nid = IN_EFFECT_START_NID;
5347 /* CrystalVoice affects all in effects */
5348 for (; nid < IN_EFFECT_END_NID; nid++, i++)
5349 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
5350
5351 /* including VoiceFX */
5352 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
5353
5354 /* set correct vipsource */
5355 oldval = stop_mic1(codec);
5356 if (ca0132_use_alt_functions(spec))
5357 ret |= ca0132_alt_set_vipsource(codec, 1);
5358 else
5359 ret |= ca0132_set_vipsource(codec, 1);
5360 resume_mic1(codec, oldval);
5361 return ret;
5362 }
5363
ca0132_mic_boost_set(struct hda_codec * codec,long val)5364 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
5365 {
5366 struct ca0132_spec *spec = codec->spec;
5367 int ret = 0;
5368
5369 if (val) /* on */
5370 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5371 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
5372 else /* off */
5373 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5374 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
5375
5376 return ret;
5377 }
5378
ca0132_alt_mic_boost_set(struct hda_codec * codec,long val)5379 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
5380 {
5381 struct ca0132_spec *spec = codec->spec;
5382 int ret = 0;
5383
5384 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
5385 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
5386 return ret;
5387 }
5388
ae5_headphone_gain_set(struct hda_codec * codec,long val)5389 static int ae5_headphone_gain_set(struct hda_codec *codec, long val)
5390 {
5391 unsigned int i;
5392
5393 for (i = 0; i < 4; i++)
5394 ca0113_mmio_command_set(codec, 0x48, 0x11 + i,
5395 ae5_headphone_gain_presets[val].vals[i]);
5396 return 0;
5397 }
5398
5399 /*
5400 * gpio pin 1 is a relay that switches on/off, apparently setting the headphone
5401 * amplifier to handle a 600 ohm load.
5402 */
zxr_headphone_gain_set(struct hda_codec * codec,long val)5403 static int zxr_headphone_gain_set(struct hda_codec *codec, long val)
5404 {
5405 ca0113_mmio_gpio_set(codec, 1, val);
5406
5407 return 0;
5408 }
5409
ca0132_vnode_switch_set(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5410 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
5411 struct snd_ctl_elem_value *ucontrol)
5412 {
5413 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5414 hda_nid_t nid = get_amp_nid(kcontrol);
5415 hda_nid_t shared_nid = 0;
5416 bool effective;
5417 int ret = 0;
5418 struct ca0132_spec *spec = codec->spec;
5419 int auto_jack;
5420
5421 if (nid == VNID_HP_SEL) {
5422 auto_jack =
5423 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5424 if (!auto_jack) {
5425 if (ca0132_use_alt_functions(spec))
5426 ca0132_alt_select_out(codec);
5427 else
5428 ca0132_select_out(codec);
5429 }
5430 return 1;
5431 }
5432
5433 if (nid == VNID_AMIC1_SEL) {
5434 auto_jack =
5435 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
5436 if (!auto_jack)
5437 ca0132_select_mic(codec);
5438 return 1;
5439 }
5440
5441 if (nid == VNID_HP_ASEL) {
5442 if (ca0132_use_alt_functions(spec))
5443 ca0132_alt_select_out(codec);
5444 else
5445 ca0132_select_out(codec);
5446 return 1;
5447 }
5448
5449 if (nid == VNID_AMIC1_ASEL) {
5450 ca0132_select_mic(codec);
5451 return 1;
5452 }
5453
5454 /* if effective conditions, then update hw immediately. */
5455 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5456 if (effective) {
5457 int dir = get_amp_direction(kcontrol);
5458 int ch = get_amp_channels(kcontrol);
5459 unsigned long pval;
5460
5461 mutex_lock(&codec->control_mutex);
5462 pval = kcontrol->private_value;
5463 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5464 0, dir);
5465 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
5466 kcontrol->private_value = pval;
5467 mutex_unlock(&codec->control_mutex);
5468 }
5469
5470 return ret;
5471 }
5472 /* End of control change helpers. */
5473
ca0132_alt_bass_redirection_xover_set(struct hda_codec * codec,long idx)5474 static void ca0132_alt_bass_redirection_xover_set(struct hda_codec *codec,
5475 long idx)
5476 {
5477 snd_hda_power_up(codec);
5478
5479 dspio_set_param(codec, 0x96, 0x20, SPEAKER_BASS_REDIRECT_XOVER_FREQ,
5480 &(float_xbass_xover_lookup[idx]), sizeof(unsigned int));
5481
5482 snd_hda_power_down(codec);
5483 }
5484
5485 /*
5486 * Below I've added controls to mess with the effect levels, I've only enabled
5487 * them on the Sound Blaster Z, but they would probably also work on the
5488 * Chromebook. I figured they were probably tuned specifically for it, and left
5489 * out for a reason.
5490 */
5491
5492 /* Sets DSP effect level from the sliders above the controls */
5493
ca0132_alt_slider_ctl_set(struct hda_codec * codec,hda_nid_t nid,const unsigned int * lookup,int idx)5494 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
5495 const unsigned int *lookup, int idx)
5496 {
5497 int i = 0;
5498 unsigned int y;
5499 /*
5500 * For X_BASS, req 2 is actually crossover freq instead of
5501 * effect level
5502 */
5503 if (nid == X_BASS)
5504 y = 2;
5505 else
5506 y = 1;
5507
5508 snd_hda_power_up(codec);
5509 if (nid == XBASS_XOVER) {
5510 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5511 if (ca0132_effects[i].nid == X_BASS)
5512 break;
5513
5514 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5515 ca0132_effects[i].reqs[1],
5516 &(lookup[idx - 1]), sizeof(unsigned int));
5517 } else {
5518 /* Find the actual effect structure */
5519 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
5520 if (nid == ca0132_effects[i].nid)
5521 break;
5522
5523 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
5524 ca0132_effects[i].reqs[y],
5525 &(lookup[idx]), sizeof(unsigned int));
5526 }
5527
5528 snd_hda_power_down(codec);
5529
5530 return 0;
5531 }
5532
ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5533 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
5534 struct snd_ctl_elem_value *ucontrol)
5535 {
5536 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5537 struct ca0132_spec *spec = codec->spec;
5538 long *valp = ucontrol->value.integer.value;
5539 hda_nid_t nid = get_amp_nid(kcontrol);
5540
5541 if (nid == BASS_REDIRECTION_XOVER)
5542 *valp = spec->bass_redirect_xover_freq;
5543 else
5544 *valp = spec->xbass_xover_freq;
5545
5546 return 0;
5547 }
5548
ca0132_alt_slider_ctl_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5549 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
5550 struct snd_ctl_elem_value *ucontrol)
5551 {
5552 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5553 struct ca0132_spec *spec = codec->spec;
5554 hda_nid_t nid = get_amp_nid(kcontrol);
5555 long *valp = ucontrol->value.integer.value;
5556 int idx = nid - OUT_EFFECT_START_NID;
5557
5558 *valp = spec->fx_ctl_val[idx];
5559 return 0;
5560 }
5561
5562 /*
5563 * The X-bass crossover starts at 10hz, so the min is 1. The
5564 * frequency is set in multiples of 10.
5565 */
ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5566 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
5567 struct snd_ctl_elem_info *uinfo)
5568 {
5569 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5570 uinfo->count = 1;
5571 uinfo->value.integer.min = 1;
5572 uinfo->value.integer.max = 100;
5573 uinfo->value.integer.step = 1;
5574
5575 return 0;
5576 }
5577
ca0132_alt_effect_slider_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5578 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
5579 struct snd_ctl_elem_info *uinfo)
5580 {
5581 int chs = get_amp_channels(kcontrol);
5582
5583 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
5584 uinfo->count = chs == 3 ? 2 : 1;
5585 uinfo->value.integer.min = 0;
5586 uinfo->value.integer.max = 100;
5587 uinfo->value.integer.step = 1;
5588
5589 return 0;
5590 }
5591
ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5592 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
5593 struct snd_ctl_elem_value *ucontrol)
5594 {
5595 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5596 struct ca0132_spec *spec = codec->spec;
5597 hda_nid_t nid = get_amp_nid(kcontrol);
5598 long *valp = ucontrol->value.integer.value;
5599 long *cur_val;
5600 int idx;
5601
5602 if (nid == BASS_REDIRECTION_XOVER)
5603 cur_val = &spec->bass_redirect_xover_freq;
5604 else
5605 cur_val = &spec->xbass_xover_freq;
5606
5607 /* any change? */
5608 if (*cur_val == *valp)
5609 return 0;
5610
5611 *cur_val = *valp;
5612
5613 idx = *valp;
5614 if (nid == BASS_REDIRECTION_XOVER)
5615 ca0132_alt_bass_redirection_xover_set(codec, *cur_val);
5616 else
5617 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
5618
5619 return 0;
5620 }
5621
ca0132_alt_effect_slider_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5622 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
5623 struct snd_ctl_elem_value *ucontrol)
5624 {
5625 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5626 struct ca0132_spec *spec = codec->spec;
5627 hda_nid_t nid = get_amp_nid(kcontrol);
5628 long *valp = ucontrol->value.integer.value;
5629 int idx;
5630
5631 idx = nid - EFFECT_START_NID;
5632 /* any change? */
5633 if (spec->fx_ctl_val[idx] == *valp)
5634 return 0;
5635
5636 spec->fx_ctl_val[idx] = *valp;
5637
5638 idx = *valp;
5639 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
5640
5641 return 0;
5642 }
5643
5644
5645 /*
5646 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
5647 * only has off or full 30 dB, and didn't like making a volume slider that has
5648 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
5649 */
5650 #define MIC_BOOST_NUM_OF_STEPS 4
5651 #define MIC_BOOST_ENUM_MAX_STRLEN 10
5652
ca0132_alt_mic_boost_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5653 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
5654 struct snd_ctl_elem_info *uinfo)
5655 {
5656 char *sfx = "dB";
5657 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5658
5659 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5660 uinfo->count = 1;
5661 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
5662 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
5663 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
5664 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
5665 strcpy(uinfo->value.enumerated.name, namestr);
5666 return 0;
5667 }
5668
ca0132_alt_mic_boost_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5669 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
5670 struct snd_ctl_elem_value *ucontrol)
5671 {
5672 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5673 struct ca0132_spec *spec = codec->spec;
5674
5675 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
5676 return 0;
5677 }
5678
ca0132_alt_mic_boost_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5679 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
5680 struct snd_ctl_elem_value *ucontrol)
5681 {
5682 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5683 struct ca0132_spec *spec = codec->spec;
5684 int sel = ucontrol->value.enumerated.item[0];
5685 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
5686
5687 if (sel >= items)
5688 return 0;
5689
5690 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
5691 sel);
5692
5693 spec->mic_boost_enum_val = sel;
5694
5695 if (spec->in_enum_val != REAR_LINE_IN)
5696 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
5697
5698 return 1;
5699 }
5700
5701 /*
5702 * Sound BlasterX AE-5 Headphone Gain Controls.
5703 */
5704 #define AE5_HEADPHONE_GAIN_MAX 3
ae5_headphone_gain_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5705 static int ae5_headphone_gain_info(struct snd_kcontrol *kcontrol,
5706 struct snd_ctl_elem_info *uinfo)
5707 {
5708 char *sfx = " Ohms)";
5709 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5710
5711 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5712 uinfo->count = 1;
5713 uinfo->value.enumerated.items = AE5_HEADPHONE_GAIN_MAX;
5714 if (uinfo->value.enumerated.item >= AE5_HEADPHONE_GAIN_MAX)
5715 uinfo->value.enumerated.item = AE5_HEADPHONE_GAIN_MAX - 1;
5716 sprintf(namestr, "%s %s",
5717 ae5_headphone_gain_presets[uinfo->value.enumerated.item].name,
5718 sfx);
5719 strcpy(uinfo->value.enumerated.name, namestr);
5720 return 0;
5721 }
5722
ae5_headphone_gain_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5723 static int ae5_headphone_gain_get(struct snd_kcontrol *kcontrol,
5724 struct snd_ctl_elem_value *ucontrol)
5725 {
5726 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5727 struct ca0132_spec *spec = codec->spec;
5728
5729 ucontrol->value.enumerated.item[0] = spec->ae5_headphone_gain_val;
5730 return 0;
5731 }
5732
ae5_headphone_gain_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5733 static int ae5_headphone_gain_put(struct snd_kcontrol *kcontrol,
5734 struct snd_ctl_elem_value *ucontrol)
5735 {
5736 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5737 struct ca0132_spec *spec = codec->spec;
5738 int sel = ucontrol->value.enumerated.item[0];
5739 unsigned int items = AE5_HEADPHONE_GAIN_MAX;
5740
5741 if (sel >= items)
5742 return 0;
5743
5744 codec_dbg(codec, "ae5_headphone_gain: boost=%d\n",
5745 sel);
5746
5747 spec->ae5_headphone_gain_val = sel;
5748
5749 if (spec->out_enum_val == HEADPHONE_OUT)
5750 ae5_headphone_gain_set(codec, spec->ae5_headphone_gain_val);
5751
5752 return 1;
5753 }
5754
5755 /*
5756 * Sound BlasterX AE-5 sound filter enumerated control.
5757 */
5758 #define AE5_SOUND_FILTER_MAX 3
5759
ae5_sound_filter_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5760 static int ae5_sound_filter_info(struct snd_kcontrol *kcontrol,
5761 struct snd_ctl_elem_info *uinfo)
5762 {
5763 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5764
5765 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5766 uinfo->count = 1;
5767 uinfo->value.enumerated.items = AE5_SOUND_FILTER_MAX;
5768 if (uinfo->value.enumerated.item >= AE5_SOUND_FILTER_MAX)
5769 uinfo->value.enumerated.item = AE5_SOUND_FILTER_MAX - 1;
5770 sprintf(namestr, "%s",
5771 ae5_filter_presets[uinfo->value.enumerated.item].name);
5772 strcpy(uinfo->value.enumerated.name, namestr);
5773 return 0;
5774 }
5775
ae5_sound_filter_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5776 static int ae5_sound_filter_get(struct snd_kcontrol *kcontrol,
5777 struct snd_ctl_elem_value *ucontrol)
5778 {
5779 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5780 struct ca0132_spec *spec = codec->spec;
5781
5782 ucontrol->value.enumerated.item[0] = spec->ae5_filter_val;
5783 return 0;
5784 }
5785
ae5_sound_filter_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5786 static int ae5_sound_filter_put(struct snd_kcontrol *kcontrol,
5787 struct snd_ctl_elem_value *ucontrol)
5788 {
5789 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5790 struct ca0132_spec *spec = codec->spec;
5791 int sel = ucontrol->value.enumerated.item[0];
5792 unsigned int items = AE5_SOUND_FILTER_MAX;
5793
5794 if (sel >= items)
5795 return 0;
5796
5797 codec_dbg(codec, "ae5_sound_filter: %s\n",
5798 ae5_filter_presets[sel].name);
5799
5800 spec->ae5_filter_val = sel;
5801
5802 ca0113_mmio_command_set_type2(codec, 0x48, 0x07,
5803 ae5_filter_presets[sel].val);
5804
5805 return 1;
5806 }
5807
5808 /*
5809 * Input Select Control for alternative ca0132 codecs. This exists because
5810 * front microphone has no auto-detect, and we need a way to set the rear
5811 * as line-in
5812 */
ca0132_alt_input_source_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5813 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
5814 struct snd_ctl_elem_info *uinfo)
5815 {
5816 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5817 uinfo->count = 1;
5818 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
5819 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
5820 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
5821 strcpy(uinfo->value.enumerated.name,
5822 in_src_str[uinfo->value.enumerated.item]);
5823 return 0;
5824 }
5825
ca0132_alt_input_source_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5826 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
5827 struct snd_ctl_elem_value *ucontrol)
5828 {
5829 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5830 struct ca0132_spec *spec = codec->spec;
5831
5832 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
5833 return 0;
5834 }
5835
ca0132_alt_input_source_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5836 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
5837 struct snd_ctl_elem_value *ucontrol)
5838 {
5839 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5840 struct ca0132_spec *spec = codec->spec;
5841 int sel = ucontrol->value.enumerated.item[0];
5842 unsigned int items = IN_SRC_NUM_OF_INPUTS;
5843
5844 /*
5845 * The AE-7 has no front microphone, so limit items to 2: rear mic and
5846 * line-in.
5847 */
5848 if (ca0132_quirk(spec) == QUIRK_AE7)
5849 items = 2;
5850
5851 if (sel >= items)
5852 return 0;
5853
5854 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
5855 sel, in_src_str[sel]);
5856
5857 spec->in_enum_val = sel;
5858
5859 ca0132_alt_select_in(codec);
5860
5861 return 1;
5862 }
5863
5864 /* Sound Blaster Z Output Select Control */
ca0132_alt_output_select_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5865 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5866 struct snd_ctl_elem_info *uinfo)
5867 {
5868 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5869 uinfo->count = 1;
5870 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5871 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5872 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5873 strcpy(uinfo->value.enumerated.name,
5874 out_type_str[uinfo->value.enumerated.item]);
5875 return 0;
5876 }
5877
ca0132_alt_output_select_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5878 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5879 struct snd_ctl_elem_value *ucontrol)
5880 {
5881 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5882 struct ca0132_spec *spec = codec->spec;
5883
5884 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5885 return 0;
5886 }
5887
ca0132_alt_output_select_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5888 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5889 struct snd_ctl_elem_value *ucontrol)
5890 {
5891 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5892 struct ca0132_spec *spec = codec->spec;
5893 int sel = ucontrol->value.enumerated.item[0];
5894 unsigned int items = NUM_OF_OUTPUTS;
5895 unsigned int auto_jack;
5896
5897 if (sel >= items)
5898 return 0;
5899
5900 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5901 sel, out_type_str[sel]);
5902
5903 spec->out_enum_val = sel;
5904
5905 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5906
5907 if (!auto_jack)
5908 ca0132_alt_select_out(codec);
5909
5910 return 1;
5911 }
5912
5913 /* Select surround output type: 2.1, 4.0, 4.1, or 5.1. */
ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5914 static int ca0132_alt_speaker_channel_cfg_get_info(struct snd_kcontrol *kcontrol,
5915 struct snd_ctl_elem_info *uinfo)
5916 {
5917 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
5918
5919 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5920 uinfo->count = 1;
5921 uinfo->value.enumerated.items = items;
5922 if (uinfo->value.enumerated.item >= items)
5923 uinfo->value.enumerated.item = items - 1;
5924 strcpy(uinfo->value.enumerated.name,
5925 speaker_channel_cfgs[uinfo->value.enumerated.item].name);
5926 return 0;
5927 }
5928
ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5929 static int ca0132_alt_speaker_channel_cfg_get(struct snd_kcontrol *kcontrol,
5930 struct snd_ctl_elem_value *ucontrol)
5931 {
5932 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5933 struct ca0132_spec *spec = codec->spec;
5934
5935 ucontrol->value.enumerated.item[0] = spec->channel_cfg_val;
5936 return 0;
5937 }
5938
ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5939 static int ca0132_alt_speaker_channel_cfg_put(struct snd_kcontrol *kcontrol,
5940 struct snd_ctl_elem_value *ucontrol)
5941 {
5942 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5943 struct ca0132_spec *spec = codec->spec;
5944 int sel = ucontrol->value.enumerated.item[0];
5945 unsigned int items = SPEAKER_CHANNEL_CFG_COUNT;
5946
5947 if (sel >= items)
5948 return 0;
5949
5950 codec_dbg(codec, "ca0132_alt_speaker_channels: sel=%d, channels=%s\n",
5951 sel, speaker_channel_cfgs[sel].name);
5952
5953 spec->channel_cfg_val = sel;
5954
5955 if (spec->out_enum_val == SPEAKER_OUT)
5956 ca0132_alt_select_out(codec);
5957
5958 return 1;
5959 }
5960
5961 /*
5962 * Smart Volume output setting control. Three different settings, Normal,
5963 * which takes the value from the smart volume slider. The two others, loud
5964 * and night, disregard the slider value and have uneditable values.
5965 */
5966 #define NUM_OF_SVM_SETTINGS 3
5967 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5968
ca0132_alt_svm_setting_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)5969 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5970 struct snd_ctl_elem_info *uinfo)
5971 {
5972 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5973 uinfo->count = 1;
5974 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5975 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5976 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5977 strcpy(uinfo->value.enumerated.name,
5978 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5979 return 0;
5980 }
5981
ca0132_alt_svm_setting_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5982 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5983 struct snd_ctl_elem_value *ucontrol)
5984 {
5985 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5986 struct ca0132_spec *spec = codec->spec;
5987
5988 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5989 return 0;
5990 }
5991
ca0132_alt_svm_setting_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)5992 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5993 struct snd_ctl_elem_value *ucontrol)
5994 {
5995 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5996 struct ca0132_spec *spec = codec->spec;
5997 int sel = ucontrol->value.enumerated.item[0];
5998 unsigned int items = NUM_OF_SVM_SETTINGS;
5999 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
6000 unsigned int tmp;
6001
6002 if (sel >= items)
6003 return 0;
6004
6005 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
6006 sel, out_svm_set_enum_str[sel]);
6007
6008 spec->smart_volume_setting = sel;
6009
6010 switch (sel) {
6011 case 0:
6012 tmp = FLOAT_ZERO;
6013 break;
6014 case 1:
6015 tmp = FLOAT_ONE;
6016 break;
6017 case 2:
6018 tmp = FLOAT_TWO;
6019 break;
6020 default:
6021 tmp = FLOAT_ZERO;
6022 break;
6023 }
6024 /* Req 2 is the Smart Volume Setting req. */
6025 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6026 ca0132_effects[idx].reqs[2], tmp);
6027 return 1;
6028 }
6029
6030 /* Sound Blaster Z EQ preset controls */
ca0132_alt_eq_preset_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6031 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
6032 struct snd_ctl_elem_info *uinfo)
6033 {
6034 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6035
6036 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6037 uinfo->count = 1;
6038 uinfo->value.enumerated.items = items;
6039 if (uinfo->value.enumerated.item >= items)
6040 uinfo->value.enumerated.item = items - 1;
6041 strcpy(uinfo->value.enumerated.name,
6042 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
6043 return 0;
6044 }
6045
ca0132_alt_eq_preset_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6046 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
6047 struct snd_ctl_elem_value *ucontrol)
6048 {
6049 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6050 struct ca0132_spec *spec = codec->spec;
6051
6052 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
6053 return 0;
6054 }
6055
ca0132_alt_eq_preset_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6056 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
6057 struct snd_ctl_elem_value *ucontrol)
6058 {
6059 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6060 struct ca0132_spec *spec = codec->spec;
6061 int i, err = 0;
6062 int sel = ucontrol->value.enumerated.item[0];
6063 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
6064
6065 if (sel >= items)
6066 return 0;
6067
6068 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
6069 ca0132_alt_eq_presets[sel].name);
6070 /*
6071 * Idx 0 is default.
6072 * Default needs to qualify with CrystalVoice state.
6073 */
6074 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
6075 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
6076 ca0132_alt_eq_enum.reqs[i],
6077 ca0132_alt_eq_presets[sel].vals[i]);
6078 if (err < 0)
6079 break;
6080 }
6081
6082 if (err >= 0)
6083 spec->eq_preset_val = sel;
6084
6085 return 1;
6086 }
6087
ca0132_voicefx_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6088 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
6089 struct snd_ctl_elem_info *uinfo)
6090 {
6091 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
6092
6093 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
6094 uinfo->count = 1;
6095 uinfo->value.enumerated.items = items;
6096 if (uinfo->value.enumerated.item >= items)
6097 uinfo->value.enumerated.item = items - 1;
6098 strcpy(uinfo->value.enumerated.name,
6099 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
6100 return 0;
6101 }
6102
ca0132_voicefx_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6103 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
6104 struct snd_ctl_elem_value *ucontrol)
6105 {
6106 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6107 struct ca0132_spec *spec = codec->spec;
6108
6109 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
6110 return 0;
6111 }
6112
ca0132_voicefx_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6113 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
6114 struct snd_ctl_elem_value *ucontrol)
6115 {
6116 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6117 struct ca0132_spec *spec = codec->spec;
6118 int i, err = 0;
6119 int sel = ucontrol->value.enumerated.item[0];
6120
6121 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
6122 return 0;
6123
6124 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
6125 sel, ca0132_voicefx_presets[sel].name);
6126
6127 /*
6128 * Idx 0 is default.
6129 * Default needs to qualify with CrystalVoice state.
6130 */
6131 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
6132 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
6133 ca0132_voicefx.reqs[i],
6134 ca0132_voicefx_presets[sel].vals[i]);
6135 if (err < 0)
6136 break;
6137 }
6138
6139 if (err >= 0) {
6140 spec->voicefx_val = sel;
6141 /* enable voice fx */
6142 ca0132_voicefx_set(codec, (sel ? 1 : 0));
6143 }
6144
6145 return 1;
6146 }
6147
ca0132_switch_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6148 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
6149 struct snd_ctl_elem_value *ucontrol)
6150 {
6151 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6152 struct ca0132_spec *spec = codec->spec;
6153 hda_nid_t nid = get_amp_nid(kcontrol);
6154 int ch = get_amp_channels(kcontrol);
6155 long *valp = ucontrol->value.integer.value;
6156
6157 /* vnode */
6158 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6159 if (ch & 1) {
6160 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
6161 valp++;
6162 }
6163 if (ch & 2) {
6164 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
6165 valp++;
6166 }
6167 return 0;
6168 }
6169
6170 /* effects, include PE and CrystalVoice */
6171 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
6172 *valp = spec->effects_switch[nid - EFFECT_START_NID];
6173 return 0;
6174 }
6175
6176 /* mic boost */
6177 if (nid == spec->input_pins[0]) {
6178 *valp = spec->cur_mic_boost;
6179 return 0;
6180 }
6181
6182 if (nid == ZXR_HEADPHONE_GAIN) {
6183 *valp = spec->zxr_gain_set;
6184 return 0;
6185 }
6186
6187 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6188 *valp = spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT];
6189 return 0;
6190 }
6191
6192 if (nid == BASS_REDIRECTION) {
6193 *valp = spec->bass_redirection_val;
6194 return 0;
6195 }
6196
6197 return 0;
6198 }
6199
ca0132_switch_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6200 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
6201 struct snd_ctl_elem_value *ucontrol)
6202 {
6203 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6204 struct ca0132_spec *spec = codec->spec;
6205 hda_nid_t nid = get_amp_nid(kcontrol);
6206 int ch = get_amp_channels(kcontrol);
6207 long *valp = ucontrol->value.integer.value;
6208 int changed = 1;
6209
6210 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
6211 nid, *valp);
6212
6213 snd_hda_power_up(codec);
6214 /* vnode */
6215 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
6216 if (ch & 1) {
6217 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
6218 valp++;
6219 }
6220 if (ch & 2) {
6221 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
6222 valp++;
6223 }
6224 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
6225 goto exit;
6226 }
6227
6228 /* PE */
6229 if (nid == PLAY_ENHANCEMENT) {
6230 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6231 changed = ca0132_pe_switch_set(codec);
6232 goto exit;
6233 }
6234
6235 /* CrystalVoice */
6236 if (nid == CRYSTAL_VOICE) {
6237 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6238 changed = ca0132_cvoice_switch_set(codec);
6239 goto exit;
6240 }
6241
6242 /* out and in effects */
6243 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
6244 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
6245 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
6246 changed = ca0132_effects_set(codec, nid, *valp);
6247 goto exit;
6248 }
6249
6250 /* mic boost */
6251 if (nid == spec->input_pins[0]) {
6252 spec->cur_mic_boost = *valp;
6253 if (ca0132_use_alt_functions(spec)) {
6254 if (spec->in_enum_val != REAR_LINE_IN)
6255 changed = ca0132_mic_boost_set(codec, *valp);
6256 } else {
6257 /* Mic boost does not apply to Digital Mic */
6258 if (spec->cur_mic_type != DIGITAL_MIC)
6259 changed = ca0132_mic_boost_set(codec, *valp);
6260 }
6261
6262 goto exit;
6263 }
6264
6265 if (nid == ZXR_HEADPHONE_GAIN) {
6266 spec->zxr_gain_set = *valp;
6267 if (spec->cur_out_type == HEADPHONE_OUT)
6268 changed = zxr_headphone_gain_set(codec, *valp);
6269 else
6270 changed = 0;
6271
6272 goto exit;
6273 }
6274
6275 if (nid == SPEAKER_FULL_RANGE_FRONT || nid == SPEAKER_FULL_RANGE_REAR) {
6276 spec->speaker_range_val[nid - SPEAKER_FULL_RANGE_FRONT] = *valp;
6277 if (spec->cur_out_type == SPEAKER_OUT)
6278 ca0132_alt_set_full_range_speaker(codec);
6279
6280 changed = 0;
6281 }
6282
6283 if (nid == BASS_REDIRECTION) {
6284 spec->bass_redirection_val = *valp;
6285 if (spec->cur_out_type == SPEAKER_OUT)
6286 ca0132_alt_surround_set_bass_redirection(codec, *valp);
6287
6288 changed = 0;
6289 }
6290
6291 exit:
6292 snd_hda_power_down(codec);
6293 return changed;
6294 }
6295
6296 /*
6297 * Volume related
6298 */
6299 /*
6300 * Sets the internal DSP decibel level to match the DAC for output, and the
6301 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
6302 * all alternative codecs set DSP playback volume.
6303 */
ca0132_alt_dsp_volume_put(struct hda_codec * codec,hda_nid_t nid)6304 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
6305 {
6306 struct ca0132_spec *spec = codec->spec;
6307 unsigned int dsp_dir;
6308 unsigned int lookup_val;
6309
6310 if (nid == VNID_SPK)
6311 dsp_dir = DSP_VOL_OUT;
6312 else
6313 dsp_dir = DSP_VOL_IN;
6314
6315 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
6316
6317 dspio_set_uint_param(codec,
6318 ca0132_alt_vol_ctls[dsp_dir].mid,
6319 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
6320 float_vol_db_lookup[lookup_val]);
6321
6322 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
6323
6324 dspio_set_uint_param(codec,
6325 ca0132_alt_vol_ctls[dsp_dir].mid,
6326 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
6327 float_vol_db_lookup[lookup_val]);
6328
6329 dspio_set_uint_param(codec,
6330 ca0132_alt_vol_ctls[dsp_dir].mid,
6331 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
6332 }
6333
ca0132_volume_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)6334 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
6335 struct snd_ctl_elem_info *uinfo)
6336 {
6337 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6338 struct ca0132_spec *spec = codec->spec;
6339 hda_nid_t nid = get_amp_nid(kcontrol);
6340 int ch = get_amp_channels(kcontrol);
6341 int dir = get_amp_direction(kcontrol);
6342 unsigned long pval;
6343 int err;
6344
6345 switch (nid) {
6346 case VNID_SPK:
6347 /* follow shared_out info */
6348 nid = spec->shared_out_nid;
6349 mutex_lock(&codec->control_mutex);
6350 pval = kcontrol->private_value;
6351 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6352 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6353 kcontrol->private_value = pval;
6354 mutex_unlock(&codec->control_mutex);
6355 break;
6356 case VNID_MIC:
6357 /* follow shared_mic info */
6358 nid = spec->shared_mic_nid;
6359 mutex_lock(&codec->control_mutex);
6360 pval = kcontrol->private_value;
6361 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6362 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6363 kcontrol->private_value = pval;
6364 mutex_unlock(&codec->control_mutex);
6365 break;
6366 default:
6367 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
6368 }
6369 return err;
6370 }
6371
ca0132_volume_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6372 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
6373 struct snd_ctl_elem_value *ucontrol)
6374 {
6375 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6376 struct ca0132_spec *spec = codec->spec;
6377 hda_nid_t nid = get_amp_nid(kcontrol);
6378 int ch = get_amp_channels(kcontrol);
6379 long *valp = ucontrol->value.integer.value;
6380
6381 /* store the left and right volume */
6382 if (ch & 1) {
6383 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
6384 valp++;
6385 }
6386 if (ch & 2) {
6387 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
6388 valp++;
6389 }
6390 return 0;
6391 }
6392
ca0132_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6393 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
6394 struct snd_ctl_elem_value *ucontrol)
6395 {
6396 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6397 struct ca0132_spec *spec = codec->spec;
6398 hda_nid_t nid = get_amp_nid(kcontrol);
6399 int ch = get_amp_channels(kcontrol);
6400 long *valp = ucontrol->value.integer.value;
6401 hda_nid_t shared_nid = 0;
6402 bool effective;
6403 int changed = 1;
6404
6405 /* store the left and right volume */
6406 if (ch & 1) {
6407 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
6408 valp++;
6409 }
6410 if (ch & 2) {
6411 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
6412 valp++;
6413 }
6414
6415 /* if effective conditions, then update hw immediately. */
6416 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
6417 if (effective) {
6418 int dir = get_amp_direction(kcontrol);
6419 unsigned long pval;
6420
6421 snd_hda_power_up(codec);
6422 mutex_lock(&codec->control_mutex);
6423 pval = kcontrol->private_value;
6424 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
6425 0, dir);
6426 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6427 kcontrol->private_value = pval;
6428 mutex_unlock(&codec->control_mutex);
6429 snd_hda_power_down(codec);
6430 }
6431
6432 return changed;
6433 }
6434
6435 /*
6436 * This function is the same as the one above, because using an if statement
6437 * inside of the above volume control for the DSP volume would cause too much
6438 * lag. This is a lot more smooth.
6439 */
ca0132_alt_volume_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)6440 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
6441 struct snd_ctl_elem_value *ucontrol)
6442 {
6443 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6444 struct ca0132_spec *spec = codec->spec;
6445 hda_nid_t nid = get_amp_nid(kcontrol);
6446 int ch = get_amp_channels(kcontrol);
6447 long *valp = ucontrol->value.integer.value;
6448 hda_nid_t vnid = 0;
6449 int changed;
6450
6451 switch (nid) {
6452 case 0x02:
6453 vnid = VNID_SPK;
6454 break;
6455 case 0x07:
6456 vnid = VNID_MIC;
6457 break;
6458 }
6459
6460 /* store the left and right volume */
6461 if (ch & 1) {
6462 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
6463 valp++;
6464 }
6465 if (ch & 2) {
6466 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
6467 valp++;
6468 }
6469
6470 snd_hda_power_up(codec);
6471 ca0132_alt_dsp_volume_put(codec, vnid);
6472 mutex_lock(&codec->control_mutex);
6473 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
6474 mutex_unlock(&codec->control_mutex);
6475 snd_hda_power_down(codec);
6476
6477 return changed;
6478 }
6479
ca0132_volume_tlv(struct snd_kcontrol * kcontrol,int op_flag,unsigned int size,unsigned int __user * tlv)6480 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
6481 unsigned int size, unsigned int __user *tlv)
6482 {
6483 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
6484 struct ca0132_spec *spec = codec->spec;
6485 hda_nid_t nid = get_amp_nid(kcontrol);
6486 int ch = get_amp_channels(kcontrol);
6487 int dir = get_amp_direction(kcontrol);
6488 unsigned long pval;
6489 int err;
6490
6491 switch (nid) {
6492 case VNID_SPK:
6493 /* follow shared_out tlv */
6494 nid = spec->shared_out_nid;
6495 mutex_lock(&codec->control_mutex);
6496 pval = kcontrol->private_value;
6497 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6498 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6499 kcontrol->private_value = pval;
6500 mutex_unlock(&codec->control_mutex);
6501 break;
6502 case VNID_MIC:
6503 /* follow shared_mic tlv */
6504 nid = spec->shared_mic_nid;
6505 mutex_lock(&codec->control_mutex);
6506 pval = kcontrol->private_value;
6507 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
6508 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6509 kcontrol->private_value = pval;
6510 mutex_unlock(&codec->control_mutex);
6511 break;
6512 default:
6513 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
6514 }
6515 return err;
6516 }
6517
6518 /* Add volume slider control for effect level */
ca0132_alt_add_effect_slider(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6519 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
6520 const char *pfx, int dir)
6521 {
6522 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6523 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6524 struct snd_kcontrol_new knew =
6525 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
6526
6527 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
6528
6529 knew.tlv.c = NULL;
6530
6531 switch (nid) {
6532 case XBASS_XOVER:
6533 knew.info = ca0132_alt_xbass_xover_slider_info;
6534 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6535 knew.put = ca0132_alt_xbass_xover_slider_put;
6536 break;
6537 default:
6538 knew.info = ca0132_alt_effect_slider_info;
6539 knew.get = ca0132_alt_slider_ctl_get;
6540 knew.put = ca0132_alt_effect_slider_put;
6541 knew.private_value =
6542 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
6543 break;
6544 }
6545
6546 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6547 }
6548
6549 /*
6550 * Added FX: prefix for the alternative codecs, because otherwise the surround
6551 * effect would conflict with the Surround sound volume control. Also seems more
6552 * clear as to what the switches do. Left alone for others.
6553 */
add_fx_switch(struct hda_codec * codec,hda_nid_t nid,const char * pfx,int dir)6554 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
6555 const char *pfx, int dir)
6556 {
6557 struct ca0132_spec *spec = codec->spec;
6558 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
6559 int type = dir ? HDA_INPUT : HDA_OUTPUT;
6560 struct snd_kcontrol_new knew =
6561 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
6562 /* If using alt_controls, add FX: prefix. But, don't add FX:
6563 * prefix to OutFX or InFX enable controls.
6564 */
6565 if (ca0132_use_alt_controls(spec) && (nid <= IN_EFFECT_END_NID))
6566 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
6567 else
6568 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
6569
6570 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
6571 }
6572
add_voicefx(struct hda_codec * codec)6573 static int add_voicefx(struct hda_codec *codec)
6574 {
6575 struct snd_kcontrol_new knew =
6576 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
6577 VOICEFX, 1, 0, HDA_INPUT);
6578 knew.info = ca0132_voicefx_info;
6579 knew.get = ca0132_voicefx_get;
6580 knew.put = ca0132_voicefx_put;
6581 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
6582 }
6583
6584 /* Create the EQ Preset control */
add_ca0132_alt_eq_presets(struct hda_codec * codec)6585 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
6586 {
6587 struct snd_kcontrol_new knew =
6588 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
6589 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
6590 knew.info = ca0132_alt_eq_preset_info;
6591 knew.get = ca0132_alt_eq_preset_get;
6592 knew.put = ca0132_alt_eq_preset_put;
6593 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
6594 snd_ctl_new1(&knew, codec));
6595 }
6596
6597 /*
6598 * Add enumerated control for the three different settings of the smart volume
6599 * output effect. Normal just uses the slider value, and loud and night are
6600 * their own things that ignore that value.
6601 */
ca0132_alt_add_svm_enum(struct hda_codec * codec)6602 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
6603 {
6604 struct snd_kcontrol_new knew =
6605 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
6606 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
6607 knew.info = ca0132_alt_svm_setting_info;
6608 knew.get = ca0132_alt_svm_setting_get;
6609 knew.put = ca0132_alt_svm_setting_put;
6610 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
6611 snd_ctl_new1(&knew, codec));
6612
6613 }
6614
6615 /*
6616 * Create an Output Select enumerated control for codecs with surround
6617 * out capabilities.
6618 */
ca0132_alt_add_output_enum(struct hda_codec * codec)6619 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
6620 {
6621 struct snd_kcontrol_new knew =
6622 HDA_CODEC_MUTE_MONO("Output Select",
6623 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
6624 knew.info = ca0132_alt_output_select_get_info;
6625 knew.get = ca0132_alt_output_select_get;
6626 knew.put = ca0132_alt_output_select_put;
6627 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
6628 snd_ctl_new1(&knew, codec));
6629 }
6630
6631 /*
6632 * Add a control for selecting channel count on speaker output. Setting this
6633 * allows the DSP to do bass redirection and channel upmixing on surround
6634 * configurations.
6635 */
ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec * codec)6636 static int ca0132_alt_add_speaker_channel_cfg_enum(struct hda_codec *codec)
6637 {
6638 struct snd_kcontrol_new knew =
6639 HDA_CODEC_MUTE_MONO("Surround Channel Config",
6640 SPEAKER_CHANNEL_CFG_ENUM, 1, 0, HDA_OUTPUT);
6641 knew.info = ca0132_alt_speaker_channel_cfg_get_info;
6642 knew.get = ca0132_alt_speaker_channel_cfg_get;
6643 knew.put = ca0132_alt_speaker_channel_cfg_put;
6644 return snd_hda_ctl_add(codec, SPEAKER_CHANNEL_CFG_ENUM,
6645 snd_ctl_new1(&knew, codec));
6646 }
6647
6648 /*
6649 * Full range front stereo and rear surround switches. When these are set to
6650 * full range, the lower frequencies from these channels are no longer
6651 * redirected to the LFE channel.
6652 */
ca0132_alt_add_front_full_range_switch(struct hda_codec * codec)6653 static int ca0132_alt_add_front_full_range_switch(struct hda_codec *codec)
6654 {
6655 struct snd_kcontrol_new knew =
6656 CA0132_CODEC_MUTE_MONO("Full-Range Front Speakers",
6657 SPEAKER_FULL_RANGE_FRONT, 1, HDA_OUTPUT);
6658
6659 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_FRONT,
6660 snd_ctl_new1(&knew, codec));
6661 }
6662
ca0132_alt_add_rear_full_range_switch(struct hda_codec * codec)6663 static int ca0132_alt_add_rear_full_range_switch(struct hda_codec *codec)
6664 {
6665 struct snd_kcontrol_new knew =
6666 CA0132_CODEC_MUTE_MONO("Full-Range Rear Speakers",
6667 SPEAKER_FULL_RANGE_REAR, 1, HDA_OUTPUT);
6668
6669 return snd_hda_ctl_add(codec, SPEAKER_FULL_RANGE_REAR,
6670 snd_ctl_new1(&knew, codec));
6671 }
6672
6673 /*
6674 * Bass redirection redirects audio below the crossover frequency to the LFE
6675 * channel on speakers that are set as not being full-range. On configurations
6676 * without an LFE channel, it does nothing. Bass redirection seems to be the
6677 * replacement for X-Bass on configurations with an LFE channel.
6678 */
ca0132_alt_add_bass_redirection_crossover(struct hda_codec * codec)6679 static int ca0132_alt_add_bass_redirection_crossover(struct hda_codec *codec)
6680 {
6681 const char *namestr = "Bass Redirection Crossover";
6682 struct snd_kcontrol_new knew =
6683 HDA_CODEC_VOLUME_MONO(namestr, BASS_REDIRECTION_XOVER, 1, 0,
6684 HDA_OUTPUT);
6685
6686 knew.tlv.c = NULL;
6687 knew.info = ca0132_alt_xbass_xover_slider_info;
6688 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
6689 knew.put = ca0132_alt_xbass_xover_slider_put;
6690
6691 return snd_hda_ctl_add(codec, BASS_REDIRECTION_XOVER,
6692 snd_ctl_new1(&knew, codec));
6693 }
6694
ca0132_alt_add_bass_redirection_switch(struct hda_codec * codec)6695 static int ca0132_alt_add_bass_redirection_switch(struct hda_codec *codec)
6696 {
6697 const char *namestr = "Bass Redirection";
6698 struct snd_kcontrol_new knew =
6699 CA0132_CODEC_MUTE_MONO(namestr, BASS_REDIRECTION, 1,
6700 HDA_OUTPUT);
6701
6702 return snd_hda_ctl_add(codec, BASS_REDIRECTION,
6703 snd_ctl_new1(&knew, codec));
6704 }
6705
6706 /*
6707 * Create an Input Source enumerated control for the alternate ca0132 codecs
6708 * because the front microphone has no auto-detect, and Line-in has to be set
6709 * somehow.
6710 */
ca0132_alt_add_input_enum(struct hda_codec * codec)6711 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
6712 {
6713 struct snd_kcontrol_new knew =
6714 HDA_CODEC_MUTE_MONO("Input Source",
6715 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
6716 knew.info = ca0132_alt_input_source_info;
6717 knew.get = ca0132_alt_input_source_get;
6718 knew.put = ca0132_alt_input_source_put;
6719 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
6720 snd_ctl_new1(&knew, codec));
6721 }
6722
6723 /*
6724 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
6725 * more control than the original mic boost, which is either full 30dB or off.
6726 */
ca0132_alt_add_mic_boost_enum(struct hda_codec * codec)6727 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
6728 {
6729 struct snd_kcontrol_new knew =
6730 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
6731 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
6732 knew.info = ca0132_alt_mic_boost_info;
6733 knew.get = ca0132_alt_mic_boost_get;
6734 knew.put = ca0132_alt_mic_boost_put;
6735 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
6736 snd_ctl_new1(&knew, codec));
6737
6738 }
6739
6740 /*
6741 * Add headphone gain enumerated control for the AE-5. This switches between
6742 * three modes, low, medium, and high. When non-headphone outputs are selected,
6743 * it is automatically set to high. This is the same behavior as Windows.
6744 */
ae5_add_headphone_gain_enum(struct hda_codec * codec)6745 static int ae5_add_headphone_gain_enum(struct hda_codec *codec)
6746 {
6747 struct snd_kcontrol_new knew =
6748 HDA_CODEC_MUTE_MONO("AE-5: Headphone Gain",
6749 AE5_HEADPHONE_GAIN_ENUM, 1, 0, HDA_OUTPUT);
6750 knew.info = ae5_headphone_gain_info;
6751 knew.get = ae5_headphone_gain_get;
6752 knew.put = ae5_headphone_gain_put;
6753 return snd_hda_ctl_add(codec, AE5_HEADPHONE_GAIN_ENUM,
6754 snd_ctl_new1(&knew, codec));
6755 }
6756
6757 /*
6758 * Add sound filter enumerated control for the AE-5. This adds three different
6759 * settings: Slow Roll Off, Minimum Phase, and Fast Roll Off. From what I've
6760 * read into it, it changes the DAC's interpolation filter.
6761 */
ae5_add_sound_filter_enum(struct hda_codec * codec)6762 static int ae5_add_sound_filter_enum(struct hda_codec *codec)
6763 {
6764 struct snd_kcontrol_new knew =
6765 HDA_CODEC_MUTE_MONO("AE-5: Sound Filter",
6766 AE5_SOUND_FILTER_ENUM, 1, 0, HDA_OUTPUT);
6767 knew.info = ae5_sound_filter_info;
6768 knew.get = ae5_sound_filter_get;
6769 knew.put = ae5_sound_filter_put;
6770 return snd_hda_ctl_add(codec, AE5_SOUND_FILTER_ENUM,
6771 snd_ctl_new1(&knew, codec));
6772 }
6773
zxr_add_headphone_gain_switch(struct hda_codec * codec)6774 static int zxr_add_headphone_gain_switch(struct hda_codec *codec)
6775 {
6776 struct snd_kcontrol_new knew =
6777 CA0132_CODEC_MUTE_MONO("ZxR: 600 Ohm Gain",
6778 ZXR_HEADPHONE_GAIN, 1, HDA_OUTPUT);
6779
6780 return snd_hda_ctl_add(codec, ZXR_HEADPHONE_GAIN,
6781 snd_ctl_new1(&knew, codec));
6782 }
6783
6784 /*
6785 * Need to create follower controls for the alternate codecs that have surround
6786 * capabilities.
6787 */
6788 static const char * const ca0132_alt_follower_pfxs[] = {
6789 "Front", "Surround", "Center", "LFE", NULL,
6790 };
6791
6792 /*
6793 * Also need special channel map, because the default one is incorrect.
6794 * I think this has to do with the pin for rear surround being 0x11,
6795 * and the center/lfe being 0x10. Usually the pin order is the opposite.
6796 */
6797 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
6798 { .channels = 2,
6799 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
6800 { .channels = 4,
6801 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6802 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6803 { .channels = 6,
6804 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
6805 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
6806 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
6807 { }
6808 };
6809
6810 /* Add the correct chmap for streams with 6 channels. */
ca0132_alt_add_chmap_ctls(struct hda_codec * codec)6811 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
6812 {
6813 int err = 0;
6814 struct hda_pcm *pcm;
6815
6816 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
6817 struct hda_pcm_stream *hinfo =
6818 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
6819 struct snd_pcm_chmap *chmap;
6820 const struct snd_pcm_chmap_elem *elem;
6821
6822 elem = ca0132_alt_chmaps;
6823 if (hinfo->channels_max == 6) {
6824 err = snd_pcm_add_chmap_ctls(pcm->pcm,
6825 SNDRV_PCM_STREAM_PLAYBACK,
6826 elem, hinfo->channels_max, 0, &chmap);
6827 if (err < 0)
6828 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
6829 }
6830 }
6831 }
6832
6833 /*
6834 * When changing Node IDs for Mixer Controls below, make sure to update
6835 * Node IDs in ca0132_config() as well.
6836 */
6837 static const struct snd_kcontrol_new ca0132_mixer[] = {
6838 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
6839 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
6840 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6841 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6842 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
6843 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
6844 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6845 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6846 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
6847 0x12, 1, HDA_INPUT),
6848 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
6849 VNID_HP_SEL, 1, HDA_OUTPUT),
6850 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
6851 VNID_AMIC1_SEL, 1, HDA_INPUT),
6852 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6853 VNID_HP_ASEL, 1, HDA_OUTPUT),
6854 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
6855 VNID_AMIC1_ASEL, 1, HDA_INPUT),
6856 { } /* end */
6857 };
6858
6859 /*
6860 * Desktop specific control mixer. Removes auto-detect for mic, and adds
6861 * surround controls. Also sets both the Front Playback and Capture Volume
6862 * controls to alt so they set the DSP's decibel level.
6863 */
6864 static const struct snd_kcontrol_new desktop_mixer[] = {
6865 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6866 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6867 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6868 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6869 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6870 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6871 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6872 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6873 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
6874 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6875 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6876 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6877 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6878 VNID_HP_ASEL, 1, HDA_OUTPUT),
6879 { } /* end */
6880 };
6881
6882 /*
6883 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
6884 * because it doesn't set decibel levels for the DSP for capture.
6885 */
6886 static const struct snd_kcontrol_new r3di_mixer[] = {
6887 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
6888 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
6889 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
6890 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
6891 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
6892 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
6893 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
6894 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
6895 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
6896 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
6897 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
6898 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
6899 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
6900 VNID_HP_ASEL, 1, HDA_OUTPUT),
6901 { } /* end */
6902 };
6903
ca0132_build_controls(struct hda_codec * codec)6904 static int ca0132_build_controls(struct hda_codec *codec)
6905 {
6906 struct ca0132_spec *spec = codec->spec;
6907 int i, num_fx, num_sliders;
6908 int err = 0;
6909
6910 /* Add Mixer controls */
6911 for (i = 0; i < spec->num_mixers; i++) {
6912 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
6913 if (err < 0)
6914 return err;
6915 }
6916 /* Setup vmaster with surround followers for desktop ca0132 devices */
6917 if (ca0132_use_alt_functions(spec)) {
6918 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
6919 spec->tlv);
6920 snd_hda_add_vmaster(codec, "Master Playback Volume",
6921 spec->tlv, ca0132_alt_follower_pfxs,
6922 "Playback Volume");
6923 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
6924 NULL, ca0132_alt_follower_pfxs,
6925 "Playback Switch",
6926 true, &spec->vmaster_mute.sw_kctl);
6927 if (err < 0)
6928 return err;
6929 }
6930
6931 /* Add in and out effects controls.
6932 * VoiceFX, PE and CrystalVoice are added separately.
6933 */
6934 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6935 for (i = 0; i < num_fx; i++) {
6936 /* Desktop cards break if Echo Cancellation is used. */
6937 if (ca0132_use_pci_mmio(spec)) {
6938 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
6939 OUT_EFFECTS_COUNT))
6940 continue;
6941 }
6942
6943 err = add_fx_switch(codec, ca0132_effects[i].nid,
6944 ca0132_effects[i].name,
6945 ca0132_effects[i].direct);
6946 if (err < 0)
6947 return err;
6948 }
6949 /*
6950 * If codec has use_alt_controls set to true, add effect level sliders,
6951 * EQ presets, and Smart Volume presets. Also, change names to add FX
6952 * prefix, and change PlayEnhancement and CrystalVoice to match.
6953 */
6954 if (ca0132_use_alt_controls(spec)) {
6955 err = ca0132_alt_add_svm_enum(codec);
6956 if (err < 0)
6957 return err;
6958
6959 err = add_ca0132_alt_eq_presets(codec);
6960 if (err < 0)
6961 return err;
6962
6963 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6964 "Enable OutFX", 0);
6965 if (err < 0)
6966 return err;
6967
6968 err = add_fx_switch(codec, CRYSTAL_VOICE,
6969 "Enable InFX", 1);
6970 if (err < 0)
6971 return err;
6972
6973 num_sliders = OUT_EFFECTS_COUNT - 1;
6974 for (i = 0; i < num_sliders; i++) {
6975 err = ca0132_alt_add_effect_slider(codec,
6976 ca0132_effects[i].nid,
6977 ca0132_effects[i].name,
6978 ca0132_effects[i].direct);
6979 if (err < 0)
6980 return err;
6981 }
6982
6983 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
6984 "X-Bass Crossover", EFX_DIR_OUT);
6985
6986 if (err < 0)
6987 return err;
6988 } else {
6989 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
6990 "PlayEnhancement", 0);
6991 if (err < 0)
6992 return err;
6993
6994 err = add_fx_switch(codec, CRYSTAL_VOICE,
6995 "CrystalVoice", 1);
6996 if (err < 0)
6997 return err;
6998 }
6999 err = add_voicefx(codec);
7000 if (err < 0)
7001 return err;
7002
7003 /*
7004 * If the codec uses alt_functions, you need the enumerated controls
7005 * to select the new outputs and inputs, plus add the new mic boost
7006 * setting control.
7007 */
7008 if (ca0132_use_alt_functions(spec)) {
7009 err = ca0132_alt_add_output_enum(codec);
7010 if (err < 0)
7011 return err;
7012 err = ca0132_alt_add_speaker_channel_cfg_enum(codec);
7013 if (err < 0)
7014 return err;
7015 err = ca0132_alt_add_front_full_range_switch(codec);
7016 if (err < 0)
7017 return err;
7018 err = ca0132_alt_add_rear_full_range_switch(codec);
7019 if (err < 0)
7020 return err;
7021 err = ca0132_alt_add_bass_redirection_crossover(codec);
7022 if (err < 0)
7023 return err;
7024 err = ca0132_alt_add_bass_redirection_switch(codec);
7025 if (err < 0)
7026 return err;
7027 err = ca0132_alt_add_mic_boost_enum(codec);
7028 if (err < 0)
7029 return err;
7030 /*
7031 * ZxR only has microphone input, there is no front panel
7032 * header on the card, and aux-in is handled by the DBPro board.
7033 */
7034 if (ca0132_quirk(spec) != QUIRK_ZXR) {
7035 err = ca0132_alt_add_input_enum(codec);
7036 if (err < 0)
7037 return err;
7038 }
7039 }
7040
7041 switch (ca0132_quirk(spec)) {
7042 case QUIRK_AE5:
7043 case QUIRK_AE7:
7044 err = ae5_add_headphone_gain_enum(codec);
7045 if (err < 0)
7046 return err;
7047 err = ae5_add_sound_filter_enum(codec);
7048 if (err < 0)
7049 return err;
7050 break;
7051 case QUIRK_ZXR:
7052 err = zxr_add_headphone_gain_switch(codec);
7053 if (err < 0)
7054 return err;
7055 break;
7056 default:
7057 break;
7058 }
7059
7060 #ifdef ENABLE_TUNING_CONTROLS
7061 add_tuning_ctls(codec);
7062 #endif
7063
7064 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
7065 if (err < 0)
7066 return err;
7067
7068 if (spec->dig_out) {
7069 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7070 spec->dig_out);
7071 if (err < 0)
7072 return err;
7073 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
7074 if (err < 0)
7075 return err;
7076 /* spec->multiout.share_spdif = 1; */
7077 }
7078
7079 if (spec->dig_in) {
7080 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7081 if (err < 0)
7082 return err;
7083 }
7084
7085 if (ca0132_use_alt_functions(spec))
7086 ca0132_alt_add_chmap_ctls(codec);
7087
7088 return 0;
7089 }
7090
dbpro_build_controls(struct hda_codec * codec)7091 static int dbpro_build_controls(struct hda_codec *codec)
7092 {
7093 struct ca0132_spec *spec = codec->spec;
7094 int err = 0;
7095
7096 if (spec->dig_out) {
7097 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
7098 spec->dig_out);
7099 if (err < 0)
7100 return err;
7101 }
7102
7103 if (spec->dig_in) {
7104 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
7105 if (err < 0)
7106 return err;
7107 }
7108
7109 return 0;
7110 }
7111
7112 /*
7113 * PCM
7114 */
7115 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
7116 .substreams = 1,
7117 .channels_min = 2,
7118 .channels_max = 6,
7119 .ops = {
7120 .prepare = ca0132_playback_pcm_prepare,
7121 .cleanup = ca0132_playback_pcm_cleanup,
7122 .get_delay = ca0132_playback_pcm_delay,
7123 },
7124 };
7125
7126 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
7127 .substreams = 1,
7128 .channels_min = 2,
7129 .channels_max = 2,
7130 .ops = {
7131 .prepare = ca0132_capture_pcm_prepare,
7132 .cleanup = ca0132_capture_pcm_cleanup,
7133 .get_delay = ca0132_capture_pcm_delay,
7134 },
7135 };
7136
7137 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
7138 .substreams = 1,
7139 .channels_min = 2,
7140 .channels_max = 2,
7141 .ops = {
7142 .open = ca0132_dig_playback_pcm_open,
7143 .close = ca0132_dig_playback_pcm_close,
7144 .prepare = ca0132_dig_playback_pcm_prepare,
7145 .cleanup = ca0132_dig_playback_pcm_cleanup
7146 },
7147 };
7148
7149 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
7150 .substreams = 1,
7151 .channels_min = 2,
7152 .channels_max = 2,
7153 };
7154
ca0132_build_pcms(struct hda_codec * codec)7155 static int ca0132_build_pcms(struct hda_codec *codec)
7156 {
7157 struct ca0132_spec *spec = codec->spec;
7158 struct hda_pcm *info;
7159
7160 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
7161 if (!info)
7162 return -ENOMEM;
7163 if (ca0132_use_alt_functions(spec)) {
7164 info->own_chmap = true;
7165 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
7166 = ca0132_alt_chmaps;
7167 }
7168 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
7169 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
7170 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
7171 spec->multiout.max_channels;
7172 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7173 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7174 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7175
7176 /* With the DSP enabled, desktops don't use this ADC. */
7177 if (!ca0132_use_alt_functions(spec)) {
7178 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
7179 if (!info)
7180 return -ENOMEM;
7181 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7182 ca0132_pcm_analog_capture;
7183 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7184 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
7185 }
7186
7187 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
7188 if (!info)
7189 return -ENOMEM;
7190 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7191 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7192 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
7193
7194 if (!spec->dig_out && !spec->dig_in)
7195 return 0;
7196
7197 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7198 if (!info)
7199 return -ENOMEM;
7200 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7201 if (spec->dig_out) {
7202 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7203 ca0132_pcm_digital_playback;
7204 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7205 }
7206 if (spec->dig_in) {
7207 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7208 ca0132_pcm_digital_capture;
7209 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7210 }
7211
7212 return 0;
7213 }
7214
dbpro_build_pcms(struct hda_codec * codec)7215 static int dbpro_build_pcms(struct hda_codec *codec)
7216 {
7217 struct ca0132_spec *spec = codec->spec;
7218 struct hda_pcm *info;
7219
7220 info = snd_hda_codec_pcm_new(codec, "CA0132 Alt Analog");
7221 if (!info)
7222 return -ENOMEM;
7223 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
7224 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
7225 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
7226
7227
7228 if (!spec->dig_out && !spec->dig_in)
7229 return 0;
7230
7231 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
7232 if (!info)
7233 return -ENOMEM;
7234 info->pcm_type = HDA_PCM_TYPE_SPDIF;
7235 if (spec->dig_out) {
7236 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
7237 ca0132_pcm_digital_playback;
7238 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
7239 }
7240 if (spec->dig_in) {
7241 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
7242 ca0132_pcm_digital_capture;
7243 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
7244 }
7245
7246 return 0;
7247 }
7248
init_output(struct hda_codec * codec,hda_nid_t pin,hda_nid_t dac)7249 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
7250 {
7251 if (pin) {
7252 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
7253 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
7254 snd_hda_codec_write(codec, pin, 0,
7255 AC_VERB_SET_AMP_GAIN_MUTE,
7256 AMP_OUT_UNMUTE);
7257 }
7258 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
7259 snd_hda_codec_write(codec, dac, 0,
7260 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
7261 }
7262
init_input(struct hda_codec * codec,hda_nid_t pin,hda_nid_t adc)7263 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
7264 {
7265 if (pin) {
7266 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
7267 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
7268 snd_hda_codec_write(codec, pin, 0,
7269 AC_VERB_SET_AMP_GAIN_MUTE,
7270 AMP_IN_UNMUTE(0));
7271 }
7272 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
7273 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
7274 AMP_IN_UNMUTE(0));
7275
7276 /* init to 0 dB and unmute. */
7277 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7278 HDA_AMP_VOLMASK, 0x5a);
7279 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
7280 HDA_AMP_MUTE, 0);
7281 }
7282 }
7283
refresh_amp_caps(struct hda_codec * codec,hda_nid_t nid,int dir)7284 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
7285 {
7286 unsigned int caps;
7287
7288 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
7289 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
7290 snd_hda_override_amp_caps(codec, nid, dir, caps);
7291 }
7292
7293 /*
7294 * Switch between Digital built-in mic and analog mic.
7295 */
ca0132_set_dmic(struct hda_codec * codec,int enable)7296 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
7297 {
7298 struct ca0132_spec *spec = codec->spec;
7299 unsigned int tmp;
7300 u8 val;
7301 unsigned int oldval;
7302
7303 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
7304
7305 oldval = stop_mic1(codec);
7306 ca0132_set_vipsource(codec, 0);
7307 if (enable) {
7308 /* set DMic input as 2-ch */
7309 tmp = FLOAT_TWO;
7310 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7311
7312 val = spec->dmic_ctl;
7313 val |= 0x80;
7314 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7315 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7316
7317 if (!(spec->dmic_ctl & 0x20))
7318 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
7319 } else {
7320 /* set AMic input as mono */
7321 tmp = FLOAT_ONE;
7322 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7323
7324 val = spec->dmic_ctl;
7325 /* clear bit7 and bit5 to disable dmic */
7326 val &= 0x5f;
7327 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7328 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7329
7330 if (!(spec->dmic_ctl & 0x20))
7331 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
7332 }
7333 ca0132_set_vipsource(codec, 1);
7334 resume_mic1(codec, oldval);
7335 }
7336
7337 /*
7338 * Initialization for Digital Mic.
7339 */
ca0132_init_dmic(struct hda_codec * codec)7340 static void ca0132_init_dmic(struct hda_codec *codec)
7341 {
7342 struct ca0132_spec *spec = codec->spec;
7343 u8 val;
7344
7345 /* Setup Digital Mic here, but don't enable.
7346 * Enable based on jack detect.
7347 */
7348
7349 /* MCLK uses MPIO1, set to enable.
7350 * Bit 2-0: MPIO select
7351 * Bit 3: set to disable
7352 * Bit 7-4: reserved
7353 */
7354 val = 0x01;
7355 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7356 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
7357
7358 /* Data1 uses MPIO3. Data2 not use
7359 * Bit 2-0: Data1 MPIO select
7360 * Bit 3: set disable Data1
7361 * Bit 6-4: Data2 MPIO select
7362 * Bit 7: set disable Data2
7363 */
7364 val = 0x83;
7365 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7366 VENDOR_CHIPIO_DMIC_PIN_SET, val);
7367
7368 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
7369 * Bit 3-0: Channel mask
7370 * Bit 4: set for 48KHz, clear for 32KHz
7371 * Bit 5: mode
7372 * Bit 6: set to select Data2, clear for Data1
7373 * Bit 7: set to enable DMic, clear for AMic
7374 */
7375 if (ca0132_quirk(spec) == QUIRK_ALIENWARE_M17XR4)
7376 val = 0x33;
7377 else
7378 val = 0x23;
7379 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
7380 spec->dmic_ctl = val;
7381 snd_hda_codec_write(codec, spec->input_pins[0], 0,
7382 VENDOR_CHIPIO_DMIC_CTL_SET, val);
7383 }
7384
7385 /*
7386 * Initialization for Analog Mic 2
7387 */
ca0132_init_analog_mic2(struct hda_codec * codec)7388 static void ca0132_init_analog_mic2(struct hda_codec *codec)
7389 {
7390 struct ca0132_spec *spec = codec->spec;
7391
7392 mutex_lock(&spec->chipio_mutex);
7393 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7394 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7395 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7396 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7397 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7398 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7399 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7400 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
7401 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7402 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7403 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7404 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7405 mutex_unlock(&spec->chipio_mutex);
7406 }
7407
ca0132_refresh_widget_caps(struct hda_codec * codec)7408 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
7409 {
7410 struct ca0132_spec *spec = codec->spec;
7411 int i;
7412
7413 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
7414 snd_hda_codec_update_widgets(codec);
7415
7416 for (i = 0; i < spec->multiout.num_dacs; i++)
7417 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
7418
7419 for (i = 0; i < spec->num_outputs; i++)
7420 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
7421
7422 for (i = 0; i < spec->num_inputs; i++) {
7423 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
7424 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
7425 }
7426 }
7427
7428 /*
7429 * Default speaker tuning values setup for alternative codecs.
7430 */
7431 static const unsigned int sbz_default_delay_values[] = {
7432 /* Non-zero values are floating point 0.000198. */
7433 0x394f9e38, 0x394f9e38, 0x00000000, 0x00000000, 0x00000000, 0x00000000
7434 };
7435
7436 static const unsigned int zxr_default_delay_values[] = {
7437 /* Non-zero values are floating point 0.000220. */
7438 0x00000000, 0x00000000, 0x3966afcd, 0x3966afcd, 0x3966afcd, 0x3966afcd
7439 };
7440
7441 static const unsigned int ae5_default_delay_values[] = {
7442 /* Non-zero values are floating point 0.000100. */
7443 0x00000000, 0x00000000, 0x38d1b717, 0x38d1b717, 0x38d1b717, 0x38d1b717
7444 };
7445
7446 /*
7447 * If we never change these, probably only need them on initialization.
7448 */
ca0132_alt_init_speaker_tuning(struct hda_codec * codec)7449 static void ca0132_alt_init_speaker_tuning(struct hda_codec *codec)
7450 {
7451 struct ca0132_spec *spec = codec->spec;
7452 unsigned int i, tmp, start_req, end_req;
7453 const unsigned int *values;
7454
7455 switch (ca0132_quirk(spec)) {
7456 case QUIRK_SBZ:
7457 values = sbz_default_delay_values;
7458 break;
7459 case QUIRK_ZXR:
7460 values = zxr_default_delay_values;
7461 break;
7462 case QUIRK_AE5:
7463 case QUIRK_AE7:
7464 values = ae5_default_delay_values;
7465 break;
7466 default:
7467 values = sbz_default_delay_values;
7468 break;
7469 }
7470
7471 tmp = FLOAT_ZERO;
7472 dspio_set_uint_param(codec, 0x96, SPEAKER_TUNING_ENABLE_CENTER_EQ, tmp);
7473
7474 start_req = SPEAKER_TUNING_FRONT_LEFT_VOL_LEVEL;
7475 end_req = SPEAKER_TUNING_REAR_RIGHT_VOL_LEVEL;
7476 for (i = start_req; i < end_req + 1; i++)
7477 dspio_set_uint_param(codec, 0x96, i, tmp);
7478
7479 start_req = SPEAKER_TUNING_FRONT_LEFT_INVERT;
7480 end_req = SPEAKER_TUNING_REAR_RIGHT_INVERT;
7481 for (i = start_req; i < end_req + 1; i++)
7482 dspio_set_uint_param(codec, 0x96, i, tmp);
7483
7484
7485 for (i = 0; i < 6; i++)
7486 dspio_set_uint_param(codec, 0x96,
7487 SPEAKER_TUNING_FRONT_LEFT_DELAY + i, values[i]);
7488 }
7489
7490 /*
7491 * Creates a dummy stream to bind the output to. This seems to have to be done
7492 * after changing the main outputs source and destination streams.
7493 */
ca0132_alt_create_dummy_stream(struct hda_codec * codec)7494 static void ca0132_alt_create_dummy_stream(struct hda_codec *codec)
7495 {
7496 struct ca0132_spec *spec = codec->spec;
7497 unsigned int stream_format;
7498
7499 stream_format = snd_hdac_calc_stream_format(48000, 2,
7500 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
7501
7502 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
7503 0, stream_format);
7504
7505 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
7506 }
7507
7508 /*
7509 * Initialize mic for non-chromebook ca0132 implementations.
7510 */
ca0132_alt_init_analog_mics(struct hda_codec * codec)7511 static void ca0132_alt_init_analog_mics(struct hda_codec *codec)
7512 {
7513 struct ca0132_spec *spec = codec->spec;
7514 unsigned int tmp;
7515
7516 /* Mic 1 Setup */
7517 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7518 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7519 if (ca0132_quirk(spec) == QUIRK_R3DI) {
7520 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7521 tmp = FLOAT_ONE;
7522 } else
7523 tmp = FLOAT_THREE;
7524 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7525
7526 /* Mic 2 setup (not present on desktop cards) */
7527 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
7528 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
7529 if (ca0132_quirk(spec) == QUIRK_R3DI)
7530 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
7531 tmp = FLOAT_ZERO;
7532 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
7533 }
7534
7535 /*
7536 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
7537 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
7538 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
7539 * having an updated DAC, which changes the destination to that DAC.
7540 */
sbz_connect_streams(struct hda_codec * codec)7541 static void sbz_connect_streams(struct hda_codec *codec)
7542 {
7543 struct ca0132_spec *spec = codec->spec;
7544
7545 mutex_lock(&spec->chipio_mutex);
7546
7547 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
7548
7549 chipio_set_stream_channels(codec, 0x0C, 6);
7550 chipio_set_stream_control(codec, 0x0C, 1);
7551
7552 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
7553 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
7554
7555 /* Setup stream 0x14 with it's source and destination points */
7556 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
7557 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
7558 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
7559 chipio_set_stream_channels(codec, 0x14, 2);
7560 chipio_set_stream_control(codec, 0x14, 1);
7561
7562 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
7563
7564 mutex_unlock(&spec->chipio_mutex);
7565 }
7566
7567 /*
7568 * Write data through ChipIO to setup proper stream destinations.
7569 * Not sure how it exactly works, but it seems to direct data
7570 * to different destinations. Example is f8 to c0, e0 to c0.
7571 * All I know is, if you don't set these, you get no sound.
7572 */
sbz_chipio_startup_data(struct hda_codec * codec)7573 static void sbz_chipio_startup_data(struct hda_codec *codec)
7574 {
7575 struct ca0132_spec *spec = codec->spec;
7576
7577 mutex_lock(&spec->chipio_mutex);
7578 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
7579
7580 /* These control audio output */
7581 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
7582 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
7583 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
7584 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
7585 /* Signal to update I think */
7586 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7587
7588 chipio_set_stream_channels(codec, 0x0C, 6);
7589 chipio_set_stream_control(codec, 0x0C, 1);
7590 /* No clue what these control */
7591 if (ca0132_quirk(spec) == QUIRK_SBZ) {
7592 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
7593 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
7594 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
7595 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
7596 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
7597 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
7598 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
7599 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
7600 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
7601 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
7602 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
7603 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
7604 } else if (ca0132_quirk(spec) == QUIRK_ZXR) {
7605 chipio_write_no_mutex(codec, 0x190038, 0x000140c2);
7606 chipio_write_no_mutex(codec, 0x19003c, 0x000141c3);
7607 chipio_write_no_mutex(codec, 0x190040, 0x000150c4);
7608 chipio_write_no_mutex(codec, 0x190044, 0x000151c5);
7609 chipio_write_no_mutex(codec, 0x190050, 0x000142c8);
7610 chipio_write_no_mutex(codec, 0x190054, 0x000143c9);
7611 chipio_write_no_mutex(codec, 0x190058, 0x000152ca);
7612 chipio_write_no_mutex(codec, 0x19005c, 0x000153cb);
7613 }
7614 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7615
7616 codec_dbg(codec, "Startup Data exited, mutex released.\n");
7617 mutex_unlock(&spec->chipio_mutex);
7618 }
7619
7620 /*
7621 * Custom DSP SCP commands where the src value is 0x00 instead of 0x20. This is
7622 * done after the DSP is loaded.
7623 */
ca0132_alt_dsp_scp_startup(struct hda_codec * codec)7624 static void ca0132_alt_dsp_scp_startup(struct hda_codec *codec)
7625 {
7626 struct ca0132_spec *spec = codec->spec;
7627 unsigned int tmp, i;
7628
7629 /*
7630 * Gotta run these twice, or else mic works inconsistently. Not clear
7631 * why this is, but multiple tests have confirmed it.
7632 */
7633 for (i = 0; i < 2; i++) {
7634 switch (ca0132_quirk(spec)) {
7635 case QUIRK_SBZ:
7636 case QUIRK_AE5:
7637 case QUIRK_AE7:
7638 tmp = 0x00000003;
7639 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7640 tmp = 0x00000000;
7641 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7642 tmp = 0x00000001;
7643 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7644 tmp = 0x00000004;
7645 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7646 tmp = 0x00000005;
7647 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7648 tmp = 0x00000000;
7649 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7650 break;
7651 case QUIRK_R3D:
7652 case QUIRK_R3DI:
7653 tmp = 0x00000000;
7654 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
7655 tmp = 0x00000001;
7656 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
7657 tmp = 0x00000004;
7658 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7659 tmp = 0x00000005;
7660 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7661 tmp = 0x00000000;
7662 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
7663 break;
7664 default:
7665 break;
7666 }
7667 msleep(100);
7668 }
7669 }
7670
ca0132_alt_dsp_initial_mic_setup(struct hda_codec * codec)7671 static void ca0132_alt_dsp_initial_mic_setup(struct hda_codec *codec)
7672 {
7673 struct ca0132_spec *spec = codec->spec;
7674 unsigned int tmp;
7675
7676 chipio_set_stream_control(codec, 0x03, 0);
7677 chipio_set_stream_control(codec, 0x04, 0);
7678
7679 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
7680 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
7681
7682 tmp = FLOAT_THREE;
7683 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
7684
7685 chipio_set_stream_control(codec, 0x03, 1);
7686 chipio_set_stream_control(codec, 0x04, 1);
7687
7688 switch (ca0132_quirk(spec)) {
7689 case QUIRK_SBZ:
7690 chipio_write(codec, 0x18b098, 0x0000000c);
7691 chipio_write(codec, 0x18b09C, 0x0000000c);
7692 break;
7693 case QUIRK_AE5:
7694 chipio_write(codec, 0x18b098, 0x0000000c);
7695 chipio_write(codec, 0x18b09c, 0x0000004c);
7696 break;
7697 default:
7698 break;
7699 }
7700 }
7701
ae5_post_dsp_register_set(struct hda_codec * codec)7702 static void ae5_post_dsp_register_set(struct hda_codec *codec)
7703 {
7704 struct ca0132_spec *spec = codec->spec;
7705
7706 chipio_8051_write_direct(codec, 0x93, 0x10);
7707 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7708 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
7709 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7710 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
7711
7712 writeb(0xff, spec->mem_base + 0x304);
7713 writeb(0xff, spec->mem_base + 0x304);
7714 writeb(0xff, spec->mem_base + 0x304);
7715 writeb(0xff, spec->mem_base + 0x304);
7716 writeb(0x00, spec->mem_base + 0x100);
7717 writeb(0xff, spec->mem_base + 0x304);
7718 writeb(0x00, spec->mem_base + 0x100);
7719 writeb(0xff, spec->mem_base + 0x304);
7720 writeb(0x00, spec->mem_base + 0x100);
7721 writeb(0xff, spec->mem_base + 0x304);
7722 writeb(0x00, spec->mem_base + 0x100);
7723 writeb(0xff, spec->mem_base + 0x304);
7724
7725 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x3f);
7726 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
7727 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7728 }
7729
ae5_post_dsp_param_setup(struct hda_codec * codec)7730 static void ae5_post_dsp_param_setup(struct hda_codec *codec)
7731 {
7732 /*
7733 * Param3 in the 8051's memory is represented by the ascii string 'mch'
7734 * which seems to be 'multichannel'. This is also mentioned in the
7735 * AE-5's registry values in Windows.
7736 */
7737 chipio_set_control_param(codec, 3, 0);
7738 /*
7739 * I believe ASI is 'audio serial interface' and that it's used to
7740 * change colors on the external LED strip connected to the AE-5.
7741 */
7742 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
7743
7744 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
7745 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
7746
7747 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7748 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
7749 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7750 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
7751 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7752 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
7753 }
7754
ae5_post_dsp_pll_setup(struct hda_codec * codec)7755 static void ae5_post_dsp_pll_setup(struct hda_codec *codec)
7756 {
7757 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7758 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
7759 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7760 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
7761
7762 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7763 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x45);
7764 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7765 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcc);
7766
7767 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7768 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x40);
7769 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7770 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xcb);
7771
7772 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7773 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7774 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7775 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7776
7777 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7778 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x51);
7779 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7780 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x8d);
7781 }
7782
ae5_post_dsp_stream_setup(struct hda_codec * codec)7783 static void ae5_post_dsp_stream_setup(struct hda_codec *codec)
7784 {
7785 struct ca0132_spec *spec = codec->spec;
7786
7787 mutex_lock(&spec->chipio_mutex);
7788
7789 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7790
7791 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7792
7793 chipio_set_stream_channels(codec, 0x0C, 6);
7794 chipio_set_stream_control(codec, 0x0C, 1);
7795
7796 chipio_set_stream_source_dest(codec, 0x5, 0x43, 0x0);
7797
7798 chipio_set_stream_source_dest(codec, 0x18, 0x9, 0xd0);
7799 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7800 chipio_set_stream_channels(codec, 0x18, 6);
7801 chipio_set_stream_control(codec, 0x18, 1);
7802
7803 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7804
7805 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7806 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7807 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7808 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7809
7810 ca0113_mmio_command_set(codec, 0x48, 0x01, 0x80);
7811
7812 mutex_unlock(&spec->chipio_mutex);
7813 }
7814
ae5_post_dsp_startup_data(struct hda_codec * codec)7815 static void ae5_post_dsp_startup_data(struct hda_codec *codec)
7816 {
7817 struct ca0132_spec *spec = codec->spec;
7818
7819 mutex_lock(&spec->chipio_mutex);
7820
7821 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7822 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7823 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7824 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7825
7826 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7827 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7828 ca0113_mmio_command_set(codec, 0x48, 0x0b, 0x12);
7829 ca0113_mmio_command_set(codec, 0x48, 0x04, 0x00);
7830 ca0113_mmio_command_set(codec, 0x48, 0x06, 0x48);
7831 ca0113_mmio_command_set(codec, 0x48, 0x0a, 0x05);
7832 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
7833 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7834 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7835 ca0113_mmio_gpio_set(codec, 0, true);
7836 ca0113_mmio_gpio_set(codec, 1, true);
7837 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x80);
7838
7839 chipio_write_no_mutex(codec, 0x18b03c, 0x00000012);
7840
7841 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7842 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7843
7844 mutex_unlock(&spec->chipio_mutex);
7845 }
7846
7847 static const unsigned int ae7_port_set_data[] = {
7848 0x0001e0c0, 0x0001e1c1, 0x0001e4c2, 0x0001e5c3, 0x0001e2c4, 0x0001e3c5,
7849 0x0001e8c6, 0x0001e9c7, 0x0001ecc8, 0x0001edc9, 0x0001eaca, 0x0001ebcb
7850 };
7851
ae7_post_dsp_setup_ports(struct hda_codec * codec)7852 static void ae7_post_dsp_setup_ports(struct hda_codec *codec)
7853 {
7854 struct ca0132_spec *spec = codec->spec;
7855 unsigned int i, count, addr;
7856
7857 mutex_lock(&spec->chipio_mutex);
7858
7859 chipio_set_stream_channels(codec, 0x0c, 6);
7860 chipio_set_stream_control(codec, 0x0c, 1);
7861
7862 count = ARRAY_SIZE(ae7_port_set_data);
7863 addr = 0x190030;
7864 for (i = 0; i < count; i++) {
7865 chipio_write_no_mutex(codec, addr, ae7_port_set_data[i]);
7866
7867 /* Addresses are incremented by 4-bytes. */
7868 addr += 0x04;
7869 }
7870
7871 /*
7872 * Port setting always ends with a write of 0x1 to address 0x19042c.
7873 */
7874 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
7875
7876 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
7877 ca0113_mmio_command_set(codec, 0x48, 0x0d, 0x40);
7878 ca0113_mmio_command_set(codec, 0x48, 0x17, 0x00);
7879 ca0113_mmio_command_set(codec, 0x48, 0x19, 0x00);
7880 ca0113_mmio_command_set(codec, 0x48, 0x11, 0xff);
7881 ca0113_mmio_command_set(codec, 0x48, 0x12, 0xff);
7882 ca0113_mmio_command_set(codec, 0x48, 0x13, 0xff);
7883 ca0113_mmio_command_set(codec, 0x48, 0x14, 0x7f);
7884
7885 mutex_unlock(&spec->chipio_mutex);
7886 }
7887
ae7_post_dsp_asi_stream_setup(struct hda_codec * codec)7888 static void ae7_post_dsp_asi_stream_setup(struct hda_codec *codec)
7889 {
7890 struct ca0132_spec *spec = codec->spec;
7891
7892 mutex_lock(&spec->chipio_mutex);
7893
7894 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x725, 0x81);
7895 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
7896
7897 chipio_set_conn_rate_no_mutex(codec, 0x70, SR_96_000);
7898 chipio_set_stream_channels(codec, 0x0c, 6);
7899 chipio_set_stream_control(codec, 0x0c, 1);
7900
7901 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
7902 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
7903
7904 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7905 chipio_set_stream_channels(codec, 0x18, 6);
7906 chipio_set_stream_control(codec, 0x18, 1);
7907
7908 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 4);
7909
7910 mutex_unlock(&spec->chipio_mutex);
7911 }
7912
ae7_post_dsp_pll_setup(struct hda_codec * codec)7913 static void ae7_post_dsp_pll_setup(struct hda_codec *codec)
7914 {
7915 static const unsigned int addr[] = {
7916 0x41, 0x45, 0x40, 0x43, 0x51
7917 };
7918 static const unsigned int data[] = {
7919 0xc8, 0xcc, 0xcb, 0xc7, 0x8d
7920 };
7921 unsigned int i;
7922
7923 for (i = 0; i < ARRAY_SIZE(addr); i++) {
7924 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7925 VENDOR_CHIPIO_8051_ADDRESS_LOW, addr[i]);
7926 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7927 VENDOR_CHIPIO_PLL_PMU_WRITE, data[i]);
7928 }
7929 }
7930
ae7_post_dsp_asi_setup_ports(struct hda_codec * codec)7931 static void ae7_post_dsp_asi_setup_ports(struct hda_codec *codec)
7932 {
7933 struct ca0132_spec *spec = codec->spec;
7934 static const unsigned int target[] = {
7935 0x0b, 0x04, 0x06, 0x0a, 0x0c, 0x11, 0x12, 0x13, 0x14
7936 };
7937 static const unsigned int data[] = {
7938 0x12, 0x00, 0x48, 0x05, 0x5f, 0xff, 0xff, 0xff, 0x7f
7939 };
7940 unsigned int i;
7941
7942 mutex_lock(&spec->chipio_mutex);
7943
7944 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7945 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
7946 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7947 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
7948
7949 chipio_write_no_mutex(codec, 0x189000, 0x0001f101);
7950 chipio_write_no_mutex(codec, 0x189004, 0x0001f101);
7951 chipio_write_no_mutex(codec, 0x189024, 0x00014004);
7952 chipio_write_no_mutex(codec, 0x189028, 0x0002000f);
7953
7954 ae7_post_dsp_pll_setup(codec);
7955 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
7956
7957 for (i = 0; i < ARRAY_SIZE(target); i++)
7958 ca0113_mmio_command_set(codec, 0x48, target[i], data[i]);
7959
7960 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
7961 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7962 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7963
7964 chipio_set_stream_source_dest(codec, 0x21, 0x64, 0x56);
7965 chipio_set_stream_channels(codec, 0x21, 2);
7966 chipio_set_conn_rate_no_mutex(codec, 0x56, SR_8_000);
7967
7968 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_NODE_ID, 0x09);
7969 /*
7970 * In the 8051's memory, this param is referred to as 'n2sid', which I
7971 * believe is 'node to streamID'. It seems to be a way to assign a
7972 * stream to a given HDA node.
7973 */
7974 chipio_set_control_param_no_mutex(codec, 0x20, 0x21);
7975
7976 chipio_write_no_mutex(codec, 0x18b038, 0x00000088);
7977
7978 /*
7979 * Now, at this point on Windows, an actual stream is setup and
7980 * seemingly sends data to the HDA node 0x09, which is the digital
7981 * audio input node. This is left out here, because obviously I don't
7982 * know what data is being sent. Interestingly, the AE-5 seems to go
7983 * through the motions of getting here and never actually takes this
7984 * step, but the AE-7 does.
7985 */
7986
7987 ca0113_mmio_gpio_set(codec, 0, 1);
7988 ca0113_mmio_gpio_set(codec, 1, 1);
7989
7990 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
7991 chipio_write_no_mutex(codec, 0x18b03c, 0x00000000);
7992 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x00);
7993 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x00);
7994
7995 chipio_set_stream_source_dest(codec, 0x05, 0x43, 0x00);
7996 chipio_set_stream_source_dest(codec, 0x18, 0x09, 0xd0);
7997
7998 chipio_set_conn_rate_no_mutex(codec, 0xd0, SR_96_000);
7999 chipio_set_stream_channels(codec, 0x18, 6);
8000
8001 /*
8002 * Runs again, this has been repeated a few times, but I'm just
8003 * following what the Windows driver does.
8004 */
8005 ae7_post_dsp_pll_setup(codec);
8006 chipio_set_control_param_no_mutex(codec, CONTROL_PARAM_ASI, 7);
8007
8008 mutex_unlock(&spec->chipio_mutex);
8009 }
8010
8011 /*
8012 * The Windows driver has commands that seem to setup ASI, which I believe to
8013 * be some sort of audio serial interface. My current speculation is that it's
8014 * related to communicating with the new DAC.
8015 */
ae7_post_dsp_asi_setup(struct hda_codec * codec)8016 static void ae7_post_dsp_asi_setup(struct hda_codec *codec)
8017 {
8018 chipio_8051_write_direct(codec, 0x93, 0x10);
8019
8020 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8021 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
8022 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8023 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
8024
8025 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8026 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8027
8028 chipio_set_control_param(codec, 3, 3);
8029 chipio_set_control_flag(codec, CONTROL_FLAG_ASI_96KHZ, 1);
8030
8031 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x724, 0x83);
8032 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8033 snd_hda_codec_write(codec, 0x17, 0, 0x794, 0x00);
8034
8035 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8036 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x92);
8037 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8038 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0xfa);
8039 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8040 VENDOR_CHIPIO_8051_DATA_WRITE, 0x22);
8041
8042 ae7_post_dsp_pll_setup(codec);
8043 ae7_post_dsp_asi_stream_setup(codec);
8044
8045 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8046 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x43);
8047 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
8048 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc7);
8049
8050 ae7_post_dsp_asi_setup_ports(codec);
8051 }
8052
8053 /*
8054 * Setup default parameters for DSP
8055 */
ca0132_setup_defaults(struct hda_codec * codec)8056 static void ca0132_setup_defaults(struct hda_codec *codec)
8057 {
8058 struct ca0132_spec *spec = codec->spec;
8059 unsigned int tmp;
8060 int num_fx;
8061 int idx, i;
8062
8063 if (spec->dsp_state != DSP_DOWNLOADED)
8064 return;
8065
8066 /* out, in effects + voicefx */
8067 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8068 for (idx = 0; idx < num_fx; idx++) {
8069 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8070 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
8071 ca0132_effects[idx].reqs[i],
8072 ca0132_effects[idx].def_vals[i]);
8073 }
8074 }
8075
8076 /*remove DSP headroom*/
8077 tmp = FLOAT_ZERO;
8078 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8079
8080 /*set speaker EQ bypass attenuation*/
8081 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
8082
8083 /* set AMic1 and AMic2 as mono mic */
8084 tmp = FLOAT_ONE;
8085 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
8086 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
8087
8088 /* set AMic1 as CrystalVoice input */
8089 tmp = FLOAT_ONE;
8090 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
8091
8092 /* set WUH source */
8093 tmp = FLOAT_TWO;
8094 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8095 }
8096
8097 /*
8098 * Setup default parameters for Recon3D/Recon3Di DSP.
8099 */
8100
r3d_setup_defaults(struct hda_codec * codec)8101 static void r3d_setup_defaults(struct hda_codec *codec)
8102 {
8103 struct ca0132_spec *spec = codec->spec;
8104 unsigned int tmp;
8105 int num_fx;
8106 int idx, i;
8107
8108 if (spec->dsp_state != DSP_DOWNLOADED)
8109 return;
8110
8111 ca0132_alt_dsp_scp_startup(codec);
8112 ca0132_alt_init_analog_mics(codec);
8113
8114 /*remove DSP headroom*/
8115 tmp = FLOAT_ZERO;
8116 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8117
8118 /* set WUH source */
8119 tmp = FLOAT_TWO;
8120 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8121 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8122
8123 /* Set speaker source? */
8124 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8125
8126 if (ca0132_quirk(spec) == QUIRK_R3DI)
8127 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
8128
8129 /* Disable mute on Center/LFE. */
8130 if (ca0132_quirk(spec) == QUIRK_R3D) {
8131 ca0113_mmio_gpio_set(codec, 2, false);
8132 ca0113_mmio_gpio_set(codec, 4, true);
8133 }
8134
8135 /* Setup effect defaults */
8136 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8137 for (idx = 0; idx < num_fx; idx++) {
8138 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8139 dspio_set_uint_param(codec,
8140 ca0132_effects[idx].mid,
8141 ca0132_effects[idx].reqs[i],
8142 ca0132_effects[idx].def_vals[i]);
8143 }
8144 }
8145 }
8146
8147 /*
8148 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
8149 * than the Chromebook setup.
8150 */
sbz_setup_defaults(struct hda_codec * codec)8151 static void sbz_setup_defaults(struct hda_codec *codec)
8152 {
8153 struct ca0132_spec *spec = codec->spec;
8154 unsigned int tmp;
8155 int num_fx;
8156 int idx, i;
8157
8158 if (spec->dsp_state != DSP_DOWNLOADED)
8159 return;
8160
8161 ca0132_alt_dsp_scp_startup(codec);
8162 ca0132_alt_init_analog_mics(codec);
8163 sbz_connect_streams(codec);
8164 sbz_chipio_startup_data(codec);
8165
8166 chipio_set_stream_control(codec, 0x03, 1);
8167 chipio_set_stream_control(codec, 0x04, 1);
8168
8169 /*
8170 * Sets internal input loopback to off, used to have a switch to
8171 * enable input loopback, but turned out to be way too buggy.
8172 */
8173 tmp = FLOAT_ONE;
8174 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8175 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8176
8177 /*remove DSP headroom*/
8178 tmp = FLOAT_ZERO;
8179 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8180
8181 /* set WUH source */
8182 tmp = FLOAT_TWO;
8183 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8184 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8185
8186 /* Set speaker source? */
8187 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8188
8189 ca0132_alt_dsp_initial_mic_setup(codec);
8190
8191 /* out, in effects + voicefx */
8192 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8193 for (idx = 0; idx < num_fx; idx++) {
8194 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8195 dspio_set_uint_param(codec,
8196 ca0132_effects[idx].mid,
8197 ca0132_effects[idx].reqs[i],
8198 ca0132_effects[idx].def_vals[i]);
8199 }
8200 }
8201
8202 ca0132_alt_init_speaker_tuning(codec);
8203
8204 ca0132_alt_create_dummy_stream(codec);
8205 }
8206
8207 /*
8208 * Setup default parameters for the Sound BlasterX AE-5 DSP.
8209 */
ae5_setup_defaults(struct hda_codec * codec)8210 static void ae5_setup_defaults(struct hda_codec *codec)
8211 {
8212 struct ca0132_spec *spec = codec->spec;
8213 unsigned int tmp;
8214 int num_fx;
8215 int idx, i;
8216
8217 if (spec->dsp_state != DSP_DOWNLOADED)
8218 return;
8219
8220 ca0132_alt_dsp_scp_startup(codec);
8221 ca0132_alt_init_analog_mics(codec);
8222 chipio_set_stream_control(codec, 0x03, 1);
8223 chipio_set_stream_control(codec, 0x04, 1);
8224
8225 /* New, unknown SCP req's */
8226 tmp = FLOAT_ZERO;
8227 dspio_set_uint_param(codec, 0x96, 0x29, tmp);
8228 dspio_set_uint_param(codec, 0x96, 0x2a, tmp);
8229 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8230 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8231
8232 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8233 ca0113_mmio_gpio_set(codec, 0, false);
8234 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8235
8236 /* Internal loopback off */
8237 tmp = FLOAT_ONE;
8238 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8239 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8240
8241 /*remove DSP headroom*/
8242 tmp = FLOAT_ZERO;
8243 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8244
8245 /* set WUH source */
8246 tmp = FLOAT_TWO;
8247 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8248 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8249
8250 /* Set speaker source? */
8251 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8252
8253 ca0132_alt_dsp_initial_mic_setup(codec);
8254 ae5_post_dsp_register_set(codec);
8255 ae5_post_dsp_param_setup(codec);
8256 ae5_post_dsp_pll_setup(codec);
8257 ae5_post_dsp_stream_setup(codec);
8258 ae5_post_dsp_startup_data(codec);
8259
8260 /* out, in effects + voicefx */
8261 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8262 for (idx = 0; idx < num_fx; idx++) {
8263 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8264 dspio_set_uint_param(codec,
8265 ca0132_effects[idx].mid,
8266 ca0132_effects[idx].reqs[i],
8267 ca0132_effects[idx].def_vals[i]);
8268 }
8269 }
8270
8271 ca0132_alt_init_speaker_tuning(codec);
8272
8273 ca0132_alt_create_dummy_stream(codec);
8274 }
8275
8276 /*
8277 * Setup default parameters for the Sound Blaster AE-7 DSP.
8278 */
ae7_setup_defaults(struct hda_codec * codec)8279 static void ae7_setup_defaults(struct hda_codec *codec)
8280 {
8281 struct ca0132_spec *spec = codec->spec;
8282 unsigned int tmp;
8283 int num_fx;
8284 int idx, i;
8285
8286 if (spec->dsp_state != DSP_DOWNLOADED)
8287 return;
8288
8289 ca0132_alt_dsp_scp_startup(codec);
8290 ca0132_alt_init_analog_mics(codec);
8291 ae7_post_dsp_setup_ports(codec);
8292
8293 tmp = FLOAT_ZERO;
8294 dspio_set_uint_param(codec, 0x96,
8295 SPEAKER_TUNING_FRONT_LEFT_INVERT, tmp);
8296 dspio_set_uint_param(codec, 0x96,
8297 SPEAKER_TUNING_FRONT_RIGHT_INVERT, tmp);
8298
8299 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
8300
8301 /* New, unknown SCP req's */
8302 dspio_set_uint_param(codec, 0x80, 0x0d, tmp);
8303 dspio_set_uint_param(codec, 0x80, 0x0e, tmp);
8304
8305 ca0113_mmio_gpio_set(codec, 0, false);
8306
8307 /* Internal loopback off */
8308 tmp = FLOAT_ONE;
8309 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
8310 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
8311
8312 /*remove DSP headroom*/
8313 tmp = FLOAT_ZERO;
8314 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
8315
8316 /* set WUH source */
8317 tmp = FLOAT_TWO;
8318 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
8319 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8320
8321 /* Set speaker source? */
8322 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
8323 ca0113_mmio_command_set(codec, 0x30, 0x28, 0x00);
8324
8325 /*
8326 * This is the second time we've called this, but this is seemingly
8327 * what Windows does.
8328 */
8329 ca0132_alt_init_analog_mics(codec);
8330
8331 ae7_post_dsp_asi_setup(codec);
8332
8333 /*
8334 * Not sure why, but these are both set to 1. They're only set to 0
8335 * upon shutdown.
8336 */
8337 ca0113_mmio_gpio_set(codec, 0, true);
8338 ca0113_mmio_gpio_set(codec, 1, true);
8339
8340 /* Volume control related. */
8341 ca0113_mmio_command_set(codec, 0x48, 0x0f, 0x04);
8342 ca0113_mmio_command_set(codec, 0x48, 0x10, 0x04);
8343 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x80);
8344
8345 /* out, in effects + voicefx */
8346 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
8347 for (idx = 0; idx < num_fx; idx++) {
8348 for (i = 0; i <= ca0132_effects[idx].params; i++) {
8349 dspio_set_uint_param(codec,
8350 ca0132_effects[idx].mid,
8351 ca0132_effects[idx].reqs[i],
8352 ca0132_effects[idx].def_vals[i]);
8353 }
8354 }
8355
8356 ca0132_alt_init_speaker_tuning(codec);
8357
8358 ca0132_alt_create_dummy_stream(codec);
8359 }
8360
8361 /*
8362 * Initialization of flags in chip
8363 */
ca0132_init_flags(struct hda_codec * codec)8364 static void ca0132_init_flags(struct hda_codec *codec)
8365 {
8366 struct ca0132_spec *spec = codec->spec;
8367
8368 if (ca0132_use_alt_functions(spec)) {
8369 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
8370 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
8371 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
8372 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
8373 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
8374 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8375 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
8376 chipio_set_control_flag(codec,
8377 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8378 chipio_set_control_flag(codec,
8379 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
8380 } else {
8381 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
8382 chipio_set_control_flag(codec,
8383 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
8384 chipio_set_control_flag(codec,
8385 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
8386 chipio_set_control_flag(codec,
8387 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
8388 chipio_set_control_flag(codec,
8389 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
8390 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
8391 }
8392 }
8393
8394 /*
8395 * Initialization of parameters in chip
8396 */
ca0132_init_params(struct hda_codec * codec)8397 static void ca0132_init_params(struct hda_codec *codec)
8398 {
8399 struct ca0132_spec *spec = codec->spec;
8400
8401 if (ca0132_use_alt_functions(spec)) {
8402 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8403 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
8404 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
8405 chipio_set_control_param(codec, 0, 0);
8406 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
8407 }
8408
8409 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
8410 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
8411 }
8412
ca0132_set_dsp_msr(struct hda_codec * codec,bool is96k)8413 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
8414 {
8415 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
8416 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
8417 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
8418 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
8419 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
8420 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
8421
8422 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
8423 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
8424 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
8425 }
8426
ca0132_download_dsp_images(struct hda_codec * codec)8427 static bool ca0132_download_dsp_images(struct hda_codec *codec)
8428 {
8429 bool dsp_loaded = false;
8430 struct ca0132_spec *spec = codec->spec;
8431 const struct dsp_image_seg *dsp_os_image;
8432 const struct firmware *fw_entry = NULL;
8433 /*
8434 * Alternate firmwares for different variants. The Recon3Di apparently
8435 * can use the default firmware, but I'll leave the option in case
8436 * it needs it again.
8437 */
8438 switch (ca0132_quirk(spec)) {
8439 case QUIRK_SBZ:
8440 case QUIRK_R3D:
8441 case QUIRK_AE5:
8442 if (request_firmware(&fw_entry, DESKTOP_EFX_FILE,
8443 codec->card->dev) != 0)
8444 codec_dbg(codec, "Desktop firmware not found.");
8445 else
8446 codec_dbg(codec, "Desktop firmware selected.");
8447 break;
8448 case QUIRK_R3DI:
8449 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
8450 codec->card->dev) != 0)
8451 codec_dbg(codec, "Recon3Di alt firmware not detected.");
8452 else
8453 codec_dbg(codec, "Recon3Di firmware selected.");
8454 break;
8455 default:
8456 break;
8457 }
8458 /*
8459 * Use default ctefx.bin if no alt firmware is detected, or if none
8460 * exists for your particular codec.
8461 */
8462 if (!fw_entry) {
8463 codec_dbg(codec, "Default firmware selected.");
8464 if (request_firmware(&fw_entry, EFX_FILE,
8465 codec->card->dev) != 0)
8466 return false;
8467 }
8468
8469 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
8470 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
8471 codec_err(codec, "ca0132 DSP load image failed\n");
8472 goto exit_download;
8473 }
8474
8475 dsp_loaded = dspload_wait_loaded(codec);
8476
8477 exit_download:
8478 release_firmware(fw_entry);
8479
8480 return dsp_loaded;
8481 }
8482
ca0132_download_dsp(struct hda_codec * codec)8483 static void ca0132_download_dsp(struct hda_codec *codec)
8484 {
8485 struct ca0132_spec *spec = codec->spec;
8486
8487 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
8488 return; /* NOP */
8489 #endif
8490
8491 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
8492 return; /* don't retry failures */
8493
8494 chipio_enable_clocks(codec);
8495 if (spec->dsp_state != DSP_DOWNLOADED) {
8496 spec->dsp_state = DSP_DOWNLOADING;
8497
8498 if (!ca0132_download_dsp_images(codec))
8499 spec->dsp_state = DSP_DOWNLOAD_FAILED;
8500 else
8501 spec->dsp_state = DSP_DOWNLOADED;
8502 }
8503
8504 /* For codecs using alt functions, this is already done earlier */
8505 if (spec->dsp_state == DSP_DOWNLOADED && !ca0132_use_alt_functions(spec))
8506 ca0132_set_dsp_msr(codec, true);
8507 }
8508
ca0132_process_dsp_response(struct hda_codec * codec,struct hda_jack_callback * callback)8509 static void ca0132_process_dsp_response(struct hda_codec *codec,
8510 struct hda_jack_callback *callback)
8511 {
8512 struct ca0132_spec *spec = codec->spec;
8513
8514 codec_dbg(codec, "ca0132_process_dsp_response\n");
8515 snd_hda_power_up_pm(codec);
8516 if (spec->wait_scp) {
8517 if (dspio_get_response_data(codec) >= 0)
8518 spec->wait_scp = 0;
8519 }
8520
8521 dspio_clear_response_queue(codec);
8522 snd_hda_power_down_pm(codec);
8523 }
8524
hp_callback(struct hda_codec * codec,struct hda_jack_callback * cb)8525 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8526 {
8527 struct ca0132_spec *spec = codec->spec;
8528 struct hda_jack_tbl *tbl;
8529
8530 /* Delay enabling the HP amp, to let the mic-detection
8531 * state machine run.
8532 */
8533 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
8534 if (tbl)
8535 tbl->block_report = 1;
8536 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
8537 }
8538
amic_callback(struct hda_codec * codec,struct hda_jack_callback * cb)8539 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
8540 {
8541 struct ca0132_spec *spec = codec->spec;
8542
8543 if (ca0132_use_alt_functions(spec))
8544 ca0132_alt_select_in(codec);
8545 else
8546 ca0132_select_mic(codec);
8547 }
8548
ca0132_init_unsol(struct hda_codec * codec)8549 static void ca0132_init_unsol(struct hda_codec *codec)
8550 {
8551 struct ca0132_spec *spec = codec->spec;
8552 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
8553 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
8554 amic_callback);
8555 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
8556 ca0132_process_dsp_response);
8557 /* Front headphone jack detection */
8558 if (ca0132_use_alt_functions(spec))
8559 snd_hda_jack_detect_enable_callback(codec,
8560 spec->unsol_tag_front_hp, hp_callback);
8561 }
8562
8563 /*
8564 * Verbs tables.
8565 */
8566
8567 /* Sends before DSP download. */
8568 static const struct hda_verb ca0132_base_init_verbs[] = {
8569 /*enable ct extension*/
8570 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
8571 {}
8572 };
8573
8574 /* Send at exit. */
8575 static const struct hda_verb ca0132_base_exit_verbs[] = {
8576 /*set afg to D3*/
8577 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
8578 /*disable ct extension*/
8579 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
8580 {}
8581 };
8582
8583 /* Other verbs tables. Sends after DSP download. */
8584
8585 static const struct hda_verb ca0132_init_verbs0[] = {
8586 /* chip init verbs */
8587 {0x15, 0x70D, 0xF0},
8588 {0x15, 0x70E, 0xFE},
8589 {0x15, 0x707, 0x75},
8590 {0x15, 0x707, 0xD3},
8591 {0x15, 0x707, 0x09},
8592 {0x15, 0x707, 0x53},
8593 {0x15, 0x707, 0xD4},
8594 {0x15, 0x707, 0xEF},
8595 {0x15, 0x707, 0x75},
8596 {0x15, 0x707, 0xD3},
8597 {0x15, 0x707, 0x09},
8598 {0x15, 0x707, 0x02},
8599 {0x15, 0x707, 0x37},
8600 {0x15, 0x707, 0x78},
8601 {0x15, 0x53C, 0xCE},
8602 {0x15, 0x575, 0xC9},
8603 {0x15, 0x53D, 0xCE},
8604 {0x15, 0x5B7, 0xC9},
8605 {0x15, 0x70D, 0xE8},
8606 {0x15, 0x70E, 0xFE},
8607 {0x15, 0x707, 0x02},
8608 {0x15, 0x707, 0x68},
8609 {0x15, 0x707, 0x62},
8610 {0x15, 0x53A, 0xCE},
8611 {0x15, 0x546, 0xC9},
8612 {0x15, 0x53B, 0xCE},
8613 {0x15, 0x5E8, 0xC9},
8614 {}
8615 };
8616
8617 /* Extra init verbs for desktop cards. */
8618 static const struct hda_verb ca0132_init_verbs1[] = {
8619 {0x15, 0x70D, 0x20},
8620 {0x15, 0x70E, 0x19},
8621 {0x15, 0x707, 0x00},
8622 {0x15, 0x539, 0xCE},
8623 {0x15, 0x546, 0xC9},
8624 {0x15, 0x70D, 0xB7},
8625 {0x15, 0x70E, 0x09},
8626 {0x15, 0x707, 0x10},
8627 {0x15, 0x70D, 0xAF},
8628 {0x15, 0x70E, 0x09},
8629 {0x15, 0x707, 0x01},
8630 {0x15, 0x707, 0x05},
8631 {0x15, 0x70D, 0x73},
8632 {0x15, 0x70E, 0x09},
8633 {0x15, 0x707, 0x14},
8634 {0x15, 0x6FF, 0xC4},
8635 {}
8636 };
8637
ca0132_init_chip(struct hda_codec * codec)8638 static void ca0132_init_chip(struct hda_codec *codec)
8639 {
8640 struct ca0132_spec *spec = codec->spec;
8641 int num_fx;
8642 int i;
8643 unsigned int on;
8644
8645 mutex_init(&spec->chipio_mutex);
8646
8647 spec->cur_out_type = SPEAKER_OUT;
8648 if (!ca0132_use_alt_functions(spec))
8649 spec->cur_mic_type = DIGITAL_MIC;
8650 else
8651 spec->cur_mic_type = REAR_MIC;
8652
8653 spec->cur_mic_boost = 0;
8654
8655 for (i = 0; i < VNODES_COUNT; i++) {
8656 spec->vnode_lvol[i] = 0x5a;
8657 spec->vnode_rvol[i] = 0x5a;
8658 spec->vnode_lswitch[i] = 0;
8659 spec->vnode_rswitch[i] = 0;
8660 }
8661
8662 /*
8663 * Default states for effects are in ca0132_effects[].
8664 */
8665 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
8666 for (i = 0; i < num_fx; i++) {
8667 on = (unsigned int)ca0132_effects[i].reqs[0];
8668 spec->effects_switch[i] = on ? 1 : 0;
8669 }
8670 /*
8671 * Sets defaults for the effect slider controls, only for alternative
8672 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
8673 */
8674 if (ca0132_use_alt_controls(spec)) {
8675 /* Set speakers to default to full range. */
8676 spec->speaker_range_val[0] = 1;
8677 spec->speaker_range_val[1] = 1;
8678
8679 spec->xbass_xover_freq = 8;
8680 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
8681 spec->fx_ctl_val[i] = effect_slider_defaults[i];
8682
8683 spec->bass_redirect_xover_freq = 8;
8684 }
8685
8686 spec->voicefx_val = 0;
8687 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
8688 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
8689
8690 /*
8691 * The ZxR doesn't have a front panel header, and it's line-in is on
8692 * the daughter board. So, there is no input enum control, and we need
8693 * to make sure that spec->in_enum_val is set properly.
8694 */
8695 if (ca0132_quirk(spec) == QUIRK_ZXR)
8696 spec->in_enum_val = REAR_MIC;
8697
8698 #ifdef ENABLE_TUNING_CONTROLS
8699 ca0132_init_tuning_defaults(codec);
8700 #endif
8701 }
8702
8703 /*
8704 * Recon3Di exit specific commands.
8705 */
8706 /* prevents popping noise on shutdown */
r3di_gpio_shutdown(struct hda_codec * codec)8707 static void r3di_gpio_shutdown(struct hda_codec *codec)
8708 {
8709 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
8710 }
8711
8712 /*
8713 * Sound Blaster Z exit specific commands.
8714 */
sbz_region2_exit(struct hda_codec * codec)8715 static void sbz_region2_exit(struct hda_codec *codec)
8716 {
8717 struct ca0132_spec *spec = codec->spec;
8718 unsigned int i;
8719
8720 for (i = 0; i < 4; i++)
8721 writeb(0x0, spec->mem_base + 0x100);
8722 for (i = 0; i < 8; i++)
8723 writeb(0xb3, spec->mem_base + 0x304);
8724
8725 ca0113_mmio_gpio_set(codec, 0, false);
8726 ca0113_mmio_gpio_set(codec, 1, false);
8727 ca0113_mmio_gpio_set(codec, 4, true);
8728 ca0113_mmio_gpio_set(codec, 5, false);
8729 ca0113_mmio_gpio_set(codec, 7, false);
8730 }
8731
sbz_set_pin_ctl_default(struct hda_codec * codec)8732 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
8733 {
8734 static const hda_nid_t pins[] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
8735 unsigned int i;
8736
8737 snd_hda_codec_write(codec, 0x11, 0,
8738 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
8739
8740 for (i = 0; i < ARRAY_SIZE(pins); i++)
8741 snd_hda_codec_write(codec, pins[i], 0,
8742 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
8743 }
8744
ca0132_clear_unsolicited(struct hda_codec * codec)8745 static void ca0132_clear_unsolicited(struct hda_codec *codec)
8746 {
8747 static const hda_nid_t pins[] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
8748 unsigned int i;
8749
8750 for (i = 0; i < ARRAY_SIZE(pins); i++) {
8751 snd_hda_codec_write(codec, pins[i], 0,
8752 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
8753 }
8754 }
8755
8756 /* On shutdown, sends commands in sets of three */
sbz_gpio_shutdown_commands(struct hda_codec * codec,int dir,int mask,int data)8757 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
8758 int mask, int data)
8759 {
8760 if (dir >= 0)
8761 snd_hda_codec_write(codec, 0x01, 0,
8762 AC_VERB_SET_GPIO_DIRECTION, dir);
8763 if (mask >= 0)
8764 snd_hda_codec_write(codec, 0x01, 0,
8765 AC_VERB_SET_GPIO_MASK, mask);
8766
8767 if (data >= 0)
8768 snd_hda_codec_write(codec, 0x01, 0,
8769 AC_VERB_SET_GPIO_DATA, data);
8770 }
8771
zxr_dbpro_power_state_shutdown(struct hda_codec * codec)8772 static void zxr_dbpro_power_state_shutdown(struct hda_codec *codec)
8773 {
8774 static const hda_nid_t pins[] = {0x05, 0x0c, 0x09, 0x0e, 0x08, 0x11, 0x01};
8775 unsigned int i;
8776
8777 for (i = 0; i < ARRAY_SIZE(pins); i++)
8778 snd_hda_codec_write(codec, pins[i], 0,
8779 AC_VERB_SET_POWER_STATE, 0x03);
8780 }
8781
sbz_exit_chip(struct hda_codec * codec)8782 static void sbz_exit_chip(struct hda_codec *codec)
8783 {
8784 chipio_set_stream_control(codec, 0x03, 0);
8785 chipio_set_stream_control(codec, 0x04, 0);
8786
8787 /* Mess with GPIO */
8788 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
8789 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
8790 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
8791
8792 chipio_set_stream_control(codec, 0x14, 0);
8793 chipio_set_stream_control(codec, 0x0C, 0);
8794
8795 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8796 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8797
8798 chipio_write(codec, 0x18a020, 0x00000083);
8799
8800 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
8801 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
8802 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
8803
8804 chipio_set_stream_control(codec, 0x0C, 0);
8805
8806 chipio_set_control_param(codec, 0x0D, 0x24);
8807
8808 ca0132_clear_unsolicited(codec);
8809 sbz_set_pin_ctl_default(codec);
8810
8811 snd_hda_codec_write(codec, 0x0B, 0,
8812 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8813
8814 sbz_region2_exit(codec);
8815 }
8816
r3d_exit_chip(struct hda_codec * codec)8817 static void r3d_exit_chip(struct hda_codec *codec)
8818 {
8819 ca0132_clear_unsolicited(codec);
8820 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8821 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
8822 }
8823
ae5_exit_chip(struct hda_codec * codec)8824 static void ae5_exit_chip(struct hda_codec *codec)
8825 {
8826 chipio_set_stream_control(codec, 0x03, 0);
8827 chipio_set_stream_control(codec, 0x04, 0);
8828
8829 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8830 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8831 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
8832 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8833 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8834 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x00);
8835 ca0113_mmio_gpio_set(codec, 0, false);
8836 ca0113_mmio_gpio_set(codec, 1, false);
8837
8838 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8839 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8840
8841 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8842
8843 chipio_set_stream_control(codec, 0x18, 0);
8844 chipio_set_stream_control(codec, 0x0c, 0);
8845
8846 snd_hda_codec_write(codec, 0x01, 0, 0x724, 0x83);
8847 }
8848
ae7_exit_chip(struct hda_codec * codec)8849 static void ae7_exit_chip(struct hda_codec *codec)
8850 {
8851 chipio_set_stream_control(codec, 0x18, 0);
8852 chipio_set_stream_source_dest(codec, 0x21, 0xc8, 0xc8);
8853 chipio_set_stream_channels(codec, 0x21, 0);
8854 chipio_set_control_param(codec, CONTROL_PARAM_NODE_ID, 0x09);
8855 chipio_set_control_param(codec, 0x20, 0x01);
8856
8857 chipio_set_control_param(codec, CONTROL_PARAM_ASI, 0);
8858
8859 chipio_set_stream_control(codec, 0x18, 0);
8860 chipio_set_stream_control(codec, 0x0c, 0);
8861
8862 ca0113_mmio_command_set(codec, 0x30, 0x2b, 0x00);
8863 snd_hda_codec_write(codec, 0x15, 0, 0x724, 0x83);
8864 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
8865 ca0113_mmio_command_set(codec, 0x30, 0x30, 0x00);
8866 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x00);
8867 ca0113_mmio_gpio_set(codec, 0, false);
8868 ca0113_mmio_gpio_set(codec, 1, false);
8869 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
8870
8871 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8872 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8873 }
8874
zxr_exit_chip(struct hda_codec * codec)8875 static void zxr_exit_chip(struct hda_codec *codec)
8876 {
8877 chipio_set_stream_control(codec, 0x03, 0);
8878 chipio_set_stream_control(codec, 0x04, 0);
8879 chipio_set_stream_control(codec, 0x14, 0);
8880 chipio_set_stream_control(codec, 0x0C, 0);
8881
8882 chipio_set_conn_rate(codec, 0x41, SR_192_000);
8883 chipio_set_conn_rate(codec, 0x91, SR_192_000);
8884
8885 chipio_write(codec, 0x18a020, 0x00000083);
8886
8887 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
8888 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
8889
8890 ca0132_clear_unsolicited(codec);
8891 sbz_set_pin_ctl_default(codec);
8892 snd_hda_codec_write(codec, 0x0B, 0, AC_VERB_SET_EAPD_BTLENABLE, 0x00);
8893
8894 ca0113_mmio_gpio_set(codec, 5, false);
8895 ca0113_mmio_gpio_set(codec, 2, false);
8896 ca0113_mmio_gpio_set(codec, 3, false);
8897 ca0113_mmio_gpio_set(codec, 0, false);
8898 ca0113_mmio_gpio_set(codec, 4, true);
8899 ca0113_mmio_gpio_set(codec, 0, true);
8900 ca0113_mmio_gpio_set(codec, 5, true);
8901 ca0113_mmio_gpio_set(codec, 2, false);
8902 ca0113_mmio_gpio_set(codec, 3, false);
8903 }
8904
ca0132_exit_chip(struct hda_codec * codec)8905 static void ca0132_exit_chip(struct hda_codec *codec)
8906 {
8907 /* put any chip cleanup stuffs here. */
8908
8909 if (dspload_is_loaded(codec))
8910 dsp_reset(codec);
8911 }
8912
8913 /*
8914 * This fixes a problem that was hard to reproduce. Very rarely, I would
8915 * boot up, and there would be no sound, but the DSP indicated it had loaded
8916 * properly. I did a few memory dumps to see if anything was different, and
8917 * there were a few areas of memory uninitialized with a1a2a3a4. This function
8918 * checks if those areas are uninitialized, and if they are, it'll attempt to
8919 * reload the card 3 times. Usually it fixes by the second.
8920 */
sbz_dsp_startup_check(struct hda_codec * codec)8921 static void sbz_dsp_startup_check(struct hda_codec *codec)
8922 {
8923 struct ca0132_spec *spec = codec->spec;
8924 unsigned int dsp_data_check[4];
8925 unsigned int cur_address = 0x390;
8926 unsigned int i;
8927 unsigned int failure = 0;
8928 unsigned int reload = 3;
8929
8930 if (spec->startup_check_entered)
8931 return;
8932
8933 spec->startup_check_entered = true;
8934
8935 for (i = 0; i < 4; i++) {
8936 chipio_read(codec, cur_address, &dsp_data_check[i]);
8937 cur_address += 0x4;
8938 }
8939 for (i = 0; i < 4; i++) {
8940 if (dsp_data_check[i] == 0xa1a2a3a4)
8941 failure = 1;
8942 }
8943
8944 codec_dbg(codec, "Startup Check: %d ", failure);
8945 if (failure)
8946 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
8947 /*
8948 * While the failure condition is true, and we haven't reached our
8949 * three reload limit, continue trying to reload the driver and
8950 * fix the issue.
8951 */
8952 while (failure && (reload != 0)) {
8953 codec_info(codec, "Reloading... Tries left: %d", reload);
8954 sbz_exit_chip(codec);
8955 spec->dsp_state = DSP_DOWNLOAD_INIT;
8956 codec->patch_ops.init(codec);
8957 failure = 0;
8958 for (i = 0; i < 4; i++) {
8959 chipio_read(codec, cur_address, &dsp_data_check[i]);
8960 cur_address += 0x4;
8961 }
8962 for (i = 0; i < 4; i++) {
8963 if (dsp_data_check[i] == 0xa1a2a3a4)
8964 failure = 1;
8965 }
8966 reload--;
8967 }
8968
8969 if (!failure && reload < 3)
8970 codec_info(codec, "DSP fixed.");
8971
8972 if (!failure)
8973 return;
8974
8975 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
8976 }
8977
8978 /*
8979 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
8980 * extra precision for decibel values. If you had the dB value in floating point
8981 * you would take the value after the decimal point, multiply by 64, and divide
8982 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
8983 * implement fixed point or floating point dB volumes. For now, I'll set them
8984 * to 0 just incase a value has lingered from a boot into Windows.
8985 */
ca0132_alt_vol_setup(struct hda_codec * codec)8986 static void ca0132_alt_vol_setup(struct hda_codec *codec)
8987 {
8988 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
8989 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
8990 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
8991 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
8992 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
8993 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
8994 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
8995 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
8996 }
8997
8998 /*
8999 * Extra commands that don't really fit anywhere else.
9000 */
sbz_pre_dsp_setup(struct hda_codec * codec)9001 static void sbz_pre_dsp_setup(struct hda_codec *codec)
9002 {
9003 struct ca0132_spec *spec = codec->spec;
9004
9005 writel(0x00820680, spec->mem_base + 0x01C);
9006 writel(0x00820680, spec->mem_base + 0x01C);
9007
9008 chipio_write(codec, 0x18b0a4, 0x000000c2);
9009
9010 snd_hda_codec_write(codec, 0x11, 0,
9011 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9012 }
9013
r3d_pre_dsp_setup(struct hda_codec * codec)9014 static void r3d_pre_dsp_setup(struct hda_codec *codec)
9015 {
9016 chipio_write(codec, 0x18b0a4, 0x000000c2);
9017
9018 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9019 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
9020 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9021 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
9022 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9023 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
9024
9025 snd_hda_codec_write(codec, 0x11, 0,
9026 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
9027 }
9028
r3di_pre_dsp_setup(struct hda_codec * codec)9029 static void r3di_pre_dsp_setup(struct hda_codec *codec)
9030 {
9031 chipio_write(codec, 0x18b0a4, 0x000000c2);
9032
9033 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9034 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
9035 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9036 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
9037 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9038 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
9039
9040 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9041 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
9042 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9043 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
9044 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9045 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
9046 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9047 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
9048
9049 snd_hda_codec_write(codec, 0x11, 0,
9050 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
9051 }
9052
9053 /*
9054 * These are sent before the DSP is downloaded. Not sure
9055 * what they do, or if they're necessary. Could possibly
9056 * be removed. Figure they're better to leave in.
9057 */
9058 static const unsigned int ca0113_mmio_init_address_sbz[] = {
9059 0x400, 0x408, 0x40c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c,
9060 0xc0c, 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04
9061 };
9062
9063 static const unsigned int ca0113_mmio_init_data_sbz[] = {
9064 0x00000030, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9065 0x00000003, 0x000000c1, 0x000000f1, 0x00000001, 0x000000c7,
9066 0x000000c1, 0x00000080
9067 };
9068
9069 static const unsigned int ca0113_mmio_init_data_zxr[] = {
9070 0x00000030, 0x00000000, 0x00000000, 0x00000003, 0x00000003,
9071 0x00000003, 0x00000001, 0x000000f1, 0x00000001, 0x000000c7,
9072 0x000000c1, 0x00000080
9073 };
9074
9075 static const unsigned int ca0113_mmio_init_address_ae5[] = {
9076 0x400, 0x42c, 0x46c, 0x4ac, 0x4ec, 0x43c, 0x47c, 0x4bc, 0x4fc, 0x408,
9077 0x100, 0x410, 0x40c, 0x100, 0x100, 0x830, 0x86c, 0x800, 0x86c, 0x800,
9078 0x804, 0x20c, 0x01c, 0xc0c, 0xc00, 0xc04, 0xc0c, 0xc0c, 0xc0c, 0xc0c,
9079 0xc08, 0xc08, 0xc08, 0xc08, 0xc08, 0xc04, 0x01c
9080 };
9081
9082 static const unsigned int ca0113_mmio_init_data_ae5[] = {
9083 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
9084 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000001,
9085 0x00000600, 0x00000014, 0x00000001, 0x0000060f, 0x0000070f,
9086 0x00000aff, 0x00000000, 0x0000006b, 0x00000001, 0x0000006b,
9087 0x00000057, 0x00800000, 0x00880680, 0x00000080, 0x00000030,
9088 0x00000000, 0x00000000, 0x00000003, 0x00000003, 0x00000003,
9089 0x00000001, 0x000000f1, 0x00000001, 0x000000c7, 0x000000c1,
9090 0x00000080, 0x00880680
9091 };
9092
ca0132_mmio_init_sbz(struct hda_codec * codec)9093 static void ca0132_mmio_init_sbz(struct hda_codec *codec)
9094 {
9095 struct ca0132_spec *spec = codec->spec;
9096 unsigned int tmp[2], i, count, cur_addr;
9097 const unsigned int *addr, *data;
9098
9099 addr = ca0113_mmio_init_address_sbz;
9100 for (i = 0; i < 3; i++)
9101 writel(0x00000000, spec->mem_base + addr[i]);
9102
9103 cur_addr = i;
9104 switch (ca0132_quirk(spec)) {
9105 case QUIRK_ZXR:
9106 tmp[0] = 0x00880480;
9107 tmp[1] = 0x00000080;
9108 break;
9109 case QUIRK_SBZ:
9110 tmp[0] = 0x00820680;
9111 tmp[1] = 0x00000083;
9112 break;
9113 case QUIRK_R3D:
9114 tmp[0] = 0x00880680;
9115 tmp[1] = 0x00000083;
9116 break;
9117 default:
9118 tmp[0] = 0x00000000;
9119 tmp[1] = 0x00000000;
9120 break;
9121 }
9122
9123 for (i = 0; i < 2; i++)
9124 writel(tmp[i], spec->mem_base + addr[cur_addr + i]);
9125
9126 cur_addr += i;
9127
9128 switch (ca0132_quirk(spec)) {
9129 case QUIRK_ZXR:
9130 count = ARRAY_SIZE(ca0113_mmio_init_data_zxr);
9131 data = ca0113_mmio_init_data_zxr;
9132 break;
9133 default:
9134 count = ARRAY_SIZE(ca0113_mmio_init_data_sbz);
9135 data = ca0113_mmio_init_data_sbz;
9136 break;
9137 }
9138
9139 for (i = 0; i < count; i++)
9140 writel(data[i], spec->mem_base + addr[cur_addr + i]);
9141 }
9142
ca0132_mmio_init_ae5(struct hda_codec * codec)9143 static void ca0132_mmio_init_ae5(struct hda_codec *codec)
9144 {
9145 struct ca0132_spec *spec = codec->spec;
9146 const unsigned int *addr, *data;
9147 unsigned int i, count;
9148
9149 addr = ca0113_mmio_init_address_ae5;
9150 data = ca0113_mmio_init_data_ae5;
9151 count = ARRAY_SIZE(ca0113_mmio_init_data_ae5);
9152
9153 if (ca0132_quirk(spec) == QUIRK_AE7) {
9154 writel(0x00000680, spec->mem_base + 0x1c);
9155 writel(0x00880680, spec->mem_base + 0x1c);
9156 }
9157
9158 for (i = 0; i < count; i++) {
9159 /*
9160 * AE-7 shares all writes with the AE-5, except that it writes
9161 * a different value to 0x20c.
9162 */
9163 if (i == 21 && ca0132_quirk(spec) == QUIRK_AE7) {
9164 writel(0x00800001, spec->mem_base + addr[i]);
9165 continue;
9166 }
9167
9168 writel(data[i], spec->mem_base + addr[i]);
9169 }
9170
9171 if (ca0132_quirk(spec) == QUIRK_AE5)
9172 writel(0x00880680, spec->mem_base + 0x1c);
9173 }
9174
ca0132_mmio_init(struct hda_codec * codec)9175 static void ca0132_mmio_init(struct hda_codec *codec)
9176 {
9177 struct ca0132_spec *spec = codec->spec;
9178
9179 switch (ca0132_quirk(spec)) {
9180 case QUIRK_R3D:
9181 case QUIRK_SBZ:
9182 case QUIRK_ZXR:
9183 ca0132_mmio_init_sbz(codec);
9184 break;
9185 case QUIRK_AE5:
9186 ca0132_mmio_init_ae5(codec);
9187 break;
9188 default:
9189 break;
9190 }
9191 }
9192
9193 static const unsigned int ca0132_ae5_register_set_addresses[] = {
9194 0x304, 0x304, 0x304, 0x304, 0x100, 0x304, 0x100, 0x304, 0x100, 0x304,
9195 0x100, 0x304, 0x86c, 0x800, 0x86c, 0x800, 0x804
9196 };
9197
9198 static const unsigned char ca0132_ae5_register_set_data[] = {
9199 0x0f, 0x0e, 0x1f, 0x0c, 0x3f, 0x08, 0x7f, 0x00, 0xff, 0x00, 0x6b,
9200 0x01, 0x6b, 0x57
9201 };
9202
9203 /*
9204 * This function writes to some SFR's, does some region2 writes, and then
9205 * eventually resets the codec with the 0x7ff verb. Not quite sure why it does
9206 * what it does.
9207 */
ae5_register_set(struct hda_codec * codec)9208 static void ae5_register_set(struct hda_codec *codec)
9209 {
9210 struct ca0132_spec *spec = codec->spec;
9211 unsigned int count = ARRAY_SIZE(ca0132_ae5_register_set_addresses);
9212 const unsigned int *addr = ca0132_ae5_register_set_addresses;
9213 const unsigned char *data = ca0132_ae5_register_set_data;
9214 unsigned int i, cur_addr;
9215 unsigned char tmp[3];
9216
9217 if (ca0132_quirk(spec) == QUIRK_AE7) {
9218 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9219 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x41);
9220 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9221 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc8);
9222 }
9223
9224 chipio_8051_write_direct(codec, 0x93, 0x10);
9225 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9226 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x44);
9227 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9228 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xc2);
9229
9230 if (ca0132_quirk(spec) == QUIRK_AE7) {
9231 tmp[0] = 0x03;
9232 tmp[1] = 0x03;
9233 tmp[2] = 0x07;
9234 } else {
9235 tmp[0] = 0x0f;
9236 tmp[1] = 0x0f;
9237 tmp[2] = 0x0f;
9238 }
9239
9240 for (i = cur_addr = 0; i < 3; i++, cur_addr++)
9241 writeb(tmp[i], spec->mem_base + addr[cur_addr]);
9242
9243 /*
9244 * First writes are in single bytes, final are in 4 bytes. So, we use
9245 * writeb, then writel.
9246 */
9247 for (i = 0; cur_addr < 12; i++, cur_addr++)
9248 writeb(data[i], spec->mem_base + addr[cur_addr]);
9249
9250 for (; cur_addr < count; i++, cur_addr++)
9251 writel(data[i], spec->mem_base + addr[cur_addr]);
9252
9253 writel(0x00800001, spec->mem_base + 0x20c);
9254
9255 if (ca0132_quirk(spec) == QUIRK_AE7) {
9256 ca0113_mmio_command_set_type2(codec, 0x48, 0x07, 0x83);
9257 ca0113_mmio_command_set(codec, 0x30, 0x2e, 0x3f);
9258 } else {
9259 ca0113_mmio_command_set(codec, 0x30, 0x2d, 0x3f);
9260 }
9261
9262 chipio_8051_write_direct(codec, 0x90, 0x00);
9263 chipio_8051_write_direct(codec, 0x90, 0x10);
9264
9265 if (ca0132_quirk(spec) == QUIRK_AE5)
9266 ca0113_mmio_command_set(codec, 0x48, 0x07, 0x83);
9267
9268 chipio_write(codec, 0x18b0a4, 0x000000c2);
9269
9270 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
9271 snd_hda_codec_write(codec, 0x01, 0, 0x7ff, 0x00);
9272 }
9273
9274 /*
9275 * Extra init functions for alternative ca0132 codecs. Done
9276 * here so they don't clutter up the main ca0132_init function
9277 * anymore than they have to.
9278 */
ca0132_alt_init(struct hda_codec * codec)9279 static void ca0132_alt_init(struct hda_codec *codec)
9280 {
9281 struct ca0132_spec *spec = codec->spec;
9282
9283 ca0132_alt_vol_setup(codec);
9284
9285 switch (ca0132_quirk(spec)) {
9286 case QUIRK_SBZ:
9287 codec_dbg(codec, "SBZ alt_init");
9288 ca0132_gpio_init(codec);
9289 sbz_pre_dsp_setup(codec);
9290 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9291 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9292 break;
9293 case QUIRK_R3DI:
9294 codec_dbg(codec, "R3DI alt_init");
9295 ca0132_gpio_init(codec);
9296 ca0132_gpio_setup(codec);
9297 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
9298 r3di_pre_dsp_setup(codec);
9299 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9300 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
9301 break;
9302 case QUIRK_R3D:
9303 r3d_pre_dsp_setup(codec);
9304 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9305 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9306 break;
9307 case QUIRK_AE5:
9308 ca0132_gpio_init(codec);
9309 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9310 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
9311 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9312 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
9313 chipio_write(codec, 0x18b030, 0x00000020);
9314 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9315 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9316 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9317 break;
9318 case QUIRK_AE7:
9319 ca0132_gpio_init(codec);
9320 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9321 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x49);
9322 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9323 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x88);
9324 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9325 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9326 chipio_write(codec, 0x18b008, 0x000000f8);
9327 chipio_write(codec, 0x18b008, 0x000000f0);
9328 chipio_write(codec, 0x18b030, 0x00000020);
9329 ca0113_mmio_command_set(codec, 0x30, 0x32, 0x3f);
9330 break;
9331 case QUIRK_ZXR:
9332 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9333 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
9334 break;
9335 default:
9336 break;
9337 }
9338 }
9339
ca0132_init(struct hda_codec * codec)9340 static int ca0132_init(struct hda_codec *codec)
9341 {
9342 struct ca0132_spec *spec = codec->spec;
9343 struct auto_pin_cfg *cfg = &spec->autocfg;
9344 int i;
9345 bool dsp_loaded;
9346
9347 /*
9348 * If the DSP is already downloaded, and init has been entered again,
9349 * there's only two reasons for it. One, the codec has awaken from a
9350 * suspended state, and in that case dspload_is_loaded will return
9351 * false, and the init will be ran again. The other reason it gets
9352 * re entered is on startup for some reason it triggers a suspend and
9353 * resume state. In this case, it will check if the DSP is downloaded,
9354 * and not run the init function again. For codecs using alt_functions,
9355 * it will check if the DSP is loaded properly.
9356 */
9357 if (spec->dsp_state == DSP_DOWNLOADED) {
9358 dsp_loaded = dspload_is_loaded(codec);
9359 if (!dsp_loaded) {
9360 spec->dsp_reload = true;
9361 spec->dsp_state = DSP_DOWNLOAD_INIT;
9362 } else {
9363 if (ca0132_quirk(spec) == QUIRK_SBZ)
9364 sbz_dsp_startup_check(codec);
9365 return 0;
9366 }
9367 }
9368
9369 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
9370 spec->dsp_state = DSP_DOWNLOAD_INIT;
9371 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
9372
9373 if (ca0132_use_pci_mmio(spec))
9374 ca0132_mmio_init(codec);
9375
9376 snd_hda_power_up_pm(codec);
9377
9378 if (ca0132_quirk(spec) == QUIRK_AE5 || ca0132_quirk(spec) == QUIRK_AE7)
9379 ae5_register_set(codec);
9380
9381 ca0132_init_unsol(codec);
9382 ca0132_init_params(codec);
9383 ca0132_init_flags(codec);
9384
9385 snd_hda_sequence_write(codec, spec->base_init_verbs);
9386
9387 if (ca0132_use_alt_functions(spec))
9388 ca0132_alt_init(codec);
9389
9390 ca0132_download_dsp(codec);
9391
9392 ca0132_refresh_widget_caps(codec);
9393
9394 switch (ca0132_quirk(spec)) {
9395 case QUIRK_R3DI:
9396 case QUIRK_R3D:
9397 r3d_setup_defaults(codec);
9398 break;
9399 case QUIRK_SBZ:
9400 case QUIRK_ZXR:
9401 sbz_setup_defaults(codec);
9402 break;
9403 case QUIRK_AE5:
9404 ae5_setup_defaults(codec);
9405 break;
9406 case QUIRK_AE7:
9407 ae7_setup_defaults(codec);
9408 break;
9409 default:
9410 ca0132_setup_defaults(codec);
9411 ca0132_init_analog_mic2(codec);
9412 ca0132_init_dmic(codec);
9413 break;
9414 }
9415
9416 for (i = 0; i < spec->num_outputs; i++)
9417 init_output(codec, spec->out_pins[i], spec->dacs[0]);
9418
9419 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9420
9421 for (i = 0; i < spec->num_inputs; i++)
9422 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9423
9424 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9425
9426 if (!ca0132_use_alt_functions(spec)) {
9427 snd_hda_sequence_write(codec, spec->chip_init_verbs);
9428 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9429 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
9430 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
9431 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
9432 }
9433
9434 if (ca0132_quirk(spec) == QUIRK_SBZ)
9435 ca0132_gpio_setup(codec);
9436
9437 snd_hda_sequence_write(codec, spec->spec_init_verbs);
9438 if (ca0132_use_alt_functions(spec)) {
9439 ca0132_alt_select_out(codec);
9440 ca0132_alt_select_in(codec);
9441 } else {
9442 ca0132_select_out(codec);
9443 ca0132_select_mic(codec);
9444 }
9445
9446 snd_hda_jack_report_sync(codec);
9447
9448 /*
9449 * Re set the PlayEnhancement switch on a resume event, because the
9450 * controls will not be reloaded.
9451 */
9452 if (spec->dsp_reload) {
9453 spec->dsp_reload = false;
9454 ca0132_pe_switch_set(codec);
9455 }
9456
9457 snd_hda_power_down_pm(codec);
9458
9459 return 0;
9460 }
9461
dbpro_init(struct hda_codec * codec)9462 static int dbpro_init(struct hda_codec *codec)
9463 {
9464 struct ca0132_spec *spec = codec->spec;
9465 struct auto_pin_cfg *cfg = &spec->autocfg;
9466 unsigned int i;
9467
9468 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
9469 init_input(codec, cfg->dig_in_pin, spec->dig_in);
9470
9471 for (i = 0; i < spec->num_inputs; i++)
9472 init_input(codec, spec->input_pins[i], spec->adcs[i]);
9473
9474 return 0;
9475 }
9476
ca0132_free(struct hda_codec * codec)9477 static void ca0132_free(struct hda_codec *codec)
9478 {
9479 struct ca0132_spec *spec = codec->spec;
9480
9481 cancel_delayed_work_sync(&spec->unsol_hp_work);
9482 snd_hda_power_up(codec);
9483 switch (ca0132_quirk(spec)) {
9484 case QUIRK_SBZ:
9485 sbz_exit_chip(codec);
9486 break;
9487 case QUIRK_ZXR:
9488 zxr_exit_chip(codec);
9489 break;
9490 case QUIRK_R3D:
9491 r3d_exit_chip(codec);
9492 break;
9493 case QUIRK_AE5:
9494 ae5_exit_chip(codec);
9495 break;
9496 case QUIRK_AE7:
9497 ae7_exit_chip(codec);
9498 break;
9499 case QUIRK_R3DI:
9500 r3di_gpio_shutdown(codec);
9501 break;
9502 default:
9503 break;
9504 }
9505
9506 snd_hda_sequence_write(codec, spec->base_exit_verbs);
9507 ca0132_exit_chip(codec);
9508
9509 snd_hda_power_down(codec);
9510 #ifdef CONFIG_PCI
9511 if (spec->mem_base)
9512 pci_iounmap(codec->bus->pci, spec->mem_base);
9513 #endif
9514 kfree(spec->spec_init_verbs);
9515 kfree(codec->spec);
9516 }
9517
dbpro_free(struct hda_codec * codec)9518 static void dbpro_free(struct hda_codec *codec)
9519 {
9520 struct ca0132_spec *spec = codec->spec;
9521
9522 zxr_dbpro_power_state_shutdown(codec);
9523
9524 kfree(spec->spec_init_verbs);
9525 kfree(codec->spec);
9526 }
9527
ca0132_reboot_notify(struct hda_codec * codec)9528 static void ca0132_reboot_notify(struct hda_codec *codec)
9529 {
9530 codec->patch_ops.free(codec);
9531 }
9532
9533 #ifdef CONFIG_PM
ca0132_suspend(struct hda_codec * codec)9534 static int ca0132_suspend(struct hda_codec *codec)
9535 {
9536 struct ca0132_spec *spec = codec->spec;
9537
9538 cancel_delayed_work_sync(&spec->unsol_hp_work);
9539 return 0;
9540 }
9541 #endif
9542
9543 static const struct hda_codec_ops ca0132_patch_ops = {
9544 .build_controls = ca0132_build_controls,
9545 .build_pcms = ca0132_build_pcms,
9546 .init = ca0132_init,
9547 .free = ca0132_free,
9548 .unsol_event = snd_hda_jack_unsol_event,
9549 #ifdef CONFIG_PM
9550 .suspend = ca0132_suspend,
9551 #endif
9552 .reboot_notify = ca0132_reboot_notify,
9553 };
9554
9555 static const struct hda_codec_ops dbpro_patch_ops = {
9556 .build_controls = dbpro_build_controls,
9557 .build_pcms = dbpro_build_pcms,
9558 .init = dbpro_init,
9559 .free = dbpro_free,
9560 };
9561
ca0132_config(struct hda_codec * codec)9562 static void ca0132_config(struct hda_codec *codec)
9563 {
9564 struct ca0132_spec *spec = codec->spec;
9565
9566 spec->dacs[0] = 0x2;
9567 spec->dacs[1] = 0x3;
9568 spec->dacs[2] = 0x4;
9569
9570 spec->multiout.dac_nids = spec->dacs;
9571 spec->multiout.num_dacs = 3;
9572
9573 if (!ca0132_use_alt_functions(spec))
9574 spec->multiout.max_channels = 2;
9575 else
9576 spec->multiout.max_channels = 6;
9577
9578 switch (ca0132_quirk(spec)) {
9579 case QUIRK_ALIENWARE:
9580 codec_dbg(codec, "%s: QUIRK_ALIENWARE applied.\n", __func__);
9581 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
9582 break;
9583 case QUIRK_SBZ:
9584 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
9585 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
9586 break;
9587 case QUIRK_ZXR:
9588 codec_dbg(codec, "%s: QUIRK_ZXR applied.\n", __func__);
9589 snd_hda_apply_pincfgs(codec, zxr_pincfgs);
9590 break;
9591 case QUIRK_R3D:
9592 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
9593 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
9594 break;
9595 case QUIRK_R3DI:
9596 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
9597 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
9598 break;
9599 case QUIRK_AE5:
9600 codec_dbg(codec, "%s: QUIRK_AE5 applied.\n", __func__);
9601 snd_hda_apply_pincfgs(codec, ae5_pincfgs);
9602 break;
9603 case QUIRK_AE7:
9604 codec_dbg(codec, "%s: QUIRK_AE7 applied.\n", __func__);
9605 snd_hda_apply_pincfgs(codec, ae7_pincfgs);
9606 break;
9607 default:
9608 break;
9609 }
9610
9611 switch (ca0132_quirk(spec)) {
9612 case QUIRK_ALIENWARE:
9613 spec->num_outputs = 2;
9614 spec->out_pins[0] = 0x0b; /* speaker out */
9615 spec->out_pins[1] = 0x0f;
9616 spec->shared_out_nid = 0x2;
9617 spec->unsol_tag_hp = 0x0f;
9618
9619 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9620 spec->adcs[1] = 0x8; /* analog mic2 */
9621 spec->adcs[2] = 0xa; /* what u hear */
9622
9623 spec->num_inputs = 3;
9624 spec->input_pins[0] = 0x12;
9625 spec->input_pins[1] = 0x11;
9626 spec->input_pins[2] = 0x13;
9627 spec->shared_mic_nid = 0x7;
9628 spec->unsol_tag_amic1 = 0x11;
9629 break;
9630 case QUIRK_SBZ:
9631 case QUIRK_R3D:
9632 spec->num_outputs = 2;
9633 spec->out_pins[0] = 0x0B; /* Line out */
9634 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9635 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9636 spec->out_pins[3] = 0x11; /* Rear surround */
9637 spec->shared_out_nid = 0x2;
9638 spec->unsol_tag_hp = spec->out_pins[1];
9639 spec->unsol_tag_front_hp = spec->out_pins[2];
9640
9641 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9642 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9643 spec->adcs[2] = 0xa; /* what u hear */
9644
9645 spec->num_inputs = 2;
9646 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9647 spec->input_pins[1] = 0x13; /* What U Hear */
9648 spec->shared_mic_nid = 0x7;
9649 spec->unsol_tag_amic1 = spec->input_pins[0];
9650
9651 /* SPDIF I/O */
9652 spec->dig_out = 0x05;
9653 spec->multiout.dig_out_nid = spec->dig_out;
9654 spec->dig_in = 0x09;
9655 break;
9656 case QUIRK_ZXR:
9657 spec->num_outputs = 2;
9658 spec->out_pins[0] = 0x0B; /* Line out */
9659 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9660 spec->out_pins[2] = 0x10; /* Center/LFE */
9661 spec->out_pins[3] = 0x11; /* Rear surround */
9662 spec->shared_out_nid = 0x2;
9663 spec->unsol_tag_hp = spec->out_pins[1];
9664 spec->unsol_tag_front_hp = spec->out_pins[2];
9665
9666 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9667 spec->adcs[1] = 0x8; /* Not connected, no front mic */
9668 spec->adcs[2] = 0xa; /* what u hear */
9669
9670 spec->num_inputs = 2;
9671 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9672 spec->input_pins[1] = 0x13; /* What U Hear */
9673 spec->shared_mic_nid = 0x7;
9674 spec->unsol_tag_amic1 = spec->input_pins[0];
9675 break;
9676 case QUIRK_ZXR_DBPRO:
9677 spec->adcs[0] = 0x8; /* ZxR DBPro Aux In */
9678
9679 spec->num_inputs = 1;
9680 spec->input_pins[0] = 0x11; /* RCA Line-in */
9681
9682 spec->dig_out = 0x05;
9683 spec->multiout.dig_out_nid = spec->dig_out;
9684
9685 spec->dig_in = 0x09;
9686 break;
9687 case QUIRK_AE5:
9688 case QUIRK_AE7:
9689 spec->num_outputs = 2;
9690 spec->out_pins[0] = 0x0B; /* Line out */
9691 spec->out_pins[1] = 0x11; /* Rear headphone out */
9692 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9693 spec->out_pins[3] = 0x0F; /* Rear surround */
9694 spec->shared_out_nid = 0x2;
9695 spec->unsol_tag_hp = spec->out_pins[1];
9696 spec->unsol_tag_front_hp = spec->out_pins[2];
9697
9698 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
9699 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
9700 spec->adcs[2] = 0xa; /* what u hear */
9701
9702 spec->num_inputs = 2;
9703 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9704 spec->input_pins[1] = 0x13; /* What U Hear */
9705 spec->shared_mic_nid = 0x7;
9706 spec->unsol_tag_amic1 = spec->input_pins[0];
9707
9708 /* SPDIF I/O */
9709 spec->dig_out = 0x05;
9710 spec->multiout.dig_out_nid = spec->dig_out;
9711 break;
9712 case QUIRK_R3DI:
9713 spec->num_outputs = 2;
9714 spec->out_pins[0] = 0x0B; /* Line out */
9715 spec->out_pins[1] = 0x0F; /* Rear headphone out */
9716 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
9717 spec->out_pins[3] = 0x11; /* Rear surround */
9718 spec->shared_out_nid = 0x2;
9719 spec->unsol_tag_hp = spec->out_pins[1];
9720 spec->unsol_tag_front_hp = spec->out_pins[2];
9721
9722 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
9723 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
9724 spec->adcs[2] = 0x0a; /* what u hear */
9725
9726 spec->num_inputs = 2;
9727 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
9728 spec->input_pins[1] = 0x13; /* What U Hear */
9729 spec->shared_mic_nid = 0x7;
9730 spec->unsol_tag_amic1 = spec->input_pins[0];
9731
9732 /* SPDIF I/O */
9733 spec->dig_out = 0x05;
9734 spec->multiout.dig_out_nid = spec->dig_out;
9735 break;
9736 default:
9737 spec->num_outputs = 2;
9738 spec->out_pins[0] = 0x0b; /* speaker out */
9739 spec->out_pins[1] = 0x10; /* headphone out */
9740 spec->shared_out_nid = 0x2;
9741 spec->unsol_tag_hp = spec->out_pins[1];
9742
9743 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
9744 spec->adcs[1] = 0x8; /* analog mic2 */
9745 spec->adcs[2] = 0xa; /* what u hear */
9746
9747 spec->num_inputs = 3;
9748 spec->input_pins[0] = 0x12;
9749 spec->input_pins[1] = 0x11;
9750 spec->input_pins[2] = 0x13;
9751 spec->shared_mic_nid = 0x7;
9752 spec->unsol_tag_amic1 = spec->input_pins[0];
9753
9754 /* SPDIF I/O */
9755 spec->dig_out = 0x05;
9756 spec->multiout.dig_out_nid = spec->dig_out;
9757 spec->dig_in = 0x09;
9758 break;
9759 }
9760 }
9761
ca0132_prepare_verbs(struct hda_codec * codec)9762 static int ca0132_prepare_verbs(struct hda_codec *codec)
9763 {
9764 /* Verbs + terminator (an empty element) */
9765 #define NUM_SPEC_VERBS 2
9766 struct ca0132_spec *spec = codec->spec;
9767
9768 spec->chip_init_verbs = ca0132_init_verbs0;
9769 /*
9770 * Since desktop cards use pci_mmio, this can be used to determine
9771 * whether or not to use these verbs instead of a separate bool.
9772 */
9773 if (ca0132_use_pci_mmio(spec))
9774 spec->desktop_init_verbs = ca0132_init_verbs1;
9775 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
9776 sizeof(struct hda_verb),
9777 GFP_KERNEL);
9778 if (!spec->spec_init_verbs)
9779 return -ENOMEM;
9780
9781 /* config EAPD */
9782 spec->spec_init_verbs[0].nid = 0x0b;
9783 spec->spec_init_verbs[0].param = 0x78D;
9784 spec->spec_init_verbs[0].verb = 0x00;
9785
9786 /* Previously commented configuration */
9787 /*
9788 spec->spec_init_verbs[2].nid = 0x0b;
9789 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
9790 spec->spec_init_verbs[2].verb = 0x02;
9791
9792 spec->spec_init_verbs[3].nid = 0x10;
9793 spec->spec_init_verbs[3].param = 0x78D;
9794 spec->spec_init_verbs[3].verb = 0x02;
9795
9796 spec->spec_init_verbs[4].nid = 0x10;
9797 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
9798 spec->spec_init_verbs[4].verb = 0x02;
9799 */
9800
9801 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
9802 return 0;
9803 }
9804
9805 /*
9806 * The Sound Blaster ZxR shares the same PCI subsystem ID as some regular
9807 * Sound Blaster Z cards. However, they have different HDA codec subsystem
9808 * ID's. So, we check for the ZxR's subsystem ID, as well as the DBPro
9809 * daughter boards ID.
9810 */
sbz_detect_quirk(struct hda_codec * codec)9811 static void sbz_detect_quirk(struct hda_codec *codec)
9812 {
9813 struct ca0132_spec *spec = codec->spec;
9814
9815 switch (codec->core.subsystem_id) {
9816 case 0x11020033:
9817 spec->quirk = QUIRK_ZXR;
9818 break;
9819 case 0x1102003f:
9820 spec->quirk = QUIRK_ZXR_DBPRO;
9821 break;
9822 default:
9823 spec->quirk = QUIRK_SBZ;
9824 break;
9825 }
9826 }
9827
patch_ca0132(struct hda_codec * codec)9828 static int patch_ca0132(struct hda_codec *codec)
9829 {
9830 struct ca0132_spec *spec;
9831 int err;
9832 const struct snd_pci_quirk *quirk;
9833
9834 codec_dbg(codec, "patch_ca0132\n");
9835
9836 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
9837 if (!spec)
9838 return -ENOMEM;
9839 codec->spec = spec;
9840 spec->codec = codec;
9841
9842 /* Detect codec quirk */
9843 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
9844 if (quirk)
9845 spec->quirk = quirk->value;
9846 else
9847 spec->quirk = QUIRK_NONE;
9848 if (ca0132_quirk(spec) == QUIRK_SBZ)
9849 sbz_detect_quirk(codec);
9850
9851 if (ca0132_quirk(spec) == QUIRK_ZXR_DBPRO)
9852 codec->patch_ops = dbpro_patch_ops;
9853 else
9854 codec->patch_ops = ca0132_patch_ops;
9855
9856 codec->pcm_format_first = 1;
9857 codec->no_sticky_stream = 1;
9858
9859
9860 spec->dsp_state = DSP_DOWNLOAD_INIT;
9861 spec->num_mixers = 1;
9862
9863 /* Set which mixers each quirk uses. */
9864 switch (ca0132_quirk(spec)) {
9865 case QUIRK_SBZ:
9866 spec->mixers[0] = desktop_mixer;
9867 snd_hda_codec_set_name(codec, "Sound Blaster Z");
9868 break;
9869 case QUIRK_ZXR:
9870 spec->mixers[0] = desktop_mixer;
9871 snd_hda_codec_set_name(codec, "Sound Blaster ZxR");
9872 break;
9873 case QUIRK_ZXR_DBPRO:
9874 break;
9875 case QUIRK_R3D:
9876 spec->mixers[0] = desktop_mixer;
9877 snd_hda_codec_set_name(codec, "Recon3D");
9878 break;
9879 case QUIRK_R3DI:
9880 spec->mixers[0] = r3di_mixer;
9881 snd_hda_codec_set_name(codec, "Recon3Di");
9882 break;
9883 case QUIRK_AE5:
9884 spec->mixers[0] = desktop_mixer;
9885 snd_hda_codec_set_name(codec, "Sound BlasterX AE-5");
9886 break;
9887 case QUIRK_AE7:
9888 spec->mixers[0] = desktop_mixer;
9889 snd_hda_codec_set_name(codec, "Sound Blaster AE-7");
9890 break;
9891 default:
9892 spec->mixers[0] = ca0132_mixer;
9893 break;
9894 }
9895
9896 /* Setup whether or not to use alt functions/controls/pci_mmio */
9897 switch (ca0132_quirk(spec)) {
9898 case QUIRK_SBZ:
9899 case QUIRK_R3D:
9900 case QUIRK_AE5:
9901 case QUIRK_AE7:
9902 case QUIRK_ZXR:
9903 spec->use_alt_controls = true;
9904 spec->use_alt_functions = true;
9905 spec->use_pci_mmio = true;
9906 break;
9907 case QUIRK_R3DI:
9908 spec->use_alt_controls = true;
9909 spec->use_alt_functions = true;
9910 spec->use_pci_mmio = false;
9911 break;
9912 default:
9913 spec->use_alt_controls = false;
9914 spec->use_alt_functions = false;
9915 spec->use_pci_mmio = false;
9916 break;
9917 }
9918
9919 #ifdef CONFIG_PCI
9920 if (spec->use_pci_mmio) {
9921 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
9922 if (spec->mem_base == NULL) {
9923 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
9924 spec->quirk = QUIRK_NONE;
9925 }
9926 }
9927 #endif
9928
9929 spec->base_init_verbs = ca0132_base_init_verbs;
9930 spec->base_exit_verbs = ca0132_base_exit_verbs;
9931
9932 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
9933
9934 ca0132_init_chip(codec);
9935
9936 ca0132_config(codec);
9937
9938 err = ca0132_prepare_verbs(codec);
9939 if (err < 0)
9940 goto error;
9941
9942 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
9943 if (err < 0)
9944 goto error;
9945
9946 return 0;
9947
9948 error:
9949 ca0132_free(codec);
9950 return err;
9951 }
9952
9953 /*
9954 * patch entries
9955 */
9956 static const struct hda_device_id snd_hda_id_ca0132[] = {
9957 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
9958 {} /* terminator */
9959 };
9960 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
9961
9962 MODULE_LICENSE("GPL");
9963 MODULE_DESCRIPTION("Creative Sound Core3D codec");
9964
9965 static struct hda_codec_driver ca0132_driver = {
9966 .id = snd_hda_id_ca0132,
9967 };
9968
9969 module_hda_codec_driver(ca0132_driver);
9970