1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for AM6 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2016-2018 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7#include <dt-bindings/phy/phy-am654-serdes.h> 8 9&cbass_main { 10 msmc_ram: sram@70000000 { 11 compatible = "mmio-sram"; 12 reg = <0x0 0x70000000 0x0 0x200000>; 13 #address-cells = <1>; 14 #size-cells = <1>; 15 ranges = <0x0 0x0 0x70000000 0x200000>; 16 17 atf-sram@0 { 18 reg = <0x0 0x20000>; 19 }; 20 21 sysfw-sram@f0000 { 22 reg = <0xf0000 0x10000>; 23 }; 24 25 l3cache-sram@100000 { 26 reg = <0x100000 0x100000>; 27 }; 28 }; 29 30 gic500: interrupt-controller@1800000 { 31 compatible = "arm,gic-v3"; 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 #interrupt-cells = <3>; 36 interrupt-controller; 37 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */ 38 <0x00 0x01880000 0x00 0x90000>, /* GICR */ 39 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 40 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 41 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 42 /* 43 * vcpumntirq: 44 * virtual CPU interface maintenance interrupt 45 */ 46 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 47 48 gic_its: msi-controller@1820000 { 49 compatible = "arm,gic-v3-its"; 50 reg = <0x00 0x01820000 0x00 0x10000>; 51 socionext,synquacer-pre-its = <0x1000000 0x400000>; 52 msi-controller; 53 #msi-cells = <1>; 54 }; 55 }; 56 57 serdes0: serdes@900000 { 58 compatible = "ti,phy-am654-serdes"; 59 reg = <0x0 0x900000 0x0 0x2000>; 60 reg-names = "serdes"; 61 #phy-cells = <2>; 62 power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; 63 clocks = <&k3_clks 153 4>, <&k3_clks 153 1>, <&serdes1 AM654_SERDES_LO_REFCLK>; 64 clock-output-names = "serdes0_cmu_refclk", "serdes0_lo_refclk", "serdes0_ro_refclk"; 65 assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; 66 assigned-clock-parents = <&k3_clks 153 8>, <&k3_clks 153 4>; 67 ti,serdes-clk = <&serdes0_clk>; 68 #clock-cells = <1>; 69 mux-controls = <&serdes_mux 0>; 70 }; 71 72 serdes1: serdes@910000 { 73 compatible = "ti,phy-am654-serdes"; 74 reg = <0x0 0x910000 0x0 0x2000>; 75 reg-names = "serdes"; 76 #phy-cells = <2>; 77 power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>; 78 clocks = <&serdes0 AM654_SERDES_RO_REFCLK>, <&k3_clks 154 1>, <&k3_clks 154 5>; 79 clock-output-names = "serdes1_cmu_refclk", "serdes1_lo_refclk", "serdes1_ro_refclk"; 80 assigned-clocks = <&k3_clks 154 5>, <&serdes1 AM654_SERDES_CMU_REFCLK>; 81 assigned-clock-parents = <&k3_clks 154 9>, <&k3_clks 154 5>; 82 ti,serdes-clk = <&serdes1_clk>; 83 #clock-cells = <1>; 84 mux-controls = <&serdes_mux 1>; 85 }; 86 87 main_uart0: serial@2800000 { 88 compatible = "ti,am654-uart"; 89 reg = <0x00 0x02800000 0x00 0x100>; 90 reg-shift = <2>; 91 reg-io-width = <4>; 92 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 93 clock-frequency = <48000000>; 94 current-speed = <115200>; 95 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 96 }; 97 98 main_uart1: serial@2810000 { 99 compatible = "ti,am654-uart"; 100 reg = <0x00 0x02810000 0x00 0x100>; 101 reg-shift = <2>; 102 reg-io-width = <4>; 103 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 104 clock-frequency = <48000000>; 105 power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; 106 }; 107 108 main_uart2: serial@2820000 { 109 compatible = "ti,am654-uart"; 110 reg = <0x00 0x02820000 0x00 0x100>; 111 reg-shift = <2>; 112 reg-io-width = <4>; 113 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 114 clock-frequency = <48000000>; 115 power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; 116 }; 117 118 crypto: crypto@4e00000 { 119 compatible = "ti,am654-sa2ul"; 120 reg = <0x0 0x4e00000 0x0 0x1200>; 121 power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>; 122 #address-cells = <2>; 123 #size-cells = <2>; 124 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>; 125 status = "okay"; 126 127 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>, 128 <&main_udmap 0x4001>; 129 dma-names = "tx", "rx1", "rx2"; 130 dma-coherent; 131 132 rng: rng@4e10000 { 133 compatible = "inside-secure,safexcel-eip76"; 134 reg = <0x0 0x4e10000 0x0 0x7d>; 135 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 136 clocks = <&k3_clks 136 1>; 137 }; 138 }; 139 140 main_pmx0: pinctrl@11c000 { 141 compatible = "pinctrl-single"; 142 reg = <0x0 0x11c000 0x0 0x2e4>; 143 #pinctrl-cells = <1>; 144 pinctrl-single,register-width = <32>; 145 pinctrl-single,function-mask = <0xffffffff>; 146 }; 147 148 main_pmx1: pinctrl@11c2e8 { 149 compatible = "pinctrl-single"; 150 reg = <0x0 0x11c2e8 0x0 0x24>; 151 #pinctrl-cells = <1>; 152 pinctrl-single,register-width = <32>; 153 pinctrl-single,function-mask = <0xffffffff>; 154 }; 155 156 main_i2c0: i2c@2000000 { 157 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 158 reg = <0x0 0x2000000 0x0 0x100>; 159 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 160 #address-cells = <1>; 161 #size-cells = <0>; 162 clock-names = "fck"; 163 clocks = <&k3_clks 110 1>; 164 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>; 165 }; 166 167 main_i2c1: i2c@2010000 { 168 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 169 reg = <0x0 0x2010000 0x0 0x100>; 170 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 clock-names = "fck"; 174 clocks = <&k3_clks 111 1>; 175 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>; 176 }; 177 178 main_i2c2: i2c@2020000 { 179 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 180 reg = <0x0 0x2020000 0x0 0x100>; 181 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 182 #address-cells = <1>; 183 #size-cells = <0>; 184 clock-names = "fck"; 185 clocks = <&k3_clks 112 1>; 186 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>; 187 }; 188 189 main_i2c3: i2c@2030000 { 190 compatible = "ti,am654-i2c", "ti,omap4-i2c"; 191 reg = <0x0 0x2030000 0x0 0x100>; 192 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 193 #address-cells = <1>; 194 #size-cells = <0>; 195 clock-names = "fck"; 196 clocks = <&k3_clks 113 1>; 197 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>; 198 }; 199 200 ecap0: pwm@3100000 { 201 compatible = "ti,am654-ecap", "ti,am3352-ecap"; 202 #pwm-cells = <3>; 203 reg = <0x0 0x03100000 0x0 0x60>; 204 power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; 205 clocks = <&k3_clks 39 0>; 206 clock-names = "fck"; 207 }; 208 209 main_spi0: spi@2100000 { 210 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 211 reg = <0x0 0x2100000 0x0 0x400>; 212 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 213 clocks = <&k3_clks 137 1>; 214 power-domains = <&k3_pds 137 TI_SCI_PD_EXCLUSIVE>; 215 #address-cells = <1>; 216 #size-cells = <0>; 217 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>; 218 dma-names = "tx0", "rx0"; 219 }; 220 221 main_spi1: spi@2110000 { 222 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 223 reg = <0x0 0x2110000 0x0 0x400>; 224 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&k3_clks 138 1>; 226 power-domains = <&k3_pds 138 TI_SCI_PD_EXCLUSIVE>; 227 #address-cells = <1>; 228 #size-cells = <0>; 229 assigned-clocks = <&k3_clks 137 1>; 230 assigned-clock-rates = <48000000>; 231 }; 232 233 main_spi2: spi@2120000 { 234 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 235 reg = <0x0 0x2120000 0x0 0x400>; 236 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&k3_clks 139 1>; 238 power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>; 239 #address-cells = <1>; 240 #size-cells = <0>; 241 }; 242 243 main_spi3: spi@2130000 { 244 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 245 reg = <0x0 0x2130000 0x0 0x400>; 246 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&k3_clks 140 1>; 248 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 249 #address-cells = <1>; 250 #size-cells = <0>; 251 }; 252 253 main_spi4: spi@2140000 { 254 compatible = "ti,am654-mcspi","ti,omap4-mcspi"; 255 reg = <0x0 0x2140000 0x0 0x400>; 256 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 257 clocks = <&k3_clks 141 1>; 258 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 }; 262 263 sdhci0: sdhci@4f80000 { 264 compatible = "ti,am654-sdhci-5.1"; 265 reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>; 266 power-domains = <&k3_pds 47 TI_SCI_PD_EXCLUSIVE>; 267 clocks = <&k3_clks 47 0>, <&k3_clks 47 1>; 268 clock-names = "clk_ahb", "clk_xin"; 269 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 270 mmc-ddr-1_8v; 271 mmc-hs200-1_8v; 272 ti,otap-del-sel-legacy = <0x0>; 273 ti,otap-del-sel-mmc-hs = <0x0>; 274 ti,otap-del-sel-sd-hs = <0x0>; 275 ti,otap-del-sel-sdr12 = <0x0>; 276 ti,otap-del-sel-sdr25 = <0x0>; 277 ti,otap-del-sel-sdr50 = <0x8>; 278 ti,otap-del-sel-sdr104 = <0x7>; 279 ti,otap-del-sel-ddr50 = <0x5>; 280 ti,otap-del-sel-ddr52 = <0x5>; 281 ti,otap-del-sel-hs200 = <0x5>; 282 ti,otap-del-sel-hs400 = <0x0>; 283 ti,trm-icp = <0x8>; 284 dma-coherent; 285 }; 286 287 sdhci1: sdhci@4fa0000 { 288 compatible = "ti,am654-sdhci-5.1"; 289 reg = <0x0 0x4fa0000 0x0 0x260>, <0x0 0x4fb0000 0x0 0x134>; 290 power-domains = <&k3_pds 48 TI_SCI_PD_EXCLUSIVE>; 291 clocks = <&k3_clks 48 0>, <&k3_clks 48 1>; 292 clock-names = "clk_ahb", "clk_xin"; 293 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 294 ti,otap-del-sel-legacy = <0x0>; 295 ti,otap-del-sel-mmc-hs = <0x0>; 296 ti,otap-del-sel-sd-hs = <0x0>; 297 ti,otap-del-sel-sdr12 = <0x0>; 298 ti,otap-del-sel-sdr25 = <0x0>; 299 ti,otap-del-sel-sdr50 = <0x8>; 300 ti,otap-del-sel-sdr104 = <0x7>; 301 ti,otap-del-sel-ddr50 = <0x4>; 302 ti,otap-del-sel-ddr52 = <0x4>; 303 ti,otap-del-sel-hs200 = <0x7>; 304 ti,clkbuf-sel = <0x7>; 305 ti,otap-del-sel = <0x2>; 306 ti,trm-icp = <0x8>; 307 dma-coherent; 308 no-1-8-v; 309 }; 310 311 scm_conf: scm-conf@100000 { 312 compatible = "syscon", "simple-mfd"; 313 reg = <0 0x00100000 0 0x1c000>; 314 #address-cells = <1>; 315 #size-cells = <1>; 316 ranges = <0x0 0x0 0x00100000 0x1c000>; 317 318 pcie0_mode: pcie-mode@4060 { 319 compatible = "syscon"; 320 reg = <0x00004060 0x4>; 321 }; 322 323 pcie1_mode: pcie-mode@4070 { 324 compatible = "syscon"; 325 reg = <0x00004070 0x4>; 326 }; 327 328 pcie_devid: pcie-devid@210 { 329 compatible = "syscon"; 330 reg = <0x00000210 0x4>; 331 }; 332 333 serdes0_clk: clock@4080 { 334 compatible = "syscon"; 335 reg = <0x00004080 0x4>; 336 }; 337 338 serdes1_clk: clock@4090 { 339 compatible = "syscon"; 340 reg = <0x00004090 0x4>; 341 }; 342 343 serdes_mux: mux-controller { 344 compatible = "mmio-mux"; 345 #mux-control-cells = <1>; 346 mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */ 347 <0x4090 0x3>; /* SERDES1 lane select */ 348 }; 349 350 dss_oldi_io_ctrl: dss-oldi-io-ctrl@41e0 { 351 compatible = "syscon"; 352 reg = <0x0000041e0 0x14>; 353 }; 354 355 ehrpwm_tbclk: clock@4140 { 356 compatible = "ti,am654-ehrpwm-tbclk", "syscon"; 357 reg = <0x4140 0x18>; 358 #clock-cells = <1>; 359 }; 360 }; 361 362 dwc3_0: dwc3@4000000 { 363 compatible = "ti,am654-dwc3"; 364 reg = <0x0 0x4000000 0x0 0x4000>; 365 #address-cells = <1>; 366 #size-cells = <1>; 367 ranges = <0x0 0x0 0x4000000 0x20000>; 368 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 369 dma-coherent; 370 power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; 371 clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 372 assigned-clocks = <&k3_clks 151 2>, <&k3_clks 151 7>; 373 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 374 <&k3_clks 151 9>; /* set PIPE3_TXB_CLK to CLK_12M_RC/256 (for HS only) */ 375 376 usb0: usb@10000 { 377 compatible = "snps,dwc3"; 378 reg = <0x10000 0x10000>; 379 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 382 interrupt-names = "peripheral", 383 "host", 384 "otg"; 385 maximum-speed = "high-speed"; 386 dr_mode = "otg"; 387 phys = <&usb0_phy>; 388 phy-names = "usb2-phy"; 389 snps,dis_u3_susphy_quirk; 390 }; 391 }; 392 393 usb0_phy: phy@4100000 { 394 compatible = "ti,am654-usb2", "ti,omap-usb2"; 395 reg = <0x0 0x4100000 0x0 0x54>; 396 syscon-phy-power = <&scm_conf 0x4000>; 397 clocks = <&k3_clks 151 0>, <&k3_clks 151 1>; 398 clock-names = "wkupclk", "refclk"; 399 #phy-cells = <0>; 400 }; 401 402 dwc3_1: dwc3@4020000 { 403 compatible = "ti,am654-dwc3"; 404 reg = <0x0 0x4020000 0x0 0x4000>; 405 #address-cells = <1>; 406 #size-cells = <1>; 407 ranges = <0x0 0x0 0x4020000 0x20000>; 408 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 409 dma-coherent; 410 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; 411 clocks = <&k3_clks 152 2>; 412 assigned-clocks = <&k3_clks 152 2>; 413 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ 414 415 usb1: usb@10000 { 416 compatible = "snps,dwc3"; 417 reg = <0x10000 0x10000>; 418 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 421 interrupt-names = "peripheral", 422 "host", 423 "otg"; 424 maximum-speed = "high-speed"; 425 dr_mode = "otg"; 426 phys = <&usb1_phy>; 427 phy-names = "usb2-phy"; 428 }; 429 }; 430 431 usb1_phy: phy@4110000 { 432 compatible = "ti,am654-usb2", "ti,omap-usb2"; 433 reg = <0x0 0x4110000 0x0 0x54>; 434 syscon-phy-power = <&scm_conf 0x4020>; 435 clocks = <&k3_clks 152 0>, <&k3_clks 152 1>; 436 clock-names = "wkupclk", "refclk"; 437 #phy-cells = <0>; 438 }; 439 440 intr_main_gpio: interrupt-controller0 { 441 compatible = "ti,sci-intr"; 442 ti,intr-trigger-type = <1>; 443 interrupt-controller; 444 interrupt-parent = <&gic500>; 445 #interrupt-cells = <1>; 446 ti,sci = <&dmsc>; 447 ti,sci-dev-id = <100>; 448 ti,interrupt-ranges = <0 392 32>; 449 }; 450 451 main-navss { 452 compatible = "simple-mfd"; 453 #address-cells = <2>; 454 #size-cells = <2>; 455 ranges; 456 dma-coherent; 457 dma-ranges; 458 459 ti,sci-dev-id = <118>; 460 461 intr_main_navss: interrupt-controller1 { 462 compatible = "ti,sci-intr"; 463 ti,intr-trigger-type = <4>; 464 interrupt-controller; 465 interrupt-parent = <&gic500>; 466 #interrupt-cells = <1>; 467 ti,sci = <&dmsc>; 468 ti,sci-dev-id = <182>; 469 ti,interrupt-ranges = <0 64 64>, 470 <64 448 64>; 471 }; 472 473 inta_main_udmass: interrupt-controller@33d00000 { 474 compatible = "ti,sci-inta"; 475 reg = <0x0 0x33d00000 0x0 0x100000>; 476 interrupt-controller; 477 interrupt-parent = <&intr_main_navss>; 478 msi-controller; 479 ti,sci = <&dmsc>; 480 ti,sci-dev-id = <179>; 481 ti,interrupt-ranges = <0 0 256>; 482 }; 483 484 secure_proxy_main: mailbox@32c00000 { 485 compatible = "ti,am654-secure-proxy"; 486 #mbox-cells = <1>; 487 reg-names = "target_data", "rt", "scfg"; 488 reg = <0x00 0x32c00000 0x00 0x100000>, 489 <0x00 0x32400000 0x00 0x100000>, 490 <0x00 0x32800000 0x00 0x100000>; 491 interrupt-names = "rx_011"; 492 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 493 }; 494 495 hwspinlock: spinlock@30e00000 { 496 compatible = "ti,am654-hwspinlock"; 497 reg = <0x00 0x30e00000 0x00 0x1000>; 498 #hwlock-cells = <1>; 499 }; 500 501 mailbox0_cluster0: mailbox@31f80000 { 502 compatible = "ti,am654-mailbox"; 503 reg = <0x00 0x31f80000 0x00 0x200>; 504 #mbox-cells = <1>; 505 ti,mbox-num-users = <4>; 506 ti,mbox-num-fifos = <16>; 507 interrupt-parent = <&intr_main_navss>; 508 }; 509 510 mailbox0_cluster1: mailbox@31f81000 { 511 compatible = "ti,am654-mailbox"; 512 reg = <0x00 0x31f81000 0x00 0x200>; 513 #mbox-cells = <1>; 514 ti,mbox-num-users = <4>; 515 ti,mbox-num-fifos = <16>; 516 interrupt-parent = <&intr_main_navss>; 517 }; 518 519 mailbox0_cluster2: mailbox@31f82000 { 520 compatible = "ti,am654-mailbox"; 521 reg = <0x00 0x31f82000 0x00 0x200>; 522 #mbox-cells = <1>; 523 ti,mbox-num-users = <4>; 524 ti,mbox-num-fifos = <16>; 525 interrupt-parent = <&intr_main_navss>; 526 }; 527 528 mailbox0_cluster3: mailbox@31f83000 { 529 compatible = "ti,am654-mailbox"; 530 reg = <0x00 0x31f83000 0x00 0x200>; 531 #mbox-cells = <1>; 532 ti,mbox-num-users = <4>; 533 ti,mbox-num-fifos = <16>; 534 interrupt-parent = <&intr_main_navss>; 535 }; 536 537 mailbox0_cluster4: mailbox@31f84000 { 538 compatible = "ti,am654-mailbox"; 539 reg = <0x00 0x31f84000 0x00 0x200>; 540 #mbox-cells = <1>; 541 ti,mbox-num-users = <4>; 542 ti,mbox-num-fifos = <16>; 543 interrupt-parent = <&intr_main_navss>; 544 }; 545 546 mailbox0_cluster5: mailbox@31f85000 { 547 compatible = "ti,am654-mailbox"; 548 reg = <0x00 0x31f85000 0x00 0x200>; 549 #mbox-cells = <1>; 550 ti,mbox-num-users = <4>; 551 ti,mbox-num-fifos = <16>; 552 interrupt-parent = <&intr_main_navss>; 553 }; 554 555 mailbox0_cluster6: mailbox@31f86000 { 556 compatible = "ti,am654-mailbox"; 557 reg = <0x00 0x31f86000 0x00 0x200>; 558 #mbox-cells = <1>; 559 ti,mbox-num-users = <4>; 560 ti,mbox-num-fifos = <16>; 561 interrupt-parent = <&intr_main_navss>; 562 }; 563 564 mailbox0_cluster7: mailbox@31f87000 { 565 compatible = "ti,am654-mailbox"; 566 reg = <0x00 0x31f87000 0x00 0x200>; 567 #mbox-cells = <1>; 568 ti,mbox-num-users = <4>; 569 ti,mbox-num-fifos = <16>; 570 interrupt-parent = <&intr_main_navss>; 571 }; 572 573 mailbox0_cluster8: mailbox@31f88000 { 574 compatible = "ti,am654-mailbox"; 575 reg = <0x00 0x31f88000 0x00 0x200>; 576 #mbox-cells = <1>; 577 ti,mbox-num-users = <4>; 578 ti,mbox-num-fifos = <16>; 579 interrupt-parent = <&intr_main_navss>; 580 }; 581 582 mailbox0_cluster9: mailbox@31f89000 { 583 compatible = "ti,am654-mailbox"; 584 reg = <0x00 0x31f89000 0x00 0x200>; 585 #mbox-cells = <1>; 586 ti,mbox-num-users = <4>; 587 ti,mbox-num-fifos = <16>; 588 interrupt-parent = <&intr_main_navss>; 589 }; 590 591 mailbox0_cluster10: mailbox@31f8a000 { 592 compatible = "ti,am654-mailbox"; 593 reg = <0x00 0x31f8a000 0x00 0x200>; 594 #mbox-cells = <1>; 595 ti,mbox-num-users = <4>; 596 ti,mbox-num-fifos = <16>; 597 interrupt-parent = <&intr_main_navss>; 598 }; 599 600 mailbox0_cluster11: mailbox@31f8b000 { 601 compatible = "ti,am654-mailbox"; 602 reg = <0x00 0x31f8b000 0x00 0x200>; 603 #mbox-cells = <1>; 604 ti,mbox-num-users = <4>; 605 ti,mbox-num-fifos = <16>; 606 interrupt-parent = <&intr_main_navss>; 607 }; 608 609 ringacc: ringacc@3c000000 { 610 compatible = "ti,am654-navss-ringacc"; 611 reg = <0x0 0x3c000000 0x0 0x400000>, 612 <0x0 0x38000000 0x0 0x400000>, 613 <0x0 0x31120000 0x0 0x100>, 614 <0x0 0x33000000 0x0 0x40000>; 615 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 616 ti,num-rings = <818>; 617 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */ 618 ti,dma-ring-reset-quirk; 619 ti,sci = <&dmsc>; 620 ti,sci-dev-id = <187>; 621 msi-parent = <&inta_main_udmass>; 622 }; 623 624 main_udmap: dma-controller@31150000 { 625 compatible = "ti,am654-navss-main-udmap"; 626 reg = <0x0 0x31150000 0x0 0x100>, 627 <0x0 0x34000000 0x0 0x100000>, 628 <0x0 0x35000000 0x0 0x100000>; 629 reg-names = "gcfg", "rchanrt", "tchanrt"; 630 msi-parent = <&inta_main_udmass>; 631 #dma-cells = <1>; 632 633 ti,sci = <&dmsc>; 634 ti,sci-dev-id = <188>; 635 ti,ringacc = <&ringacc>; 636 637 ti,sci-rm-range-tchan = <0xf>, /* TX_HCHAN */ 638 <0xd>; /* TX_CHAN */ 639 ti,sci-rm-range-rchan = <0xb>, /* RX_HCHAN */ 640 <0xa>; /* RX_CHAN */ 641 ti,sci-rm-range-rflow = <0x0>; /* GP RFLOW */ 642 }; 643 644 cpts@310d0000 { 645 compatible = "ti,am65-cpts"; 646 reg = <0x0 0x310d0000 0x0 0x400>; 647 reg-names = "cpts"; 648 clocks = <&main_cpts_mux>; 649 clock-names = "cpts"; 650 interrupts-extended = <&intr_main_navss 391>; 651 interrupt-names = "cpts"; 652 ti,cpts-periodic-outputs = <6>; 653 ti,cpts-ext-ts-inputs = <8>; 654 655 main_cpts_mux: refclk-mux { 656 #clock-cells = <0>; 657 clocks = <&k3_clks 118 5>, <&k3_clks 118 11>, 658 <&k3_clks 118 6>, <&k3_clks 118 3>, 659 <&k3_clks 118 8>, <&k3_clks 118 14>, 660 <&k3_clks 120 3>, <&k3_clks 121 3>; 661 assigned-clocks = <&main_cpts_mux>; 662 assigned-clock-parents = <&k3_clks 118 5>; 663 }; 664 }; 665 }; 666 667 main_gpio0: gpio@600000 { 668 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 669 reg = <0x0 0x600000 0x0 0x100>; 670 gpio-controller; 671 #gpio-cells = <2>; 672 interrupt-parent = <&intr_main_gpio>; 673 interrupts = <192>, <193>, <194>, <195>, <196>, <197>; 674 interrupt-controller; 675 #interrupt-cells = <2>; 676 ti,ngpio = <96>; 677 ti,davinci-gpio-unbanked = <0>; 678 clocks = <&k3_clks 57 0>; 679 clock-names = "gpio"; 680 }; 681 682 main_gpio1: gpio@601000 { 683 compatible = "ti,am654-gpio", "ti,keystone-gpio"; 684 reg = <0x0 0x601000 0x0 0x100>; 685 gpio-controller; 686 #gpio-cells = <2>; 687 interrupt-parent = <&intr_main_gpio>; 688 interrupts = <200>, <201>, <202>, <203>, <204>, <205>; 689 interrupt-controller; 690 #interrupt-cells = <2>; 691 ti,ngpio = <90>; 692 ti,davinci-gpio-unbanked = <0>; 693 clocks = <&k3_clks 58 0>; 694 clock-names = "gpio"; 695 }; 696 697 pcie0_rc: pcie@5500000 { 698 compatible = "ti,am654-pcie-rc"; 699 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x2000>, <0x0 0x5506000 0x0 0x1000>; 700 reg-names = "app", "dbics", "config", "atu"; 701 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 702 #address-cells = <3>; 703 #size-cells = <2>; 704 ranges = <0x81000000 0 0 0x0 0x10020000 0 0x00010000 705 0x82000000 0 0x10030000 0x0 0x10030000 0 0x07FD0000>; 706 ti,syscon-pcie-id = <&pcie_devid>; 707 ti,syscon-pcie-mode = <&pcie0_mode>; 708 bus-range = <0x0 0xff>; 709 num-viewport = <16>; 710 max-link-speed = <2>; 711 dma-coherent; 712 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 713 msi-map = <0x0 &gic_its 0x0 0x10000>; 714 }; 715 716 pcie0_ep: pcie-ep@5500000 { 717 compatible = "ti,am654-pcie-ep"; 718 reg = <0x0 0x5500000 0x0 0x1000>, <0x0 0x5501000 0x0 0x1000>, <0x0 0x10000000 0x0 0x8000000>, <0x0 0x5506000 0x0 0x1000>; 719 reg-names = "app", "dbics", "addr_space", "atu"; 720 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 721 ti,syscon-pcie-mode = <&pcie0_mode>; 722 num-ib-windows = <16>; 723 num-ob-windows = <16>; 724 max-link-speed = <2>; 725 dma-coherent; 726 interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>; 727 }; 728 729 pcie1_rc: pcie@5600000 { 730 compatible = "ti,am654-pcie-rc"; 731 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x2000>, <0x0 0x5606000 0x0 0x1000>; 732 reg-names = "app", "dbics", "config", "atu"; 733 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 734 #address-cells = <3>; 735 #size-cells = <2>; 736 ranges = <0x81000000 0 0 0x0 0x18020000 0 0x00010000 737 0x82000000 0 0x18030000 0x0 0x18030000 0 0x07FD0000>; 738 ti,syscon-pcie-id = <&pcie_devid>; 739 ti,syscon-pcie-mode = <&pcie1_mode>; 740 bus-range = <0x0 0xff>; 741 num-viewport = <16>; 742 max-link-speed = <2>; 743 dma-coherent; 744 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 745 msi-map = <0x0 &gic_its 0x10000 0x10000>; 746 }; 747 748 pcie1_ep: pcie-ep@5600000 { 749 compatible = "ti,am654-pcie-ep"; 750 reg = <0x0 0x5600000 0x0 0x1000>, <0x0 0x5601000 0x0 0x1000>, <0x0 0x18000000 0x0 0x4000000>, <0x0 0x5606000 0x0 0x1000>; 751 reg-names = "app", "dbics", "addr_space", "atu"; 752 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 753 ti,syscon-pcie-mode = <&pcie1_mode>; 754 num-ib-windows = <16>; 755 num-ob-windows = <16>; 756 max-link-speed = <2>; 757 dma-coherent; 758 interrupts = <GIC_SPI 355 IRQ_TYPE_EDGE_RISING>; 759 }; 760 761 mcasp0: mcasp@2b00000 { 762 compatible = "ti,am33xx-mcasp-audio"; 763 reg = <0x0 0x02b00000 0x0 0x2000>, 764 <0x0 0x02b08000 0x0 0x1000>; 765 reg-names = "mpu","dat"; 766 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 768 interrupt-names = "tx", "rx"; 769 770 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; 771 dma-names = "tx", "rx"; 772 773 clocks = <&k3_clks 104 0>; 774 clock-names = "fck"; 775 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>; 776 777 status = "disabled"; 778 }; 779 780 mcasp1: mcasp@2b10000 { 781 compatible = "ti,am33xx-mcasp-audio"; 782 reg = <0x0 0x02b10000 0x0 0x2000>, 783 <0x0 0x02b18000 0x0 0x1000>; 784 reg-names = "mpu","dat"; 785 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 787 interrupt-names = "tx", "rx"; 788 789 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>; 790 dma-names = "tx", "rx"; 791 792 clocks = <&k3_clks 105 0>; 793 clock-names = "fck"; 794 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>; 795 796 status = "disabled"; 797 }; 798 799 mcasp2: mcasp@2b20000 { 800 compatible = "ti,am33xx-mcasp-audio"; 801 reg = <0x0 0x02b20000 0x0 0x2000>, 802 <0x0 0x02b28000 0x0 0x1000>; 803 reg-names = "mpu","dat"; 804 interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>; 806 interrupt-names = "tx", "rx"; 807 808 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>; 809 dma-names = "tx", "rx"; 810 811 clocks = <&k3_clks 106 0>; 812 clock-names = "fck"; 813 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>; 814 815 status = "disabled"; 816 }; 817 818 cal: cal@6f03000 { 819 compatible = "ti,am654-cal"; 820 reg = <0x0 0x06f03000 0x0 0x400>, 821 <0x0 0x06f03800 0x0 0x40>; 822 reg-names = "cal_top", 823 "cal_rx_core0"; 824 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 825 ti,camerrx-control = <&scm_conf 0x40c0>; 826 clock-names = "fck"; 827 clocks = <&k3_clks 2 0>; 828 power-domains = <&k3_pds 2 TI_SCI_PD_EXCLUSIVE>; 829 830 ports { 831 #address-cells = <1>; 832 #size-cells = <0>; 833 834 csi2_0: port@0 { 835 reg = <0>; 836 }; 837 }; 838 }; 839 840 dss: dss@4a00000 { 841 compatible = "ti,am65x-dss"; 842 reg = <0x0 0x04a00000 0x0 0x1000>, /* common */ 843 <0x0 0x04a02000 0x0 0x1000>, /* vidl1 */ 844 <0x0 0x04a06000 0x0 0x1000>, /* vid */ 845 <0x0 0x04a07000 0x0 0x1000>, /* ovr1 */ 846 <0x0 0x04a08000 0x0 0x1000>, /* ovr2 */ 847 <0x0 0x04a0a000 0x0 0x1000>, /* vp1 */ 848 <0x0 0x04a0b000 0x0 0x1000>; /* vp2 */ 849 reg-names = "common", "vidl1", "vid", 850 "ovr1", "ovr2", "vp1", "vp2"; 851 852 ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>; 853 854 power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>; 855 856 clocks = <&k3_clks 67 1>, 857 <&k3_clks 216 1>, 858 <&k3_clks 67 2>; 859 clock-names = "fck", "vp1", "vp2"; 860 861 /* 862 * Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via 863 * DIV1. See "Figure 12-3365. DSS Integration" 864 * in AM65x TRM for details. 865 */ 866 assigned-clocks = <&k3_clks 67 2>; 867 assigned-clock-parents = <&k3_clks 67 5>; 868 869 interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>; 870 871 status = "disabled"; 872 873 dma-coherent; 874 875 dss_ports: ports { 876 #address-cells = <1>; 877 #size-cells = <0>; 878 }; 879 }; 880 881 ehrpwm0: pwm@3000000 { 882 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 883 #pwm-cells = <3>; 884 reg = <0x0 0x3000000 0x0 0x100>; 885 power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>; 886 clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>; 887 clock-names = "tbclk", "fck"; 888 }; 889 890 ehrpwm1: pwm@3010000 { 891 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 892 #pwm-cells = <3>; 893 reg = <0x0 0x3010000 0x0 0x100>; 894 power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>; 895 clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>; 896 clock-names = "tbclk", "fck"; 897 }; 898 899 ehrpwm2: pwm@3020000 { 900 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 901 #pwm-cells = <3>; 902 reg = <0x0 0x3020000 0x0 0x100>; 903 power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>; 904 clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>; 905 clock-names = "tbclk", "fck"; 906 }; 907 908 ehrpwm3: pwm@3030000 { 909 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 910 #pwm-cells = <3>; 911 reg = <0x0 0x3030000 0x0 0x100>; 912 power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>; 913 clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>; 914 clock-names = "tbclk", "fck"; 915 }; 916 917 ehrpwm4: pwm@3040000 { 918 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 919 #pwm-cells = <3>; 920 reg = <0x0 0x3040000 0x0 0x100>; 921 power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>; 922 clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>; 923 clock-names = "tbclk", "fck"; 924 }; 925 926 ehrpwm5: pwm@3050000 { 927 compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm"; 928 #pwm-cells = <3>; 929 reg = <0x0 0x3050000 0x0 0x100>; 930 power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>; 931 clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>; 932 clock-names = "tbclk", "fck"; 933 }; 934}; 935