1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3588-cru.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/rk3588-power.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12#include <dt-bindings/soc/rockchip-system-status.h> 13#include <dt-bindings/suspend/rockchip-rk3588.h> 14#include <dt-bindings/thermal/thermal.h> 15 16/ { 17 compatible = "rockchip,rk3588"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 csi2dcphy0 = &csi2_dcphy0; 25 csi2dcphy1 = &csi2_dcphy1; 26 csi2dphy0 = &csi2_dphy0; 27 csi2dphy1 = &csi2_dphy1; 28 csi2dphy2 = &csi2_dphy2; 29 csi2dphy3 = &csi2_dphy3; 30 csi2dphy4 = &csi2_dphy4; 31 csi2dphy5 = &csi2_dphy5; 32 dsi0 = &dsi0; 33 dsi1 = &dsi1; 34 ethernet1 = &gmac1; 35 gpio0 = &gpio0; 36 gpio1 = &gpio1; 37 gpio2 = &gpio2; 38 gpio3 = &gpio3; 39 gpio4 = &gpio4; 40 i2c0 = &i2c0; 41 i2c1 = &i2c1; 42 i2c2 = &i2c2; 43 i2c3 = &i2c3; 44 i2c4 = &i2c4; 45 i2c5 = &i2c5; 46 i2c6 = &i2c6; 47 i2c7 = &i2c7; 48 i2c8 = &i2c8; 49 rkcif_mipi_lvds0= &rkcif_mipi_lvds; 50 rkcif_mipi_lvds1= &rkcif_mipi_lvds1; 51 rkcif_mipi_lvds2= &rkcif_mipi_lvds2; 52 rkcif_mipi_lvds3= &rkcif_mipi_lvds3; 53 rkvdec0 = &rkvdec0; 54 rkvdec1 = &rkvdec1; 55 rkvenc0 = &rkvenc0; 56 rkvenc1 = &rkvenc1; 57 jpege0 = &jpege0; 58 jpege1 = &jpege1; 59 jpege2 = &jpege2; 60 jpege3 = &jpege3; 61 serial0 = &uart0; 62 serial1 = &uart1; 63 serial2 = &uart2; 64 serial3 = &uart3; 65 serial4 = &uart4; 66 serial5 = &uart5; 67 serial6 = &uart6; 68 serial7 = &uart7; 69 serial8 = &uart8; 70 serial9 = &uart9; 71 spi0 = &spi0; 72 spi1 = &spi1; 73 spi2 = &spi2; 74 spi3 = &spi3; 75 spi4 = &spi4; 76 spi5 = &sfc; 77 hdcp0 = &hdcp0; 78 hdcp1 = &hdcp1; 79 }; 80 81 clocks { 82 compatible = "simple-bus"; 83 #address-cells = <2>; 84 #size-cells = <2>; 85 ranges; 86 87 spll: spll { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <702000000>; 91 clock-output-names = "spll"; 92 }; 93 94 xin32k: xin32k { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <32768>; 98 clock-output-names = "xin32k"; 99 }; 100 101 xin24m: xin24m { 102 compatible = "fixed-clock"; 103 #clock-cells = <0>; 104 clock-frequency = <24000000>; 105 clock-output-names = "xin24m"; 106 }; 107 108 hclk_vo1: hclk_vo1@fd7c08ec { 109 compatible = "rockchip,rk3588-clock-gate-link"; 110 reg = <0 0xfd7c08ec 0 0x10>; 111 clock-names = "link"; 112 clocks = <&cru HCLK_VO1USB_TOP_ROOT>; 113 #power-domain-cells = <1>; 114 #clock-cells = <0>; 115 }; 116 117 aclk_vdpu_low_pre: aclk_vdpu_low_pre@fd7c08b0 { 118 compatible = "rockchip,rk3588-clock-gate-link"; 119 reg = <0 0xfd7c08b0 0 0x10>; 120 clock-names = "link"; 121 clocks = <&cru ACLK_VDPU_ROOT>; 122 #power-domain-cells = <1>; 123 #clock-cells = <0>; 124 }; 125 126 hclk_vo0: hclk_vo0@fd7c08dc { 127 compatible = "rockchip,rk3588-clock-gate-link"; 128 reg = <0 0xfd7c08dc 0 0x10>; 129 clock-names = "link"; 130 clocks = <&cru HCLK_VOP_ROOT>; 131 #power-domain-cells = <1>; 132 #clock-cells = <0>; 133 }; 134 135 hclk_usb: hclk_usb@fd7c08a8 { 136 compatible = "rockchip,rk3588-clock-gate-link"; 137 reg = <0 0xfd7c08a8 0 0x10>; 138 clock-names = "link"; 139 clocks = <&cru HCLK_VO1USB_TOP_ROOT>; 140 #power-domain-cells = <1>; 141 #clock-cells = <0>; 142 }; 143 144 hclk_nvm: hclk_nvm@fd7c087c { 145 compatible = "rockchip,rk3588-clock-gate-link"; 146 reg = <0 0xfd7c087c 0 0x10>; 147 clock-names = "link"; 148 clocks = <&cru ACLK_NVM_ROOT>; 149 #power-domain-cells = <1>; 150 #clock-cells = <0>; 151 }; 152 153 aclk_usb: aclk_usb@fd7c08a8 { 154 compatible = "rockchip,rk3588-clock-gate-link"; 155 reg = <0 0xfd7c08a8 0 0x10>; 156 clock-names = "link"; 157 clocks = <&cru ACLK_VO1USB_TOP_ROOT>; 158 #power-domain-cells = <1>; 159 #clock-cells = <0>; 160 }; 161 162 hclk_isp1_pre: hclk_isp1_pre@fd7c0868 { 163 compatible = "rockchip,rk3588-clock-gate-link"; 164 reg = <0 0xfd7c0868 0 0x10>; 165 clock-names = "link"; 166 clocks = <&cru HCLK_VI_ROOT>; 167 #power-domain-cells = <1>; 168 #clock-cells = <0>; 169 }; 170 171 aclk_isp1_pre: aclk_isp1_pre@fd7c0868 { 172 compatible = "rockchip,rk3588-clock-gate-link"; 173 reg = <0 0xfd7c0868 0 0x10>; 174 clock-names = "link"; 175 clocks = <&cru ACLK_VI_ROOT>; 176 #power-domain-cells = <1>; 177 #clock-cells = <0>; 178 }; 179 180 aclk_rkvdec0_pre: aclk_rkvdec0_pre@fd7c08a0 { 181 compatible = "rockchip,rk3588-clock-gate-link"; 182 reg = <0 0xfd7c08a0 0 0x10>; 183 clock-names = "link"; 184 clocks = <&cru ACLK_VDPU_ROOT>; 185 #power-domain-cells = <1>; 186 #clock-cells = <0>; 187 }; 188 189 hclk_rkvdec0_pre: hclk_rkvdec0_pre@fd7c08a0 { 190 compatible = "rockchip,rk3588-clock-gate-link"; 191 reg = <0 0xfd7c08a0 0 0x10>; 192 clock-names = "link"; 193 clocks = <&cru HCLK_VDPU_ROOT>; 194 #power-domain-cells = <1>; 195 #clock-cells = <0>; 196 }; 197 198 aclk_rkvdec1_pre: aclk_rkvdec1_pre@fd7c08a4 { 199 compatible = "rockchip,rk3588-clock-gate-link"; 200 reg = <0 0xfd7c08a4 0 0x10>; 201 clock-names = "link"; 202 clocks = <&cru ACLK_VDPU_ROOT>; 203 #power-domain-cells = <1>; 204 #clock-cells = <0>; 205 }; 206 207 hclk_rkvdec1_pre: hclk_rkvdec1_pre@fd7c08a4 { 208 compatible = "rockchip,rk3588-clock-gate-link"; 209 reg = <0 0xfd7c08a4 0 0x10>; 210 clock-names = "link"; 211 clocks = <&cru HCLK_VDPU_ROOT>; 212 #power-domain-cells = <1>; 213 #clock-cells = <0>; 214 }; 215 216 aclk_jpeg_decoder_pre: aclk_jpeg_decoder_pre@fd7c08b0 { 217 compatible = "rockchip,rk3588-clock-gate-link"; 218 reg = <0 0xfd7c08b0 0 0x10>; 219 clock-names = "link"; 220 clocks = <&cru ACLK_VDPU_ROOT>; 221 #power-domain-cells = <1>; 222 #clock-cells = <0>; 223 }; 224 225 aclk_rkvenc1_pre: aclk_rkvenc1_pre@fd7c08c0 { 226 compatible = "rockchip,rk3588-clock-gate-link"; 227 reg = <0 0xfd7c08c0 0 0x10>; 228 clock-names = "link"; 229 clocks = <&cru ACLK_RKVENC0>; 230 #power-domain-cells = <1>; 231 #clock-cells = <0>; 232 }; 233 234 hclk_rkvenc1_pre: hclk_rkvenc1_pre@fd7c08c0 { 235 compatible = "rockchip,rk3588-clock-gate-link"; 236 reg = <0 0xfd7c08c0 0 0x10>; 237 clock-names = "link"; 238 clocks = <&cru HCLK_RKVENC0>; 239 #power-domain-cells = <1>; 240 #clock-cells = <0>; 241 }; 242 243 aclk_hdcp0_pre: aclk_hdcp0_pre@fd7c08dc { 244 compatible = "rockchip,rk3588-clock-gate-link"; 245 reg = <0 0xfd7c08dc 0 0x10>; 246 clock-names = "link"; 247 clocks = <&cru ACLK_VOP_LOW_ROOT>; 248 #power-domain-cells = <1>; 249 #clock-cells = <0>; 250 }; 251 252 aclk_hdcp1_pre: aclk_hdcp1_pre@fd7c08ec { 253 compatible = "rockchip,rk3588-clock-gate-link"; 254 reg = <0 0xfd7c08ec 0 0x10>; 255 clock-names = "link"; 256 clocks = <&cru ACLK_VO1USB_TOP_ROOT>; 257 #power-domain-cells = <1>; 258 #clock-cells = <0>; 259 }; 260 261 pclk_av1_pre: pclk_av1_pre@fd7c0910 { 262 compatible = "rockchip,rk3588-clock-gate-link"; 263 reg = <0 0xfd7c0910 0 0x10>; 264 clock-names = "link"; 265 clocks = <&cru HCLK_VDPU_ROOT>; 266 #power-domain-cells = <1>; 267 #clock-cells = <0>; 268 }; 269 270 aclk_av1_pre: aclk_av1_pre@fd7c0910 { 271 compatible = "rockchip,rk3588-clock-gate-link"; 272 reg = <0 0xfd7c0910 0 0x10>; 273 clock-names = "link"; 274 clocks = <&cru ACLK_VDPU_ROOT>; 275 #power-domain-cells = <1>; 276 #clock-cells = <0>; 277 }; 278 279 hclk_sdio_pre: hclk_sdio_pre@fd7c092c { 280 compatible = "rockchip,rk3588-clock-gate-link"; 281 reg = <0 0xfd7c092c 0 0x10>; 282 clock-names = "link"; 283 clocks = <&hclk_nvm>; 284 #power-domain-cells = <1>; 285 #clock-cells = <0>; 286 }; 287 288 pclk_vo0_grf: pclk_vo0_grf@fd7c08dc { 289 compatible = "rockchip,rk3588-clock-gate-link"; 290 reg = <0x0 0xfd7c08dc 0x0 0x4>; 291 clocks = <&hclk_vo0>; 292 clock-names = "link"; 293 #clock-cells = <0>; 294 }; 295 296 pclk_vo1_grf: pclk_vo1_grf@fd7c08ec { 297 compatible = "rockchip,rk3588-clock-gate-link"; 298 reg = <0x0 0xfd7c08ec 0x0 0x4>; 299 clocks = <&hclk_vo1>; 300 clock-names = "link"; 301 #clock-cells = <0>; 302 }; 303 304 mclkin_i2s0: mclkin-i2s0 { 305 compatible = "fixed-clock"; 306 #clock-cells = <0>; 307 clock-frequency = <0>; 308 clock-output-names = "i2s0_mclkin"; 309 }; 310 311 mclkin_i2s1: mclkin-i2s1 { 312 compatible = "fixed-clock"; 313 #clock-cells = <0>; 314 clock-frequency = <0>; 315 clock-output-names = "i2s1_mclkin"; 316 }; 317 318 mclkin_i2s2: mclkin-i2s2 { 319 compatible = "fixed-clock"; 320 #clock-cells = <0>; 321 clock-frequency = <0>; 322 clock-output-names = "i2s2_mclkin"; 323 }; 324 325 mclkin_i2s3: mclkin-i2s3 { 326 compatible = "fixed-clock"; 327 #clock-cells = <0>; 328 clock-frequency = <0>; 329 clock-output-names = "i2s3_mclkin"; 330 }; 331 332 mclkout_i2s0: mclkout-i2s0@fd58c318 { 333 compatible = "rockchip,clk-out"; 334 reg = <0 0xfd58c318 0 0x4>; 335 clocks = <&cru I2S0_8CH_MCLKOUT>; 336 #clock-cells = <0>; 337 clock-output-names = "i2s0_mclkout_to_io"; 338 rockchip,bit-shift = <0>; 339 rockchip,bit-set-to-disable; 340 }; 341 342 mclkout_i2s1: mclkout-i2s1@fd58c318 { 343 compatible = "rockchip,clk-out"; 344 reg = <0 0xfd58c318 0 0x4>; 345 clocks = <&cru I2S1_8CH_MCLKOUT>; 346 #clock-cells = <0>; 347 clock-output-names = "i2s1_mclkout_to_io"; 348 rockchip,bit-shift = <1>; 349 rockchip,bit-set-to-disable; 350 }; 351 352 mclkout_i2s1m1: mclkout-i2s1@fd58a000 { 353 compatible = "rockchip,clk-out"; 354 reg = <0 0xfd58a000 0 0x4>; 355 clocks = <&cru I2S1_8CH_MCLKOUT>; 356 #clock-cells = <0>; 357 clock-output-names = "i2s1m1_mclkout_to_io"; 358 rockchip,bit-shift = <6>; 359 }; 360 361 mclkout_i2s2: mclkout-i2s2@fd58c318 { 362 compatible = "rockchip,clk-out"; 363 reg = <0 0xfd58c318 0 0x4>; 364 clocks = <&cru I2S2_2CH_MCLKOUT>; 365 #clock-cells = <0>; 366 clock-output-names = "i2s2_mclkout_to_io"; 367 rockchip,bit-shift = <2>; 368 rockchip,bit-set-to-disable; 369 }; 370 371 mclkout_i2s3: mclkout-i2s3@fd58c318 { 372 compatible = "rockchip,clk-out"; 373 reg = <0 0xfd58c318 0 0x4>; 374 clocks = <&cru I2S3_2CH_MCLKOUT>; 375 #clock-cells = <0>; 376 clock-output-names = "i2s3_mclkout_to_io"; 377 rockchip,bit-shift = <7>; 378 rockchip,bit-set-to-disable; 379 }; 380 }; 381 382 cpus { 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 cpu-map { 387 cluster0 { 388 core0 { 389 cpu = <&cpu_l0>; 390 }; 391 core1 { 392 cpu = <&cpu_l1>; 393 }; 394 core2 { 395 cpu = <&cpu_l2>; 396 }; 397 core3 { 398 cpu = <&cpu_l3>; 399 }; 400 }; 401 cluster1 { 402 core0 { 403 cpu = <&cpu_b0>; 404 }; 405 core1 { 406 cpu = <&cpu_b1>; 407 }; 408 }; 409 cluster2 { 410 core0 { 411 cpu = <&cpu_b2>; 412 }; 413 core1 { 414 cpu = <&cpu_b3>; 415 }; 416 }; 417 }; 418 419 cpu_l0: cpu@0 { 420 device_type = "cpu"; 421 compatible = "arm,cortex-a55"; 422 reg = <0x0>; 423 enable-method = "psci"; 424 capacity-dmips-mhz = <530>; 425 clocks = <&scmi_clk SCMI_CLK_CPUL>; 426 operating-points-v2 = <&cluster0_opp_table>; 427 cpu-idle-states = <&CPU_SLEEP>; 428 i-cache-size = <32768>; 429 i-cache-line-size = <64>; 430 i-cache-sets = <128>; 431 d-cache-size = <32768>; 432 d-cache-line-size = <64>; 433 d-cache-sets = <128>; 434 next-level-cache = <&l2_cache_l0>; 435 #cooling-cells = <2>; 436 dynamic-power-coefficient = <100>; 437 }; 438 439 cpu_l1: cpu@100 { 440 device_type = "cpu"; 441 compatible = "arm,cortex-a55"; 442 reg = <0x100>; 443 enable-method = "psci"; 444 capacity-dmips-mhz = <530>; 445 clocks = <&scmi_clk SCMI_CLK_CPUL>; 446 operating-points-v2 = <&cluster0_opp_table>; 447 cpu-idle-states = <&CPU_SLEEP>; 448 i-cache-size = <32768>; 449 i-cache-line-size = <64>; 450 i-cache-sets = <128>; 451 d-cache-size = <32768>; 452 d-cache-line-size = <64>; 453 d-cache-sets = <128>; 454 next-level-cache = <&l2_cache_l1>; 455 }; 456 457 cpu_l2: cpu@200 { 458 device_type = "cpu"; 459 compatible = "arm,cortex-a55"; 460 reg = <0x200>; 461 enable-method = "psci"; 462 capacity-dmips-mhz = <530>; 463 clocks = <&scmi_clk SCMI_CLK_CPUL>; 464 operating-points-v2 = <&cluster0_opp_table>; 465 cpu-idle-states = <&CPU_SLEEP>; 466 i-cache-size = <32768>; 467 i-cache-line-size = <64>; 468 i-cache-sets = <128>; 469 d-cache-size = <32768>; 470 d-cache-line-size = <64>; 471 d-cache-sets = <128>; 472 next-level-cache = <&l2_cache_l2>; 473 }; 474 475 cpu_l3: cpu@300 { 476 device_type = "cpu"; 477 compatible = "arm,cortex-a55"; 478 reg = <0x300>; 479 enable-method = "psci"; 480 capacity-dmips-mhz = <530>; 481 clocks = <&scmi_clk SCMI_CLK_CPUL>; 482 operating-points-v2 = <&cluster0_opp_table>; 483 cpu-idle-states = <&CPU_SLEEP>; 484 i-cache-size = <32768>; 485 i-cache-line-size = <64>; 486 i-cache-sets = <128>; 487 d-cache-size = <32768>; 488 d-cache-line-size = <64>; 489 d-cache-sets = <128>; 490 next-level-cache = <&l2_cache_l3>; 491 }; 492 493 cpu_b0: cpu@400 { 494 device_type = "cpu"; 495 compatible = "arm,cortex-a76"; 496 reg = <0x400>; 497 enable-method = "psci"; 498 capacity-dmips-mhz = <1024>; 499 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 500 operating-points-v2 = <&cluster1_opp_table>; 501 cpu-idle-states = <&CPU_SLEEP>; 502 i-cache-size = <65536>; 503 i-cache-line-size = <64>; 504 i-cache-sets = <256>; 505 d-cache-size = <65536>; 506 d-cache-line-size = <64>; 507 d-cache-sets = <256>; 508 next-level-cache = <&l2_cache_b0>; 509 #cooling-cells = <2>; 510 dynamic-power-coefficient = <300>; 511 }; 512 513 cpu_b1: cpu@500 { 514 device_type = "cpu"; 515 compatible = "arm,cortex-a76"; 516 reg = <0x500>; 517 enable-method = "psci"; 518 capacity-dmips-mhz = <1024>; 519 clocks = <&scmi_clk SCMI_CLK_CPUB01>; 520 operating-points-v2 = <&cluster1_opp_table>; 521 cpu-idle-states = <&CPU_SLEEP>; 522 i-cache-size = <65536>; 523 i-cache-line-size = <64>; 524 i-cache-sets = <256>; 525 d-cache-size = <65536>; 526 d-cache-line-size = <64>; 527 d-cache-sets = <256>; 528 next-level-cache = <&l2_cache_b1>; 529 }; 530 531 cpu_b2: cpu@600 { 532 device_type = "cpu"; 533 compatible = "arm,cortex-a76"; 534 reg = <0x600>; 535 enable-method = "psci"; 536 capacity-dmips-mhz = <1024>; 537 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 538 operating-points-v2 = <&cluster2_opp_table>; 539 cpu-idle-states = <&CPU_SLEEP>; 540 i-cache-size = <65536>; 541 i-cache-line-size = <64>; 542 i-cache-sets = <256>; 543 d-cache-size = <65536>; 544 d-cache-line-size = <64>; 545 d-cache-sets = <256>; 546 next-level-cache = <&l2_cache_b2>; 547 #cooling-cells = <2>; 548 dynamic-power-coefficient = <300>; 549 }; 550 551 cpu_b3: cpu@700 { 552 device_type = "cpu"; 553 compatible = "arm,cortex-a76"; 554 reg = <0x700>; 555 enable-method = "psci"; 556 capacity-dmips-mhz = <1024>; 557 clocks = <&scmi_clk SCMI_CLK_CPUB23>; 558 operating-points-v2 = <&cluster2_opp_table>; 559 cpu-idle-states = <&CPU_SLEEP>; 560 i-cache-size = <65536>; 561 i-cache-line-size = <64>; 562 i-cache-sets = <256>; 563 d-cache-size = <65536>; 564 d-cache-line-size = <64>; 565 d-cache-sets = <256>; 566 next-level-cache = <&l2_cache_b3>; 567 }; 568 569 idle-states { 570 entry-method = "psci"; 571 CPU_SLEEP: cpu-sleep { 572 compatible = "arm,idle-state"; 573 local-timer-stop; 574 arm,psci-suspend-param = <0x0010000>; 575 entry-latency-us = <100>; 576 exit-latency-us = <120>; 577 min-residency-us = <1000>; 578 }; 579 }; 580 581 l2_cache_l0: l2-cache-l0 { 582 compatible = "cache"; 583 cache-size = <131072>; 584 cache-line-size = <64>; 585 cache-sets = <512>; 586 next-level-cache = <&l3_cache>; 587 }; 588 589 l2_cache_l1: l2-cache-l1 { 590 compatible = "cache"; 591 cache-size = <131072>; 592 cache-line-size = <64>; 593 cache-sets = <512>; 594 next-level-cache = <&l3_cache>; 595 }; 596 597 l2_cache_l2: l2-cache-l2 { 598 compatible = "cache"; 599 cache-size = <131072>; 600 cache-line-size = <64>; 601 cache-sets = <512>; 602 next-level-cache = <&l3_cache>; 603 }; 604 605 l2_cache_l3: l2-cache-l3 { 606 compatible = "cache"; 607 cache-size = <131072>; 608 cache-line-size = <64>; 609 cache-sets = <512>; 610 next-level-cache = <&l3_cache>; 611 }; 612 613 l2_cache_b0: l2-cache-b0 { 614 compatible = "cache"; 615 cache-size = <524288>; 616 cache-line-size = <64>; 617 cache-sets = <1024>; 618 next-level-cache = <&l3_cache>; 619 }; 620 621 l2_cache_b1: l2-cache-b1 { 622 compatible = "cache"; 623 cache-size = <524288>; 624 cache-line-size = <64>; 625 cache-sets = <1024>; 626 next-level-cache = <&l3_cache>; 627 }; 628 629 l2_cache_b2: l2-cache-b2 { 630 compatible = "cache"; 631 cache-size = <524288>; 632 cache-line-size = <64>; 633 cache-sets = <1024>; 634 next-level-cache = <&l3_cache>; 635 }; 636 637 l2_cache_b3: l2-cache-b3 { 638 compatible = "cache"; 639 cache-size = <524288>; 640 cache-line-size = <64>; 641 cache-sets = <1024>; 642 next-level-cache = <&l3_cache>; 643 }; 644 645 l3_cache: l3-cache { 646 compatible = "cache"; 647 cache-size = <3145728>; 648 cache-line-size = <64>; 649 cache-sets = <4096>; 650 }; 651 }; 652 653 cluster0_opp_table: cluster0-opp-table { 654 compatible = "operating-points-v2"; 655 opp-shared; 656 657 nvmem-cells = <&cpul_leakage>, <&cpul_opp_info>, <&specification_serial_number>; 658 nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; 659 rockchip,supported-hw; 660 rockchip,opp-shared-dsu; 661 662 rockchip,pvtm-hw = <0x06>; 663 rockchip,pvtm-voltage-sel-hw = < 664 0 1365 0 665 1366 1387 1 666 1388 1409 2 667 1410 1431 3 668 1432 1453 4 669 1454 1475 5 670 1476 9999 6 671 >; 672 rockchip,pvtm-voltage-sel = < 673 0 1410 0 674 1411 1434 1 675 1435 1458 2 676 1459 1482 3 677 1483 1506 4 678 1507 1530 5 679 1531 9999 6 680 >; 681 rockchip,pvtm-pvtpll; 682 rockchip,pvtm-offset = <0x64>; 683 rockchip,pvtm-sample-time = <1100>; 684 rockchip,pvtm-freq = <1416000>; 685 rockchip,pvtm-volt = <750000>; 686 rockchip,pvtm-ref-temp = <25>; 687 rockchip,pvtm-temp-prop = <244 244>; 688 rockchip,pvtm-thermal-zone = "soc-thermal"; 689 690 rockchip,grf = <&litcore_grf>; 691 rockchip,dsu-grf = <&dsu_grf>; 692 volt-mem-read-margin = < 693 855000 1 694 765000 2 695 675000 3 696 495000 4 697 >; 698 low-volt-mem-read-margin = <4>; 699 intermediate-threshold-freq = <1008000>; /* KHz */ 700 rockchip,reboot-freq = <1416000>; /* KHz */ 701 702 rockchip,temp-hysteresis = <5000>; 703 rockchip,low-temp = <10000>; 704 rockchip,low-temp-min-volt = <750000>; 705 rockchip,high-temp = <85000>; 706 rockchip,high-temp-max-freq = <1608000>; 707 708 /* RK3588 cluster0 OPPs */ 709 opp-408000000 { 710 opp-supported-hw = <0xf9 0xffff>; 711 opp-hz = /bits/ 64 <408000000>; 712 opp-microvolt = <675000 675000 950000>, 713 <675000 675000 950000>; 714 clock-latency-ns = <40000>; 715 }; 716 opp-600000000 { 717 opp-supported-hw = <0xf9 0xffff>; 718 opp-hz = /bits/ 64 <600000000>; 719 opp-microvolt = <675000 675000 950000>, 720 <675000 675000 950000>; 721 clock-latency-ns = <40000>; 722 }; 723 opp-816000000 { 724 opp-supported-hw = <0xf9 0xffff>; 725 opp-hz = /bits/ 64 <816000000>; 726 opp-microvolt = <675000 675000 950000>, 727 <675000 675000 950000>; 728 clock-latency-ns = <40000>; 729 }; 730 opp-1008000000 { 731 opp-supported-hw = <0xf9 0xffff>; 732 opp-hz = /bits/ 64 <1008000000>; 733 opp-microvolt = <675000 675000 950000>, 734 <675000 675000 950000>; 735 clock-latency-ns = <40000>; 736 }; 737 opp-1200000000 { 738 opp-supported-hw = <0xf9 0xffff>; 739 opp-hz = /bits/ 64 <1200000000>; 740 opp-microvolt = <712500 712500 950000>, 741 <712500 712500 950000>; 742 opp-microvolt-L1 = <700000 700000 950000>, 743 <700000 700000 950000>; 744 opp-microvolt-L2 = <700000 700000 950000>, 745 <700000 700000 950000>; 746 opp-microvolt-L3 = <687500 687500 950000>, 747 <687500 687500 950000>; 748 opp-microvolt-L4 = <675000 675000 950000>, 749 <675000 675000 950000>; 750 opp-microvolt-L5 = <675000 675000 950000>, 751 <675000 675000 950000>; 752 opp-microvolt-L6 = <675000 675000 950000>, 753 <675000 675000 950000>; 754 clock-latency-ns = <40000>; 755 }; 756 opp-1416000000 { 757 opp-supported-hw = <0xf9 0xffff>; 758 opp-hz = /bits/ 64 <1416000000>; 759 opp-microvolt = <762500 762500 950000>, 760 <762500 762500 950000>; 761 opp-microvolt-L1 = <750000 750000 950000>, 762 <750000 750000 950000>; 763 opp-microvolt-L2 = <737500 737500 950000>, 764 <737500 737500 950000>; 765 opp-microvolt-L3 = <725000 725000 950000>, 766 <725000 725000 950000>; 767 opp-microvolt-L4 = <725000 725000 950000>, 768 <725000 725000 950000>; 769 opp-microvolt-L5 = <712500 712500 950000>, 770 <712500 712500 950000>; 771 opp-microvolt-L6 = <712500 712500 950000>, 772 <712500 712500 950000>; 773 clock-latency-ns = <40000>; 774 opp-suspend; 775 }; 776 opp-1608000000 { 777 opp-supported-hw = <0xf9 0xffff>; 778 opp-hz = /bits/ 64 <1608000000>; 779 opp-microvolt = <850000 850000 950000>, 780 <850000 850000 950000>; 781 opp-microvolt-L1 = <837500 837500 950000>, 782 <837500 837500 950000>; 783 opp-microvolt-L2 = <825000 825000 950000>, 784 <825000 825000 950000>; 785 opp-microvolt-L3 = <812500 812500 950000>, 786 <812500 812500 950000>; 787 opp-microvolt-L4 = <800000 800000 950000>, 788 <800000 800000 950000>; 789 opp-microvolt-L5 = <800000 800000 950000>, 790 <800000 800000 950000>; 791 opp-microvolt-L6 = <787500 787500 950000>, 792 <787500 787500 950000>; 793 clock-latency-ns = <40000>; 794 }; 795 opp-1800000000 { 796 opp-supported-hw = <0xf9 0xffff>; 797 opp-hz = /bits/ 64 <1800000000>; 798 opp-microvolt = <950000 950000 950000>, 799 <950000 950000 950000>; 800 opp-microvolt-L1 = <937500 937500 950000>, 801 <937500 937500 950000>; 802 opp-microvolt-L2 = <925000 925000 950000>, 803 <925000 925000 950000>; 804 opp-microvolt-L3 = <912500 912500 950000>, 805 <912500 912500 950000>; 806 opp-microvolt-L4 = <900000 900000 950000>, 807 <900000 900000 950000>; 808 opp-microvolt-L5 = <887500 887500 950000>, 809 <887500 887500 950000>; 810 opp-microvolt-L6 = <875000 875000 950000>, 811 <875000 875000 950000>; 812 clock-latency-ns = <40000>; 813 }; 814 815 /* RK3588J/M cluster0 OPPs */ 816 opp-j-m-408000000 { 817 opp-supported-hw = <0x06 0xffff>; 818 opp-hz = /bits/ 64 <408000000>; 819 opp-microvolt = <750000 750000 950000>, 820 <750000 750000 950000>; 821 clock-latency-ns = <40000>; 822 }; 823 opp-j-m-600000000 { 824 opp-supported-hw = <0x06 0xffff>; 825 opp-hz = /bits/ 64 <600000000>; 826 opp-microvolt = <750000 750000 950000>, 827 <750000 750000 950000>; 828 clock-latency-ns = <40000>; 829 }; 830 opp-j-m-816000000 { 831 opp-supported-hw = <0x06 0xffff>; 832 opp-hz = /bits/ 64 <816000000>; 833 opp-microvolt = <750000 750000 950000>, 834 <750000 750000 950000>; 835 clock-latency-ns = <40000>; 836 }; 837 opp-j-m-1008000000 { 838 opp-supported-hw = <0x06 0xffff>; 839 opp-hz = /bits/ 64 <1008000000>; 840 opp-microvolt = <750000 750000 950000>, 841 <750000 750000 950000>; 842 clock-latency-ns = <40000>; 843 }; 844 opp-j-m-1200000000 { 845 opp-supported-hw = <0x06 0xffff>; 846 opp-hz = /bits/ 64 <1200000000>; 847 opp-microvolt = <750000 750000 950000>, 848 <750000 750000 950000>; 849 clock-latency-ns = <40000>; 850 }; 851 opp-j-1296000000 { 852 opp-supported-hw = <0x04 0xffff>; 853 opp-hz = /bits/ 64 <1296000000>; 854 opp-microvolt = <750000 750000 950000>, 855 <750000 750000 950000>; 856 opp-microvolt-L0 = <775000 775000 950000>, 857 <775000 775000 950000>; 858 opp-microvolt-L1 = <762500 762500 950000>, 859 <762500 762500 950000>; 860 clock-latency-ns = <40000>; 861 }; 862 opp-j-m-1416000000 { 863 opp-supported-hw = <0x06 0xffff>; 864 opp-hz = /bits/ 64 <1416000000>; 865 opp-microvolt = <750000 750000 950000>, 866 <750000 750000 950000>; 867 opp-microvolt-L0 = <787500 787500 950000>, 868 <787500 787500 950000>; 869 opp-microvolt-L1 = <775000 775000 950000>, 870 <775000 775000 950000>; 871 opp-microvolt-L2 = <762500 762500 950000>, 872 <762500 762500 950000>; 873 clock-latency-ns = <40000>; 874 opp-suspend; 875 }; 876 opp-j-m-1608000000 { 877 opp-supported-hw = <0x06 0xffff>; 878 opp-hz = /bits/ 64 <1608000000>; 879 opp-microvolt = <887500 887500 950000>, 880 <887500 887500 950000>; 881 opp-microvolt-L1 = <875000 875000 950000>, 882 <875000 875000 950000>; 883 opp-microvolt-L2 = <862500 862500 950000>, 884 <862500 862500 950000>; 885 opp-microvolt-L3 = <850000 850000 950000>, 886 <850000 850000 950000>; 887 opp-microvolt-L4 = <837500 837500 950000>, 888 <837500 837500 950000>; 889 opp-microvolt-L5 = <825000 825000 950000>, 890 <825000 825000 950000>; 891 opp-microvolt-L6 = <812500 812500 950000>, 892 <812500 812500 950000>; 893 clock-latency-ns = <40000>; 894 }; 895 opp-j-m-1704000000 { 896 opp-supported-hw = <0x06 0xffff>; 897 opp-hz = /bits/ 64 <1704000000>; 898 opp-microvolt = <937500 937500 950000>, 899 <937500 937500 950000>; 900 opp-microvolt-L1 = <925000 925000 950000>, 901 <925000 925000 950000>; 902 opp-microvolt-L2 = <912500 912500 950000>, 903 <912500 912500 950000>; 904 opp-microvolt-L3 = <900000 900000 950000>, 905 <900000 900000 950000>; 906 opp-microvolt-L4 = <887500 887500 950000>, 907 <887500 887500 950000>; 908 opp-microvolt-L5 = <875000 875000 950000>, 909 <875000 875000 950000>; 910 opp-microvolt-L6 = <862500 862500 950000>, 911 <862500 862500 950000>; 912 clock-latency-ns = <40000>; 913 }; 914 }; 915 916 cluster1_opp_table: cluster1-opp-table { 917 compatible = "operating-points-v2"; 918 opp-shared; 919 920 nvmem-cells = <&cpub0_leakage>, <&cpub01_opp_info>, <&specification_serial_number>; 921 nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; 922 rockchip,supported-hw; 923 924 rockchip,pvtm-hw = <0x06>; 925 rockchip,pvtm-voltage-sel-hw = < 926 0 1539 0 927 1540 1564 1 928 1565 1589 2 929 1590 1614 3 930 1615 1644 4 931 1645 1674 5 932 1675 1704 6 933 1705 9999 7 934 >; 935 rockchip,pvtm-voltage-sel = < 936 0 1595 0 937 1596 1615 1 938 1616 1640 2 939 1641 1675 3 940 1676 1710 4 941 1711 1743 5 942 1744 1776 6 943 1777 9999 7 944 >; 945 rockchip,pvtm-pvtpll; 946 rockchip,pvtm-offset = <0x18>; 947 rockchip,pvtm-sample-time = <1100>; 948 rockchip,pvtm-freq = <1608000>; 949 rockchip,pvtm-volt = <750000>; 950 rockchip,pvtm-ref-temp = <25>; 951 rockchip,pvtm-temp-prop = <270 270>; 952 rockchip,pvtm-thermal-zone = "soc-thermal"; 953 rockchip,pvtm-low-len-sel = <3>; 954 955 rockchip,grf = <&bigcore0_grf>; 956 volt-mem-read-margin = < 957 855000 1 958 765000 2 959 675000 3 960 495000 4 961 >; 962 low-volt-mem-read-margin = <4>; 963 intermediate-threshold-freq = <1008000>; /* KHz */ 964 rockchip,idle-threshold-freq = <2208000>; /* KHz */ 965 rockchip,reboot-freq = <1800000>; /* KHz */ 966 967 rockchip,temp-hysteresis = <5000>; 968 rockchip,low-temp = <10000>; 969 rockchip,low-temp-min-volt = <750000>; 970 rockchip,high-temp = <85000>; 971 rockchip,high-temp-max-freq = <2208000>; 972 973 /* RK3588 cluster1 OPPs */ 974 opp-408000000 { 975 opp-supported-hw = <0xf9 0xffff>; 976 opp-hz = /bits/ 64 <408000000>; 977 opp-microvolt = <675000 675000 1000000>, 978 <675000 675000 1000000>; 979 clock-latency-ns = <40000>; 980 opp-suspend; 981 }; 982 opp-600000000 { 983 opp-supported-hw = <0xf9 0xffff>; 984 opp-hz = /bits/ 64 <600000000>; 985 opp-microvolt = <675000 675000 1000000>, 986 <675000 675000 1000000>; 987 clock-latency-ns = <40000>; 988 }; 989 opp-816000000 { 990 opp-supported-hw = <0xf9 0xffff>; 991 opp-hz = /bits/ 64 <816000000>; 992 opp-microvolt = <675000 675000 1000000>, 993 <675000 675000 1000000>; 994 clock-latency-ns = <40000>; 995 }; 996 opp-1008000000 { 997 opp-supported-hw = <0xf9 0xffff>; 998 opp-hz = /bits/ 64 <1008000000>; 999 opp-microvolt = <675000 675000 1000000>, 1000 <675000 675000 1000000>; 1001 clock-latency-ns = <40000>; 1002 }; 1003 opp-1200000000 { 1004 opp-supported-hw = <0xf9 0xffff>; 1005 opp-hz = /bits/ 64 <1200000000>; 1006 opp-microvolt = <675000 675000 1000000>, 1007 <675000 675000 1000000>; 1008 clock-latency-ns = <40000>; 1009 }; 1010 opp-1416000000 { 1011 opp-supported-hw = <0xf9 0xffff>; 1012 opp-hz = /bits/ 64 <1416000000>; 1013 opp-microvolt = <725000 725000 1000000>, 1014 <725000 725000 1000000>; 1015 opp-microvolt-L2 = <712500 712500 1000000>, 1016 <712500 712500 1000000>; 1017 opp-microvolt-L3 = <700000 700000 1000000>, 1018 <700000 700000 1000000>; 1019 opp-microvolt-L4 = <700000 700000 1000000>, 1020 <700000 700000 1000000>; 1021 opp-microvolt-L5 = <687500 687500 1000000>, 1022 <687500 687500 1000000>; 1023 opp-microvolt-L6 = <675000 675000 1000000>, 1024 <675000 675000 1000000>; 1025 opp-microvolt-L7 = <675000 675000 1000000>, 1026 <675000 675000 1000000>; 1027 clock-latency-ns = <40000>; 1028 }; 1029 opp-1608000000 { 1030 opp-supported-hw = <0xf9 0xffff>; 1031 opp-hz = /bits/ 64 <1608000000>; 1032 opp-microvolt = <762500 762500 1000000>, 1033 <762500 762500 1000000>; 1034 opp-microvolt-L2 = <750000 750000 1000000>, 1035 <750000 750000 1000000>; 1036 opp-microvolt-L3 = <737500 737500 1000000>, 1037 <737500 737500 1000000>; 1038 opp-microvolt-L4 = <725000 725000 1000000>, 1039 <725000 725000 1000000>; 1040 opp-microvolt-L5 = <712500 712500 1000000>, 1041 <712500 712500 1000000>; 1042 opp-microvolt-L6 = <700000 700000 1000000>, 1043 <700000 700000 1000000>; 1044 opp-microvolt-L7 = <700000 700000 1000000>, 1045 <700000 700000 1000000>; 1046 clock-latency-ns = <40000>; 1047 }; 1048 opp-1800000000 { 1049 opp-supported-hw = <0xf9 0xffff>; 1050 opp-hz = /bits/ 64 <1800000000>; 1051 opp-microvolt = <850000 850000 1000000>, 1052 <850000 850000 1000000>; 1053 opp-microvolt-L1 = <837500 837500 1000000>, 1054 <837500 837500 1000000>; 1055 opp-microvolt-L2 = <825000 825000 1000000>, 1056 <825000 825000 1000000>; 1057 opp-microvolt-L3 = <812500 812500 1000000>, 1058 <812500 812500 1000000>; 1059 opp-microvolt-L4 = <800000 800000 1000000>, 1060 <800000 800000 1000000>; 1061 opp-microvolt-L5 = <787500 787500 1000000>, 1062 <787500 787500 1000000>; 1063 opp-microvolt-L6 = <775000 775000 1000000>, 1064 <775000 775000 1000000>; 1065 opp-microvolt-L7 = <762500 762500 1000000>, 1066 <762500 762500 1000000>; 1067 clock-latency-ns = <40000>; 1068 }; 1069 opp-2016000000 { 1070 opp-supported-hw = <0xf9 0xffff>; 1071 opp-hz = /bits/ 64 <2016000000>; 1072 opp-microvolt = <925000 925000 1000000>, 1073 <925000 925000 1000000>; 1074 opp-microvolt-L1 = <912500 912500 1000000>, 1075 <912500 912500 1000000>; 1076 opp-microvolt-L2 = <900000 900000 1000000>, 1077 <900000 900000 1000000>; 1078 opp-microvolt-L3 = <887500 887500 1000000>, 1079 <887500 887500 1000000>; 1080 opp-microvolt-L4 = <875000 875000 1000000>, 1081 <875000 875000 1000000>; 1082 opp-microvolt-L5 = <862500 862500 1000000>, 1083 <862500 862500 1000000>; 1084 opp-microvolt-L6 = <850000 850000 1000000>, 1085 <850000 850000 1000000>; 1086 opp-microvolt-L7 = <837500 837500 1000000>, 1087 <837500 837500 1000000>; 1088 clock-latency-ns = <40000>; 1089 }; 1090 opp-2208000000 { 1091 opp-supported-hw = <0xf9 0xffff>; 1092 opp-hz = /bits/ 64 <2208000000>; 1093 opp-microvolt = <987500 987500 1000000>, 1094 <987500 987500 1000000>; 1095 opp-microvolt-L1 = <975000 975000 1000000>, 1096 <975000 975000 1000000>; 1097 opp-microvolt-L2 = <962500 962500 1000000>, 1098 <962500 962500 1000000>; 1099 opp-microvolt-L3 = <950000 950000 1000000>, 1100 <950000 950000 1000000>; 1101 opp-microvolt-L4 = <962500 962500 1000000>, 1102 <962500 962500 1000000>; 1103 opp-microvolt-L5 = <950000 950000 1000000>, 1104 <950000 950000 1000000>; 1105 opp-microvolt-L6 = <925000 925000 1000000>, 1106 <925000 925000 1000000>; 1107 opp-microvolt-L7 = <912500 912500 1000000>, 1108 <912500 912500 1000000>; 1109 clock-latency-ns = <40000>; 1110 }; 1111 opp-2256000000 { 1112 opp-supported-hw = <0xf9 0x13>; 1113 opp-hz = /bits/ 64 <2256000000>; 1114 opp-microvolt = <1000000 1000000 1000000>, 1115 <1000000 1000000 1000000>; 1116 clock-latency-ns = <40000>; 1117 }; 1118 opp-2304000000 { 1119 opp-supported-hw = <0xf9 0x24>; 1120 opp-hz = /bits/ 64 <2304000000>; 1121 opp-microvolt = <1000000 1000000 1000000>, 1122 <1000000 1000000 1000000>; 1123 clock-latency-ns = <40000>; 1124 }; 1125 opp-2352000000 { 1126 opp-supported-hw = <0xf9 0x48>; 1127 opp-hz = /bits/ 64 <2352000000>; 1128 opp-microvolt = <1000000 1000000 1000000>, 1129 <1000000 1000000 1000000>; 1130 clock-latency-ns = <40000>; 1131 }; 1132 opp-2400000000 { 1133 opp-supported-hw = <0xf9 0x80>; 1134 opp-hz = /bits/ 64 <2400000000>; 1135 opp-microvolt = <1000000 1000000 1000000>, 1136 <1000000 1000000 1000000>; 1137 clock-latency-ns = <40000>; 1138 }; 1139 1140 /* RK3588J/M cluster1 OPPs */ 1141 opp-j-m-408000000 { 1142 opp-supported-hw = <0x06 0xffff>; 1143 opp-hz = /bits/ 64 <408000000>; 1144 opp-microvolt = <750000 750000 950000>, 1145 <750000 750000 950000>; 1146 clock-latency-ns = <40000>; 1147 }; 1148 opp-j-m-600000000 { 1149 opp-supported-hw = <0x06 0xffff>; 1150 opp-hz = /bits/ 64 <600000000>; 1151 opp-microvolt = <750000 750000 950000>, 1152 <750000 750000 950000>; 1153 clock-latency-ns = <40000>; 1154 }; 1155 opp-j-m-816000000 { 1156 opp-supported-hw = <0x06 0xffff>; 1157 opp-hz = /bits/ 64 <816000000>; 1158 opp-microvolt = <750000 750000 950000>, 1159 <750000 750000 950000>; 1160 clock-latency-ns = <40000>; 1161 }; 1162 opp-j-m-1008000000 { 1163 opp-supported-hw = <0x06 0xffff>; 1164 opp-hz = /bits/ 64 <1008000000>; 1165 opp-microvolt = <750000 750000 950000>, 1166 <750000 750000 950000>; 1167 clock-latency-ns = <40000>; 1168 }; 1169 opp-j-m-1200000000 { 1170 opp-supported-hw = <0x06 0xffff>; 1171 opp-hz = /bits/ 64 <1200000000>; 1172 opp-microvolt = <750000 750000 950000>, 1173 <750000 750000 950000>; 1174 clock-latency-ns = <40000>; 1175 }; 1176 opp-j-m-1416000000 { 1177 opp-supported-hw = <0x06 0xffff>; 1178 opp-hz = /bits/ 64 <1416000000>; 1179 opp-microvolt = <750000 750000 950000>, 1180 <750000 750000 950000>; 1181 opp-microvolt-L0 = <762500 762500 950000>, 1182 <762500 762500 950000>; 1183 clock-latency-ns = <40000>; 1184 opp-suspend; 1185 }; 1186 opp-j-m-1608000000 { 1187 opp-supported-hw = <0x06 0xffff>; 1188 opp-hz = /bits/ 64 <1608000000>; 1189 opp-microvolt = <787500 787500 950000>, 1190 <787500 787500 950000>; 1191 opp-microvolt-L2 = <775000 775000 950000>, 1192 <775000 775000 950000>; 1193 opp-microvolt-L3 = <762500 762500 950000>, 1194 <762500 762500 950000>; 1195 opp-microvolt-L4 = <750000 750000 950000>, 1196 <750000 750000 950000>; 1197 opp-microvolt-L5 = <750000 750000 950000>, 1198 <750000 750000 950000>; 1199 opp-microvolt-L6 = <750000 750000 950000>, 1200 <750000 750000 950000>; 1201 opp-microvolt-L7 = <750000 750000 950000>, 1202 <750000 750000 950000>; 1203 clock-latency-ns = <40000>; 1204 }; 1205 opp-j-m-1800000000 { 1206 opp-supported-hw = <0x06 0xffff>; 1207 opp-hz = /bits/ 64 <1800000000>; 1208 opp-microvolt = <875000 875000 950000>, 1209 <875000 875000 950000>; 1210 opp-microvolt-L1 = <862500 862500 950000>, 1211 <862500 862500 950000>; 1212 opp-microvolt-L2 = <850000 850000 950000>, 1213 <850000 850000 950000>; 1214 opp-microvolt-L3 = <837500 837500 950000>, 1215 <837500 837500 950000>; 1216 opp-microvolt-L4 = <825000 825000 950000>, 1217 <825000 825000 950000>; 1218 opp-microvolt-L5 = <812500 812500 950000>, 1219 <812500 812500 950000>; 1220 opp-microvolt-L6 = <800000 800000 950000>, 1221 <800000 800000 950000>; 1222 opp-microvolt-L7 = <787500 787500 950000>, 1223 <787500 787500 950000>; 1224 clock-latency-ns = <40000>; 1225 }; 1226 opp-j-m-2016000000 { 1227 opp-supported-hw = <0x06 0xffff>; 1228 opp-hz = /bits/ 64 <2016000000>; 1229 opp-microvolt = <950000 950000 950000>, 1230 <950000 950000 950000>; 1231 opp-microvolt-L1 = <950000 950000 950000>, 1232 <950000 950000 950000>; 1233 opp-microvolt-L2 = <937500 937500 950000>, 1234 <937500 937500 950000>; 1235 opp-microvolt-L3 = <925000 925000 950000>, 1236 <925000 925000 950000>; 1237 opp-microvolt-L4 = <912500 912500 950000>, 1238 <912500 912500 950000>; 1239 opp-microvolt-L5 = <900000 900000 950000>, 1240 <900000 900000 950000>; 1241 opp-microvolt-L6 = <887500 887500 950000>, 1242 <887500 887500 950000>; 1243 opp-microvolt-L7 = <875000 875000 950000>, 1244 <875000 875000 950000>; 1245 clock-latency-ns = <40000>; 1246 }; 1247 }; 1248 1249 cluster2_opp_table: cluster2-opp-table { 1250 compatible = "operating-points-v2"; 1251 opp-shared; 1252 1253 nvmem-cells = <&cpub1_leakage>, <&cpub23_opp_info>, <&specification_serial_number>; 1254 nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; 1255 rockchip,supported-hw; 1256 1257 rockchip,pvtm-hw = <0x06>; 1258 rockchip,pvtm-voltage-sel-hw = < 1259 0 1539 0 1260 1540 1564 1 1261 1565 1589 2 1262 1590 1614 3 1263 1615 1644 4 1264 1645 1674 5 1265 1675 1704 6 1266 1705 9999 7 1267 >; 1268 rockchip,pvtm-voltage-sel = < 1269 0 1595 0 1270 1596 1615 1 1271 1616 1640 2 1272 1641 1675 3 1273 1676 1710 4 1274 1711 1743 5 1275 1744 1776 6 1276 1777 9999 7 1277 >; 1278 rockchip,pvtm-pvtpll; 1279 rockchip,pvtm-offset = <0x18>; 1280 rockchip,pvtm-sample-time = <1100>; 1281 rockchip,pvtm-freq = <1608000>; 1282 rockchip,pvtm-volt = <750000>; 1283 rockchip,pvtm-ref-temp = <25>; 1284 rockchip,pvtm-temp-prop = <270 270>; 1285 rockchip,pvtm-thermal-zone = "soc-thermal"; 1286 rockchip,pvtm-low-len-sel = <3>; 1287 1288 rockchip,grf = <&bigcore1_grf>; 1289 volt-mem-read-margin = < 1290 855000 1 1291 765000 2 1292 675000 3 1293 495000 4 1294 >; 1295 low-volt-mem-read-margin = <4>; 1296 intermediate-threshold-freq = <1008000>; /* KHz */ 1297 rockchip,idle-threshold-freq = <2208000>; /* KHz */ 1298 rockchip,reboot-freq = <1800000>; /* KHz */ 1299 1300 rockchip,temp-hysteresis = <5000>; 1301 rockchip,low-temp = <10000>; 1302 rockchip,low-temp-min-volt = <750000>; 1303 rockchip,high-temp = <85000>; 1304 rockchip,high-temp-max-freq = <2208000>; 1305 1306 /* RK3588 cluster2 OPPs */ 1307 opp-408000000 { 1308 opp-supported-hw = <0xf9 0x0ffff>; 1309 opp-hz = /bits/ 64 <408000000>; 1310 opp-microvolt = <675000 675000 1000000>, 1311 <675000 675000 1000000>; 1312 clock-latency-ns = <40000>; 1313 opp-suspend; 1314 }; 1315 opp-600000000 { 1316 opp-supported-hw = <0xf9 0xffff>; 1317 opp-hz = /bits/ 64 <600000000>; 1318 opp-microvolt = <675000 675000 1000000>, 1319 <675000 675000 1000000>; 1320 clock-latency-ns = <40000>; 1321 }; 1322 opp-816000000 { 1323 opp-supported-hw = <0xf9 0xffff>; 1324 opp-hz = /bits/ 64 <816000000>; 1325 opp-microvolt = <675000 675000 1000000>, 1326 <675000 675000 1000000>; 1327 clock-latency-ns = <40000>; 1328 }; 1329 opp-1008000000 { 1330 opp-supported-hw = <0xf9 0xffff>; 1331 opp-hz = /bits/ 64 <1008000000>; 1332 opp-microvolt = <675000 675000 1000000>, 1333 <675000 675000 1000000>; 1334 clock-latency-ns = <40000>; 1335 }; 1336 opp-1200000000 { 1337 opp-supported-hw = <0xf9 0xffff>; 1338 opp-hz = /bits/ 64 <1200000000>; 1339 opp-microvolt = <675000 675000 1000000>, 1340 <675000 675000 1000000>; 1341 clock-latency-ns = <40000>; 1342 }; 1343 opp-1416000000 { 1344 opp-supported-hw = <0xf9 0xffff>; 1345 opp-hz = /bits/ 64 <1416000000>; 1346 opp-microvolt = <725000 725000 1000000>, 1347 <725000 725000 1000000>; 1348 opp-microvolt-L2 = <712500 712500 1000000>, 1349 <712500 712500 1000000>; 1350 opp-microvolt-L3 = <700000 700000 1000000>, 1351 <700000 700000 1000000>; 1352 opp-microvolt-L4 = <700000 700000 1000000>, 1353 <700000 700000 1000000>; 1354 opp-microvolt-L5 = <687500 687500 1000000>, 1355 <687500 687500 1000000>; 1356 opp-microvolt-L6 = <675000 675000 1000000>, 1357 <675000 675000 1000000>; 1358 opp-microvolt-L7 = <675000 675000 1000000>, 1359 <675000 675000 1000000>; 1360 clock-latency-ns = <40000>; 1361 }; 1362 opp-1608000000 { 1363 opp-supported-hw = <0xf9 0xffff>; 1364 opp-hz = /bits/ 64 <1608000000>; 1365 opp-microvolt = <762500 762500 1000000>, 1366 <762500 762500 1000000>; 1367 opp-microvolt-L2 = <750000 750000 1000000>, 1368 <750000 750000 1000000>; 1369 opp-microvolt-L3 = <737500 737500 1000000>, 1370 <737500 737500 1000000>; 1371 opp-microvolt-L4 = <725000 725000 1000000>, 1372 <725000 725000 1000000>; 1373 opp-microvolt-L5 = <712500 712500 1000000>, 1374 <712500 712500 1000000>; 1375 opp-microvolt-L6 = <700000 700000 1000000>, 1376 <700000 700000 1000000>; 1377 opp-microvolt-L7 = <700000 700000 1000000>, 1378 <700000 700000 1000000>; 1379 clock-latency-ns = <40000>; 1380 }; 1381 opp-1800000000 { 1382 opp-supported-hw = <0xf9 0xffff>; 1383 opp-hz = /bits/ 64 <1800000000>; 1384 opp-microvolt = <850000 850000 1000000>, 1385 <850000 850000 1000000>; 1386 opp-microvolt-L1 = <837500 837500 1000000>, 1387 <837500 837500 1000000>; 1388 opp-microvolt-L2 = <825000 825000 1000000>, 1389 <825000 825000 1000000>; 1390 opp-microvolt-L3 = <812500 812500 1000000>, 1391 <812500 812500 1000000>; 1392 opp-microvolt-L4 = <800000 800000 1000000>, 1393 <800000 800000 1000000>; 1394 opp-microvolt-L5 = <787500 787500 1000000>, 1395 <787500 787500 1000000>; 1396 opp-microvolt-L6 = <775000 775000 1000000>, 1397 <775000 775000 1000000>; 1398 opp-microvolt-L7 = <762500 762500 1000000>, 1399 <762500 762500 1000000>; 1400 clock-latency-ns = <40000>; 1401 }; 1402 opp-2016000000 { 1403 opp-supported-hw = <0xf9 0xffff>; 1404 opp-hz = /bits/ 64 <2016000000>; 1405 opp-microvolt = <925000 925000 1000000>, 1406 <925000 925000 1000000>; 1407 opp-microvolt-L1 = <912500 912500 1000000>, 1408 <912500 912500 1000000>; 1409 opp-microvolt-L2 = <900000 900000 1000000>, 1410 <900000 900000 1000000>; 1411 opp-microvolt-L3 = <887500 887500 1000000>, 1412 <887500 887500 1000000>; 1413 opp-microvolt-L4 = <875000 875000 1000000>, 1414 <875000 875000 1000000>; 1415 opp-microvolt-L5 = <862500 862500 1000000>, 1416 <862500 862500 1000000>; 1417 opp-microvolt-L6 = <850000 850000 1000000>, 1418 <850000 850000 1000000>; 1419 opp-microvolt-L7 = <837500 837500 1000000>, 1420 <837500 837500 1000000>; 1421 clock-latency-ns = <40000>; 1422 }; 1423 opp-2208000000 { 1424 opp-supported-hw = <0xf9 0xffff>; 1425 opp-hz = /bits/ 64 <2208000000>; 1426 opp-microvolt = <987500 987500 1000000>, 1427 <987500 987500 1000000>; 1428 opp-microvolt-L3 = <975000 975000 1000000>, 1429 <975000 975000 1000000>; 1430 opp-microvolt-L4 = <962500 962500 1000000>, 1431 <962500 962500 1000000>; 1432 opp-microvolt-L5 = <950000 950000 1000000>, 1433 <950000 950000 1000000>; 1434 opp-microvolt-L6 = <925000 925000 1000000>, 1435 <925000 925000 1000000>; 1436 opp-microvolt-L7 = <912500 912500 1000000>, 1437 <912500 912500 1000000>; 1438 clock-latency-ns = <40000>; 1439 }; 1440 opp-2256000000 { 1441 opp-supported-hw = <0xf9 0x13>; 1442 opp-hz = /bits/ 64 <2256000000>; 1443 opp-microvolt = <1000000 1000000 1000000>, 1444 <1000000 1000000 1000000>; 1445 clock-latency-ns = <40000>; 1446 }; 1447 opp-2304000000 { 1448 opp-supported-hw = <0xf9 0x24>; 1449 opp-hz = /bits/ 64 <2304000000>; 1450 opp-microvolt = <1000000 1000000 1000000>, 1451 <1000000 1000000 1000000>; 1452 clock-latency-ns = <40000>; 1453 }; 1454 opp-2352000000 { 1455 opp-supported-hw = <0xf9 0x48>; 1456 opp-hz = /bits/ 64 <2352000000>; 1457 opp-microvolt = <1000000 1000000 1000000>, 1458 <1000000 1000000 1000000>; 1459 clock-latency-ns = <40000>; 1460 }; 1461 opp-2400000000 { 1462 opp-supported-hw = <0xf9 0x80>; 1463 opp-hz = /bits/ 64 <2400000000>; 1464 opp-microvolt = <1000000 1000000 1000000>, 1465 <1000000 1000000 1000000>; 1466 clock-latency-ns = <40000>; 1467 }; 1468 1469 /* RK3588J/M cluster2 OPPs */ 1470 opp-j-m-408000000 { 1471 opp-supported-hw = <0x06 0xffff>; 1472 opp-hz = /bits/ 64 <408000000>; 1473 opp-microvolt = <750000 750000 950000>, 1474 <750000 750000 950000>; 1475 clock-latency-ns = <40000>; 1476 }; 1477 opp-j-m-600000000 { 1478 opp-supported-hw = <0x06 0xffff>; 1479 opp-hz = /bits/ 64 <600000000>; 1480 opp-microvolt = <750000 750000 950000>, 1481 <750000 750000 950000>; 1482 clock-latency-ns = <40000>; 1483 }; 1484 opp-j-m-816000000 { 1485 opp-supported-hw = <0x06 0xffff>; 1486 opp-hz = /bits/ 64 <816000000>; 1487 opp-microvolt = <750000 750000 950000>, 1488 <750000 750000 950000>; 1489 clock-latency-ns = <40000>; 1490 }; 1491 opp-j-m-1008000000 { 1492 opp-supported-hw = <0x06 0xffff>; 1493 opp-hz = /bits/ 64 <1008000000>; 1494 opp-microvolt = <750000 750000 950000>, 1495 <750000 750000 950000>; 1496 clock-latency-ns = <40000>; 1497 }; 1498 opp-j-m-1200000000 { 1499 opp-supported-hw = <0x06 0xffff>; 1500 opp-hz = /bits/ 64 <1200000000>; 1501 opp-microvolt = <750000 750000 950000>, 1502 <750000 750000 950000>; 1503 clock-latency-ns = <40000>; 1504 }; 1505 opp-j-m-1416000000 { 1506 opp-supported-hw = <0x06 0xffff>; 1507 opp-hz = /bits/ 64 <1416000000>; 1508 opp-microvolt = <750000 750000 950000>, 1509 <750000 750000 950000>; 1510 opp-microvolt-L0 = <762500 762500 950000>, 1511 <762500 762500 950000>; 1512 clock-latency-ns = <40000>; 1513 opp-suspend; 1514 }; 1515 opp-j-m-1608000000 { 1516 opp-supported-hw = <0x06 0xffff>; 1517 opp-hz = /bits/ 64 <1608000000>; 1518 opp-microvolt = <787500 787500 950000>, 1519 <787500 787500 950000>; 1520 opp-microvolt-L2 = <775000 775000 950000>, 1521 <775000 775000 950000>; 1522 opp-microvolt-L3 = <762500 762500 950000>, 1523 <762500 762500 950000>; 1524 opp-microvolt-L4 = <750000 750000 950000>, 1525 <750000 750000 950000>; 1526 opp-microvolt-L5 = <750000 750000 950000>, 1527 <750000 750000 950000>; 1528 opp-microvolt-L6 = <750000 750000 950000>, 1529 <750000 750000 950000>; 1530 opp-microvolt-L7 = <750000 750000 950000>, 1531 <750000 750000 950000>; 1532 clock-latency-ns = <40000>; 1533 }; 1534 opp-j-m-1800000000 { 1535 opp-supported-hw = <0x06 0xffff>; 1536 opp-hz = /bits/ 64 <1800000000>; 1537 opp-microvolt = <875000 875000 950000>, 1538 <875000 875000 950000>; 1539 opp-microvolt-L1 = <862500 862500 950000>, 1540 <862500 862500 950000>; 1541 opp-microvolt-L2 = <850000 850000 950000>, 1542 <850000 850000 950000>; 1543 opp-microvolt-L3 = <837500 837500 950000>, 1544 <837500 837500 950000>; 1545 opp-microvolt-L4 = <825000 825000 950000>, 1546 <825000 825000 950000>; 1547 opp-microvolt-L5 = <812500 812500 950000>, 1548 <812500 812500 950000>; 1549 opp-microvolt-L6 = <800000 800000 950000>, 1550 <800000 800000 950000>; 1551 opp-microvolt-L7 = <787500 787500 950000>, 1552 <787500 787500 950000>; 1553 clock-latency-ns = <40000>; 1554 }; 1555 opp-j-m-2016000000 { 1556 opp-supported-hw = <0x06 0xffff>; 1557 opp-hz = /bits/ 64 <2016000000>; 1558 opp-microvolt = <950000 950000 950000>, 1559 <950000 950000 950000>; 1560 opp-microvolt-L1 = <950000 950000 950000>, 1561 <950000 950000 950000>; 1562 opp-microvolt-L2 = <937500 937500 950000>, 1563 <937500 937500 950000>; 1564 opp-microvolt-L3 = <925000 925000 950000>, 1565 <925000 925000 950000>; 1566 opp-microvolt-L4 = <912500 912500 950000>, 1567 <912500 912500 950000>; 1568 opp-microvolt-L5 = <900000 900000 950000>, 1569 <900000 900000 950000>; 1570 opp-microvolt-L6 = <887500 887500 950000>, 1571 <887500 887500 950000>; 1572 opp-microvolt-L7 = <875000 875000 950000>, 1573 <875000 875000 950000>; 1574 clock-latency-ns = <40000>; 1575 }; 1576 }; 1577 1578 arm_pmu: arm-pmu { 1579 compatible = "arm,armv8-pmuv3"; 1580 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 1581 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, <&cpu_l3>, 1582 <&cpu_b0>, <&cpu_b1>, <&cpu_b2>, <&cpu_b3>; 1583 }; 1584 1585 cpuinfo { 1586 compatible = "rockchip,cpuinfo"; 1587 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 1588 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 1589 }; 1590 1591 csi2_dcphy0: csi2-dcphy0 { 1592 compatible = "rockchip,rk3588-csi2-dphy"; 1593 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 1594 phys = <&mipidcphy0>, <&mipidcphy1>; 1595 phy-names = "dcphy0", "dcphy1"; 1596 status = "disabled"; 1597 }; 1598 1599 csi2_dcphy1: csi2-dcphy1 { 1600 compatible = "rockchip,rk3588-csi2-dphy"; 1601 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 1602 phys = <&mipidcphy0>, <&mipidcphy1>; 1603 phy-names = "dcphy0", "dcphy1"; 1604 status = "disabled"; 1605 }; 1606 1607 csi2_dphy0: csi2-dphy0 { 1608 compatible = "rockchip,rk3588-csi2-dphy"; 1609 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 1610 phys = <&mipidcphy0>, <&mipidcphy1>; 1611 phy-names = "dcphy0", "dcphy1"; 1612 status = "disabled"; 1613 }; 1614 1615 csi2_dphy1: csi2-dphy1 { 1616 compatible = "rockchip,rk3588-csi2-dphy"; 1617 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 1618 phys = <&mipidcphy0>, <&mipidcphy1>; 1619 phy-names = "dcphy0", "dcphy1"; 1620 status = "disabled"; 1621 }; 1622 1623 csi2_dphy2: csi2-dphy2 { 1624 compatible = "rockchip,rk3588-csi2-dphy"; 1625 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 1626 phys = <&mipidcphy0>, <&mipidcphy1>; 1627 phy-names = "dcphy0", "dcphy1"; 1628 status = "disabled"; 1629 }; 1630 1631 csi2_dphy3: csi2-dphy3 { 1632 compatible = "rockchip,rk3588-csi2-dphy"; 1633 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 1634 phys = <&mipidcphy0>, <&mipidcphy1>; 1635 phy-names = "dcphy0", "dcphy1"; 1636 status = "disabled"; 1637 }; 1638 1639 csi2_dphy4: csi2-dphy4 { 1640 compatible = "rockchip,rk3588-csi2-dphy"; 1641 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 1642 phys = <&mipidcphy0>, <&mipidcphy1>; 1643 phy-names = "dcphy0", "dcphy1"; 1644 status = "disabled"; 1645 }; 1646 1647 csi2_dphy5: csi2-dphy5 { 1648 compatible = "rockchip,rk3588-csi2-dphy"; 1649 rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>; 1650 phys = <&mipidcphy0>, <&mipidcphy1>; 1651 phy-names = "dcphy0", "dcphy1"; 1652 status = "disabled"; 1653 }; 1654 1655 display_subsystem: display-subsystem { 1656 compatible = "rockchip,display-subsystem"; 1657 ports = <&vop_out>; 1658 1659 route { 1660 route_dp0: route-dp0 { 1661 status = "disabled"; 1662 logo,uboot = "logo.bmp"; 1663 logo,kernel = "logo_kernel.bmp"; 1664 logo,mode = "center"; 1665 charge_logo,mode = "center"; 1666 connect = <&vp1_out_dp0>; 1667 }; 1668 1669 route_dsi0: route-dsi0 { 1670 status = "disabled"; 1671 logo,uboot = "logo.bmp"; 1672 logo,kernel = "logo_kernel.bmp"; 1673 logo,mode = "center"; 1674 charge_logo,mode = "center"; 1675 connect = <&vp3_out_dsi0>; 1676 }; 1677 1678 route_dsi1: route-dsi1 { 1679 status = "disabled"; 1680 logo,uboot = "logo.bmp"; 1681 logo,kernel = "logo_kernel.bmp"; 1682 logo,mode = "center"; 1683 charge_logo,mode = "center"; 1684 connect = <&vp3_out_dsi1>; 1685 }; 1686 1687 route_edp0: route-edp0 { 1688 status = "disabled"; 1689 logo,uboot = "logo.bmp"; 1690 logo,kernel = "logo_kernel.bmp"; 1691 logo,mode = "center"; 1692 charge_logo,mode = "center"; 1693 connect = <&vp2_out_edp0>; 1694 }; 1695 1696 route_edp1: route-edp1 { 1697 status = "disabled"; 1698 logo,uboot = "logo.bmp"; 1699 logo,kernel = "logo_kernel.bmp"; 1700 logo,mode = "center"; 1701 charge_logo,mode = "center"; 1702 }; 1703 1704 route_hdmi0: route-hdmi0 { 1705 status = "disabled"; 1706 logo,uboot = "logo.bmp"; 1707 logo,kernel = "logo_kernel.bmp"; 1708 logo,mode = "center"; 1709 charge_logo,mode = "center"; 1710 connect = <&vp0_out_hdmi0>; 1711 }; 1712 1713 route_rgb: route-rgb { 1714 status = "disabled"; 1715 logo,uboot = "logo.bmp"; 1716 logo,kernel = "logo_kernel.bmp"; 1717 logo,mode = "center"; 1718 charge_logo,mode = "center"; 1719 connect = <&vp3_out_rgb>; 1720 }; 1721 }; 1722 }; 1723 1724 dmc: dmc { 1725 compatible = "rockchip,rk3588-dmc"; 1726 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 1727 interrupt-names = "complete"; 1728 devfreq-events = <&dfi>; 1729 clocks = <&scmi_clk 4>; 1730 clock-names = "dmc_clk"; 1731 operating-points-v2 = <&dmc_opp_table>; 1732 upthreshold = <40>; 1733 downdifferential = <20>; 1734 system-status-level = < 1735 /*system status freq level*/ 1736 SYS_STATUS_NORMAL DMC_FREQ_LEVEL_MID_HIGH 1737 SYS_STATUS_REBOOT DMC_FREQ_LEVEL_HIGH 1738 SYS_STATUS_SUSPEND DMC_FREQ_LEVEL_LOW 1739 SYS_STATUS_VIDEO_4K DMC_FREQ_LEVEL_MID_HIGH 1740 SYS_STATUS_VIDEO_4K_10B DMC_FREQ_LEVEL_MID_HIGH 1741 SYS_STATUS_VIDEO_SVEP DMC_FREQ_LEVEL_MID_HIGH 1742 SYS_STATUS_BOOST DMC_FREQ_LEVEL_HIGH 1743 SYS_STATUS_ISP DMC_FREQ_LEVEL_HIGH 1744 SYS_STATUS_PERFORMANCE DMC_FREQ_LEVEL_HIGH 1745 SYS_STATUS_DUALVIEW DMC_FREQ_LEVEL_HIGH 1746 SYS_STATUS_HDMIRX DMC_FREQ_LEVEL_HIGH 1747 >; 1748 auto-freq-en = <1>; 1749 status = "disabled"; 1750 }; 1751 1752 dmc_opp_table: dmc-opp-table { 1753 compatible = "operating-points-v2"; 1754 1755 nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&specification_serial_number>; 1756 nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; 1757 rockchip,supported-hw; 1758 1759 rockchip,leakage-voltage-sel = < 1760 1 31 0 1761 32 44 1 1762 45 57 2 1763 58 254 3 1764 >; 1765 rockchip,temp-hysteresis = <5000>; 1766 rockchip,low-temp = <10000>; 1767 rockchip,low-temp-min-volt = <750000>; 1768 1769 /* RK3588 dmc OPPs */ 1770 opp-528000000 { 1771 opp-supported-hw = <0xf9 0xffff>; 1772 opp-hz = /bits/ 64 <528000000>; 1773 opp-microvolt = <675000 675000 875000>, 1774 <725000 725000 750000>; 1775 opp-microvolt-L1 = <675000 675000 875000>, 1776 <700000 700000 750000>; 1777 opp-microvolt-L2 = <675000 675000 875000>, 1778 <687500 687500 750000>; 1779 opp-microvolt-L3 = <675000 675000 875000>, 1780 <675000 675000 750000>; 1781 }; 1782 opp-1068000000 { 1783 opp-supported-hw = <0xf9 0xffff>; 1784 opp-hz = /bits/ 64 <1068000000>; 1785 opp-microvolt = <725000 725000 875000>, 1786 <737500 737500 750000>; 1787 opp-microvolt-L1 = <700000 700000 875000>, 1788 <712500 712500 750000>; 1789 opp-microvolt-L2 = <675000 675000 875000>, 1790 <700000 700000 750000>; 1791 opp-microvolt-L3 = <675000 675000 875000>, 1792 <687500 687500 750000>; 1793 }; 1794 opp-1560000000 { 1795 opp-supported-hw = <0xf9 0xffff>; 1796 opp-hz = /bits/ 64 <1560000000>; 1797 opp-microvolt = <800000 800000 875000>, 1798 <750000 750000 750000>; 1799 opp-microvolt-L1 = <775000 775000 875000>, 1800 <725000 725000 750000>; 1801 opp-microvolt-L2 = <750000 750000 875000>, 1802 <712500 712500 750000>; 1803 opp-microvolt-L3 = <725000 725000 875000>, 1804 <700000 700000 750000>; 1805 }; 1806 opp-2750000000 { 1807 opp-supported-hw = <0xf9 0xffff>; 1808 opp-hz = /bits/ 64 <2750000000>; 1809 opp-microvolt = <875000 875000 875000>, 1810 <750000 750000 750000>; 1811 opp-microvolt-L1 = <850000 850000 875000>, 1812 <750000 750000 750000>; 1813 opp-microvolt-L2 = <837500 837500 875000>, 1814 <725000 725000 750000>; 1815 opp-microvolt-L3 = <825000 820000 875000>, 1816 <700000 700000 750000>; 1817 }; 1818 1819 /* RK3588J/M dmc OPPs */ 1820 opp-j-m-528000000 { 1821 opp-supported-hw = <0x06 0xffff>; 1822 opp-hz = /bits/ 64 <528000000>; 1823 opp-microvolt = <750000 750000 875000>, 1824 <750000 750000 750000>; 1825 }; 1826 opp-j-m-1068000000 { 1827 opp-supported-hw = <0x06 0xffff>; 1828 opp-hz = /bits/ 64 <1068000000>; 1829 opp-microvolt = <750000 750000 875000>, 1830 <750000 750000 750000>; 1831 }; 1832 opp-j-m-1560000000 { 1833 opp-supported-hw = <0x06 0xffff>; 1834 opp-hz = /bits/ 64 <1560000000>; 1835 opp-microvolt = <800000 800000 875000>, 1836 <750000 750000 750000>; 1837 opp-microvolt-L1 = <775000 775000 875000>, 1838 <750000 750000 750000>; 1839 opp-microvolt-L2 = <750000 750000 875000>, 1840 <750000 750000 750000>; 1841 opp-microvolt-L3 = <750000 750000 875000>, 1842 <750000 750000 750000>; 1843 }; 1844 opp-j-m-2750000000 { 1845 opp-supported-hw = <0x06 0xffff>; 1846 opp-hz = /bits/ 64 <2750000000>; 1847 opp-microvolt = <875000 875000 875000>, 1848 <750000 750000 750000>; 1849 opp-microvolt-L1 = <850000 850000 875000>, 1850 <750000 750000 750000>; 1851 opp-microvolt-L2 = <837500 837500 875000>, 1852 <750000 750000 750000>; 1853 opp-microvolt-L3 = <825000 820000 875000>, 1854 <750000 750000 750000>; 1855 }; 1856 }; 1857 1858 firmware { 1859 scmi: scmi { 1860 compatible = "arm,scmi-smc"; 1861 shmem = <&scmi_shmem>; 1862 arm,smc-id = <0x82000010>; 1863 #address-cells = <1>; 1864 #size-cells = <0>; 1865 1866 scmi_clk: protocol@14 { 1867 reg = <0x14>; 1868 #clock-cells = <1>; 1869 1870 assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>, 1871 <&scmi_clk SCMI_CLK_CPUB01>, 1872 <&scmi_clk SCMI_CLK_CPUB23>; 1873 assigned-clock-rates = <816000000>, 1874 <816000000>, 1875 <816000000>; 1876 }; 1877 1878 scmi_reset: protocol@16 { 1879 reg = <0x16>; 1880 #reset-cells = <1>; 1881 }; 1882 }; 1883 1884 sdei: sdei { 1885 compatible = "arm,sdei-1.0"; 1886 method = "smc"; 1887 }; 1888 }; 1889 1890 jpege_ccu: jpege-ccu { 1891 compatible = "rockchip,vpu-jpege-ccu"; 1892 status = "disabled"; 1893 }; 1894 1895 /omit-if-no-ref/ 1896 mipi_dcphy1: mipi_dcphy0: mipi-dcphy-dummy { 1897 }; 1898 1899 mipi0_csi2: mipi0-csi2 { 1900 compatible = "rockchip,rk3588-mipi-csi2"; 1901 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 1902 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 1903 <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; 1904 status = "disabled"; 1905 }; 1906 1907 mipi1_csi2: mipi1-csi2 { 1908 compatible = "rockchip,rk3588-mipi-csi2"; 1909 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 1910 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 1911 <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; 1912 status = "disabled"; 1913 }; 1914 1915 mipi2_csi2: mipi2-csi2 { 1916 compatible = "rockchip,rk3588-mipi-csi2"; 1917 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 1918 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 1919 <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; 1920 status = "disabled"; 1921 }; 1922 1923 mipi3_csi2: mipi3-csi2 { 1924 compatible = "rockchip,rk3588-mipi-csi2"; 1925 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 1926 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 1927 <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; 1928 status = "disabled"; 1929 }; 1930 1931 mipi4_csi2: mipi4-csi2 { 1932 compatible = "rockchip,rk3588-mipi-csi2"; 1933 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 1934 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 1935 <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; 1936 status = "disabled"; 1937 }; 1938 1939 mipi5_csi2: mipi5-csi2 { 1940 compatible = "rockchip,rk3588-mipi-csi2"; 1941 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>, 1942 <&mipi2_csi2_hw>, <&mipi3_csi2_hw>, 1943 <&mipi4_csi2_hw>, <&mipi5_csi2_hw>; 1944 status = "disabled"; 1945 }; 1946 1947 mpp_srv: mpp-srv { 1948 compatible = "rockchip,mpp-service"; 1949 rockchip,taskqueue-count = <12>; 1950 rockchip,resetgroup-count = <1>; 1951 status = "disabled"; 1952 }; 1953 1954 psci { 1955 compatible = "arm,psci-1.0"; 1956 method = "smc"; 1957 }; 1958 1959 rkcif_dvp: rkcif-dvp { 1960 compatible = "rockchip,rkcif-dvp"; 1961 rockchip,hw = <&rkcif>; 1962 iommus = <&rkcif_mmu>; 1963 status = "disabled"; 1964 }; 1965 1966 rkcif_dvp_sditf: rkcif-dvp-sditf { 1967 compatible = "rockchip,rkcif-sditf"; 1968 rockchip,cif = <&rkcif_dvp>; 1969 status = "disabled"; 1970 }; 1971 1972 rkcif_mipi_lvds: rkcif-mipi-lvds { 1973 compatible = "rockchip,rkcif-mipi-lvds"; 1974 rockchip,hw = <&rkcif>; 1975 iommus = <&rkcif_mmu>; 1976 status = "disabled"; 1977 }; 1978 1979 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { 1980 compatible = "rockchip,rkcif-sditf"; 1981 rockchip,cif = <&rkcif_mipi_lvds>; 1982 status = "disabled"; 1983 }; 1984 1985 rkcif_mipi_lvds_sditf_vir1: rkcif-mipi-lvds-sditf-vir1 { 1986 compatible = "rockchip,rkcif-sditf"; 1987 rockchip,cif = <&rkcif_mipi_lvds>; 1988 status = "disabled"; 1989 }; 1990 1991 rkcif_mipi_lvds_sditf_vir2: rkcif-mipi-lvds-sditf-vir2 { 1992 compatible = "rockchip,rkcif-sditf"; 1993 rockchip,cif = <&rkcif_mipi_lvds>; 1994 status = "disabled"; 1995 }; 1996 1997 rkcif_mipi_lvds_sditf_vir3: rkcif-mipi-lvds-sditf-vir3 { 1998 compatible = "rockchip,rkcif-sditf"; 1999 rockchip,cif = <&rkcif_mipi_lvds>; 2000 status = "disabled"; 2001 }; 2002 2003 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 2004 compatible = "rockchip,rkcif-mipi-lvds"; 2005 rockchip,hw = <&rkcif>; 2006 iommus = <&rkcif_mmu>; 2007 status = "disabled"; 2008 }; 2009 2010 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 2011 compatible = "rockchip,rkcif-sditf"; 2012 rockchip,cif = <&rkcif_mipi_lvds1>; 2013 status = "disabled"; 2014 }; 2015 2016 rkcif_mipi_lvds1_sditf_vir1: rkcif-mipi-lvds1-sditf-vir1 { 2017 compatible = "rockchip,rkcif-sditf"; 2018 rockchip,cif = <&rkcif_mipi_lvds1>; 2019 status = "disabled"; 2020 }; 2021 2022 rkcif_mipi_lvds1_sditf_vir2: rkcif-mipi-lvds1-sditf-vir2 { 2023 compatible = "rockchip,rkcif-sditf"; 2024 rockchip,cif = <&rkcif_mipi_lvds1>; 2025 status = "disabled"; 2026 }; 2027 2028 rkcif_mipi_lvds1_sditf_vir3: rkcif-mipi-lvds1-sditf-vir3 { 2029 compatible = "rockchip,rkcif-sditf"; 2030 rockchip,cif = <&rkcif_mipi_lvds1>; 2031 status = "disabled"; 2032 }; 2033 2034 rkcif_mipi_lvds2: rkcif-mipi-lvds2 { 2035 compatible = "rockchip,rkcif-mipi-lvds"; 2036 rockchip,hw = <&rkcif>; 2037 iommus = <&rkcif_mmu>; 2038 status = "disabled"; 2039 }; 2040 2041 rkcif_mipi_lvds2_sditf: rkcif-mipi-lvds2-sditf { 2042 compatible = "rockchip,rkcif-sditf"; 2043 rockchip,cif = <&rkcif_mipi_lvds2>; 2044 status = "disabled"; 2045 }; 2046 2047 rkcif_mipi_lvds2_sditf_vir1: rkcif-mipi-lvds2-sditf-vir1 { 2048 compatible = "rockchip,rkcif-sditf"; 2049 rockchip,cif = <&rkcif_mipi_lvds2>; 2050 status = "disabled"; 2051 }; 2052 2053 rkcif_mipi_lvds2_sditf_vir2: rkcif-mipi-lvds2-sditf-vir2 { 2054 compatible = "rockchip,rkcif-sditf"; 2055 rockchip,cif = <&rkcif_mipi_lvds2>; 2056 status = "disabled"; 2057 }; 2058 2059 rkcif_mipi_lvds2_sditf_vir3: rkcif-mipi-lvds2-sditf-vir3 { 2060 compatible = "rockchip,rkcif-sditf"; 2061 rockchip,cif = <&rkcif_mipi_lvds2>; 2062 status = "disabled"; 2063 }; 2064 2065 rkcif_mipi_lvds3: rkcif-mipi-lvds3 { 2066 compatible = "rockchip,rkcif-mipi-lvds"; 2067 rockchip,hw = <&rkcif>; 2068 iommus = <&rkcif_mmu>; 2069 status = "disabled"; 2070 }; 2071 2072 rkcif_mipi_lvds3_sditf: rkcif-mipi-lvds3-sditf { 2073 compatible = "rockchip,rkcif-sditf"; 2074 rockchip,cif = <&rkcif_mipi_lvds3>; 2075 status = "disabled"; 2076 }; 2077 2078 rkcif_mipi_lvds3_sditf_vir1: rkcif-mipi-lvds3-sditf-vir1 { 2079 compatible = "rockchip,rkcif-sditf"; 2080 rockchip,cif = <&rkcif_mipi_lvds3>; 2081 status = "disabled"; 2082 }; 2083 2084 rkcif_mipi_lvds3_sditf_vir2: rkcif-mipi-lvds3-sditf-vir2 { 2085 compatible = "rockchip,rkcif-sditf"; 2086 rockchip,cif = <&rkcif_mipi_lvds3>; 2087 status = "disabled"; 2088 }; 2089 2090 rkcif_mipi_lvds3_sditf_vir3: rkcif-mipi-lvds3-sditf-vir3 { 2091 compatible = "rockchip,rkcif-sditf"; 2092 rockchip,cif = <&rkcif_mipi_lvds3>; 2093 status = "disabled"; 2094 }; 2095 2096 rkisp0_vir0: rkisp0-vir0 { 2097 compatible = "rockchip,rkisp-vir"; 2098 rockchip,hw = <&rkisp0>; 2099 /* 2100 * dual isp process image case 2101 * other rkisp hw and virtual nodes should disabled 2102 * rockchip,hw = <&rkisp_unite>; 2103 */ 2104 status = "disabled"; 2105 }; 2106 2107 rkisp0_vir1: rkisp0-vir1 { 2108 compatible = "rockchip,rkisp-vir"; 2109 rockchip,hw = <&rkisp0>; 2110 status = "disabled"; 2111 }; 2112 2113 rkisp0_vir2: rkisp0-vir2 { 2114 compatible = "rockchip,rkisp-vir"; 2115 rockchip,hw = <&rkisp0>; 2116 status = "disabled"; 2117 }; 2118 2119 rkisp0_vir3: rkisp0-vir3 { 2120 compatible = "rockchip,rkisp-vir"; 2121 rockchip,hw = <&rkisp0>; 2122 status = "disabled"; 2123 }; 2124 2125 rkisp1_vir0: rkisp1-vir0 { 2126 compatible = "rockchip,rkisp-vir"; 2127 rockchip,hw = <&rkisp1>; 2128 status = "disabled"; 2129 }; 2130 2131 rkisp1_vir1: rkisp1-vir1 { 2132 compatible = "rockchip,rkisp-vir"; 2133 rockchip,hw = <&rkisp1>; 2134 status = "disabled"; 2135 }; 2136 2137 rkisp1_vir2: rkisp1-vir2 { 2138 compatible = "rockchip,rkisp-vir"; 2139 rockchip,hw = <&rkisp1>; 2140 status = "disabled"; 2141 }; 2142 2143 rkisp1_vir3: rkisp1-vir3 { 2144 compatible = "rockchip,rkisp-vir"; 2145 rockchip,hw = <&rkisp1>; 2146 status = "disabled"; 2147 }; 2148 2149 rkispp0_vir0: rkispp0-vir0 { 2150 compatible = "rockchip,rk3588-rkispp-vir"; 2151 rockchip,hw = <&rkispp0>; 2152 status = "disabled"; 2153 }; 2154 2155 rkispp1_vir0: rkispp1-vir0 { 2156 compatible = "rockchip,rk3588-rkispp-vir"; 2157 rockchip,hw = <&rkispp1>; 2158 status = "disabled"; 2159 }; 2160 2161 rkvenc_ccu: rkvenc-ccu { 2162 compatible = "rockchip,rkv-encoder-v2-ccu"; 2163 status = "disabled"; 2164 }; 2165 2166 rockchip_suspend: rockchip-suspend { 2167 compatible = "rockchip,pm-rk3588"; 2168 status = "disabled"; 2169 rockchip,sleep-debug-en = <0>; 2170 rockchip,sleep-mode-config = < 2171 (0 2172 | RKPM_SLP_ARMOFF_LOGOFF 2173 | RKPM_SLP_PMU_PMUALIVE_32K 2174 | RKPM_SLP_PMU_DIS_OSC 2175 | RKPM_SLP_32K_EXT 2176 ) 2177 >; 2178 rockchip,wakeup-config = < 2179 (0 2180 | RKPM_GPIO_WKUP_EN 2181 ) 2182 >; 2183 }; 2184 2185 rockchip_system_monitor: rockchip-system-monitor { 2186 compatible = "rockchip,system-monitor"; 2187 2188 rockchip,thermal-zone = "soc-thermal"; 2189 }; 2190 2191 thermal_zones: thermal-zones { 2192 soc_thermal: soc-thermal { 2193 polling-delay-passive = <20>; /* milliseconds */ 2194 polling-delay = <1000>; /* milliseconds */ 2195 sustainable-power = <2100>; /* milliwatts */ 2196 2197 thermal-sensors = <&tsadc 0>; 2198 trips { 2199 threshold: trip-point-0 { 2200 temperature = <75000>; 2201 hysteresis = <2000>; 2202 type = "passive"; 2203 }; 2204 target: trip-point-1 { 2205 temperature = <85000>; 2206 hysteresis = <2000>; 2207 type = "passive"; 2208 }; 2209 soc_crit: soc-crit { 2210 /* millicelsius */ 2211 temperature = <115000>; 2212 /* millicelsius */ 2213 hysteresis = <2000>; 2214 type = "critical"; 2215 }; 2216 }; 2217 cooling-maps { 2218 map0 { 2219 trip = <&target>; 2220 cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2221 contribution = <1024>; 2222 }; 2223 map1 { 2224 trip = <&target>; 2225 cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2226 contribution = <1024>; 2227 }; 2228 map2 { 2229 trip = <&target>; 2230 cooling-device = <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2231 contribution = <1024>; 2232 }; 2233 map3 { 2234 trip = <&target>; 2235 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2236 contribution = <1024>; 2237 }; 2238 }; 2239 }; 2240 2241 bigcore0_thermal: bigcore0-thermal { 2242 polling-delay-passive = <20>; /* milliseconds */ 2243 polling-delay = <1000>; /* milliseconds */ 2244 thermal-sensors = <&tsadc 1>; 2245 }; 2246 2247 bigcore1_thermal: bigcore1-thermal { 2248 polling-delay-passive = <20>; /* milliseconds */ 2249 polling-delay = <1000>; /* milliseconds */ 2250 thermal-sensors = <&tsadc 2>; 2251 }; 2252 2253 little_core_thermal: littlecore-thermal { 2254 polling-delay-passive = <20>; /* milliseconds */ 2255 polling-delay = <1000>; /* milliseconds */ 2256 thermal-sensors = <&tsadc 3>; 2257 }; 2258 2259 center_thermal: center-thermal { 2260 polling-delay-passive = <20>; /* milliseconds */ 2261 polling-delay = <1000>; /* milliseconds */ 2262 thermal-sensors = <&tsadc 4>; 2263 }; 2264 2265 gpu_thermal: gpu-thermal { 2266 polling-delay-passive = <20>; /* milliseconds */ 2267 polling-delay = <1000>; /* milliseconds */ 2268 thermal-sensors = <&tsadc 5>; 2269 }; 2270 2271 npu_thermal: npu-thermal { 2272 polling-delay-passive = <20>; /* milliseconds */ 2273 polling-delay = <1000>; /* milliseconds */ 2274 thermal-sensors = <&tsadc 6>; 2275 }; 2276 }; 2277 2278 timer { 2279 compatible = "arm,armv8-timer"; 2280 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 2281 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 2282 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 2283 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 2284 }; 2285 2286 sram@10f000 { 2287 compatible = "mmio-sram"; 2288 reg = <0x0 0x0010f000 0x0 0x100>; 2289 #address-cells = <1>; 2290 #size-cells = <1>; 2291 ranges = <0 0x0 0x0010f000 0x100>; 2292 2293 scmi_shmem: sram@0 { 2294 compatible = "arm,scmi-shmem"; 2295 reg = <0x0 0x100>; 2296 }; 2297 }; 2298 2299 gpu: gpu@fb000000 { 2300 compatible = "arm,mali-bifrost"; 2301 reg = <0x0 0xfb000000 0x0 0x200000>; 2302 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2303 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2304 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 2305 interrupt-names = "GPU", "MMU", "JOB"; 2306 2307 clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru CLK_GPU_COREGROUP>, 2308 <&cru CLK_GPU_STACKS>, <&cru CLK_GPU>; 2309 clock-names = "clk_mali", "clk_gpu_coregroup", 2310 "clk_gpu_stacks", "clk_gpu"; 2311 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 2312 assigned-clock-rates = <200000000>; 2313 power-domains = <&power RK3588_PD_GPU>; 2314 operating-points-v2 = <&gpu_opp_table>; 2315 #cooling-cells = <2>; 2316 dynamic-power-coefficient = <2982>; 2317 2318 upthreshold = <30>; 2319 downdifferential = <10>; 2320 2321 status = "disabled"; 2322 }; 2323 2324 gpu_opp_table: gpu-opp-table { 2325 compatible = "operating-points-v2"; 2326 2327 nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&specification_serial_number>; 2328 nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; 2329 rockchip,supported-hw; 2330 2331 rockchip,pvtm-hw = <0x04>; 2332 rockchip,pvtm-voltage-sel-hw = < 2333 0 799 0 2334 800 819 1 2335 820 844 2 2336 845 869 3 2337 870 894 4 2338 895 9999 5 2339 >; 2340 rockchip,pvtm-voltage-sel = < 2341 0 815 0 2342 816 835 1 2343 836 860 2 2344 861 885 3 2345 886 910 4 2346 911 9999 5 2347 >; 2348 rockchip,pvtm-pvtpll; 2349 rockchip,pvtm-offset = <0x1c>; 2350 rockchip,pvtm-sample-time = <1100>; 2351 rockchip,pvtm-freq = <800000>; 2352 rockchip,pvtm-volt = <750000>; 2353 rockchip,pvtm-ref-temp = <25>; 2354 rockchip,pvtm-temp-prop = <(-135) (-135)>; 2355 rockchip,pvtm-thermal-zone = "gpu-thermal"; 2356 2357 clocks = <&cru CLK_GPU>; 2358 clock-names = "clk"; 2359 rockchip,grf = <&gpu_grf>; 2360 volt-mem-read-margin = < 2361 855000 1 2362 765000 2 2363 675000 3 2364 495000 4 2365 >; 2366 low-volt-mem-read-margin = <4>; 2367 intermediate-threshold-freq = <400000>; /* KHz */ 2368 2369 rockchip,temp-hysteresis = <5000>; 2370 rockchip,low-temp = <10000>; 2371 rockchip,low-temp-min-volt = <750000>; 2372 rockchip,high-temp = <85000>; 2373 rockchip,high-temp-max-freq = <800000>; 2374 2375 /* RK3588 gpu OPPs */ 2376 opp-300000000 { 2377 opp-supported-hw = <0xf9 0xffff>; 2378 opp-hz = /bits/ 64 <300000000>; 2379 opp-microvolt = <675000 675000 850000>, 2380 <675000 675000 850000>; 2381 }; 2382 opp-400000000 { 2383 opp-supported-hw = <0xf9 0xffff>; 2384 opp-hz = /bits/ 64 <400000000>; 2385 opp-microvolt = <675000 675000 850000>, 2386 <675000 675000 850000>; 2387 }; 2388 opp-500000000 { 2389 opp-supported-hw = <0xf9 0xffff>; 2390 opp-hz = /bits/ 64 <500000000>; 2391 opp-microvolt = <675000 675000 850000>, 2392 <675000 675000 850000>; 2393 }; 2394 opp-600000000 { 2395 opp-supported-hw = <0xf9 0xffff>; 2396 opp-hz = /bits/ 64 <600000000>; 2397 opp-microvolt = <675000 675000 850000>, 2398 <675000 675000 850000>; 2399 }; 2400 opp-700000000 { 2401 opp-supported-hw = <0xf9 0xffff>; 2402 opp-hz = /bits/ 64 <700000000>; 2403 opp-microvolt = <700000 700000 850000>, 2404 <700000 700000 850000>; 2405 opp-microvolt-L2 = <687500 687500 850000>, 2406 <687500 687500 850000>; 2407 opp-microvolt-L3 = <675000 675000 850000>, 2408 <675000 675000 850000>; 2409 opp-microvolt-L4 = <675000 675000 850000>, 2410 <675000 675000 850000>; 2411 opp-microvolt-L5 = <675000 675000 850000>, 2412 <675000 675000 850000>; 2413 }; 2414 opp-800000000 { 2415 opp-supported-hw = <0xf9 0xffff>; 2416 opp-hz = /bits/ 64 <800000000>; 2417 opp-microvolt = <750000 750000 850000>, 2418 <750000 750000 850000>; 2419 opp-microvolt-L1 = <737500 737500 850000>, 2420 <737500 737500 850000>; 2421 opp-microvolt-L2 = <725000 725000 850000>, 2422 <725000 725000 850000>; 2423 opp-microvolt-L3 = <712500 712500 850000>, 2424 <712500 712500 850000>; 2425 opp-microvolt-L4 = <700000 700000 850000>, 2426 <700000 700000 850000>; 2427 opp-microvolt-L5 = <700000 700000 850000>, 2428 <700000 700000 850000>; 2429 }; 2430 opp-900000000 { 2431 opp-supported-hw = <0xf9 0xffff>; 2432 opp-hz = /bits/ 64 <900000000>; 2433 opp-microvolt = <800000 800000 850000>, 2434 <800000 800000 850000>; 2435 opp-microvolt-L1 = <787500 787500 850000>, 2436 <787500 787500 850000>; 2437 opp-microvolt-L2 = <775000 775000 850000>, 2438 <775000 775000 850000>; 2439 opp-microvolt-L3 = <762500 762500 850000>, 2440 <762500 762500 850000>; 2441 opp-microvolt-L4 = <750000 750000 850000>, 2442 <750000 750000 850000>; 2443 opp-microvolt-L5 = <737500 737500 850000>, 2444 <737500 737500 850000>; 2445 }; 2446 opp-1000000000 { 2447 opp-supported-hw = <0xf9 0xffff>; 2448 opp-hz = /bits/ 64 <1000000000>; 2449 opp-microvolt = <850000 850000 850000>, 2450 <850000 850000 850000>; 2451 opp-microvolt-L1 = <837500 837500 850000>, 2452 <837500 837500 850000>; 2453 opp-microvolt-L2 = <825000 825000 850000>, 2454 <825000 825000 850000>; 2455 opp-microvolt-L3 = <812500 812500 850000>, 2456 <812500 812500 850000>; 2457 opp-microvolt-L4 = <800000 800000 850000>, 2458 <800000 800000 850000>; 2459 opp-microvolt-L5 = <787500 787500 850000>, 2460 <787500 787500 850000>; 2461 }; 2462 2463 /* RK3588J/M gpu OPPs */ 2464 opp-j-m-300000000 { 2465 opp-supported-hw = <0x06 0xffff>; 2466 opp-hz = /bits/ 64 <300000000>; 2467 opp-microvolt = <750000 750000 850000>, 2468 <750000 750000 850000>; 2469 }; 2470 opp-j-m-400000000 { 2471 opp-supported-hw = <0x06 0xffff>; 2472 opp-hz = /bits/ 64 <400000000>; 2473 opp-microvolt = <750000 750000 850000>, 2474 <750000 750000 850000>; 2475 }; 2476 opp-j-m-500000000 { 2477 opp-supported-hw = <0x06 0xffff>; 2478 opp-hz = /bits/ 64 <500000000>; 2479 opp-microvolt = <750000 750000 850000>, 2480 <750000 750000 850000>; 2481 }; 2482 opp-j-m-600000000 { 2483 opp-supported-hw = <0x06 0xffff>; 2484 opp-hz = /bits/ 64 <600000000>; 2485 opp-microvolt = <750000 750000 850000>, 2486 <750000 750000 850000>; 2487 }; 2488 opp-j-m-700000000 { 2489 opp-supported-hw = <0x06 0xffff>; 2490 opp-hz = /bits/ 64 <700000000>; 2491 opp-microvolt = <750000 750000 850000>, 2492 <750000 750000 850000>; 2493 }; 2494 /* RK3588J gpu OPPs */ 2495 opp-j-850000000 { 2496 opp-supported-hw = <0x04 0xffff>; 2497 opp-hz = /bits/ 64 <850000000>; 2498 opp-microvolt = <787500 787500 850000>, 2499 <787500 787500 850000>; 2500 opp-microvolt-L1 = <775000 775000 850000>, 2501 <775000 775000 850000>; 2502 opp-microvolt-L2 = <762500 762500 850000>, 2503 <762500 762500 850000>; 2504 opp-microvolt-L3 = <750000 750000 850000>, 2505 <750000 750000 850000>; 2506 opp-microvolt-L4 = <750000 750000 850000>, 2507 <750000 750000 850000>; 2508 opp-microvolt-L5 = <750000 750000 850000>, 2509 <750000 750000 850000>; 2510 }; 2511 /* RK3588M gpu OPPs */ 2512 opp-m-800000000 { 2513 opp-supported-hw = <0x02 0xffff>; 2514 opp-hz = /bits/ 64 <800000000>; 2515 opp-microvolt = <750000 750000 850000>, 2516 <750000 750000 850000>; 2517 }; 2518 opp-m-900000000 { 2519 opp-supported-hw = <0x02 0xffff>; 2520 opp-hz = /bits/ 64 <900000000>; 2521 opp-microvolt = <800000 800000 850000>, 2522 <800000 800000 850000>; 2523 opp-microvolt-L1 = <787500 787500 850000>, 2524 <787500 787500 850000>; 2525 opp-microvolt-L2 = <775000 775000 850000>, 2526 <775000 775000 850000>; 2527 opp-microvolt-L3 = <762500 762500 850000>, 2528 <762500 762500 850000>; 2529 opp-microvolt-L4 = <750000 750000 850000>, 2530 <750000 750000 850000>; 2531 opp-microvolt-L5 = <750000 750000 850000>, 2532 <750000 750000 850000>; 2533 }; 2534 opp-m-1000000000 { 2535 opp-supported-hw = <0x02 0xffff>; 2536 opp-hz = /bits/ 64 <1000000000>; 2537 opp-microvolt = <850000 850000 850000>, 2538 <850000 850000 850000>; 2539 opp-microvolt-L1 = <837500 837500 850000>, 2540 <837500 837500 850000>; 2541 opp-microvolt-L2 = <825000 825000 850000>, 2542 <825000 825000 850000>; 2543 opp-microvolt-L3 = <812500 812500 850000>, 2544 <812500 812500 850000>; 2545 opp-microvolt-L4 = <800000 800000 850000>, 2546 <800000 800000 850000>; 2547 opp-microvolt-L5 = <787500 787500 850000>, 2548 <787500 787500 850000>; 2549 }; 2550 }; 2551 2552 usbdrd3_0: usbdrd3_0 { 2553 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 2554 clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>, 2555 <&cru ACLK_USB3OTG0>; 2556 clock-names = "ref", "suspend", "bus"; 2557 #address-cells = <2>; 2558 #size-cells = <2>; 2559 ranges; 2560 status = "disabled"; 2561 2562 usbdrd_dwc3_0: usb@fc000000 { 2563 compatible = "snps,dwc3"; 2564 reg = <0x0 0xfc000000 0x0 0x400000>; 2565 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 2566 power-domains = <&power RK3588_PD_USB>; 2567 resets = <&cru SRST_A_USB3OTG0>; 2568 reset-names = "usb3-otg"; 2569 dr_mode = "otg"; 2570 phys = <&u2phy0_otg>, <&usbdp_phy0_u3>; 2571 phy-names = "usb2-phy", "usb3-phy"; 2572 phy_type = "utmi_wide"; 2573 snps,dis_enblslpm_quirk; 2574 snps,dis-u1-entry-quirk; 2575 snps,dis-u2-entry-quirk; 2576 snps,dis-u2-freeclk-exists-quirk; 2577 snps,dis-del-phy-power-chg-quirk; 2578 snps,dis-tx-ipgap-linecheck-quirk; 2579 snps,parkmode-disable-ss-quirk; 2580 quirk-skip-phy-init; 2581 status = "disabled"; 2582 }; 2583 }; 2584 2585 usb_host0_ehci: usb@fc800000 { 2586 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 2587 reg = <0x0 0xfc800000 0x0 0x40000>; 2588 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 2589 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>; 2590 clock-names = "usbhost", "arbiter", "utmi"; 2591 companion = <&usb_host0_ohci>; 2592 phys = <&u2phy2_host>; 2593 phy-names = "usb2-phy"; 2594 power-domains = <&power RK3588_PD_USB>; 2595 status = "disabled"; 2596 }; 2597 2598 usb_host0_ohci: usb@fc840000 { 2599 compatible = "generic-ohci"; 2600 reg = <0x0 0xfc840000 0x0 0x40000>; 2601 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; 2602 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&u2phy2>; 2603 clock-names = "usbhost", "arbiter", "utmi"; 2604 phys = <&u2phy2_host>; 2605 phy-names = "usb2-phy"; 2606 power-domains = <&power RK3588_PD_USB>; 2607 status = "disabled"; 2608 }; 2609 2610 usb_host1_ehci: usb@fc880000 { 2611 compatible = "rockchip,rk3588-ehci", "generic-ehci"; 2612 reg = <0x0 0xfc880000 0x0 0x40000>; 2613 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 2614 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>; 2615 clock-names = "usbhost", "arbiter", "utmi"; 2616 companion = <&usb_host1_ohci>; 2617 phys = <&u2phy3_host>; 2618 phy-names = "usb2-phy"; 2619 power-domains = <&power RK3588_PD_USB>; 2620 status = "disabled"; 2621 }; 2622 2623 usb_host1_ohci: usb@fc8c0000 { 2624 compatible = "generic-ohci"; 2625 reg = <0x0 0xfc8c0000 0x0 0x40000>; 2626 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 2627 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&u2phy3>; 2628 clock-names = "usbhost", "arbiter", "utmi"; 2629 phys = <&u2phy3_host>; 2630 phy-names = "usb2-phy"; 2631 power-domains = <&power RK3588_PD_USB>; 2632 status = "disabled"; 2633 }; 2634 2635 mmu600_pcie: iommu@fc900000 { 2636 compatible = "arm,smmu-v3"; 2637 reg = <0x0 0xfc900000 0x0 0x200000>; 2638 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2639 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 2640 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2641 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>; 2642 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 2643 #iommu-cells = <1>; 2644 status = "disabled"; 2645 }; 2646 2647 mmu600_php: iommu@fcb00000 { 2648 compatible = "arm,smmu-v3"; 2649 reg = <0x0 0xfcb00000 0x0 0x200000>; 2650 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 2651 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 2652 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 2653 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; 2654 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 2655 #iommu-cells = <1>; 2656 status = "disabled"; 2657 }; 2658 2659 usbhost3_0: usbhost3_0 { 2660 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 2661 clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, 2662 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, 2663 <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>; 2664 clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe"; 2665 #address-cells = <2>; 2666 #size-cells = <2>; 2667 ranges; 2668 status = "disabled"; 2669 2670 usbhost_dwc3_0: usb@fcd00000 { 2671 compatible = "snps,dwc3"; 2672 reg = <0x0 0xfcd00000 0x0 0x400000>; 2673 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 2674 resets = <&cru SRST_A_USB3OTG2>; 2675 reset-names = "usb3-host"; 2676 dr_mode = "host"; 2677 phys = <&combphy2_psu PHY_TYPE_USB3>; 2678 phy-names = "usb3-phy"; 2679 phy_type = "utmi_wide"; 2680 snps,dis_enblslpm_quirk; 2681 snps,dis-u2-freeclk-exists-quirk; 2682 snps,dis-del-phy-power-chg-quirk; 2683 snps,dis-tx-ipgap-linecheck-quirk; 2684 snps,dis_rxdet_inp3_quirk; 2685 snps,parkmode-disable-ss-quirk; 2686 status = "disabled"; 2687 }; 2688 }; 2689 2690 pmu0_grf: syscon@fd588000 { 2691 compatible = "rockchip,rk3588-pmu0-grf", "syscon", "simple-mfd"; 2692 reg = <0x0 0xfd588000 0x0 0x2000>; 2693 2694 reboot_mode: reboot-mode { 2695 compatible = "syscon-reboot-mode"; 2696 offset = <0x80>; 2697 mode-bootloader = <BOOT_BL_DOWNLOAD>; 2698 mode-charge = <BOOT_CHARGING>; 2699 mode-fastboot = <BOOT_FASTBOOT>; 2700 mode-loader = <BOOT_BL_DOWNLOAD>; 2701 mode-normal = <BOOT_NORMAL>; 2702 mode-recovery = <BOOT_RECOVERY>; 2703 mode-ums = <BOOT_UMS>; 2704 mode-panic = <BOOT_PANIC>; 2705 mode-watchdog = <BOOT_WATCHDOG>; 2706 mode-quiescent = <BOOT_QUIESCENT>; 2707 }; 2708 }; 2709 2710 pmu1_grf: syscon@fd58a000 { 2711 compatible = "rockchip,rk3588-pmu1-grf", "syscon"; 2712 reg = <0x0 0xfd58a000 0x0 0x2000>; 2713 }; 2714 2715 sys_grf: syscon@fd58c000 { 2716 compatible = "rockchip,rk3588-sys-grf", "syscon", "simple-mfd"; 2717 reg = <0x0 0xfd58c000 0x0 0x1000>; 2718 2719 rgb: rgb { 2720 compatible = "rockchip,rk3588-rgb"; 2721 pinctrl-names = "default"; 2722 pinctrl-0 = <&bt1120_pins>; 2723 status = "disabled"; 2724 2725 ports { 2726 #address-cells = <1>; 2727 #size-cells = <0>; 2728 2729 port@0 { 2730 reg = <0>; 2731 #address-cells = <1>; 2732 #size-cells = <0>; 2733 2734 rgb_in_vp3: endpoint@2 { 2735 reg = <2>; 2736 remote-endpoint = <&vp3_out_rgb>; 2737 status = "disabled"; 2738 }; 2739 }; 2740 }; 2741 }; 2742 }; 2743 2744 bigcore0_grf: syscon@fd590000 { 2745 compatible = "rockchip,rk3588-bigcore0-grf", "syscon"; 2746 reg = <0x0 0xfd590000 0x0 0x100>; 2747 }; 2748 2749 bigcore1_grf: syscon@fd592000 { 2750 compatible = "rockchip,rk3588-bigcore1-grf", "syscon"; 2751 reg = <0x0 0xfd592000 0x0 0x100>; 2752 }; 2753 2754 litcore_grf: syscon@fd594000 { 2755 compatible = "rockchip,rk3588-litcore-grf", "syscon"; 2756 reg = <0x0 0xfd594000 0x0 0x100>; 2757 }; 2758 2759 dsu_grf: syscon@fd598000 { 2760 compatible = "rockchip,rk3588-dsu-grf", "syscon"; 2761 reg = <0x0 0xfd598000 0x0 0x100>; 2762 }; 2763 2764 gpu_grf: syscon@fd5a0000 { 2765 compatible = "rockchip,rk3588-gpu-grf", "syscon"; 2766 reg = <0x0 0xfd5a0000 0x0 0x100>; 2767 }; 2768 2769 npu_grf: syscon@fd5a2000 { 2770 compatible = "rockchip,rk3588-npu-grf", "syscon"; 2771 reg = <0x0 0xfd5a2000 0x0 0x100>; 2772 }; 2773 2774 vop_grf: syscon@fd5a4000 { 2775 compatible = "rockchip,rk3588-vop-grf", "syscon"; 2776 reg = <0x0 0xfd5a4000 0x0 0x2000>; 2777 }; 2778 2779 vo0_grf: syscon@fd5a6000 { 2780 compatible = "rockchip,rk3588-vo-grf", "syscon"; 2781 reg = <0x0 0xfd5a6000 0x0 0x2000>; 2782 clocks = <&pclk_vo0_grf>; 2783 }; 2784 2785 vo1_grf: syscon@fd5a8000 { 2786 compatible = "rockchip,rk3588-vo-grf", "syscon"; 2787 reg = <0x0 0xfd5a8000 0x0 0x100>; 2788 clocks = <&pclk_vo1_grf>; 2789 }; 2790 2791 usb_grf: syscon@fd5ac000 { 2792 compatible = "rockchip,rk3588-usb-grf", "syscon"; 2793 reg = <0x0 0xfd5ac000 0x0 0x4000>; 2794 }; 2795 2796 php_grf: syscon@fd5b0000 { 2797 compatible = "rockchip,rk3588-php-grf", "syscon"; 2798 reg = <0x0 0xfd5b0000 0x0 0x1000>; 2799 }; 2800 2801 mipidphy0_grf: syscon@fd5b4000 { 2802 compatible = "rockchip,mipi-dphy-grf", "syscon"; 2803 reg = <0x0 0xfd5b4000 0x0 0x1000>; 2804 }; 2805 2806 mipidphy1_grf: syscon@fd5b5000 { 2807 compatible = "rockchip,mipi-dphy-grf", "syscon"; 2808 reg = <0x0 0xfd5b5000 0x0 0x1000>; 2809 }; 2810 2811 pipe_phy0_grf: syscon@fd5bc000 { 2812 compatible = "rockchip,pipe-phy-grf", "syscon"; 2813 reg = <0x0 0xfd5bc000 0x0 0x100>; 2814 }; 2815 2816 pipe_phy2_grf: syscon@fd5c4000 { 2817 compatible = "rockchip,pipe-phy-grf", "syscon"; 2818 reg = <0x0 0xfd5c4000 0x0 0x100>; 2819 }; 2820 2821 usbdpphy0_grf: syscon@fd5c8000 { 2822 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 2823 reg = <0x0 0xfd5c8000 0x0 0x4000>; 2824 }; 2825 2826 usb2phy0_grf: syscon@fd5d0000 { 2827 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 2828 "simple-mfd"; 2829 reg = <0x0 0xfd5d0000 0x0 0x4000>; 2830 #address-cells = <1>; 2831 #size-cells = <1>; 2832 2833 u2phy0: usb2-phy@0 { 2834 compatible = "rockchip,rk3588-usb2phy"; 2835 reg = <0x0 0x10>; 2836 interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; 2837 resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>; 2838 reset-names = "phy", "apb"; 2839 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 2840 clock-names = "phyclk"; 2841 clock-output-names = "usb480m_phy0"; 2842 #clock-cells = <0>; 2843 rockchip,usbctrl-grf = <&usb_grf>; 2844 status = "disabled"; 2845 2846 u2phy0_otg: otg-port { 2847 #phy-cells = <0>; 2848 status = "disabled"; 2849 }; 2850 }; 2851 }; 2852 2853 usb2phy2_grf: syscon@fd5d8000 { 2854 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 2855 "simple-mfd"; 2856 reg = <0x0 0xfd5d8000 0x0 0x4000>; 2857 #address-cells = <1>; 2858 #size-cells = <1>; 2859 2860 u2phy2: usb2-phy@8000 { 2861 compatible = "rockchip,rk3588-usb2phy"; 2862 reg = <0x8000 0x10>; 2863 interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>; 2864 resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>; 2865 reset-names = "phy", "apb"; 2866 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 2867 clock-names = "phyclk"; 2868 clock-output-names = "usb480m_phy2"; 2869 #clock-cells = <0>; 2870 status = "disabled"; 2871 2872 u2phy2_host: host-port { 2873 #phy-cells = <0>; 2874 status = "disabled"; 2875 }; 2876 }; 2877 }; 2878 2879 usb2phy3_grf: syscon@fd5dc000 { 2880 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 2881 "simple-mfd"; 2882 reg = <0x0 0xfd5dc000 0x0 0x4000>; 2883 #address-cells = <1>; 2884 #size-cells = <1>; 2885 2886 u2phy3: usb2-phy@c000 { 2887 compatible = "rockchip,rk3588-usb2phy"; 2888 reg = <0xc000 0x10>; 2889 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>; 2890 resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>; 2891 reset-names = "phy", "apb"; 2892 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 2893 clock-names = "phyclk"; 2894 clock-output-names = "usb480m_phy3"; 2895 #clock-cells = <0>; 2896 status = "disabled"; 2897 2898 u2phy3_host: host-port { 2899 #phy-cells = <0>; 2900 status = "disabled"; 2901 }; 2902 }; 2903 }; 2904 2905 hdptxphy0_grf: syscon@fd5e0000 { 2906 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 2907 reg = <0x0 0xfd5e0000 0x0 0x100>; 2908 }; 2909 2910 mipidcphy0_grf: syscon@fd5e8000 { 2911 compatible = "rockchip,mipi-dcphy-grf", "syscon"; 2912 reg = <0x0 0xfd5e8000 0x0 0x4000>; 2913 }; 2914 2915 mipidcphy1_grf: syscon@fd5ec000 { 2916 compatible = "rockchip,mipi-dcphy-grf", "syscon"; 2917 reg = <0x0 0xfd5ec000 0x0 0x4000>; 2918 }; 2919 2920 ioc: syscon@fd5f0000 { 2921 compatible = "rockchip,rk3588-ioc", "syscon"; 2922 reg = <0x0 0xfd5f0000 0x0 0x10000>; 2923 }; 2924 2925 cru: clock-controller@fd7c0000 { 2926 compatible = "rockchip,rk3588-cru"; 2927 rockchip,grf = <&php_grf>; 2928 reg = <0x0 0xfd7c0000 0x0 0x5c000>; 2929 #clock-cells = <1>; 2930 #reset-cells = <1>; 2931 2932 assigned-clocks = 2933 <&cru PLL_PPLL>, <&cru PLL_AUPLL>, 2934 <&cru PLL_NPLL>, <&cru PLL_GPLL>, 2935 <&cru ACLK_CENTER_ROOT>, 2936 <&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>, 2937 <&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>, 2938 <&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>, 2939 <&cru HCLK_PMU_CM0_ROOT>, 2940 <&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>, 2941 <&cru CLK_GPU>, <&cru CLK_SPDIF2_DP0>, 2942 <&cru CLK_SPDIF5_DP1>, <&cru CLK_HDMIRX_AUD>, 2943 <&cru DCLK_DECOM>; 2944 assigned-clock-rates = 2945 <1100000000>, <786432000>, 2946 <850000000>, <1188000000>, 2947 <702000000>, 2948 <400000000>, <500000000>, 2949 <750000000>, <100000000>, 2950 <400000000>, <100000000>, 2951 <200000000>, 2952 <375000000>, <150000000>, 2953 <200000000>, <12000000>, 2954 <12000000>, <99000000>, 2955 <20000000>; 2956 }; 2957 2958 i2c0: i2c@fd880000 { 2959 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 2960 reg = <0x0 0xfd880000 0x0 0x1000>; 2961 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 2962 clock-names = "i2c", "pclk"; 2963 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 2964 pinctrl-names = "default"; 2965 pinctrl-0 = <&i2c0m0_xfer>; 2966 #address-cells = <1>; 2967 #size-cells = <0>; 2968 status = "disabled"; 2969 }; 2970 2971 uart0: serial@fd890000 { 2972 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 2973 reg = <0x0 0xfd890000 0x0 0x100>; 2974 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 2975 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 2976 clock-names = "baudclk", "apb_pclk"; 2977 reg-shift = <2>; 2978 reg-io-width = <4>; 2979 dmas = <&dmac0 6>, <&dmac0 7>; 2980 pinctrl-names = "default"; 2981 pinctrl-0 = <&uart0m1_xfer>; 2982 status = "disabled"; 2983 }; 2984 2985 pwm0: pwm@fd8b0000 { 2986 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2987 reg = <0x0 0xfd8b0000 0x0 0x10>; 2988 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 2989 #pwm-cells = <3>; 2990 pinctrl-names = "active"; 2991 pinctrl-0 = <&pwm0m0_pins>; 2992 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 2993 clock-names = "pwm", "pclk"; 2994 status = "disabled"; 2995 }; 2996 2997 pwm1: pwm@fd8b0010 { 2998 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 2999 reg = <0x0 0xfd8b0010 0x0 0x10>; 3000 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 3001 #pwm-cells = <3>; 3002 pinctrl-names = "active"; 3003 pinctrl-0 = <&pwm1m0_pins>; 3004 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 3005 clock-names = "pwm", "pclk"; 3006 status = "disabled"; 3007 }; 3008 3009 pwm2: pwm@fd8b0020 { 3010 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 3011 reg = <0x0 0xfd8b0020 0x0 0x10>; 3012 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 3013 #pwm-cells = <3>; 3014 pinctrl-names = "active"; 3015 pinctrl-0 = <&pwm2m0_pins>; 3016 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 3017 clock-names = "pwm", "pclk"; 3018 status = "disabled"; 3019 }; 3020 3021 pwm3: pwm@fd8b0030 { 3022 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 3023 reg = <0x0 0xfd8b0030 0x0 0x10>; 3024 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3025 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; 3026 #pwm-cells = <3>; 3027 pinctrl-names = "active"; 3028 pinctrl-0 = <&pwm3m0_pins>; 3029 clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>; 3030 clock-names = "pwm", "pclk"; 3031 status = "disabled"; 3032 }; 3033 3034 pmu: power-management@fd8d8000 { 3035 compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd"; 3036 reg = <0x0 0xfd8d8000 0x0 0x400>; 3037 3038 power: power-controller { 3039 compatible = "rockchip,rk3588-power-controller"; 3040 #power-domain-cells = <1>; 3041 #address-cells = <1>; 3042 #size-cells = <0>; 3043 status = "okay"; 3044 3045 /* These power domains are grouped by VD_NPU */ 3046 power-domain@RK3588_PD_NPU { 3047 reg = <RK3588_PD_NPU>; 3048 #address-cells = <1>; 3049 #size-cells = <0>; 3050 3051 power-domain@RK3588_PD_NPUTOP { 3052 reg = <RK3588_PD_NPUTOP>; 3053 #address-cells = <1>; 3054 #size-cells = <0>; 3055 clocks = <&cru HCLK_NPU_ROOT>, 3056 <&cru PCLK_NPU_ROOT>, 3057 <&cru CLK_NPU_DSU0>, 3058 <&cru HCLK_NPU_CM0_ROOT>; 3059 pm_qos = <&qos_npu0_mwr>, 3060 <&qos_npu0_mro>, 3061 <&qos_mcu_npu>; 3062 3063 power-domain@RK3588_PD_NPU1 { 3064 reg = <RK3588_PD_NPU1>; 3065 clocks = <&cru HCLK_NPU_ROOT>, 3066 <&cru PCLK_NPU_ROOT>, 3067 <&cru CLK_NPU_DSU0>; 3068 pm_qos = <&qos_npu1>; 3069 }; 3070 power-domain@RK3588_PD_NPU2 { 3071 reg = <RK3588_PD_NPU2>; 3072 clocks = <&cru HCLK_NPU_ROOT>, 3073 <&cru PCLK_NPU_ROOT>, 3074 <&cru CLK_NPU_DSU0>; 3075 pm_qos = <&qos_npu2>; 3076 }; 3077 }; 3078 }; 3079 /* These power domains are grouped by VD_GPU */ 3080 power-domain@RK3588_PD_GPU { 3081 reg = <RK3588_PD_GPU>; 3082 clocks = <&cru CLK_GPU>, 3083 <&cru CLK_GPU_COREGROUP>, 3084 <&cru CLK_GPU_STACKS>; 3085 pm_qos = <&qos_gpu_m0>, 3086 <&qos_gpu_m1>, 3087 <&qos_gpu_m2>, 3088 <&qos_gpu_m3>; 3089 }; 3090 /* These power domains are grouped by VD_VCODEC */ 3091 power-domain@RK3588_PD_VCODEC { 3092 reg = <RK3588_PD_VCODEC>; 3093 #address-cells = <1>; 3094 #size-cells = <0>; 3095 3096 power-domain@RK3588_PD_RKVDEC0 { 3097 reg = <RK3588_PD_RKVDEC0>; 3098 clocks = <&cru HCLK_RKVDEC0>, 3099 <&cru HCLK_VDPU_ROOT>, 3100 <&cru ACLK_VDPU_ROOT>, 3101 <&cru ACLK_RKVDEC0>, 3102 <&cru ACLK_RKVDEC_CCU>; 3103 pm_qos = <&qos_rkvdec0>; 3104 }; 3105 power-domain@RK3588_PD_RKVDEC1 { 3106 reg = <RK3588_PD_RKVDEC1>; 3107 clocks = <&cru HCLK_RKVDEC1>, 3108 <&cru HCLK_VDPU_ROOT>, 3109 <&cru ACLK_VDPU_ROOT>, 3110 <&cru ACLK_RKVDEC1>; 3111 pm_qos = <&qos_rkvdec1>; 3112 }; 3113 power-domain@RK3588_PD_VENC0 { 3114 reg = <RK3588_PD_VENC0>; 3115 #address-cells = <1>; 3116 #size-cells = <0>; 3117 clocks = <&cru HCLK_RKVENC0>, 3118 <&cru ACLK_RKVENC0>; 3119 pm_qos = <&qos_rkvenc0_m0ro>, 3120 <&qos_rkvenc0_m1ro>, 3121 <&qos_rkvenc0_m2wo>; 3122 3123 power-domain@RK3588_PD_VENC1 { 3124 reg = <RK3588_PD_VENC1>; 3125 clocks = <&cru HCLK_RKVENC1>, 3126 <&cru HCLK_RKVENC0>, 3127 <&cru ACLK_RKVENC0>, 3128 <&cru ACLK_RKVENC1>; 3129 pm_qos = <&qos_rkvenc1_m0ro>, 3130 <&qos_rkvenc1_m1ro>, 3131 <&qos_rkvenc1_m2wo>; 3132 }; 3133 }; 3134 }; 3135 /* These power domains are grouped by VD_LOGIC */ 3136 power-domain@RK3588_PD_VDPU { 3137 reg = <RK3588_PD_VDPU>; 3138 #address-cells = <1>; 3139 #size-cells = <0>; 3140 clocks = <&cru HCLK_VDPU_ROOT>, 3141 <&cru ACLK_VDPU_LOW_ROOT>, 3142 <&cru ACLK_VDPU_ROOT>, 3143 <&cru ACLK_JPEG_DECODER_ROOT>, 3144 <&cru ACLK_IEP2P0>, 3145 <&cru HCLK_IEP2P0>, 3146 <&cru ACLK_JPEG_ENCODER0>, 3147 <&cru HCLK_JPEG_ENCODER0>, 3148 <&cru ACLK_JPEG_ENCODER1>, 3149 <&cru HCLK_JPEG_ENCODER1>, 3150 <&cru ACLK_JPEG_ENCODER2>, 3151 <&cru HCLK_JPEG_ENCODER2>, 3152 <&cru ACLK_JPEG_ENCODER3>, 3153 <&cru HCLK_JPEG_ENCODER3>, 3154 <&cru ACLK_JPEG_DECODER>, 3155 <&cru HCLK_JPEG_DECODER>, 3156 <&cru ACLK_RGA2>, 3157 <&cru HCLK_RGA2>; 3158 pm_qos = <&qos_iep>, 3159 <&qos_jpeg_dec>, 3160 <&qos_jpeg_enc0>, 3161 <&qos_jpeg_enc1>, 3162 <&qos_jpeg_enc2>, 3163 <&qos_jpeg_enc3>, 3164 <&qos_rga2_mro>, 3165 <&qos_rga2_mwo>; 3166 3167 power-domain@RK3588_PD_AV1 { 3168 reg = <RK3588_PD_AV1>; 3169 clocks = <&cru PCLK_AV1>, 3170 <&cru ACLK_AV1>, 3171 <&cru HCLK_VDPU_ROOT>; 3172 pm_qos = <&qos_av1>; 3173 }; 3174 power-domain@RK3588_PD_RKVDEC0 { 3175 reg = <RK3588_PD_RKVDEC0>; 3176 clocks = <&cru HCLK_RKVDEC0>, 3177 <&cru HCLK_VDPU_ROOT>, 3178 <&cru ACLK_VDPU_ROOT>, 3179 <&cru ACLK_RKVDEC0>; 3180 pm_qos = <&qos_rkvdec0>; 3181 }; 3182 power-domain@RK3588_PD_RKVDEC1 { 3183 reg = <RK3588_PD_RKVDEC1>; 3184 clocks = <&cru HCLK_RKVDEC1>, 3185 <&cru HCLK_VDPU_ROOT>, 3186 <&cru ACLK_VDPU_ROOT>; 3187 pm_qos = <&qos_rkvdec1>; 3188 }; 3189 power-domain@RK3588_PD_RGA30 { 3190 reg = <RK3588_PD_RGA30>; 3191 clocks = <&cru ACLK_RGA3_0>, 3192 <&cru HCLK_RGA3_0>; 3193 pm_qos = <&qos_rga3_0>; 3194 }; 3195 }; 3196 power-domain@RK3588_PD_VOP { 3197 reg = <RK3588_PD_VOP>; 3198 #address-cells = <1>; 3199 #size-cells = <0>; 3200 clocks = <&cru PCLK_VOP_ROOT>, 3201 <&cru HCLK_VOP_ROOT>, 3202 <&cru ACLK_VOP>; 3203 pm_qos = <&qos_vop_m0>, 3204 <&qos_vop_m1>; 3205 3206 power-domain@RK3588_PD_VO0 { 3207 reg = <RK3588_PD_VO0>; 3208 clocks = <&cru PCLK_VO0_ROOT>, 3209 <&cru PCLK_VO0_S_ROOT>, 3210 <&cru HCLK_VO0_S_ROOT>, 3211 <&cru ACLK_VO0_ROOT>, 3212 <&cru HCLK_HDCP0>, 3213 <&cru ACLK_HDCP0>, 3214 <&cru HCLK_VOP_ROOT>; 3215 pm_qos = <&qos_hdcp0>; 3216 }; 3217 }; 3218 power-domain@RK3588_PD_VO1 { 3219 reg = <RK3588_PD_VO1>; 3220 clocks = <&cru PCLK_VO1_ROOT>, 3221 <&cru PCLK_VO1_S_ROOT>, 3222 <&cru HCLK_VO1_S_ROOT>, 3223 <&cru HCLK_HDCP1>, 3224 <&cru ACLK_HDCP1>, 3225 <&cru ACLK_HDMIRX_ROOT>, 3226 <&cru HCLK_VO1USB_TOP_ROOT>; 3227 pm_qos = <&qos_hdcp1>, 3228 <&qos_hdmirx>; 3229 }; 3230 power-domain@RK3588_PD_VI { 3231 reg = <RK3588_PD_VI>; 3232 #address-cells = <1>; 3233 #size-cells = <0>; 3234 clocks = <&cru HCLK_VI_ROOT>, 3235 <&cru PCLK_VI_ROOT>, 3236 <&cru HCLK_ISP0>, 3237 <&cru ACLK_ISP0>, 3238 <&cru HCLK_VICAP>, 3239 <&cru ACLK_VICAP>; 3240 pm_qos = <&qos_isp0_mro>, 3241 <&qos_isp0_mwo>, 3242 <&qos_vicap_m0>, 3243 <&qos_vicap_m1>; 3244 3245 power-domain@RK3588_PD_ISP1 { 3246 reg = <RK3588_PD_ISP1>; 3247 clocks = <&cru HCLK_ISP1>, 3248 <&cru ACLK_ISP1>, 3249 <&cru HCLK_VI_ROOT>, 3250 <&cru PCLK_VI_ROOT>; 3251 pm_qos = <&qos_isp1_mwo>, 3252 <&qos_isp1_mro>; 3253 }; 3254 power-domain@RK3588_PD_FEC { 3255 reg = <RK3588_PD_FEC>; 3256 clocks = <&cru HCLK_FISHEYE0>, 3257 <&cru ACLK_FISHEYE0>, 3258 <&cru HCLK_FISHEYE1>, 3259 <&cru ACLK_FISHEYE1>, 3260 <&cru PCLK_VI_ROOT>; 3261 pm_qos = <&qos_fisheye0>, 3262 <&qos_fisheye1>; 3263 }; 3264 }; 3265 power-domain@RK3588_PD_RGA31 { 3266 reg = <RK3588_PD_RGA31>; 3267 clocks = <&cru HCLK_RGA3_1>, 3268 <&cru ACLK_RGA3_1>; 3269 pm_qos = <&qos_rga3_1>; 3270 }; 3271 power-domain@RK3588_PD_USB { 3272 reg = <RK3588_PD_USB>; 3273 clocks = <&cru PCLK_PHP_ROOT>, 3274 <&cru ACLK_USB_ROOT>, 3275 <&cru HCLK_USB_ROOT>, 3276 <&cru HCLK_HOST0>, 3277 <&cru HCLK_HOST_ARB0>, 3278 <&cru HCLK_HOST1>, 3279 <&cru HCLK_HOST_ARB1>; 3280 pm_qos = <&qos_usb3_0>, 3281 <&qos_usb3_1>, 3282 <&qos_usb2host_0>, 3283 <&qos_usb2host_1>; 3284 }; 3285 power-domain@RK3588_PD_GMAC { 3286 reg = <RK3588_PD_GMAC>; 3287 clocks = <&cru PCLK_PHP_ROOT>, 3288 <&cru ACLK_PCIE_ROOT>, 3289 <&cru ACLK_PHP_ROOT>; 3290 }; 3291 power-domain@RK3588_PD_PCIE { 3292 reg = <RK3588_PD_PCIE>; 3293 clocks = <&cru PCLK_PHP_ROOT>, 3294 <&cru ACLK_PCIE_ROOT>, 3295 <&cru ACLK_PHP_ROOT>; 3296 }; 3297 power-domain@RK3588_PD_SDIO { 3298 reg = <RK3588_PD_SDIO>; 3299 clocks = <&cru HCLK_SDIO>, 3300 <&cru HCLK_NVM_ROOT>; 3301 pm_qos = <&qos_sdio>; 3302 }; 3303 power-domain@RK3588_PD_AUDIO { 3304 reg = <RK3588_PD_AUDIO>; 3305 clocks = <&cru HCLK_AUDIO_ROOT>, 3306 <&cru PCLK_AUDIO_ROOT>; 3307 }; 3308 power-domain@RK3588_PD_SDMMC { 3309 reg = <RK3588_PD_SDMMC>; 3310 pm_qos = <&qos_sdmmc>; 3311 }; 3312 }; 3313 }; 3314 3315 pvtm@fda40000 { 3316 compatible = "rockchip,rk3588-bigcore0-pvtm"; 3317 reg = <0x0 0xfda40000 0x0 0x100>; 3318 #address-cells = <1>; 3319 #size-cells = <0>; 3320 pvtm@0 { 3321 reg = <0>; 3322 clocks = <&cru CLK_BIGCORE0_PVTM>, <&cru PCLK_BIGCORE0_PVTM>; 3323 clock-names = "clk", "pclk"; 3324 }; 3325 }; 3326 3327 pvtm@fda50000 { 3328 compatible = "rockchip,rk3588-bigcore1-pvtm"; 3329 reg = <0x0 0xfda50000 0x0 0x100>; 3330 #address-cells = <1>; 3331 #size-cells = <0>; 3332 pvtm@1 { 3333 reg = <1>; 3334 clocks = <&cru CLK_BIGCORE1_PVTM>, <&cru PCLK_BIGCORE1_PVTM>; 3335 clock-names = "clk", "pclk"; 3336 }; 3337 }; 3338 3339 pvtm@fda60000 { 3340 compatible = "rockchip,rk3588-litcore-pvtm"; 3341 reg = <0x0 0xfda60000 0x0 0x100>; 3342 #address-cells = <1>; 3343 #size-cells = <0>; 3344 pvtm@2 { 3345 reg = <2>; 3346 clocks = <&cru CLK_LITCORE_PVTM>, <&cru PCLK_LITCORE_PVTM>; 3347 clock-names = "clk", "pclk"; 3348 }; 3349 }; 3350 3351 pvtm@fdaf0000 { 3352 compatible = "rockchip,rk3588-npu-pvtm"; 3353 reg = <0x0 0xfdaf0000 0x0 0x100>; 3354 #address-cells = <1>; 3355 #size-cells = <0>; 3356 pvtm@3 { 3357 reg = <3>; 3358 clocks = <&cru CLK_NPU_PVTM>, <&cru PCLK_NPU_PVTM>; 3359 clock-names = "clk", "pclk"; 3360 resets = <&cru SRST_NPU_PVTM>, <&cru SRST_P_NPU_PVTM>; 3361 reset-names = "rts", "rst-p"; 3362 }; 3363 }; 3364 3365 pvtm@fdb30000 { 3366 compatible = "rockchip,rk3588-gpu-pvtm"; 3367 reg = <0x0 0xfdb30000 0x0 0x100>; 3368 #address-cells = <1>; 3369 #size-cells = <0>; 3370 pvtm@4 { 3371 reg = <4>; 3372 clocks = <&cru CLK_GPU_PVTM>; 3373 clock-names = "clk"; 3374 resets = <&cru SRST_GPU_PVTM>, <&cru SRST_P_GPU_PVTM>; 3375 reset-names = "rts", "rst-p"; 3376 }; 3377 }; 3378 3379 rknpu: npu@fdab0000 { 3380 compatible = "rockchip,rk3588-rknpu"; 3381 reg = <0x0 0xfdab0000 0x0 0x10000>, 3382 <0x0 0xfdac0000 0x0 0x10000>, 3383 <0x0 0xfdad0000 0x0 0x10000>; 3384 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 3387 interrupt-names = "npu0_irq", "npu1_irq", "npu2_irq"; 3388 clocks = <&scmi_clk SCMI_CLK_NPU>, <&cru ACLK_NPU0>, 3389 <&cru ACLK_NPU1>, <&cru ACLK_NPU2>, 3390 <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, 3391 <&cru HCLK_NPU2>, <&cru PCLK_NPU_ROOT>; 3392 clock-names = "clk_npu", "aclk0", 3393 "aclk1", "aclk2", 3394 "hclk0", "hclk1", 3395 "hclk2", "pclk"; 3396 assigned-clocks = <&scmi_clk SCMI_CLK_NPU>; 3397 assigned-clock-rates = <200000000>; 3398 resets = <&cru SRST_A_RKNN0>, <&cru SRST_A_RKNN1>, <&cru SRST_A_RKNN2>, 3399 <&cru SRST_H_RKNN0>, <&cru SRST_H_RKNN1>, <&cru SRST_H_RKNN2>; 3400 reset-names = "srst_a0", "srst_a1", "srst_a2", 3401 "srst_h0", "srst_h1", "srst_h2"; 3402 power-domains = <&power RK3588_PD_NPUTOP>, 3403 <&power RK3588_PD_NPU1>, 3404 <&power RK3588_PD_NPU2>; 3405 power-domain-names = "npu0", "npu1", "npu2"; 3406 operating-points-v2 = <&npu_opp_table>; 3407 iommus = <&rknpu_mmu>; 3408 status = "disabled"; 3409 }; 3410 3411 npu_opp_table: npu-opp-table { 3412 compatible = "operating-points-v2"; 3413 3414 nvmem-cells = <&npu_leakage>, <&npu_opp_info>, <&specification_serial_number>; 3415 nvmem-cell-names = "leakage", "opp-info", "specification_serial_number"; 3416 rockchip,supported-hw; 3417 3418 rockchip,pvtm-hw = <0x06>; 3419 rockchip,pvtm-voltage-sel-hw = < 3420 0 799 0 3421 800 819 1 3422 820 844 2 3423 845 869 3 3424 870 894 4 3425 895 9999 5 3426 >; 3427 rockchip,pvtm-voltage-sel = < 3428 0 815 0 3429 816 835 1 3430 836 860 2 3431 861 885 3 3432 886 910 4 3433 911 9999 5 3434 >; 3435 rockchip,pvtm-pvtpll; 3436 rockchip,pvtm-offset = <0x50>; 3437 rockchip,pvtm-sample-time = <1100>; 3438 rockchip,pvtm-freq = <800000>; 3439 rockchip,pvtm-volt = <750000>; 3440 rockchip,pvtm-ref-temp = <25>; 3441 rockchip,pvtm-temp-prop = <(-113) (-113)>; 3442 rockchip,pvtm-thermal-zone = "npu-thermal"; 3443 3444 clocks = <&cru PCLK_NPU_GRF>; 3445 clock-names = "pclk"; 3446 rockchip,grf = <&npu_grf>; 3447 volt-mem-read-margin = < 3448 855000 1 3449 765000 2 3450 675000 3 3451 495000 4 3452 >; 3453 low-volt-mem-read-margin = <4>; 3454 intermediate-threshold-freq = <500000>; /* KHz*/ 3455 rockchip,init-freq = <1000000>; /* KHz */ 3456 3457 rockchip,temp-hysteresis = <5000>; 3458 rockchip,low-temp = <10000>; 3459 rockchip,low-temp-min-volt = <750000>; 3460 rockchip,high-temp = <85000>; 3461 rockchip,high-temp-max-freq = <800000>; 3462 3463 /* RK3588 npu OPPs */ 3464 opp-300000000 { 3465 opp-supported-hw = <0xf9 0xffff>; 3466 opp-hz = /bits/ 64 <300000000>; 3467 opp-microvolt = <700000 700000 850000>, 3468 <700000 700000 850000>; 3469 opp-microvolt-L1 = <687500 687500 850000>, 3470 <687500 687500 850000>; 3471 opp-microvolt-L2 = <675000 675000 850000>, 3472 <675000 675000 850000>; 3473 opp-microvolt-L3 = <675000 675000 850000>, 3474 <675000 675000 850000>; 3475 opp-microvolt-L4 = <675000 675000 850000>, 3476 <675000 675000 850000>; 3477 opp-microvolt-L5 = <675000 675000 850000>, 3478 <675000 675000 850000>; 3479 }; 3480 opp-400000000 { 3481 opp-supported-hw = <0xf9 0xffff>; 3482 opp-hz = /bits/ 64 <400000000>; 3483 opp-microvolt = <700000 700000 850000>, 3484 <700000 700000 850000>; 3485 opp-microvolt-L1 = <687500 687500 850000>, 3486 <687500 687500 850000>; 3487 opp-microvolt-L2 = <675000 675000 850000>, 3488 <675000 675000 850000>; 3489 opp-microvolt-L3 = <675000 675000 850000>, 3490 <675000 675000 850000>; 3491 opp-microvolt-L4 = <675000 675000 850000>, 3492 <675000 675000 850000>; 3493 opp-microvolt-L5 = <675000 675000 850000>, 3494 <675000 675000 850000>; 3495 }; 3496 opp-500000000 { 3497 opp-supported-hw = <0xf9 0xffff>; 3498 opp-hz = /bits/ 64 <500000000>; 3499 opp-microvolt = <700000 700000 850000>, 3500 <700000 700000 850000>; 3501 opp-microvolt-L1 = <687500 687500 850000>, 3502 <687500 687500 850000>; 3503 opp-microvolt-L2 = <675000 675000 850000>, 3504 <675000 675000 850000>; 3505 opp-microvolt-L3 = <675000 675000 850000>, 3506 <675000 675000 850000>; 3507 opp-microvolt-L4 = <675000 675000 850000>, 3508 <675000 675000 850000>; 3509 opp-microvolt-L5 = <675000 675000 850000>, 3510 <675000 675000 850000>; 3511 }; 3512 opp-600000000 { 3513 opp-supported-hw = <0xf9 0xffff>; 3514 opp-hz = /bits/ 64 <600000000>; 3515 opp-microvolt = <700000 700000 850000>, 3516 <700000 700000 850000>; 3517 opp-microvolt-L1 = <687500 687500 850000>, 3518 <687500 687500 850000>; 3519 opp-microvolt-L2 = <675000 675000 850000>, 3520 <675000 675000 850000>; 3521 opp-microvolt-L3 = <675000 675000 850000>, 3522 <675000 675000 850000>; 3523 opp-microvolt-L4 = <675000 675000 850000>, 3524 <675000 675000 850000>; 3525 opp-microvolt-L5 = <675000 675000 850000>, 3526 <675000 675000 850000>; 3527 }; 3528 opp-700000000 { 3529 opp-supported-hw = <0xf9 0xffff>; 3530 opp-hz = /bits/ 64 <700000000>; 3531 opp-microvolt = <700000 700000 850000>, 3532 <700000 700000 850000>; 3533 opp-microvolt-L3 = <687500 687500 850000>, 3534 <687500 687500 850000>; 3535 opp-microvolt-L4 = <675000 675000 850000>, 3536 <675000 675000 850000>; 3537 opp-microvolt-L5 = <675000 675000 850000>, 3538 <675000 675000 850000>; 3539 }; 3540 opp-800000000 { 3541 opp-supported-hw = <0xf9 0xffff>; 3542 opp-hz = /bits/ 64 <800000000>; 3543 opp-microvolt = <750000 750000 850000>, 3544 <750000 750000 850000>; 3545 opp-microvolt-L2 = <737500 737500 850000>, 3546 <737500 737500 850000>; 3547 opp-microvolt-L3 = <725000 725000 850000>, 3548 <725000 725000 850000>; 3549 opp-microvolt-L4 = <712500 712500 850000>, 3550 <712500 712500 850000>; 3551 opp-microvolt-L5 = <700000 700000 850000>, 3552 <700000 700000 850000>; 3553 }; 3554 opp-900000000 { 3555 opp-supported-hw = <0xf9 0xffff>; 3556 opp-hz = /bits/ 64 <900000000>; 3557 opp-microvolt = <800000 800000 850000>, 3558 <800000 800000 850000>; 3559 opp-microvolt-L1 = <787500 787500 850000>, 3560 <787500 787500 850000>; 3561 opp-microvolt-L2 = <775000 775000 850000>, 3562 <775000 775000 850000>; 3563 opp-microvolt-L3 = <762500 762500 850000>, 3564 <762500 762500 850000>; 3565 opp-microvolt-L4 = <750000 750000 850000>, 3566 <750000 750000 850000>; 3567 opp-microvolt-L5 = <737500 737500 850000>, 3568 <737500 737500 850000>; 3569 }; 3570 opp-1000000000 { 3571 opp-supported-hw = <0xf9 0xffff>; 3572 opp-hz = /bits/ 64 <1000000000>; 3573 opp-microvolt = <850000 850000 850000>, 3574 <850000 850000 850000>; 3575 opp-microvolt-L1 = <837500 837500 850000>, 3576 <837500 837500 850000>; 3577 opp-microvolt-L2 = <825000 825000 850000>, 3578 <825000 825000 850000>; 3579 opp-microvolt-L3 = <812500 812500 850000>, 3580 <812500 812500 850000>; 3581 opp-microvolt-L4 = <800000 800000 850000>, 3582 <800000 800000 850000>; 3583 opp-microvolt-L5 = <787500 787500 850000>, 3584 <787500 787500 850000>; 3585 }; 3586 3587 /* RK3588J/M npu OPPs */ 3588 opp-j-m-300000000 { 3589 opp-supported-hw = <0x06 0xffff>; 3590 opp-hz = /bits/ 64 <300000000>; 3591 opp-microvolt = <750000 750000 850000>, 3592 <750000 750000 850000>; 3593 }; 3594 opp-j-m-400000000 { 3595 opp-supported-hw = <0x06 0xffff>; 3596 opp-hz = /bits/ 64 <400000000>; 3597 opp-microvolt = <750000 750000 850000>, 3598 <750000 750000 850000>; 3599 }; 3600 opp-j-m-500000000 { 3601 opp-supported-hw = <0x06 0xffff>; 3602 opp-hz = /bits/ 64 <500000000>; 3603 opp-microvolt = <750000 750000 850000>, 3604 <750000 750000 850000>; 3605 }; 3606 opp-j-m-600000000 { 3607 opp-supported-hw = <0x06 0xffff>; 3608 opp-hz = /bits/ 64 <600000000>; 3609 opp-microvolt = <750000 750000 850000>, 3610 <750000 750000 850000>; 3611 }; 3612 opp-j-m-700000000 { 3613 opp-supported-hw = <0x06 0xffff>; 3614 opp-hz = /bits/ 64 <700000000>; 3615 opp-microvolt = <750000 750000 850000>, 3616 <750000 750000 850000>; 3617 }; 3618 opp-j-m-800000000 { 3619 opp-supported-hw = <0x06 0xffff>; 3620 opp-hz = /bits/ 64 <800000000>; 3621 opp-microvolt = <750000 750000 850000>, 3622 <750000 750000 850000>; 3623 }; 3624 opp-j-m-950000000 { 3625 opp-supported-hw = <0x06 0xffff>; 3626 opp-hz = /bits/ 64 <950000000>; 3627 opp-microvolt = <837500 837500 850000>, 3628 <837500 837500 850000>; 3629 opp-microvolt-L1 = <825000 825000 850000>, 3630 <825000 825000 850000>; 3631 opp-microvolt-L2 = <812500 812500 850000>, 3632 <812500 812500 850000>; 3633 opp-microvolt-L3 = <800000 800000 850000>, 3634 <800000 800000 850000>; 3635 opp-microvolt-L4 = <787500 787500 850000>, 3636 <787500 787500 850000>; 3637 opp-microvolt-L5 = <775000 775000 850000>, 3638 <775000 775000 850000>; 3639 }; 3640 }; 3641 3642 rknpu_mmu: iommu@fdab9000 { 3643 compatible = "rockchip,iommu-v2"; 3644 reg = <0x0 0xfdab9000 0x0 0x100>, 3645 <0x0 0xfdaba000 0x0 0x100>, 3646 <0x0 0xfdaca000 0x0 0x100>, 3647 <0x0 0xfdada000 0x0 0x100>; 3648 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3649 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3650 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 3651 interrupt-names = "npu0_mmu", "npu1_mmu", "npu2_mmu"; 3652 clocks = <&cru ACLK_NPU0>, <&cru ACLK_NPU1>, <&cru ACLK_NPU2>, 3653 <&cru HCLK_NPU0>, <&cru HCLK_NPU1>, <&cru HCLK_NPU2>; 3654 clock-names = "aclk0", "aclk1", "aclk2", 3655 "iface0", "iface1", "iface2"; 3656 #iommu-cells = <0>; 3657 status = "disabled"; 3658 }; 3659 3660 vepu: vepu@fdb50000 { 3661 compatible = "rockchip,vpu-encoder-v2"; 3662 reg = <0x0 0xfdb50000 0x0 0x400>; 3663 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 3664 interrupt-names = "irq_vepu"; 3665 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 3666 clock-names = "aclk_vcodec", "hclk_vcodec"; 3667 rockchip,normal-rates = <594000000>, <0>; 3668 assigned-clocks = <&cru ACLK_VPU>; 3669 assigned-clock-rates = <594000000>; 3670 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; 3671 reset-names = "shared_video_a", "shared_video_h"; 3672 rockchip,skip-pmu-idle-request; 3673 rockchip,disable-auto-freq; 3674 iommus = <&vdpu_mmu>; 3675 rockchip,srv = <&mpp_srv>; 3676 rockchip,taskqueue-node = <0>; 3677 rockchip,resetgroup-node = <0>; 3678 power-domains = <&power RK3588_PD_VDPU>; 3679 status = "disabled"; 3680 }; 3681 3682 vdpu: vdpu@fdb50400 { 3683 compatible = "rockchip,vpu-decoder-v2"; 3684 reg = <0x0 0xfdb50400 0x0 0x400>; 3685 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 3686 interrupt-names = "irq_vdpu"; 3687 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 3688 clock-names = "aclk_vcodec", "hclk_vcodec"; 3689 rockchip,normal-rates = <594000000>, <0>; 3690 assigned-clocks = <&cru ACLK_VPU>; 3691 assigned-clock-rates = <594000000>; 3692 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; 3693 reset-names = "shared_video_a", "shared_video_h"; 3694 rockchip,skip-pmu-idle-request; 3695 rockchip,disable-auto-freq; 3696 iommus = <&vdpu_mmu>; 3697 rockchip,srv = <&mpp_srv>; 3698 rockchip,taskqueue-node = <0>; 3699 rockchip,resetgroup-node = <0>; 3700 power-domains = <&power RK3588_PD_VDPU>; 3701 status = "disabled"; 3702 }; 3703 3704 vdpu_mmu: iommu@fdb50800 { 3705 compatible = "rockchip,iommu-v2"; 3706 reg = <0x0 0xfdb50800 0x0 0x40>; 3707 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 3708 interrupt-names = "irq_vdpu_mmu"; 3709 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 3710 clock-names = "aclk", "iface"; 3711 power-domains = <&power RK3588_PD_VDPU>; 3712 #iommu-cells = <0>; 3713 status = "disabled"; 3714 }; 3715 3716 avsd: avsd-plus@fdb51000 { 3717 compatible = "rockchip,avs-plus-decoder"; 3718 reg = <0x0 0xfdb51000 0x0 0x200>; 3719 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 3720 interrupt-names = "irq_avsd"; 3721 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 3722 clock-names = "aclk_vcodec", "hclk_vcodec"; 3723 rockchip,normal-rates = <594000000>, <0>; 3724 assigned-clocks = <&cru ACLK_VPU>; 3725 assigned-clock-rates = <594000000>; 3726 resets = <&cru SRST_A_VPU>, <&cru SRST_H_VPU>; 3727 reset-names = "shared_video_a", "shared_video_h"; 3728 rockchip,skip-pmu-idle-request; 3729 rockchip,disable-auto-freq; 3730 iommus = <&vdpu_mmu>; 3731 power-domains = <&power RK3588_PD_VDPU>; 3732 rockchip,srv = <&mpp_srv>; 3733 rockchip,taskqueue-node = <0>; 3734 rockchip,resetgroup-node = <0>; 3735 status = "disabled"; 3736 }; 3737 3738 rga3_core0: rga@fdb60000 { 3739 compatible = "rockchip,rga3_core0"; 3740 reg = <0x0 0xfdb60000 0x0 0x1000>; 3741 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3742 interrupt-names = "rga3_core0_irq"; 3743 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>; 3744 clock-names = "aclk_rga3_0", "hclk_rga3_0", "clk_rga3_0"; 3745 power-domains = <&power RK3588_PD_RGA30>; 3746 iommus = <&rga3_0_mmu>; 3747 status = "disabled"; 3748 }; 3749 3750 rga3_0_mmu: iommu@fdb60f00 { 3751 compatible = "rockchip,iommu-v2"; 3752 reg = <0x0 0xfdb60f00 0x0 0x100>; 3753 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 3754 interrupt-names = "rga3_0_mmu"; 3755 clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; 3756 clock-names = "aclk", "iface"; 3757 power-domains = <&power RK3588_PD_RGA30>; 3758 #iommu-cells = <0>; 3759 status = "disabled"; 3760 }; 3761 3762 rga3_core1: rga@fdb70000 { 3763 compatible = "rockchip,rga3_core1"; 3764 reg = <0x0 0xfdb70000 0x0 0x1000>; 3765 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3766 interrupt-names = "rga3_core1_irq"; 3767 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>; 3768 clock-names = "aclk_rga3_1", "hclk_rga3_1", "clk_rga3_1"; 3769 power-domains = <&power RK3588_PD_RGA31>; 3770 iommus = <&rga3_1_mmu>; 3771 status = "disabled"; 3772 }; 3773 3774 rga3_1_mmu: iommu@fdb70f00 { 3775 compatible = "rockchip,iommu-v2"; 3776 reg = <0x0 0xfdb70f00 0x0 0x100>; 3777 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 3778 interrupt-names = "rga3_1_mmu"; 3779 clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; 3780 clock-names = "aclk", "iface"; 3781 power-domains = <&power RK3588_PD_RGA31>; 3782 #iommu-cells = <0>; 3783 status = "disabled"; 3784 }; 3785 3786 rga2: rga@fdb80000 { 3787 compatible = "rockchip,rga2_core0"; 3788 reg = <0x0 0xfdb80000 0x0 0x1000>; 3789 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 3790 interrupt-names = "rga2_irq"; 3791 clocks = <&cru ACLK_RGA2>, <&cru HCLK_RGA2>, <&cru CLK_RGA2_CORE>; 3792 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; 3793 power-domains = <&power RK3588_PD_VDPU>; 3794 status = "disabled"; 3795 }; 3796 3797 jpegd: jpegd@fdb90000 { 3798 compatible = "rockchip,rkv-jpeg-decoder-v1"; 3799 reg = <0x0 0xfdb90000 0x0 0x400>; 3800 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 3801 interrupt-names = "irq_jpegd"; 3802 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 3803 clock-names = "aclk_vcodec", "hclk_vcodec"; 3804 rockchip,normal-rates = <600000000>, <0>; 3805 assigned-clocks = <&cru ACLK_JPEG_DECODER>; 3806 assigned-clock-rates = <600000000>; 3807 resets = <&cru SRST_A_JPEG_DECODER>, <&cru SRST_H_JPEG_DECODER>; 3808 reset-names = "video_a", "video_h"; 3809 rockchip,skip-pmu-idle-request; 3810 iommus = <&jpegd_mmu>; 3811 rockchip,srv = <&mpp_srv>; 3812 rockchip,taskqueue-node = <1>; 3813 power-domains = <&power RK3588_PD_VDPU>; 3814 status = "disabled"; 3815 }; 3816 3817 jpegd_mmu: iommu@fdb90480 { 3818 compatible = "rockchip,iommu-v2"; 3819 reg = <0x0 0xfdb90480 0x0 0x40>; 3820 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 3821 interrupt-names = "irq_jpegd_mmu"; 3822 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 3823 clock-names = "aclk", "iface"; 3824 power-domains = <&power RK3588_PD_VDPU>; 3825 #iommu-cells = <0>; 3826 status = "disabled"; 3827 }; 3828 3829 jpege0: jpege-core@fdba0000 { 3830 compatible = "rockchip,vpu-jpege-core"; 3831 reg = <0x0 0xfdba0000 0x0 0x400>; 3832 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 3833 interrupt-names = "irq_jpege0"; 3834 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 3835 clock-names = "aclk_vcodec", "hclk_vcodec"; 3836 rockchip,normal-rates = <594000000>, <0>; 3837 assigned-clocks = <&cru ACLK_JPEG_ENCODER0>; 3838 assigned-clock-rates = <594000000>; 3839 resets = <&cru SRST_A_JPEG_ENCODER0>, <&cru SRST_H_JPEG_ENCODER0>; 3840 reset-names = "video_a", "video_h"; 3841 rockchip,skip-pmu-idle-request; 3842 rockchip,disable-auto-freq; 3843 iommus = <&jpege0_mmu>; 3844 rockchip,srv = <&mpp_srv>; 3845 rockchip,taskqueue-node = <2>; 3846 rockchip,ccu = <&jpege_ccu>; 3847 power-domains = <&power RK3588_PD_VDPU>; 3848 status = "disabled"; 3849 }; 3850 3851 jpege0_mmu: iommu@fdba0800 { 3852 compatible = "rockchip,iommu-v2"; 3853 reg = <0x0 0xfdba0800 0x0 0x40>; 3854 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 3855 interrupt-names = "irq_jpege0_mmu"; 3856 clocks = <&cru ACLK_JPEG_ENCODER0>, <&cru HCLK_JPEG_ENCODER0>; 3857 clock-names = "aclk", "iface"; 3858 power-domains = <&power RK3588_PD_VDPU>; 3859 #iommu-cells = <0>; 3860 status = "disabled"; 3861 }; 3862 3863 jpege1: jpege-core@fdba4000 { 3864 compatible = "rockchip,vpu-jpege-core"; 3865 reg = <0x0 0xfdba4000 0x0 0x400>; 3866 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 3867 interrupt-names = "irq_jpege1"; 3868 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 3869 clock-names = "aclk_vcodec", "hclk_vcodec"; 3870 rockchip,normal-rates = <594000000>, <0>; 3871 assigned-clocks = <&cru ACLK_JPEG_ENCODER1>; 3872 assigned-clock-rates = <594000000>; 3873 resets = <&cru SRST_A_JPEG_ENCODER1>, <&cru SRST_H_JPEG_ENCODER1>; 3874 reset-names = "video_a", "video_h"; 3875 rockchip,skip-pmu-idle-request; 3876 rockchip,disable-auto-freq; 3877 iommus = <&jpege1_mmu>; 3878 rockchip,srv = <&mpp_srv>; 3879 rockchip,taskqueue-node = <2>; 3880 rockchip,ccu = <&jpege_ccu>; 3881 power-domains = <&power RK3588_PD_VDPU>; 3882 status = "disabled"; 3883 }; 3884 3885 jpege1_mmu: iommu@fdba4800 { 3886 compatible = "rockchip,iommu-v2"; 3887 reg = <0x0 0xfdba4800 0x0 0x40>; 3888 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 3889 interrupt-names = "irq_jpege1_mmu"; 3890 clocks = <&cru ACLK_JPEG_ENCODER1>, <&cru HCLK_JPEG_ENCODER1>; 3891 clock-names = "aclk", "iface"; 3892 power-domains = <&power RK3588_PD_VDPU>; 3893 #iommu-cells = <0>; 3894 status = "disabled"; 3895 }; 3896 3897 jpege2: jpege-core@fdba8000 { 3898 compatible = "rockchip,vpu-jpege-core"; 3899 reg = <0x0 0xfdba8000 0x0 0x400>; 3900 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 3901 interrupt-names = "irq_jpege2"; 3902 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 3903 clock-names = "aclk_vcodec", "hclk_vcodec"; 3904 rockchip,normal-rates = <594000000>, <0>; 3905 assigned-clocks = <&cru ACLK_JPEG_ENCODER2>; 3906 assigned-clock-rates = <594000000>; 3907 resets = <&cru SRST_A_JPEG_ENCODER2>, <&cru SRST_H_JPEG_ENCODER2>; 3908 reset-names = "video_a", "video_h"; 3909 rockchip,skip-pmu-idle-request; 3910 rockchip,disable-auto-freq; 3911 iommus = <&jpege2_mmu>; 3912 rockchip,srv = <&mpp_srv>; 3913 rockchip,taskqueue-node = <2>; 3914 rockchip,ccu = <&jpege_ccu>; 3915 power-domains = <&power RK3588_PD_VDPU>; 3916 status = "disabled"; 3917 }; 3918 3919 jpege2_mmu: iommu@fdba8800 { 3920 compatible = "rockchip,iommu-v2"; 3921 reg = <0x0 0xfdba8800 0x0 0x40>; 3922 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 3923 interrupt-names = "irq_jpege2_mmu"; 3924 clocks = <&cru ACLK_JPEG_ENCODER2>, <&cru HCLK_JPEG_ENCODER2>; 3925 clock-names = "aclk", "iface"; 3926 power-domains = <&power RK3588_PD_VDPU>; 3927 #iommu-cells = <0>; 3928 status = "disabled"; 3929 }; 3930 3931 jpege3: jpege-core@fdbac000 { 3932 compatible = "rockchip,vpu-jpege-core"; 3933 reg = <0x0 0xfdbac000 0x0 0x400>; 3934 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 3935 interrupt-names = "irq_jpege3"; 3936 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 3937 clock-names = "aclk_vcodec", "hclk_vcodec"; 3938 rockchip,normal-rates = <594000000>, <0>; 3939 assigned-clocks = <&cru ACLK_JPEG_ENCODER3>; 3940 assigned-clock-rates = <594000000>; 3941 resets = <&cru SRST_A_JPEG_ENCODER3>, <&cru SRST_H_JPEG_ENCODER3>; 3942 reset-names = "video_a", "video_h"; 3943 rockchip,skip-pmu-idle-request; 3944 rockchip,disable-auto-freq; 3945 iommus = <&jpege3_mmu>; 3946 rockchip,srv = <&mpp_srv>; 3947 rockchip,taskqueue-node = <2>; 3948 rockchip,ccu = <&jpege_ccu>; 3949 power-domains = <&power RK3588_PD_VDPU>; 3950 status = "disabled"; 3951 }; 3952 3953 jpege3_mmu: iommu@fdbac800 { 3954 compatible = "rockchip,iommu-v2"; 3955 reg = <0x0 0xfdbac800 0x0 0x40>; 3956 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 3957 interrupt-names = "irq_jpege3_mmu"; 3958 clocks = <&cru ACLK_JPEG_ENCODER3>, <&cru HCLK_JPEG_ENCODER3>; 3959 clock-names = "aclk", "iface"; 3960 power-domains = <&power RK3588_PD_VDPU>; 3961 #iommu-cells = <0>; 3962 status = "disabled"; 3963 }; 3964 3965 iep: iep@fdbb0000 { 3966 compatible = "rockchip,iep-v2"; 3967 reg = <0x0 0xfdbb0000 0x0 0x500>; 3968 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 3969 interrupt-names = "irq_iep"; 3970 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>, <&cru CLK_IEP2P0_CORE>; 3971 clock-names = "aclk", "hclk", "sclk"; 3972 rockchip,normal-rates = <594000000>, <0>; 3973 assigned-clocks = <&cru ACLK_IEP2P0>; 3974 assigned-clock-rates = <594000000>; 3975 resets = <&cru SRST_A_IEP2P0>, <&cru SRST_H_IEP2P0>, <&cru SRST_IEP2P0_CORE>; 3976 reset-names = "rst_a", "rst_h", "rst_s"; 3977 rockchip,skip-pmu-idle-request; 3978 rockchip,disable-auto-freq; 3979 power-domains = <&power RK3588_PD_VDPU>; 3980 rockchip,srv = <&mpp_srv>; 3981 rockchip,taskqueue-node = <6>; 3982 iommus = <&iep_mmu>; 3983 status = "disabled"; 3984 }; 3985 3986 iep_mmu: iommu@fdbb0800 { 3987 compatible = "rockchip,iommu-v2"; 3988 reg = <0x0 0xfdbb0800 0x0 0x100>; 3989 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 3990 interrupt-names = "irq_iep_mmu"; 3991 clocks = <&cru ACLK_IEP2P0>, <&cru HCLK_IEP2P0>; 3992 clock-names = "aclk", "iface"; 3993 #iommu-cells = <0>; 3994 power-domains = <&power RK3588_PD_VDPU>; 3995 status = "disabled"; 3996 }; 3997 3998 rkvenc0: rkvenc-core@fdbd0000 { 3999 compatible = "rockchip,rkv-encoder-v2-core"; 4000 reg = <0x0 0xfdbd0000 0x0 0x6000>; 4001 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 4002 interrupt-names = "irq_rkvenc0"; 4003 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>; 4004 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 4005 rockchip,normal-rates = <500000000>, <0>, <800000000>; 4006 assigned-clocks = <&cru ACLK_RKVENC0>, <&cru CLK_RKVENC0_CORE>; 4007 assigned-clock-rates = <500000000>, <800000000>; 4008 resets = <&cru SRST_A_RKVENC0>, <&cru SRST_H_RKVENC0>, <&cru SRST_RKVENC0_CORE>; 4009 reset-names = "video_a", "video_h", "video_core"; 4010 rockchip,skip-pmu-idle-request; 4011 iommus = <&rkvenc0_mmu>; 4012 rockchip,srv = <&mpp_srv>; 4013 rockchip,ccu = <&rkvenc_ccu>; 4014 rockchip,taskqueue-node = <7>; 4015 rockchip,task-capacity = <8>; 4016 power-domains = <&power RK3588_PD_VENC0>; 4017 operating-points-v2 = <&venc_opp_table>; 4018 status = "disabled"; 4019 }; 4020 4021 rkvenc0_mmu: iommu@fdbdf000 { 4022 compatible = "rockchip,iommu-v2"; 4023 reg = <0x0 0xfdbdf000 0x0 0x40>, <0x0 0xfdbdf040 0x0 0x40>; 4024 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4025 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 4026 interrupt-names = "irq_rkvenc0_mmu0", "irq_rkvenc0_mmu1"; 4027 clocks = <&cru ACLK_RKVENC0>, <&cru HCLK_RKVENC0>; 4028 clock-names = "aclk", "iface"; 4029 rockchip,disable-mmu-reset; 4030 rockchip,enable-cmd-retry; 4031 rockchip,shootdown-entire; 4032 #iommu-cells = <0>; 4033 power-domains = <&power RK3588_PD_VENC0>; 4034 status = "disabled"; 4035 }; 4036 4037 rkvenc1: rkvenc-core@fdbe0000 { 4038 compatible = "rockchip,rkv-encoder-v2-core"; 4039 reg = <0x0 0xfdbe0000 0x0 0x6000>; 4040 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 4041 interrupt-names = "irq_rkvenc1"; 4042 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>; 4043 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 4044 rockchip,normal-rates = <500000000>, <0>, <800000000>; 4045 assigned-clocks = <&cru ACLK_RKVENC1>, <&cru CLK_RKVENC1_CORE>; 4046 assigned-clock-rates = <500000000>, <800000000>; 4047 resets = <&cru SRST_A_RKVENC1>, <&cru SRST_H_RKVENC1>, <&cru SRST_RKVENC1_CORE>; 4048 reset-names = "video_a", "video_h", "video_core"; 4049 rockchip,skip-pmu-idle-request; 4050 iommus = <&rkvenc1_mmu>; 4051 rockchip,srv = <&mpp_srv>; 4052 rockchip,ccu = <&rkvenc_ccu>; 4053 rockchip,taskqueue-node = <7>; 4054 rockchip,task-capacity = <8>; 4055 power-domains = <&power RK3588_PD_VENC1>; 4056 operating-points-v2 = <&venc_opp_table>; 4057 status = "disabled"; 4058 }; 4059 4060 rkvenc1_mmu: iommu@fdbef000 { 4061 compatible = "rockchip,iommu-v2"; 4062 reg = <0x0 0xfdbef000 0x0 0x40>, <0x0 0xfdbef040 0x0 0x40>; 4063 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 4065 interrupt-names = "irq_rkvenc1_mmu0", "irq_rkvenc1_mmu1"; 4066 clocks = <&cru ACLK_RKVENC1>, <&cru HCLK_RKVENC1>; 4067 lock-names = "aclk", "iface"; 4068 rockchip,disable-mmu-reset; 4069 rockchip,enable-cmd-retry; 4070 rockchip,shootdown-entire; 4071 #iommu-cells = <0>; 4072 power-domains = <&power RK3588_PD_VENC1>; 4073 status = "disabled"; 4074 }; 4075 4076 venc_opp_table: venc-opp-table { 4077 compatible = "operating-points-v2"; 4078 4079 nvmem-cells = <&codec_leakage>, <&venc_opp_info>; 4080 nvmem-cell-names = "leakage", "opp-info"; 4081 rockchip,leakage-voltage-sel = < 4082 1 8 0 4083 9 20 1 4084 21 254 2 4085 >; 4086 4087 rockchip,grf = <&sys_grf>; 4088 volt-mem-read-margin = < 4089 855000 1 4090 765000 2 4091 675000 3 4092 495000 4 4093 >; 4094 4095 opp-800000000 { 4096 opp-hz = /bits/ 64 <800000000>; 4097 opp-microvolt = <750000 750000 850000>, 4098 <750000 750000 850000>; 4099 opp-microvolt-L0 = <800000 800000 850000>, 4100 <800000 800000 850000>; 4101 opp-microvolt-L1 = <775000 775000 850000>, 4102 <775000 775000 850000>; 4103 opp-microvolt-L2 = <750000 750000 850000>, 4104 <750000 750000 850000>; 4105 }; 4106 }; 4107 4108 rkvdec_ccu: rkvdec-ccu@fdc30000 { 4109 compatible = "rockchip,rkv-decoder-v2-ccu"; 4110 reg = <0x0 0xfdc30000 0x0 0x100>; 4111 reg-names = "ccu"; 4112 clocks = <&cru ACLK_RKVDEC_CCU>; 4113 clock-names = "aclk_ccu"; 4114 assigned-clocks = <&cru ACLK_RKVDEC_CCU>; 4115 assigned-clock-rates = <600000000>; 4116 resets = <&cru SRST_A_RKVDEC_CCU>; 4117 reset-names = "video_ccu"; 4118 rockchip,skip-pmu-idle-request; 4119 /* 1: soft ccu 2: hw ccu */ 4120 rockchip,ccu-mode = <1>; 4121 power-domains = <&power RK3588_PD_RKVDEC0>; 4122 status = "disabled"; 4123 }; 4124 4125 rkvdec0: rkvdec-core@fdc38000 { 4126 compatible = "rockchip,rkv-decoder-v2"; 4127 reg = <0x0 0xfdc38100 0x0 0x400>, <0x0 0xfdc38000 0x0 0x100>; 4128 reg-names = "regs", "link"; 4129 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 4130 interrupt-names = "irq_rkvdec0"; 4131 clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, 4132 <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; 4133 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", 4134 "clk_cabac", "clk_hevc_cabac"; 4135 rockchip,normal-rates = <800000000>, <0>, <600000000>, 4136 <600000000>, <1000000000>; 4137 assigned-clocks = <&cru ACLK_RKVDEC0>, <&cru CLK_RKVDEC0_CORE>, 4138 <&cru CLK_RKVDEC0_CA>, <&cru CLK_RKVDEC0_HEVC_CA>; 4139 assigned-clock-rates = <800000000>, <600000000>, 4140 <600000000>, <1000000000>; 4141 resets = <&cru SRST_A_RKVDEC0>, <&cru SRST_H_RKVDEC0>, <&cru SRST_RKVDEC0_CORE>, 4142 <&cru SRST_RKVDEC0_CA>, <&cru SRST_RKVDEC0_HEVC_CA>; 4143 reset-names = "video_a", "video_h", "video_core", 4144 "video_cabac", "video_hevc_cabac"; 4145 rockchip,skip-pmu-idle-request; 4146 iommus = <&rkvdec0_mmu>; 4147 rockchip,srv = <&mpp_srv>; 4148 rockchip,ccu = <&rkvdec_ccu>; 4149 rockchip,core-mask = <0x00010001>; 4150 rockchip,task-capacity = <16>; 4151 rockchip,taskqueue-node = <9>; 4152 rockchip,sram = <&rkvdec0_sram>; 4153 /* rcb_iova: start and size 1M@4095M */ 4154 rockchip,rcb-iova = <0xFFF00000 0x100000>; 4155 rockchip,rcb-info = <136 24576>, <137 49152>, <141 90112>, <140 49152>, 4156 <139 180224>, <133 49152>, <134 8192>, <135 4352>, 4157 <138 13056>, <142 291584>; 4158 rockchip,rcb-min-width = <512>; 4159 power-domains = <&power RK3588_PD_RKVDEC0>; 4160 status = "disabled"; 4161 }; 4162 4163 rkvdec0_mmu: iommu@fdc38700 { 4164 compatible = "rockchip,iommu-v2"; 4165 reg = <0x0 0xfdc38700 0x0 0x40>, <0x0 0xfdc38740 0x0 0x40>; 4166 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 4167 interrupt-names = "irq_rkvdec0_mmu"; 4168 clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>; 4169 clock-names = "aclk", "iface"; 4170 rockchip,disable-mmu-reset; 4171 rockchip,enable-cmd-retry; 4172 rockchip,shootdown-entire; 4173 rockchip,master-handle-irq; 4174 #iommu-cells = <0>; 4175 power-domains = <&power RK3588_PD_RKVDEC0>; 4176 status = "disabled"; 4177 }; 4178 4179 rkvdec1: rkvdec-core@fdc48000 { 4180 compatible = "rockchip,rkv-decoder-v2"; 4181 reg = <0x0 0xfdc48100 0x0 0x400>, <0x0 0xfdc48000 0x0 0x100>; 4182 reg-names = "regs", "link"; 4183 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 4184 interrupt-names = "irq_rkvdec1"; 4185 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, 4186 <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; 4187 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core", 4188 "clk_cabac", "clk_hevc_cabac"; 4189 rockchip,normal-rates = <800000000>, <0>, <600000000>, 4190 <600000000>, <1000000000>; 4191 assigned-clocks = <&cru ACLK_RKVDEC1>, <&cru CLK_RKVDEC1_CORE>, 4192 <&cru CLK_RKVDEC1_CA>, <&cru CLK_RKVDEC1_HEVC_CA>; 4193 assigned-clock-rates = <800000000>, <600000000>, 4194 <600000000>, <1000000000>; 4195 resets = <&cru SRST_A_RKVDEC1>, <&cru SRST_H_RKVDEC1>, <&cru SRST_RKVDEC1_CORE>, 4196 <&cru SRST_RKVDEC1_CA>, <&cru SRST_RKVDEC1_HEVC_CA>; 4197 reset-names = "video_a", "video_h", "video_core", 4198 "video_cabac", "video_hevc_cabac"; 4199 rockchip,skip-pmu-idle-request; 4200 iommus = <&rkvdec1_mmu>; 4201 rockchip,srv = <&mpp_srv>; 4202 rockchip,ccu = <&rkvdec_ccu>; 4203 rockchip,core-mask = <0x00020002>; 4204 rockchip,task-capacity = <16>; 4205 rockchip,taskqueue-node = <9>; 4206 rockchip,sram = <&rkvdec1_sram>; 4207 /* rcb_iova: start and size 1M@4094M */ 4208 rockchip,rcb-iova = <0xFFE00000 0x100000>; 4209 rockchip,rcb-info = <136 24576>, <137 49152>, <141 90112>, <140 49152>, 4210 <139 180224>, <133 49152>, <134 8192>, <135 4352>, 4211 <138 13056>, <142 291584>; 4212 rockchip,rcb-min-width = <512>; 4213 power-domains = <&power RK3588_PD_RKVDEC1>; 4214 status = "disabled"; 4215 }; 4216 4217 rkvdec1_mmu: iommu@fdc48700 { 4218 compatible = "rockchip,iommu-v2"; 4219 reg = <0x0 0xfdc48700 0x0 0x40>, <0x0 0xfdc48740 0x0 0x40>; 4220 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 4221 interrupt-names = "irq_rkvdec1_mmu"; 4222 clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>; 4223 clock-names = "aclk", "iface"; 4224 rockchip,disable-mmu-reset; 4225 rockchip,enable-cmd-retry; 4226 rockchip,shootdown-entire; 4227 rockchip,master-handle-irq; 4228 #iommu-cells = <0>; 4229 power-domains = <&power RK3588_PD_RKVDEC1>; 4230 status = "disabled"; 4231 }; 4232 4233 av1d: av1d@fdc70000 { 4234 compatible = "rockchip,av1-decoder"; 4235 reg = <0x0 0xfdc70000 0x0 0x800>, <0x0 0xfdc80000 0x0 0x400>, 4236 <0x0 0xfdc90000 0x0 0x400>; 4237 reg-names = "vcd", "cache", "afbc"; 4238 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4239 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 4240 interrupt-names = "irq_av1d", "irq_cache", "irq_afbc"; 4241 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 4242 clock-names = "aclk_vcodec", "hclk_vcodec"; 4243 rockchip,normal-rates = <400000000>, <400000000>; 4244 assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 4245 assigned-clock-rates = <400000000>, <400000000>; 4246 resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>; 4247 reset-names = "video_a", "video_h"; 4248 iommus = <&av1d_mmu>; 4249 rockchip,srv = <&mpp_srv>; 4250 rockchip,taskqueue-node = <11>; 4251 power-domains = <&power RK3588_PD_AV1>; 4252 status = "disabled"; 4253 }; 4254 4255 av1d_mmu: iommu@fdca0000 { 4256 compatible = "rockchip,iommu-av1"; 4257 reg = <0x0 0xfdca0000 0x0 0x600>; 4258 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 4259 interrupt-names = "irq_av1d_mmu"; 4260 clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; 4261 clock-names = "aclk", "iface"; 4262 #iommu-cells = <0>; 4263 power-domains = <&power RK3588_PD_AV1>; 4264 status = "disabled"; 4265 }; 4266 4267 rkisp_unite: rkisp-unite@fdcb0000 { 4268 compatible = "rockchip,rk3588-rkisp-unite"; 4269 reg = <0x0 0xfdcb0000 0x0 0x10000>, 4270 <0x0 0xfdcc0000 0x0 0x10000>; 4271 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4272 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 4273 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4274 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 4275 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, 4276 <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>, 4277 <&cru CLK_ISP0_CORE_VICAP>, <&cru ACLK_ISP1>, 4278 <&cru HCLK_ISP1>, <&cru CLK_ISP1_CORE>, 4279 <&cru CLK_ISP1_CORE_MARVIN>, <&cru CLK_ISP1_CORE_VICAP>; 4280 clock-names = "aclk_isp0", "hclk_isp0", "clk_isp_core0", 4281 "clk_isp_core_marvin0", "clk_isp_core_vicap0", 4282 "aclk_isp1", "hclk_isp1", "clk_isp_core1", 4283 "clk_isp_core_marvin1", "clk_isp_core_vicap1"; 4284 power-domains = <&power RK3588_PD_ISP1>; 4285 iommus = <&rkisp_unite_mmu>; 4286 status = "disabled"; 4287 }; 4288 4289 rkisp0: rkisp@fdcb0000 { 4290 compatible = "rockchip,rk3588-rkisp"; 4291 reg = <0x0 0xfdcb0000 0x0 0x7f00>; 4292 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4293 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 4294 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 4295 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 4296 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, 4297 <&cru CLK_ISP0_CORE>, <&cru CLK_ISP0_CORE_MARVIN>, 4298 <&cru CLK_ISP0_CORE_VICAP>; 4299 clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", 4300 "clk_isp_core_marvin", "clk_isp_core_vicap"; 4301 power-domains = <&power RK3588_PD_VI>; 4302 iommus = <&isp0_mmu>; 4303 status = "disabled"; 4304 }; 4305 4306 rkisp_unite_mmu: rkisp-unite-mmu@fdcb7f00 { 4307 compatible = "rockchip,iommu-v2"; 4308 reg = <0x0 0xfdcb7f00 0x0 0x100>, <0x0 0xfdcc7f00 0x0 0x100>; 4309 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 4310 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 4311 interrupt-names = "isp0_mmu", "isp1_mmu"; 4312 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>, 4313 <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; 4314 clock-names = "aclk0", "iface0", "aclk1", "iface1"; 4315 power-domains = <&power RK3588_PD_ISP1>; 4316 #iommu-cells = <0>; 4317 rockchip,disable-mmu-reset; 4318 status = "disabled"; 4319 }; 4320 4321 isp0_mmu: iommu@fdcb7f00 { 4322 compatible = "rockchip,iommu-v2"; 4323 reg = <0x0 0xfdcb7f00 0x0 0x100>; 4324 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 4325 interrupt-names = "isp0_mmu"; 4326 clocks = <&cru ACLK_ISP0>, <&cru HCLK_ISP0>; 4327 clock-names = "aclk", "iface"; 4328 power-domains = <&power RK3588_PD_VI>; 4329 #iommu-cells = <0>; 4330 rockchip,disable-mmu-reset; 4331 status = "disabled"; 4332 }; 4333 4334 rkisp1: rkisp@fdcc0000 { 4335 compatible = "rockchip,rk3588-rkisp"; 4336 reg = <0x0 0xfdcc0000 0x0 0x7f00>; 4337 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 4338 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 4339 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 4340 interrupt-names = "isp_irq", "mi_irq", "mipi_irq"; 4341 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>, 4342 <&cru CLK_ISP1_CORE>, <&cru CLK_ISP1_CORE_MARVIN>, 4343 <&cru CLK_ISP1_CORE_VICAP>; 4344 clock-names = "aclk_isp", "hclk_isp", "clk_isp_core", 4345 "clk_isp_core_marvin", "clk_isp_core_vicap"; 4346 power-domains = <&power RK3588_PD_ISP1>; 4347 iommus = <&isp1_mmu>; 4348 status = "disabled"; 4349 }; 4350 4351 isp1_mmu: iommu@fdcc7f00 { 4352 compatible = "rockchip,iommu-v2"; 4353 reg = <0x0 0xfdcc7f00 0x0 0x100>; 4354 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 4355 interrupt-names = "isp1_mmu"; 4356 clocks = <&cru ACLK_ISP1>, <&cru HCLK_ISP1>; 4357 clock-names = "aclk", "iface"; 4358 power-domains = <&power RK3588_PD_ISP1>; 4359 #iommu-cells = <0>; 4360 rockchip,disable-mmu-reset; 4361 status = "disabled"; 4362 }; 4363 4364 rkispp0: rkispp@fdcd0000 { 4365 compatible = "rockchip,rk3588-rkispp"; 4366 reg = <0x0 0xfdcd0000 0x0 0x0f00>; 4367 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 4368 interrupt-names = "fec_irq"; 4369 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>, 4370 <&cru CLK_FISHEYE0_CORE>; 4371 clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; 4372 assigned-clocks = <&cru HCLK_FISHEYE0>; 4373 assigned-clock-rates = <100000000>; 4374 power-domains = <&power RK3588_PD_FEC>; 4375 iommus = <&fec0_mmu>; 4376 status = "disabled"; 4377 }; 4378 4379 fec0_mmu: iommu@fdcd0f00 { 4380 compatible = "rockchip,iommu-v2"; 4381 reg = <0x0 0xfdcd0f00 0x0 0x100>; 4382 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 4383 interrupt-names = "fec0_mmu"; 4384 clocks = <&cru ACLK_FISHEYE0>, <&cru HCLK_FISHEYE0>, <&cru CLK_FISHEYE0_CORE>; 4385 clock-names = "aclk", "iface", "pclk"; 4386 power-domains = <&power RK3588_PD_FEC>; 4387 #iommu-cells = <0>; 4388 rockchip,disable-mmu-reset; 4389 status = "disabled"; 4390 }; 4391 4392 rkispp1: rkispp@fdcd8000 { 4393 compatible = "rockchip,rk3588-rkispp"; 4394 reg = <0x0 0xfdcd8000 0x0 0x0f00>; 4395 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 4396 interrupt-names = "fec_irq"; 4397 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>, 4398 <&cru CLK_FISHEYE1_CORE>; 4399 clock-names = "aclk_ispp", "hclk_ispp", "clk_ispp"; 4400 assigned-clocks = <&cru HCLK_FISHEYE1>; 4401 assigned-clock-rates = <100000000>; 4402 power-domains = <&power RK3588_PD_FEC>; 4403 iommus = <&fec1_mmu>; 4404 status = "disabled"; 4405 }; 4406 4407 fec1_mmu: iommu@fdcd8f00 { 4408 compatible = "rockchip,iommu-v2"; 4409 reg = <0x0 0xfdcd8f00 0x0 0x100>; 4410 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 4411 interrupt-names = "fec1_mmu"; 4412 clocks = <&cru ACLK_FISHEYE1>, <&cru HCLK_FISHEYE1>, <&cru CLK_FISHEYE1_CORE>; 4413 clock-names = "aclk", "iface", "pclk"; 4414 power-domains = <&power RK3588_PD_FEC>; 4415 #iommu-cells = <0>; 4416 rockchip,disable-mmu-reset; 4417 status = "disabled"; 4418 }; 4419 4420 rkcif: rkcif@fdce0000 { 4421 compatible = "rockchip,rk3588-cif"; 4422 reg = <0x0 0xfdce0000 0x0 0x800>; 4423 reg-names = "cif_regs"; 4424 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 4425 interrupt-names = "cif-intr"; 4426 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, <&cru DCLK_VICAP>, 4427 <&cru ICLK_CSIHOST0>, <&cru ICLK_CSIHOST1>; 4428 clock-names = "aclk_cif", "hclk_cif", "dclk_cif", 4429 "iclk_host0", "iclk_host1"; 4430 resets = <&cru SRST_A_VICAP>, <&cru SRST_H_VICAP>, <&cru SRST_D_VICAP>, 4431 <&cru SRST_CSIHOST0_VICAP>, <&cru SRST_CSIHOST1_VICAP>, 4432 <&cru SRST_CSIHOST2_VICAP>, <&cru SRST_CSIHOST3_VICAP>, 4433 <&cru SRST_CSIHOST4_VICAP>, <&cru SRST_CSIHOST5_VICAP>; 4434 reset-names = "rst_cif_a", "rst_cif_h", "rst_cif_d", 4435 "rst_cif_host0", "rst_cif_host1", "rst_cif_host2", 4436 "rst_cif_host3", "rst_cif_host4", "rst_cif_host5"; 4437 assigned-clocks = <&cru DCLK_VICAP>; 4438 assigned-clock-rates = <600000000>; 4439 power-domains = <&power RK3588_PD_VI>; 4440 rockchip,grf = <&sys_grf>; 4441 iommus = <&rkcif_mmu>; 4442 nvmem-cells = <&specification_serial_number>, 4443 <&package_serial_number_low>, 4444 <&package_serial_number_high>; 4445 nvmem-cell-names = "specification", 4446 "package_low", 4447 "package_high"; 4448 status = "disabled"; 4449 }; 4450 4451 rkcif_mmu: iommu@fdce0800 { 4452 compatible = "rockchip,iommu-v2"; 4453 reg = <0x0 0xfdce0800 0x0 0x100>, 4454 <0x0 0xfdce0900 0x0 0x100>; 4455 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 4456 interrupt-names = "cif_mmu"; 4457 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>; 4458 clock-names = "aclk", "iface"; 4459 power-domains = <&power RK3588_PD_VI>; 4460 rockchip,disable-mmu-reset; 4461 #iommu-cells = <0>; 4462 status = "disabled"; 4463 }; 4464 4465 mipi0_csi2_hw: mipi0-csi2-hw@fdd10000 { 4466 compatible = "rockchip,rk3588-mipi-csi2-hw"; 4467 reg = <0x0 0xfdd10000 0x0 0x10000>; 4468 reg-names = "csihost_regs"; 4469 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 4470 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 4471 interrupt-names = "csi-intr1", "csi-intr2"; 4472 clocks = <&cru PCLK_CSI_HOST_0>; 4473 clock-names = "pclk_csi2host"; 4474 resets = <&cru SRST_P_CSI_HOST_0>; 4475 reset-names = "srst_csihost_p"; 4476 status = "okay"; 4477 }; 4478 4479 mipi1_csi2_hw: mipi1-csi2-hw@fdd20000 { 4480 compatible = "rockchip,rk3588-mipi-csi2-hw"; 4481 reg = <0x0 0xfdd20000 0x0 0x10000>; 4482 reg-names = "csihost_regs"; 4483 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 4484 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 4485 interrupt-names = "csi-intr1", "csi-intr2"; 4486 clocks = <&cru PCLK_CSI_HOST_1>; 4487 clock-names = "pclk_csi2host"; 4488 resets = <&cru SRST_P_CSI_HOST_1>; 4489 reset-names = "srst_csihost_p"; 4490 status = "okay"; 4491 }; 4492 4493 mipi2_csi2_hw: mipi2-csi2-hw@fdd30000 { 4494 compatible = "rockchip,rk3588-mipi-csi2-hw"; 4495 reg = <0x0 0xfdd30000 0x0 0x10000>; 4496 reg-names = "csihost_regs"; 4497 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 4498 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 4499 interrupt-names = "csi-intr1", "csi-intr2"; 4500 clocks = <&cru PCLK_CSI_HOST_2>; 4501 clock-names = "pclk_csi2host"; 4502 resets = <&cru SRST_P_CSI_HOST_2>; 4503 reset-names = "srst_csihost_p"; 4504 status = "okay"; 4505 }; 4506 4507 mipi3_csi2_hw: mipi3-csi2-hw@fdd40000 { 4508 compatible = "rockchip,rk3588-mipi-csi2-hw"; 4509 reg = <0x0 0xfdd40000 0x0 0x10000>; 4510 reg-names = "csihost_regs"; 4511 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 4512 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 4513 interrupt-names = "csi-intr1", "csi-intr2"; 4514 clocks = <&cru PCLK_CSI_HOST_3>; 4515 clock-names = "pclk_csi2host"; 4516 resets = <&cru SRST_P_CSI_HOST_3>; 4517 reset-names = "srst_csihost_p"; 4518 status = "okay"; 4519 }; 4520 4521 mipi4_csi2_hw: mipi4-csi2-hw@fdd50000 { 4522 compatible = "rockchip,rk3588-mipi-csi2-hw"; 4523 reg = <0x0 0xfdd50000 0x0 0x10000>; 4524 reg-names = "csihost_regs"; 4525 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 4526 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 4527 interrupt-names = "csi-intr1", "csi-intr2"; 4528 clocks = <&cru PCLK_CSI_HOST_4>; 4529 clock-names = "pclk_csi2host"; 4530 resets = <&cru SRST_P_CSI_HOST_4>; 4531 reset-names = "srst_csihost_p"; 4532 status = "okay"; 4533 }; 4534 4535 mipi5_csi2_hw: mipi5-csi2-hw@fdd60000 { 4536 compatible = "rockchip,rk3588-mipi-csi2-hw"; 4537 reg = <0x0 0xfdd60000 0x0 0x10000>; 4538 reg-names = "csihost_regs"; 4539 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 4540 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 4541 interrupt-names = "csi-intr1", "csi-intr2"; 4542 clocks = <&cru PCLK_CSI_HOST_5>; 4543 clock-names = "pclk_csi2host"; 4544 resets = <&cru SRST_P_CSI_HOST_5>; 4545 reset-names = "srst_csihost_p"; 4546 status = "okay"; 4547 }; 4548 4549 vop: vop@fdd90000 { 4550 compatible = "rockchip,rk3588-vop"; 4551 reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; 4552 reg-names = "regs", "gamma_lut"; 4553 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 4554 clocks = <&cru ACLK_VOP>, 4555 <&cru HCLK_VOP>, 4556 <&cru DCLK_VOP0>, 4557 <&cru DCLK_VOP1>, 4558 <&cru DCLK_VOP2>, 4559 <&cru DCLK_VOP3>, 4560 <&cru PCLK_VOP_ROOT>, 4561 <&cru DCLK_VOP0_SRC>, 4562 <&cru DCLK_VOP1_SRC>, 4563 <&cru DCLK_VOP2_SRC>; 4564 clock-names = "aclk_vop", 4565 "hclk_vop", 4566 "dclk_vp0", 4567 "dclk_vp1", 4568 "dclk_vp2", 4569 "dclk_vp3", 4570 "pclk_vop", 4571 "dclk_src_vp0", 4572 "dclk_src_vp1", 4573 "dclk_src_vp2"; 4574 assigned-clocks = <&cru ACLK_VOP>; 4575 assigned-clock-rates = <750000000>; 4576 resets = <&cru SRST_A_VOP>, 4577 <&cru SRST_H_VOP>, 4578 <&cru SRST_D_VOP0>, 4579 <&cru SRST_D_VOP1>, 4580 <&cru SRST_D_VOP2>, 4581 <&cru SRST_D_VOP3>; 4582 reset-names = "axi", 4583 "ahb", 4584 "dclk_vp0", 4585 "dclk_vp1", 4586 "dclk_vp2", 4587 "dclk_vp3"; 4588 iommus = <&vop_mmu>; 4589 power-domains = <&power RK3588_PD_VOP>; 4590 rockchip,grf = <&sys_grf>; 4591 rockchip,vop-grf = <&vop_grf>; 4592 rockchip,vo1-grf = <&vo1_grf>; 4593 rockchip,pmu = <&pmu>; 4594 4595 status = "disabled"; 4596 4597 vop_out: ports { 4598 #address-cells = <1>; 4599 #size-cells = <0>; 4600 4601 vp0: port@0 { 4602 #address-cells = <1>; 4603 #size-cells = <0>; 4604 reg = <0>; 4605 4606 vp0_out_dp0: endpoint@0 { 4607 reg = <0>; 4608 remote-endpoint = <&dp0_in_vp0>; 4609 }; 4610 4611 vp0_out_edp0: endpoint@1 { 4612 reg = <1>; 4613 remote-endpoint = <&edp0_in_vp0>; 4614 }; 4615 4616 vp0_out_hdmi0: endpoint@2 { 4617 reg = <2>; 4618 remote-endpoint = <&hdmi0_in_vp0>; 4619 }; 4620 }; 4621 4622 vp1: port@1 { 4623 #address-cells = <1>; 4624 #size-cells = <0>; 4625 reg = <1>; 4626 4627 vp1_out_dp0: endpoint@0 { 4628 reg = <0>; 4629 remote-endpoint = <&dp0_in_vp1>; 4630 }; 4631 4632 vp1_out_edp0: endpoint@1 { 4633 reg = <1>; 4634 remote-endpoint = <&edp0_in_vp1>; 4635 }; 4636 4637 vp1_out_hdmi0: endpoint@2 { 4638 reg = <2>; 4639 remote-endpoint = <&hdmi0_in_vp1>; 4640 }; 4641 }; 4642 4643 vp2: port@2 { 4644 #address-cells = <1>; 4645 #size-cells = <0>; 4646 reg = <2>; 4647 4648 assigned-clocks = <&cru DCLK_VOP2_SRC>; 4649 assigned-clock-parents = <&cru PLL_V0PLL>; 4650 4651 vp2_out_dp0: endpoint@0 { 4652 reg = <0>; 4653 remote-endpoint = <&dp0_in_vp2>; 4654 }; 4655 4656 vp2_out_edp0: endpoint@1 { 4657 reg = <1>; 4658 remote-endpoint = <&edp0_in_vp2>; 4659 }; 4660 4661 vp2_out_hdmi0: endpoint@2 { 4662 reg = <2>; 4663 remote-endpoint = <&hdmi0_in_vp2>; 4664 }; 4665 4666 vp2_out_dsi0: endpoint@3 { 4667 reg = <3>; 4668 remote-endpoint = <&dsi0_in_vp2>; 4669 }; 4670 4671 vp2_out_dsi1: endpoint@4 { 4672 reg = <4>; 4673 remote-endpoint = <&dsi1_in_vp2>; 4674 }; 4675 }; 4676 4677 vp3: port@3 { 4678 #address-cells = <1>; 4679 #size-cells = <0>; 4680 reg = <3>; 4681 4682 vp3_out_dsi0: endpoint@0 { 4683 reg = <0>; 4684 remote-endpoint = <&dsi0_in_vp3>; 4685 }; 4686 4687 vp3_out_dsi1: endpoint@1 { 4688 reg = <1>; 4689 remote-endpoint = <&dsi1_in_vp3>; 4690 }; 4691 4692 vp3_out_rgb: endpoint@2 { 4693 reg = <2>; 4694 remote-endpoint = <&rgb_in_vp3>; 4695 }; 4696 }; 4697 }; 4698 }; 4699 4700 vop_mmu: iommu@fdd97e00 { 4701 compatible = "rockchip,iommu-v2"; 4702 reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; 4703 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 4704 interrupt-names = "vop_mmu"; 4705 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 4706 clock-names = "aclk", "iface"; 4707 #iommu-cells = <0>; 4708 rockchip,disable-device-link-resume; 4709 rockchip,shootdown-entire; 4710 status = "disabled"; 4711 }; 4712 4713 spdif_tx2: spdif-tx@fddb0000 { 4714 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 4715 reg = <0x0 0xfddb0000 0x0 0x1000>; 4716 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 4717 dmas = <&dmac1 6>; 4718 dma-names = "tx"; 4719 clock-names = "mclk", "hclk"; 4720 clocks = <&cru MCLK_SPDIF2>, <&cru HCLK_SPDIF2_DP0>; 4721 assigned-clocks = <&cru CLK_SPDIF2_DP0_SRC>; 4722 assigned-clock-parents = <&cru PLL_AUPLL>; 4723 power-domains = <&power RK3588_PD_VO0>; 4724 #sound-dai-cells = <0>; 4725 status = "disabled"; 4726 }; 4727 4728 i2s4_8ch: i2s@fddc0000 { 4729 compatible = "rockchip,rk3588-i2s-tdm"; 4730 reg = <0x0 0xfddc0000 0x0 0x1000>; 4731 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 4732 clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>; 4733 clock-names = "mclk_tx", "mclk_rx", "hclk"; 4734 assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>; 4735 assigned-clock-parents = <&cru PLL_AUPLL>; 4736 dmas = <&dmac2 0>; 4737 dma-names = "tx"; 4738 power-domains = <&power RK3588_PD_VO0>; 4739 resets = <&cru SRST_M_I2S4_8CH_TX>; 4740 reset-names = "tx-m"; 4741 rockchip,playback-only; 4742 #sound-dai-cells = <0>; 4743 status = "disabled"; 4744 }; 4745 4746 spdif_tx3: spdif-tx@fdde0000 { 4747 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 4748 reg = <0x0 0xfdde0000 0x0 0x1000>; 4749 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 4750 dmas = <&dmac1 7>; 4751 dma-names = "tx"; 4752 clock-names = "mclk", "hclk"; 4753 clocks = <&cru MCLK_SPDIF3>, <&cru HCLK_SPDIF3>; 4754 assigned-clocks = <&cru CLK_SPDIF3_SRC>; 4755 assigned-clock-parents = <&cru PLL_AUPLL>; 4756 power-domains = <&power RK3588_PD_VO1>; 4757 #sound-dai-cells = <0>; 4758 status = "disabled"; 4759 }; 4760 4761 i2s5_8ch: i2s@fddf0000 { 4762 compatible = "rockchip,rk3588-i2s-tdm"; 4763 reg = <0x0 0xfddf0000 0x0 0x1000>; 4764 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 4765 clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>; 4766 clock-names = "mclk_tx", "mclk_rx", "hclk"; 4767 assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>; 4768 assigned-clock-parents = <&cru PLL_GPLL>; 4769 dmas = <&dmac2 2>; 4770 dma-names = "tx"; 4771 power-domains = <&power RK3588_PD_VO1>; 4772 resets = <&cru SRST_M_I2S5_8CH_TX>; 4773 reset-names = "tx-m"; 4774 rockchip,always-on; 4775 rockchip,hdmi-path; 4776 rockchip,playback-only; 4777 #sound-dai-cells = <0>; 4778 status = "disabled"; 4779 }; 4780 4781 i2s9_8ch: i2s@fddfc000 { 4782 compatible = "rockchip,rk3588-i2s-tdm"; 4783 reg = <0x0 0xfddfc000 0x0 0x1000>; 4784 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 4785 clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>; 4786 clock-names = "mclk_tx", "mclk_rx", "hclk"; 4787 assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>; 4788 assigned-clock-parents = <&cru PLL_AUPLL>; 4789 dmas = <&dmac2 23>; 4790 dma-names = "rx"; 4791 power-domains = <&power RK3588_PD_VO1>; 4792 resets = <&cru SRST_M_I2S9_8CH_RX>; 4793 reset-names = "rx-m"; 4794 rockchip,capture-only; 4795 #sound-dai-cells = <0>; 4796 status = "disabled"; 4797 }; 4798 4799 spdif_rx0: spdif-rx@fde08000 { 4800 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 4801 reg = <0x0 0xfde08000 0x0 0x1000>; 4802 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 4803 clocks = <&cru MCLK_SPDIFRX0>, <&cru HCLK_SPDIFRX0>; 4804 clock-names = "mclk", "hclk"; 4805 assigned-clocks = <&cru MCLK_SPDIFRX0>; 4806 assigned-clock-parents = <&cru PLL_AUPLL>; 4807 dmas = <&dmac0 21>; 4808 dma-names = "rx"; 4809 power-domains = <&power RK3588_PD_VO1>; 4810 resets = <&cru SRST_M_SPDIFRX0>; 4811 reset-names = "spdifrx-m"; 4812 #sound-dai-cells = <0>; 4813 status = "disabled"; 4814 }; 4815 4816 dsi0: dsi@fde20000 { 4817 compatible = "rockchip,rk3588-mipi-dsi2"; 4818 reg = <0x0 0xfde20000 0x0 0x10000>; 4819 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 4820 clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>; 4821 clock-names = "pclk", "sys_clk"; 4822 resets = <&cru SRST_P_DSIHOST0>; 4823 reset-names = "apb"; 4824 power-domains = <&power RK3588_PD_VOP>; 4825 phys = <&mipidcphy0>; 4826 phy-names = "dcphy"; 4827 rockchip,grf = <&vop_grf>; 4828 #address-cells = <1>; 4829 #size-cells = <0>; 4830 status = "disabled"; 4831 4832 ports { 4833 #address-cells = <1>; 4834 #size-cells = <0>; 4835 4836 dsi0_in: port@0 { 4837 reg = <0>; 4838 #address-cells = <1>; 4839 #size-cells = <0>; 4840 4841 dsi0_in_vp2: endpoint@0 { 4842 reg = <0>; 4843 remote-endpoint = <&vp2_out_dsi0>; 4844 status = "disabled"; 4845 }; 4846 4847 dsi0_in_vp3: endpoint@1 { 4848 reg = <1>; 4849 remote-endpoint = <&vp3_out_dsi0>; 4850 status = "disabled"; 4851 }; 4852 }; 4853 }; 4854 }; 4855 4856 dsi1: dsi@fde30000 { 4857 compatible = "rockchip,rk3588-mipi-dsi2"; 4858 reg = <0x0 0xfde30000 0x0 0x10000>; 4859 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 4860 clocks = <&cru PCLK_DSIHOST1>, <&cru CLK_DSIHOST1>; 4861 clock-names = "pclk", "sys_clk"; 4862 resets = <&cru SRST_P_DSIHOST1>; 4863 reset-names = "apb"; 4864 power-domains = <&power RK3588_PD_VOP>; 4865 phys = <&mipidcphy1>; 4866 phy-names = "dcphy"; 4867 rockchip,grf = <&vop_grf>; 4868 #address-cells = <1>; 4869 #size-cells = <0>; 4870 status = "disabled"; 4871 4872 ports { 4873 #address-cells = <1>; 4874 #size-cells = <0>; 4875 4876 dsi1_in: port@0 { 4877 reg = <0>; 4878 #address-cells = <1>; 4879 #size-cells = <0>; 4880 4881 dsi1_in_vp2: endpoint@0 { 4882 reg = <0>; 4883 remote-endpoint = <&vp2_out_dsi1>; 4884 status = "disabled"; 4885 }; 4886 4887 dsi1_in_vp3: endpoint@1 { 4888 reg = <1>; 4889 remote-endpoint = <&vp3_out_dsi1>; 4890 status = "disabled"; 4891 }; 4892 }; 4893 }; 4894 }; 4895 4896 hdcp0: hdcp@fde40000 { 4897 compatible = "rockchip,rk3588-hdcp"; 4898 reg = <0x0 0xfde40000 0x0 0x80>; 4899 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 4900 clocks = <&cru ACLK_HDCP0>, <&cru PCLK_HDCP0>, 4901 <&cru HCLK_HDCP0>, <&cru HCLK_HDCP_KEY0>, 4902 <&cru ACLK_TRNG0>, <&cru PCLK_TRNG0>; 4903 clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng"; 4904 resets = <&cru SRST_HDCP0>, <&cru SRST_H_HDCP0>, 4905 <&cru SRST_A_HDCP0>, <&cru SRST_H_HDCP_KEY0>, 4906 <&cru SRST_P_TRNG0>; 4907 reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng"; 4908 power-domains = <&power RK3588_PD_VO0>; 4909 rockchip,vo-grf = <&vo0_grf>; 4910 status = "disabled"; 4911 }; 4912 4913 dp0: dp@fde50000 { 4914 compatible = "rockchip,rk3588-dp"; 4915 reg = <0x0 0xfde50000 0x0 0x4000>; 4916 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 4917 clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, 4918 <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_SPDIF2_DP0>, 4919 <&hclk_vo0>, <&cru CLK_DP0>; 4920 clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp"; 4921 assigned-clocks = <&cru CLK_AUX16M_0>; 4922 assigned-clock-rates = <16000000>; 4923 resets = <&cru SRST_DP0>; 4924 phys = <&usbdp_phy0_dp>; 4925 power-domains = <&power RK3588_PD_VO0>; 4926 #sound-dai-cells = <1>; 4927 status = "disabled"; 4928 4929 ports { 4930 #address-cells = <1>; 4931 #size-cells = <0>; 4932 4933 port@0 { 4934 reg = <0>; 4935 #address-cells = <1>; 4936 #size-cells = <0>; 4937 4938 dp0_in_vp0: endpoint@0 { 4939 reg = <0>; 4940 remote-endpoint = <&vp0_out_dp0>; 4941 status = "disabled"; 4942 }; 4943 4944 dp0_in_vp1: endpoint@1 { 4945 reg = <1>; 4946 remote-endpoint = <&vp1_out_dp0>; 4947 status = "disabled"; 4948 }; 4949 4950 dp0_in_vp2: endpoint@2 { 4951 reg = <2>; 4952 remote-endpoint = <&vp2_out_dp0>; 4953 status = "disabled"; 4954 }; 4955 }; 4956 4957 port@1 { 4958 reg = <1>; 4959 4960 dp0_out: endpoint { }; 4961 }; 4962 }; 4963 }; 4964 4965 hdcp1: hdcp@fde70000 { 4966 compatible = "rockchip,rk3588-hdcp"; 4967 reg = <0x0 0xfde70000 0x0 0x80>; 4968 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 4969 clocks = <&cru ACLK_HDCP1>, <&cru PCLK_HDCP1>, 4970 <&cru HCLK_HDCP1>, <&cru HCLK_HDCP_KEY1>, 4971 <&cru ACLK_TRNG1>, <&cru PCLK_TRNG1>; 4972 clock-names = "aclk", "pclk", "hclk", "hclk_key", "aclk_trng", "pclk_trng"; 4973 resets = <&cru SRST_HDCP1>, <&cru SRST_H_HDCP1>, 4974 <&cru SRST_A_HDCP1>, <&cru SRST_H_HDCP_KEY1>, 4975 <&cru SRST_P_TRNG1>; 4976 reset-names = "hdcp", "h_hdcp", "a_hdcp", "hdcp_key", "trng"; 4977 power-domains = <&power RK3588_PD_VO1>; 4978 rockchip,vo-grf = <&vo1_grf>; 4979 status = "disabled"; 4980 }; 4981 4982 hdmi0: hdmi@fde80000 { 4983 compatible = "rockchip,rk3588-dw-hdmi"; 4984 reg = <0x0 0xfde80000 0x0 0x20000>; 4985 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 4986 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 4987 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 4988 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 4989 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 4990 clocks = <&cru PCLK_HDMITX0>, 4991 <&cru CLK_HDMIHDP0>, 4992 <&cru CLK_HDMITX0_EARC>, 4993 <&cru CLK_HDMITX0_REF>, 4994 <&cru MCLK_I2S5_8CH_TX>, 4995 <&cru DCLK_VOP0>, 4996 <&cru DCLK_VOP1>, 4997 <&cru DCLK_VOP2>, 4998 <&cru DCLK_VOP3>, 4999 <&hclk_vo1>, 5000 <&hdptxphy_hdmi_clk0>; 5001 clock-names = "pclk", 5002 "hpd", 5003 "earc", 5004 "hdmitx_ref", 5005 "aud", 5006 "dclk_vp0", 5007 "dclk_vp1", 5008 "dclk_vp2", 5009 "dclk_vp3", 5010 "hclk_vo1", 5011 "link_clk"; 5012 resets = <&cru SRST_HDMITX0_REF>, <&cru SRST_HDMIHDP0>; 5013 reset-names = "ref", "hdp"; 5014 power-domains = <&power RK3588_PD_VO1>; 5015 pinctrl-names = "default"; 5016 pinctrl-0 = <&hdmim0_tx0_cec &hdmim0_tx0_hpd &hdmim0_tx0_scl &hdmim0_tx0_sda>; 5017 reg-io-width = <4>; 5018 rockchip,grf = <&sys_grf>; 5019 rockchip,vo1_grf = <&vo1_grf>; 5020 phys = <&hdptxphy_hdmi0>; 5021 phy-names = "hdmi"; 5022 #sound-dai-cells = <0>; 5023 status = "disabled"; 5024 5025 ports { 5026 #address-cells = <1>; 5027 #size-cells = <0>; 5028 5029 hdmi0_in: port@0 { 5030 reg = <0>; 5031 #address-cells = <1>; 5032 #size-cells = <0>; 5033 5034 hdmi0_in_vp0: endpoint@0 { 5035 reg = <0>; 5036 remote-endpoint = <&vp0_out_hdmi0>; 5037 status = "disabled"; 5038 }; 5039 5040 hdmi0_in_vp1: endpoint@1 { 5041 reg = <1>; 5042 remote-endpoint = <&vp1_out_hdmi0>; 5043 status = "disabled"; 5044 }; 5045 5046 hdmi0_in_vp2: endpoint@2 { 5047 reg = <2>; 5048 remote-endpoint = <&vp2_out_hdmi0>; 5049 status = "disabled"; 5050 }; 5051 }; 5052 }; 5053 }; 5054 5055 edp0: edp@fdec0000 { 5056 compatible = "rockchip,rk3588-edp"; 5057 reg = <0x0 0xfdec0000 0x0 0x1000>; 5058 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 5059 clocks = <&cru CLK_EDP0_24M>, <&cru PCLK_EDP0>, 5060 <&cru CLK_EDP0_200M>, <&hclk_vo1>; 5061 clock-names = "dp", "pclk", "spdif", "hclk"; 5062 resets = <&cru SRST_EDP0_24M>, <&cru SRST_P_EDP0>; 5063 reset-names = "dp", "apb"; 5064 phys = <&hdptxphy0>; 5065 phy-names = "dp"; 5066 power-domains = <&power RK3588_PD_VO1>; 5067 rockchip,grf = <&vo1_grf>; 5068 status = "disabled"; 5069 5070 ports { 5071 #address-cells = <1>; 5072 #size-cells = <0>; 5073 5074 port@0 { 5075 reg = <0>; 5076 #address-cells = <1>; 5077 #size-cells = <0>; 5078 5079 edp0_in_vp0: endpoint@0 { 5080 reg = <0>; 5081 remote-endpoint = <&vp0_out_edp0>; 5082 status = "disabled"; 5083 }; 5084 5085 edp0_in_vp1: endpoint@1 { 5086 reg = <1>; 5087 remote-endpoint = <&vp1_out_edp0>; 5088 status = "disabled"; 5089 }; 5090 5091 edp0_in_vp2: endpoint@2 { 5092 reg = <2>; 5093 remote-endpoint = <&vp2_out_edp0>; 5094 status = "disabled"; 5095 }; 5096 }; 5097 5098 port@1 { 5099 reg = <1>; 5100 5101 edp0_out: endpoint { }; 5102 }; 5103 }; 5104 }; 5105 5106 qos_gpu_m0: qos@fdf35000 { 5107 compatible = "syscon"; 5108 reg = <0x0 0xfdf35000 0x0 0x20>; 5109 }; 5110 5111 qos_gpu_m1: qos@fdf35200 { 5112 compatible = "syscon"; 5113 reg = <0x0 0xfdf35200 0x0 0x20>; 5114 }; 5115 5116 qos_gpu_m2: qos@fdf35400 { 5117 compatible = "syscon"; 5118 reg = <0x0 0xfdf35400 0x0 0x20>; 5119 }; 5120 5121 qos_gpu_m3: qos@fdf35600 { 5122 compatible = "syscon"; 5123 reg = <0x0 0xfdf35600 0x0 0x20>; 5124 }; 5125 5126 qos_rga3_1: qos@fdf36000 { 5127 compatible = "syscon"; 5128 reg = <0x0 0xfdf36000 0x0 0x20>; 5129 }; 5130 5131 qos_sdio: qos@fdf39000 { 5132 compatible = "syscon"; 5133 reg = <0x0 0xfdf39000 0x0 0x20>; 5134 }; 5135 5136 qos_sdmmc: qos@fdf3d800 { 5137 compatible = "syscon"; 5138 reg = <0x0 0xfdf3d800 0x0 0x20>; 5139 }; 5140 5141 qos_usb3_1: qos@fdf3e000 { 5142 compatible = "syscon"; 5143 reg = <0x0 0xfdf3e000 0x0 0x20>; 5144 }; 5145 5146 qos_usb3_0: qos@fdf3e200 { 5147 compatible = "syscon"; 5148 reg = <0x0 0xfdf3e200 0x0 0x20>; 5149 }; 5150 5151 qos_usb2host_0: qos@fdf3e400 { 5152 compatible = "syscon"; 5153 reg = <0x0 0xfdf3e400 0x0 0x20>; 5154 }; 5155 5156 qos_usb2host_1: qos@fdf3e600 { 5157 compatible = "syscon"; 5158 reg = <0x0 0xfdf3e600 0x0 0x20>; 5159 }; 5160 5161 qos_fisheye0: qos@fdf40000 { 5162 compatible = "syscon"; 5163 reg = <0x0 0xfdf40000 0x0 0x20>; 5164 }; 5165 5166 qos_fisheye1: qos@fdf40200 { 5167 compatible = "syscon"; 5168 reg = <0x0 0xfdf40200 0x0 0x20>; 5169 }; 5170 5171 qos_isp0_mro: qos@fdf40400 { 5172 compatible = "syscon"; 5173 reg = <0x0 0xfdf40400 0x0 0x20>; 5174 }; 5175 5176 qos_isp0_mwo: qos@fdf40500 { 5177 compatible = "syscon"; 5178 reg = <0x0 0xfdf40500 0x0 0x20>; 5179 }; 5180 5181 qos_vicap_m0: qos@fdf40600 { 5182 compatible = "syscon"; 5183 reg = <0x0 0xfdf40600 0x0 0x20>; 5184 }; 5185 5186 qos_vicap_m1: qos@fdf40800 { 5187 compatible = "syscon"; 5188 reg = <0x0 0xfdf40800 0x0 0x20>; 5189 }; 5190 5191 qos_isp1_mwo: qos@fdf41000 { 5192 compatible = "syscon"; 5193 reg = <0x0 0xfdf41000 0x0 0x20>; 5194 }; 5195 5196 qos_isp1_mro: qos@fdf41100 { 5197 compatible = "syscon"; 5198 reg = <0x0 0xfdf41100 0x0 0x20>; 5199 }; 5200 5201 qos_rkvenc0_m0ro: qos@fdf60000 { 5202 compatible = "syscon"; 5203 reg = <0x0 0xfdf60000 0x0 0x20>; 5204 }; 5205 5206 qos_rkvenc0_m1ro: qos@fdf60200 { 5207 compatible = "syscon"; 5208 reg = <0x0 0xfdf60200 0x0 0x20>; 5209 }; 5210 5211 qos_rkvenc0_m2wo: qos@fdf60400 { 5212 compatible = "syscon"; 5213 reg = <0x0 0xfdf60400 0x0 0x20>; 5214 }; 5215 5216 qos_rkvenc1_m0ro: qos@fdf61000 { 5217 compatible = "syscon"; 5218 reg = <0x0 0xfdf61000 0x0 0x20>; 5219 }; 5220 5221 qos_rkvenc1_m1ro: qos@fdf61200 { 5222 compatible = "syscon"; 5223 reg = <0x0 0xfdf61200 0x0 0x20>; 5224 }; 5225 5226 qos_rkvenc1_m2wo: qos@fdf61400 { 5227 compatible = "syscon"; 5228 reg = <0x0 0xfdf61400 0x0 0x20>; 5229 }; 5230 5231 qos_rkvdec0: qos@fdf62000 { 5232 compatible = "syscon"; 5233 reg = <0x0 0xfdf62000 0x0 0x20>; 5234 }; 5235 5236 qos_rkvdec1: qos@fdf63000 { 5237 compatible = "syscon"; 5238 reg = <0x0 0xfdf63000 0x0 0x20>; 5239 }; 5240 5241 qos_av1: qos@fdf64000 { 5242 compatible = "syscon"; 5243 reg = <0x0 0xfdf64000 0x0 0x20>; 5244 }; 5245 5246 qos_iep: qos@fdf66000 { 5247 compatible = "syscon"; 5248 reg = <0x0 0xfdf66000 0x0 0x20>; 5249 }; 5250 5251 qos_jpeg_dec: qos@fdf66200 { 5252 compatible = "syscon"; 5253 reg = <0x0 0xfdf66200 0x0 0x20>; 5254 }; 5255 5256 qos_jpeg_enc0: qos@fdf66400 { 5257 compatible = "syscon"; 5258 reg = <0x0 0xfdf66400 0x0 0x20>; 5259 }; 5260 5261 qos_jpeg_enc1: qos@fdf66600 { 5262 compatible = "syscon"; 5263 reg = <0x0 0xfdf66600 0x0 0x20>; 5264 }; 5265 5266 qos_jpeg_enc2: qos@fdf66800 { 5267 compatible = "syscon"; 5268 reg = <0x0 0xfdf66800 0x0 0x20>; 5269 }; 5270 5271 qos_jpeg_enc3: qos@fdf66a00 { 5272 compatible = "syscon"; 5273 reg = <0x0 0xfdf66a00 0x0 0x20>; 5274 }; 5275 5276 qos_rga2_mro: qos@fdf66c00 { 5277 compatible = "syscon"; 5278 reg = <0x0 0xfdf66c00 0x0 0x20>; 5279 }; 5280 5281 qos_rga2_mwo: qos@fdf66e00 { 5282 compatible = "syscon"; 5283 reg = <0x0 0xfdf66e00 0x0 0x20>; 5284 }; 5285 5286 qos_rga3_0: qos@fdf67000 { 5287 compatible = "syscon"; 5288 reg = <0x0 0xfdf67000 0x0 0x20>; 5289 }; 5290 5291 qos_vdpu: qos@fdf67200 { 5292 compatible = "syscon"; 5293 reg = <0x0 0xfdf67200 0x0 0x20>; 5294 }; 5295 5296 qos_npu1: qos@fdf70000 { 5297 compatible = "syscon"; 5298 reg = <0x0 0xfdf70000 0x0 0x20>; 5299 }; 5300 5301 qos_npu2: qos@fdf71000 { 5302 compatible = "syscon"; 5303 reg = <0x0 0xfdf71000 0x0 0x20>; 5304 }; 5305 5306 qos_npu0_mwr: qos@fdf72000 { 5307 compatible = "syscon"; 5308 reg = <0x0 0xfdf72000 0x0 0x20>; 5309 }; 5310 5311 qos_npu0_mro: qos@fdf72200 { 5312 compatible = "syscon"; 5313 reg = <0x0 0xfdf72200 0x0 0x20>; 5314 }; 5315 5316 qos_mcu_npu: qos@fdf72400 { 5317 compatible = "syscon"; 5318 reg = <0x0 0xfdf72400 0x0 0x20>; 5319 }; 5320 5321 qos_hdcp0: qos@fdf80000 { 5322 compatible = "syscon"; 5323 reg = <0x0 0xfdf80000 0x0 0x20>; 5324 }; 5325 5326 qos_hdcp1: qos@fdf81000 { 5327 compatible = "syscon"; 5328 reg = <0x0 0xfdf81000 0x0 0x20>; 5329 }; 5330 5331 qos_hdmirx: qos@fdf81200 { 5332 compatible = "syscon"; 5333 reg = <0x0 0xfdf81200 0x0 0x20>; 5334 }; 5335 5336 qos_vop_m0: qos@fdf82000 { 5337 compatible = "syscon"; 5338 reg = <0x0 0xfdf82000 0x0 0x20>; 5339 }; 5340 5341 qos_vop_m1: qos@fdf82200 { 5342 compatible = "syscon"; 5343 reg = <0x0 0xfdf82200 0x0 0x20>; 5344 }; 5345 5346 dfi: dfi@fe060000 { 5347 compatible = "rockchip,rk3588-dfi"; 5348 reg = <0x00 0xfe060000 0x00 0x10000>; 5349 rockchip,pmu_grf = <&pmu1_grf>; 5350 status = "disabled"; 5351 }; 5352 5353 pcie2x1l1: pcie@fe180000 { 5354 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 5355 #address-cells = <3>; 5356 #size-cells = <2>; 5357 bus-range = <0x30 0x3f>; 5358 clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>, 5359 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>, 5360 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>; 5361 clock-names = "aclk_mst", "aclk_slv", 5362 "aclk_dbi", "pclk", 5363 "aux", "pipe"; 5364 device_type = "pci"; 5365 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 5366 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 5367 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 5368 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 5369 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 5370 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 5371 #interrupt-cells = <1>; 5372 interrupt-map-mask = <0 0 0 7>; 5373 interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>, 5374 <0 0 0 2 &pcie2x1l1_intc 1>, 5375 <0 0 0 3 &pcie2x1l1_intc 2>, 5376 <0 0 0 4 &pcie2x1l1_intc 3>; 5377 linux,pci-domain = <3>; 5378 num-ib-windows = <8>; 5379 num-ob-windows = <8>; 5380 num-viewport = <4>; 5381 max-link-speed = <2>; 5382 msi-map = <0x3000 &its0 0x3000 0x1000>; 5383 num-lanes = <1>; 5384 phys = <&combphy2_psu PHY_TYPE_PCIE>; 5385 phy-names = "pcie-phy"; 5386 ranges = <0x00000800 0x0 0xf3000000 0x0 0xf3000000 0x0 0x100000 5387 0x81000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x100000 5388 0x82000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0xe00000 5389 0xc3000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>; 5390 reg = <0x0 0xfe180000 0x0 0x10000>, 5391 <0xa 0x40c00000 0x0 0x400000>; 5392 reg-names = "pcie-apb", "pcie-dbi"; 5393 resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>; 5394 reset-names = "pcie", "periph"; 5395 rockchip,pipe-grf = <&php_grf>; 5396 status = "disabled"; 5397 5398 pcie2x1l1_intc: legacy-interrupt-controller { 5399 interrupt-controller; 5400 #address-cells = <0>; 5401 #interrupt-cells = <1>; 5402 interrupt-parent = <&gic>; 5403 interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING>; 5404 }; 5405 }; 5406 5407 pcie2x1l2: pcie@fe190000 { 5408 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 5409 #address-cells = <3>; 5410 #size-cells = <2>; 5411 bus-range = <0x40 0x4f>; 5412 clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>, 5413 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>, 5414 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>; 5415 clock-names = "aclk_mst", "aclk_slv", 5416 "aclk_dbi", "pclk", 5417 "aux", "pipe"; 5418 device_type = "pci"; 5419 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 5420 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 5421 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 5422 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 5423 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 5424 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 5425 #interrupt-cells = <1>; 5426 interrupt-map-mask = <0 0 0 7>; 5427 interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>, 5428 <0 0 0 2 &pcie2x1l2_intc 1>, 5429 <0 0 0 3 &pcie2x1l2_intc 2>, 5430 <0 0 0 4 &pcie2x1l2_intc 3>; 5431 linux,pci-domain = <4>; 5432 num-ib-windows = <8>; 5433 num-ob-windows = <8>; 5434 num-viewport = <4>; 5435 max-link-speed = <2>; 5436 msi-map = <0x4000 &its0 0x4000 0x1000>; 5437 num-lanes = <1>; 5438 phys = <&combphy0_ps PHY_TYPE_PCIE>; 5439 phy-names = "pcie-phy"; 5440 ranges = <0x00000800 0x0 0xf4000000 0x0 0xf4000000 0x0 0x100000 5441 0x81000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x100000 5442 0x82000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0xe00000 5443 0xc3000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>; 5444 reg = <0x0 0xfe190000 0x0 0x10000>, 5445 <0xa 0x41000000 0x0 0x400000>; 5446 reg-names = "pcie-apb", "pcie-dbi"; 5447 resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>; 5448 reset-names = "pcie", "periph"; 5449 rockchip,pipe-grf = <&php_grf>; 5450 status = "disabled"; 5451 5452 pcie2x1l2_intc: legacy-interrupt-controller { 5453 interrupt-controller; 5454 #address-cells = <0>; 5455 #interrupt-cells = <1>; 5456 interrupt-parent = <&gic>; 5457 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>; 5458 }; 5459 }; 5460 5461 gmac_uio1: uio@fe1c0000 { 5462 compatible = "rockchip,uio-gmac"; 5463 reg = <0x0 0xfe1c0000 0x0 0x10000>; 5464 rockchip,ethernet = <&gmac1>; 5465 status = "disabled"; 5466 }; 5467 5468 gmac1: ethernet@fe1c0000 { 5469 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 5470 reg = <0x0 0xfe1c0000 0x0 0x10000>; 5471 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 5472 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 5473 interrupt-names = "macirq", "eth_wake_irq"; 5474 rockchip,grf = <&sys_grf>; 5475 rockchip,php_grf = <&php_grf>; 5476 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 5477 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>, 5478 <&cru CLK_GMAC1_PTP_REF>; 5479 clock-names = "stmmaceth", "clk_mac_ref", 5480 "pclk_mac", "aclk_mac", 5481 "ptp_ref"; 5482 resets = <&cru SRST_A_GMAC1>; 5483 reset-names = "stmmaceth"; 5484 power-domains = <&power RK3588_PD_GMAC>; 5485 5486 snps,mixed-burst; 5487 snps,tso; 5488 5489 snps,axi-config = <&gmac1_stmmac_axi_setup>; 5490 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 5491 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 5492 status = "disabled"; 5493 5494 mdio1: mdio { 5495 compatible = "snps,dwmac-mdio"; 5496 #address-cells = <0x1>; 5497 #size-cells = <0x0>; 5498 }; 5499 5500 gmac1_stmmac_axi_setup: stmmac-axi-config { 5501 snps,wr_osr_lmt = <4>; 5502 snps,rd_osr_lmt = <8>; 5503 snps,blen = <0 0 0 0 16 8 4>; 5504 }; 5505 5506 gmac1_mtl_rx_setup: rx-queues-config { 5507 snps,rx-queues-to-use = <1>; 5508 queue0 {}; 5509 }; 5510 5511 gmac1_mtl_tx_setup: tx-queues-config { 5512 snps,tx-queues-to-use = <1>; 5513 queue0 {}; 5514 }; 5515 }; 5516 5517 sata0: sata@fe210000 { 5518 compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; 5519 reg = <0 0xfe210000 0 0x1000>; 5520 clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>, 5521 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>, 5522 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>; 5523 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 5524 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>; 5525 interrupt-names = "hostc"; 5526 phys = <&combphy0_ps PHY_TYPE_SATA>; 5527 phy-names = "sata-phy"; 5528 ports-implemented = <0x1>; 5529 status = "disabled"; 5530 }; 5531 5532 sata2: sata@fe230000 { 5533 compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; 5534 reg = <0 0xfe230000 0 0x1000>; 5535 clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>, 5536 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>, 5537 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>; 5538 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 5539 interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>; 5540 interrupt-names = "hostc"; 5541 phys = <&combphy2_psu PHY_TYPE_SATA>; 5542 phy-names = "sata-phy"; 5543 ports-implemented = <0x1>; 5544 status = "disabled"; 5545 }; 5546 5547 sfc: spi@fe2b0000 { 5548 compatible = "rockchip,sfc"; 5549 reg = <0x0 0xfe2b0000 0x0 0x4000>; 5550 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 5551 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 5552 clock-names = "clk_sfc", "hclk_sfc"; 5553 assigned-clocks = <&cru SCLK_SFC>; 5554 assigned-clock-rates = <100000000>; 5555 #address-cells = <1>; 5556 #size-cells = <0>; 5557 status = "disabled"; 5558 }; 5559 5560 sdmmc: mmc@fe2c0000 { 5561 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 5562 reg = <0x0 0xfe2c0000 0x0 0x4000>; 5563 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 5564 clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>, 5565 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 5566 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 5567 fifo-depth = <0x100>; 5568 max-frequency = <200000000>; 5569 pinctrl-names = "default"; 5570 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 5571 power-domains = <&power RK3588_PD_SDMMC>; 5572 status = "disabled"; 5573 }; 5574 5575 sdio: mmc@fe2d0000 { 5576 compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; 5577 reg = <0x0 0xfe2d0000 0x0 0x4000>; 5578 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 5579 clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>, 5580 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 5581 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 5582 fifo-depth = <0x100>; 5583 max-frequency = <200000000>; 5584 pinctrl-names = "default"; 5585 pinctrl-0 = <&sdiom1_pins>; 5586 power-domains = <&power RK3588_PD_SDIO>; 5587 status = "disabled"; 5588 }; 5589 5590 sdhci: mmc@fe2e0000 { 5591 compatible = "rockchip,rk3588-dwcmshc", "rockchip,dwcmshc-sdhci"; 5592 reg = <0x0 0xfe2e0000 0x0 0x10000>; 5593 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 5594 assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>; 5595 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 5596 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>, 5597 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 5598 <&cru TMCLK_EMMC>; 5599 clock-names = "core", "bus", "axi", "block", "timer"; 5600 resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>, 5601 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>, 5602 <&cru SRST_T_EMMC>; 5603 reset-names = "core", "bus", "axi", "block", "timer"; 5604 max-frequency = <200000000>; 5605 status = "disabled"; 5606 }; 5607 5608 crypto: crypto@fe370000 { 5609 compatible = "rockchip,rk3588-crypto"; 5610 reg = <0x0 0xfe370000 0x0 0x2000>; 5611 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 5612 clocks = <&scmi_clk SCMI_ACLK_SECURE_NS>, <&scmi_clk SCMI_HCLK_SECURE_NS>, 5613 <&scmi_clk SCMI_CRYPTO_CORE>, <&scmi_clk SCMI_CRYPTO_PKA>; 5614 clock-names = "aclk", "hclk", "sclk", "pka"; 5615 resets = <&scmi_reset SRST_CRYPTO_CORE>; 5616 reset-names = "crypto-rst"; 5617 status = "disabled"; 5618 }; 5619 5620 rng: rng@fe378000 { 5621 compatible = "rockchip,trngv1"; 5622 reg = <0x0 0xfe378000 0x0 0x200>; 5623 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>; 5624 clocks = <&scmi_clk SCMI_HCLK_SECURE_NS>; 5625 clock-names = "hclk_trng"; 5626 resets = <&scmi_reset SRST_H_TRNG_NS>; 5627 reset-names = "reset"; 5628 status = "disabled"; 5629 }; 5630 5631 i2s0_8ch: i2s@fe470000 { 5632 compatible = "rockchip,rk3588-i2s-tdm"; 5633 reg = <0x0 0xfe470000 0x0 0x1000>; 5634 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 5635 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>; 5636 clock-names = "mclk_tx", "mclk_rx", "hclk"; 5637 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>; 5638 assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>; 5639 dmas = <&dmac0 0>, <&dmac0 1>; 5640 dma-names = "tx", "rx"; 5641 power-domains = <&power RK3588_PD_AUDIO>; 5642 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>; 5643 reset-names = "tx-m", "rx-m"; 5644 rockchip,clk-trcm = <1>; 5645 pinctrl-names = "default", "idle", "clk"; 5646 pinctrl-0 = <&i2s0_sdi0 5647 &i2s0_sdi1 5648 &i2s0_sdi2 5649 &i2s0_sdi3 5650 &i2s0_sdo0 5651 &i2s0_sdo1>; 5652 pinctrl-1 = <&i2s0_idle>; 5653 pinctrl-2 = <&i2s0_lrck 5654 &i2s0_sclk>; 5655 #sound-dai-cells = <0>; 5656 status = "disabled"; 5657 }; 5658 5659 i2s1_8ch: i2s@fe480000 { 5660 compatible = "rockchip,rk3588-i2s-tdm"; 5661 reg = <0x0 0xfe480000 0x0 0x1000>; 5662 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 5663 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>; 5664 clock-names = "mclk_tx", "mclk_rx", "hclk"; 5665 dmas = <&dmac0 2>, <&dmac0 3>; 5666 dma-names = "tx", "rx"; 5667 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>; 5668 reset-names = "tx-m", "rx-m"; 5669 rockchip,clk-trcm = <1>; 5670 pinctrl-names = "default"; 5671 pinctrl-0 = <&i2s1m0_lrck 5672 &i2s1m0_sclk 5673 &i2s1m0_sdi0 5674 &i2s1m0_sdi1 5675 &i2s1m0_sdi2 5676 &i2s1m0_sdi3 5677 &i2s1m0_sdo0 5678 &i2s1m0_sdo1 5679 &i2s1m0_sdo2 5680 &i2s1m0_sdo3>; 5681 #sound-dai-cells = <0>; 5682 status = "disabled"; 5683 }; 5684 5685 i2s2_2ch: i2s@fe490000 { 5686 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 5687 reg = <0x0 0xfe490000 0x0 0x1000>; 5688 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 5689 clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>; 5690 clock-names = "i2s_clk", "i2s_hclk"; 5691 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>; 5692 assigned-clock-parents = <&cru PLL_AUPLL>; 5693 dmas = <&dmac1 0>, <&dmac1 1>; 5694 dma-names = "tx", "rx"; 5695 power-domains = <&power RK3588_PD_AUDIO>; 5696 rockchip,clk-trcm = <1>; 5697 pinctrl-names = "default", "idle", "clk"; 5698 pinctrl-0 = <&i2s2m1_sdi 5699 &i2s2m1_sdo>; 5700 pinctrl-1 = <&i2s2m1_idle>; 5701 pinctrl-2 = <&i2s2m1_lrck 5702 &i2s2m1_sclk>; 5703 #sound-dai-cells = <0>; 5704 status = "disabled"; 5705 }; 5706 5707 i2s3_2ch: i2s@fe4a0000 { 5708 compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s"; 5709 reg = <0x0 0xfe4a0000 0x0 0x1000>; 5710 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 5711 clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>; 5712 clock-names = "i2s_clk", "i2s_hclk"; 5713 assigned-clocks = <&cru CLK_I2S3_2CH_SRC>; 5714 assigned-clock-parents = <&cru PLL_AUPLL>; 5715 dmas = <&dmac1 2>, <&dmac1 3>; 5716 dma-names = "tx", "rx"; 5717 power-domains = <&power RK3588_PD_AUDIO>; 5718 rockchip,clk-trcm = <1>; 5719 pinctrl-names = "default", "idle", "clk"; 5720 pinctrl-0 = <&i2s3_sdi 5721 &i2s3_sdo>; 5722 pinctrl-1 = <&i2s3_idle>; 5723 pinctrl-2 = <&i2s3_lrck 5724 &i2s3_sclk>; 5725 #sound-dai-cells = <0>; 5726 status = "disabled"; 5727 }; 5728 5729 pdm0: pdm@fe4b0000 { 5730 compatible = "rockchip,rk3588-pdm"; 5731 reg = <0x0 0xfe4b0000 0x0 0x1000>; 5732 clocks = <&cru MCLK_PDM0>, <&cru HCLK_PDM0>; 5733 clock-names = "pdm_clk", "pdm_hclk"; 5734 dmas = <&dmac0 4>; 5735 dma-names = "rx"; 5736 pinctrl-names = "default", "idle", "clk"; 5737 pinctrl-0 = <&pdm0m0_sdi0 5738 &pdm0m0_sdi1 5739 &pdm0m0_sdi2 5740 &pdm0m0_sdi3>; 5741 pinctrl-1 = <&pdm0m0_idle>; 5742 pinctrl-2 = <&pdm0m0_clk 5743 &pdm0m0_clk1>; 5744 #sound-dai-cells = <0>; 5745 status = "disabled"; 5746 }; 5747 5748 pdm1: pdm@fe4c0000 { 5749 compatible = "rockchip,rk3588-pdm"; 5750 reg = <0x0 0xfe4c0000 0x0 0x1000>; 5751 clocks = <&cru MCLK_PDM1>, <&cru HCLK_PDM1>; 5752 clock-names = "pdm_clk", "pdm_hclk"; 5753 assigned-clocks = <&cru MCLK_PDM1>; 5754 assigned-clock-parents = <&cru PLL_AUPLL>; 5755 dmas = <&dmac1 4>; 5756 dma-names = "rx"; 5757 power-domains = <&power RK3588_PD_AUDIO>; 5758 pinctrl-names = "default", "idle", "clk"; 5759 pinctrl-0 = <&pdm1m0_sdi0 5760 &pdm1m0_sdi1 5761 &pdm1m0_sdi2 5762 &pdm1m0_sdi3>; 5763 pinctrl-1 = <&pdm1m0_idle>; 5764 pinctrl-2 = <&pdm1m0_clk 5765 &pdm1m0_clk1>; 5766 #sound-dai-cells = <0>; 5767 status = "disabled"; 5768 }; 5769 5770 vad: vad@fe4d0000 { 5771 compatible = "rockchip,rk3588-vad"; 5772 reg = <0x0 0xfe4d0000 0x0 0x1000>; 5773 reg-names = "vad"; 5774 clocks = <&cru HCLK_VAD>; 5775 clock-names = "hclk"; 5776 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 5777 rockchip,audio-src = <0>; 5778 rockchip,det-channel = <0>; 5779 rockchip,mode = <0>; 5780 #sound-dai-cells = <0>; 5781 status = "disabled"; 5782 }; 5783 5784 spdif_tx0: spdif-tx@fe4e0000 { 5785 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 5786 reg = <0x0 0xfe4e0000 0x0 0x1000>; 5787 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 5788 dmas = <&dmac0 5>; 5789 dma-names = "tx"; 5790 clock-names = "mclk", "hclk"; 5791 clocks = <&cru MCLK_SPDIF0>, <&cru HCLK_SPDIF0>; 5792 assigned-clocks = <&cru CLK_SPDIF0_SRC>; 5793 assigned-clock-parents = <&cru PLL_AUPLL>; 5794 power-domains = <&power RK3588_PD_AUDIO>; 5795 pinctrl-names = "default"; 5796 pinctrl-0 = <&spdif0m0_tx>; 5797 #sound-dai-cells = <0>; 5798 status = "disabled"; 5799 }; 5800 5801 spdif_tx1: spdif-tx@fe4f0000 { 5802 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 5803 reg = <0x0 0xfe4f0000 0x0 0x1000>; 5804 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 5805 dmas = <&dmac1 5>; 5806 dma-names = "tx"; 5807 clock-names = "mclk", "hclk"; 5808 clocks = <&cru MCLK_SPDIF1>, <&cru HCLK_SPDIF1>; 5809 assigned-clocks = <&cru CLK_SPDIF1_SRC>; 5810 assigned-clock-parents = <&cru PLL_AUPLL>; 5811 power-domains = <&power RK3588_PD_AUDIO>; 5812 pinctrl-names = "default"; 5813 pinctrl-0 = <&spdif1m0_tx>; 5814 #sound-dai-cells = <0>; 5815 status = "disabled"; 5816 }; 5817 5818 acdcdig_dsm: codec-digital@fe500000 { 5819 compatible = "rockchip,rk3588-codec-digital", "rockchip,codec-digital-v1"; 5820 reg = <0x0 0xfe500000 0x0 0x1000>; 5821 clocks = <&cru CLK_DAC_ACDCDIG>, <&cru PCLK_ACDCDIG>; 5822 clock-names = "dac", "pclk"; 5823 power-domains = <&power RK3588_PD_AUDIO>; 5824 resets = <&cru SRST_DAC_ACDCDIG>; 5825 reset-names = "reset" ; 5826 rockchip,grf = <&sys_grf>; 5827 rockchip,pwm-output-mode; 5828 pinctrl-names = "default"; 5829 pinctrl-0 = <&auddsm_pins>; 5830 #sound-dai-cells = <0>; 5831 status = "disabled"; 5832 }; 5833 5834 hwlock: hwspinlock@fe5a0000 { 5835 compatible = "rockchip,hwspinlock"; 5836 reg = <0 0xfe5a0000 0 0x100>; 5837 #hwlock-cells = <1>; 5838 }; 5839 5840 gic: interrupt-controller@fe600000 { 5841 compatible = "arm,gic-v3"; 5842 #interrupt-cells = <3>; 5843 #address-cells = <2>; 5844 #size-cells = <2>; 5845 ranges; 5846 interrupt-controller; 5847 5848 reg = <0x0 0xfe600000 0 0x10000>, /* GICD */ 5849 <0x0 0xfe680000 0 0x100000>; /* GICR */ 5850 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5851 its0: msi-controller@fe640000 { 5852 compatible = "arm,gic-v3-its"; 5853 msi-controller; 5854 #msi-cells = <1>; 5855 reg = <0x0 0xfe640000 0x0 0x20000>; 5856 }; 5857 its1: msi-controller@fe660000 { 5858 compatible = "arm,gic-v3-its"; 5859 msi-controller; 5860 #msi-cells = <1>; 5861 reg = <0x0 0xfe660000 0x0 0x20000>; 5862 }; 5863 }; 5864 5865 dmac0: dma-controller@fea10000 { 5866 compatible = "arm,pl330", "arm,primecell"; 5867 reg = <0x0 0xfea10000 0x0 0x4000>; 5868 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 5869 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 5870 clocks = <&cru ACLK_DMAC0>; 5871 clock-names = "apb_pclk"; 5872 #dma-cells = <1>; 5873 arm,pl330-periph-burst; 5874 }; 5875 5876 dmac1: dma-controller@fea30000 { 5877 compatible = "arm,pl330", "arm,primecell"; 5878 reg = <0x0 0xfea30000 0x0 0x4000>; 5879 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 5880 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 5881 clocks = <&cru ACLK_DMAC1>; 5882 clock-names = "apb_pclk"; 5883 #dma-cells = <1>; 5884 arm,pl330-periph-burst; 5885 }; 5886 5887 can0: can@fea50000 { 5888 compatible = "rockchip,can-2.0"; 5889 reg = <0x0 0xfea50000 0x0 0x1000>; 5890 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 5891 clocks = <&cru CLK_CAN0>, <&cru PCLK_CAN0>; 5892 clock-names = "baudclk", "apb_pclk"; 5893 resets = <&cru SRST_CAN0>, <&cru SRST_P_CAN0>; 5894 reset-names = "can", "can-apb"; 5895 pinctrl-names = "default"; 5896 pinctrl-0 = <&can0m0_pins>; 5897 tx-fifo-depth = <1>; 5898 rx-fifo-depth = <6>; 5899 status = "disabled"; 5900 }; 5901 5902 can1: can@fea60000 { 5903 compatible = "rockchip,can-2.0"; 5904 reg = <0x0 0xfea60000 0x0 0x1000>; 5905 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 5906 clocks = <&cru CLK_CAN1>, <&cru PCLK_CAN1>; 5907 clock-names = "baudclk", "apb_pclk"; 5908 resets = <&cru SRST_CAN1>, <&cru SRST_P_CAN1>; 5909 reset-names = "can", "can-apb"; 5910 pinctrl-names = "default"; 5911 pinctrl-0 = <&can1m0_pins>; 5912 tx-fifo-depth = <1>; 5913 rx-fifo-depth = <6>; 5914 status = "disabled"; 5915 }; 5916 5917 can2: can@fea70000 { 5918 compatible = "rockchip,can-2.0"; 5919 reg = <0x0 0xfea70000 0x0 0x1000>; 5920 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 5921 clocks = <&cru CLK_CAN2>, <&cru PCLK_CAN2>; 5922 clock-names = "baudclk", "apb_pclk"; 5923 resets = <&cru SRST_CAN2>, <&cru SRST_P_CAN2>; 5924 reset-names = "can", "can-apb"; 5925 pinctrl-names = "default"; 5926 pinctrl-0 = <&can2m0_pins>; 5927 tx-fifo-depth = <1>; 5928 rx-fifo-depth = <6>; 5929 status = "disabled"; 5930 }; 5931 5932 hw_decompress: decompress@fea80000 { 5933 compatible = "rockchip,hw-decompress"; 5934 reg = <0x0 0xfea80000 0x0 0x1000>; 5935 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 5936 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 5937 clock-names = "aclk", "dclk", "pclk"; 5938 resets = <&cru SRST_D_DECOM>; 5939 reset-names = "dresetn"; 5940 status = "disabled"; 5941 }; 5942 5943 i2c1: i2c@fea90000 { 5944 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 5945 reg = <0x0 0xfea90000 0x0 0x1000>; 5946 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 5947 clock-names = "i2c", "pclk"; 5948 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 5949 pinctrl-names = "default"; 5950 pinctrl-0 = <&i2c1m0_xfer>; 5951 #address-cells = <1>; 5952 #size-cells = <0>; 5953 status = "disabled"; 5954 }; 5955 5956 i2c2: i2c@feaa0000 { 5957 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 5958 reg = <0x0 0xfeaa0000 0x0 0x1000>; 5959 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 5960 clock-names = "i2c", "pclk"; 5961 interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 5962 pinctrl-names = "default"; 5963 pinctrl-0 = <&i2c2m0_xfer>; 5964 #address-cells = <1>; 5965 #size-cells = <0>; 5966 status = "disabled"; 5967 }; 5968 5969 i2c3: i2c@feab0000 { 5970 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 5971 reg = <0x0 0xfeab0000 0x0 0x1000>; 5972 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 5973 clock-names = "i2c", "pclk"; 5974 interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>; 5975 pinctrl-names = "default"; 5976 pinctrl-0 = <&i2c3m0_xfer>; 5977 #address-cells = <1>; 5978 #size-cells = <0>; 5979 status = "disabled"; 5980 }; 5981 5982 i2c4: i2c@feac0000 { 5983 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 5984 reg = <0x0 0xfeac0000 0x0 0x1000>; 5985 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 5986 clock-names = "i2c", "pclk"; 5987 interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 5988 pinctrl-names = "default"; 5989 pinctrl-0 = <&i2c4m0_xfer>; 5990 #address-cells = <1>; 5991 #size-cells = <0>; 5992 status = "disabled"; 5993 }; 5994 5995 i2c5: i2c@fead0000 { 5996 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 5997 reg = <0x0 0xfead0000 0x0 0x1000>; 5998 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 5999 clock-names = "i2c", "pclk"; 6000 interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>; 6001 pinctrl-names = "default"; 6002 pinctrl-0 = <&i2c5m0_xfer>; 6003 #address-cells = <1>; 6004 #size-cells = <0>; 6005 status = "disabled"; 6006 }; 6007 6008 rktimer: timer@feae0000 { 6009 compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer"; 6010 reg = <0x0 0xfeae0000 0x0 0x20>; 6011 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 6012 clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>; 6013 clock-names = "pclk", "timer"; 6014 }; 6015 6016 wdt: watchdog@feaf0000 { 6017 compatible = "snps,dw-wdt"; 6018 reg = <0x0 0xfeaf0000 0x0 0x100>; 6019 clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>; 6020 clock-names = "tclk", "pclk"; 6021 interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 6022 status = "disabled"; 6023 }; 6024 6025 spi0: spi@feb00000 { 6026 compatible = "rockchip,rk3066-spi"; 6027 reg = <0x0 0xfeb00000 0x0 0x1000>; 6028 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 6029 #address-cells = <1>; 6030 #size-cells = <0>; 6031 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 6032 clock-names = "spiclk", "apb_pclk"; 6033 dmas = <&dmac0 14>, <&dmac0 15>; 6034 dma-names = "tx", "rx"; 6035 pinctrl-names = "default"; 6036 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>; 6037 num-cs = <2>; 6038 status = "disabled"; 6039 }; 6040 6041 spi1: spi@feb10000 { 6042 compatible = "rockchip,rk3066-spi"; 6043 reg = <0x0 0xfeb10000 0x0 0x1000>; 6044 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 6045 #address-cells = <1>; 6046 #size-cells = <0>; 6047 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>; 6048 clock-names = "spiclk", "apb_pclk"; 6049 dmas = <&dmac0 16>, <&dmac0 17>; 6050 dma-names = "tx", "rx"; 6051 pinctrl-names = "default"; 6052 pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>; 6053 num-cs = <2>; 6054 status = "disabled"; 6055 }; 6056 6057 spi2: spi@feb20000 { 6058 compatible = "rockchip,rk3066-spi"; 6059 reg = <0x0 0xfeb20000 0x0 0x1000>; 6060 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 6061 #address-cells = <1>; 6062 #size-cells = <0>; 6063 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>; 6064 clock-names = "spiclk", "apb_pclk"; 6065 dmas = <&dmac1 15>, <&dmac1 16>; 6066 dma-names = "tx", "rx"; 6067 pinctrl-names = "default"; 6068 pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>; 6069 num-cs = <2>; 6070 status = "disabled"; 6071 }; 6072 6073 spi3: spi@feb30000 { 6074 compatible = "rockchip,rk3066-spi"; 6075 reg = <0x0 0xfeb30000 0x0 0x1000>; 6076 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 6077 #address-cells = <1>; 6078 #size-cells = <0>; 6079 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>; 6080 clock-names = "spiclk", "apb_pclk"; 6081 dmas = <&dmac1 17>, <&dmac1 18>; 6082 dma-names = "tx", "rx"; 6083 pinctrl-names = "default"; 6084 pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>; 6085 num-cs = <2>; 6086 status = "disabled"; 6087 }; 6088 6089 uart1: serial@feb40000 { 6090 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 6091 reg = <0x0 0xfeb40000 0x0 0x100>; 6092 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 6093 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 6094 clock-names = "baudclk", "apb_pclk"; 6095 reg-shift = <2>; 6096 reg-io-width = <4>; 6097 dmas = <&dmac0 8>, <&dmac0 9>; 6098 pinctrl-names = "default"; 6099 pinctrl-0 = <&uart1m1_xfer>; 6100 status = "disabled"; 6101 }; 6102 6103 uart2: serial@feb50000 { 6104 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 6105 reg = <0x0 0xfeb50000 0x0 0x100>; 6106 interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>; 6107 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 6108 clock-names = "baudclk", "apb_pclk"; 6109 reg-shift = <2>; 6110 reg-io-width = <4>; 6111 dmas = <&dmac0 10>, <&dmac0 11>; 6112 pinctrl-names = "default"; 6113 pinctrl-0 = <&uart2m1_xfer>; 6114 status = "disabled"; 6115 }; 6116 6117 uart3: serial@feb60000 { 6118 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 6119 reg = <0x0 0xfeb60000 0x0 0x100>; 6120 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>; 6121 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 6122 clock-names = "baudclk", "apb_pclk"; 6123 reg-shift = <2>; 6124 reg-io-width = <4>; 6125 dmas = <&dmac0 12>, <&dmac0 13>; 6126 pinctrl-names = "default"; 6127 pinctrl-0 = <&uart3m1_xfer>; 6128 status = "disabled"; 6129 }; 6130 6131 uart4: serial@feb70000 { 6132 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 6133 reg = <0x0 0xfeb70000 0x0 0x100>; 6134 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; 6135 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 6136 clock-names = "baudclk", "apb_pclk"; 6137 reg-shift = <2>; 6138 reg-io-width = <4>; 6139 dmas = <&dmac1 9>, <&dmac1 10>; 6140 pinctrl-names = "default"; 6141 pinctrl-0 = <&uart4m1_xfer>; 6142 status = "disabled"; 6143 }; 6144 6145 uart5: serial@feb80000 { 6146 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 6147 reg = <0x0 0xfeb80000 0x0 0x100>; 6148 interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>; 6149 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 6150 clock-names = "baudclk", "apb_pclk"; 6151 reg-shift = <2>; 6152 reg-io-width = <4>; 6153 dmas = <&dmac1 11>, <&dmac1 12>; 6154 pinctrl-names = "default"; 6155 pinctrl-0 = <&uart5m1_xfer>; 6156 status = "disabled"; 6157 }; 6158 6159 uart6: serial@feb90000 { 6160 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 6161 reg = <0x0 0xfeb90000 0x0 0x100>; 6162 interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 6163 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 6164 clock-names = "baudclk", "apb_pclk"; 6165 reg-shift = <2>; 6166 reg-io-width = <4>; 6167 dmas = <&dmac1 13>, <&dmac1 14>; 6168 pinctrl-names = "default"; 6169 pinctrl-0 = <&uart6m1_xfer>; 6170 status = "disabled"; 6171 }; 6172 6173 uart7: serial@feba0000 { 6174 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 6175 reg = <0x0 0xfeba0000 0x0 0x100>; 6176 interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>; 6177 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 6178 clock-names = "baudclk", "apb_pclk"; 6179 reg-shift = <2>; 6180 reg-io-width = <4>; 6181 dmas = <&dmac2 7>, <&dmac2 8>; 6182 pinctrl-names = "default"; 6183 pinctrl-0 = <&uart7m1_xfer>; 6184 status = "disabled"; 6185 }; 6186 6187 uart8: serial@febb0000 { 6188 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 6189 reg = <0x0 0xfebb0000 0x0 0x100>; 6190 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 6191 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>; 6192 clock-names = "baudclk", "apb_pclk"; 6193 reg-shift = <2>; 6194 reg-io-width = <4>; 6195 dmas = <&dmac2 9>, <&dmac2 10>; 6196 pinctrl-names = "default"; 6197 pinctrl-0 = <&uart8m1_xfer>; 6198 status = "disabled"; 6199 }; 6200 6201 uart9: serial@febc0000 { 6202 compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; 6203 reg = <0x0 0xfebc0000 0x0 0x100>; 6204 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 6205 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>; 6206 clock-names = "baudclk", "apb_pclk"; 6207 reg-shift = <2>; 6208 reg-io-width = <4>; 6209 dmas = <&dmac2 11>, <&dmac2 12>; 6210 pinctrl-names = "default"; 6211 pinctrl-0 = <&uart9m1_xfer>; 6212 status = "disabled"; 6213 }; 6214 6215 pwm4: pwm@febd0000 { 6216 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6217 reg = <0x0 0xfebd0000 0x0 0x10>; 6218 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 6219 #pwm-cells = <3>; 6220 pinctrl-names = "active"; 6221 pinctrl-0 = <&pwm4m0_pins>; 6222 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 6223 clock-names = "pwm", "pclk"; 6224 status = "disabled"; 6225 }; 6226 6227 pwm5: pwm@febd0010 { 6228 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6229 reg = <0x0 0xfebd0010 0x0 0x10>; 6230 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 6231 #pwm-cells = <3>; 6232 pinctrl-names = "active"; 6233 pinctrl-0 = <&pwm5m0_pins>; 6234 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 6235 clock-names = "pwm", "pclk"; 6236 status = "disabled"; 6237 }; 6238 6239 pwm6: pwm@febd0020 { 6240 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6241 reg = <0x0 0xfebd0020 0x0 0x10>; 6242 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; 6243 #pwm-cells = <3>; 6244 pinctrl-names = "active"; 6245 pinctrl-0 = <&pwm6m0_pins>; 6246 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 6247 clock-names = "pwm", "pclk"; 6248 status = "disabled"; 6249 }; 6250 6251 pwm7: pwm@febd0030 { 6252 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6253 reg = <0x0 0xfebd0030 0x0 0x10>; 6254 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 6255 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; 6256 #pwm-cells = <3>; 6257 pinctrl-names = "active"; 6258 pinctrl-0 = <&pwm7m0_pins>; 6259 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 6260 clock-names = "pwm", "pclk"; 6261 status = "disabled"; 6262 }; 6263 6264 pwm8: pwm@febe0000 { 6265 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6266 reg = <0x0 0xfebe0000 0x0 0x10>; 6267 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 6268 #pwm-cells = <3>; 6269 pinctrl-names = "active"; 6270 pinctrl-0 = <&pwm8m0_pins>; 6271 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 6272 clock-names = "pwm", "pclk"; 6273 status = "disabled"; 6274 }; 6275 6276 pwm9: pwm@febe0010 { 6277 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6278 reg = <0x0 0xfebe0010 0x0 0x10>; 6279 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 6280 #pwm-cells = <3>; 6281 pinctrl-names = "active"; 6282 pinctrl-0 = <&pwm9m0_pins>; 6283 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 6284 clock-names = "pwm", "pclk"; 6285 status = "disabled"; 6286 }; 6287 6288 pwm10: pwm@febe0020 { 6289 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6290 reg = <0x0 0xfebe0020 0x0 0x10>; 6291 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; 6292 #pwm-cells = <3>; 6293 pinctrl-names = "active"; 6294 pinctrl-0 = <&pwm10m0_pins>; 6295 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 6296 clock-names = "pwm", "pclk"; 6297 status = "disabled"; 6298 }; 6299 6300 pwm11: pwm@febe0030 { 6301 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6302 reg = <0x0 0xfebe0030 0x0 0x10>; 6303 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 6304 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>; 6305 #pwm-cells = <3>; 6306 pinctrl-names = "active"; 6307 pinctrl-0 = <&pwm11m0_pins>; 6308 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 6309 clock-names = "pwm", "pclk"; 6310 status = "disabled"; 6311 }; 6312 6313 pwm12: pwm@febf0000 { 6314 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6315 reg = <0x0 0xfebf0000 0x0 0x10>; 6316 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 6317 #pwm-cells = <3>; 6318 pinctrl-names = "active"; 6319 pinctrl-0 = <&pwm12m0_pins>; 6320 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 6321 clock-names = "pwm", "pclk"; 6322 status = "disabled"; 6323 }; 6324 6325 pwm13: pwm@febf0010 { 6326 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6327 reg = <0x0 0xfebf0010 0x0 0x10>; 6328 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 6329 #pwm-cells = <3>; 6330 pinctrl-names = "active"; 6331 pinctrl-0 = <&pwm13m0_pins>; 6332 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 6333 clock-names = "pwm", "pclk"; 6334 status = "disabled"; 6335 }; 6336 6337 pwm14: pwm@febf0020 { 6338 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6339 reg = <0x0 0xfebf0020 0x0 0x10>; 6340 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>; 6341 #pwm-cells = <3>; 6342 pinctrl-names = "active"; 6343 pinctrl-0 = <&pwm14m0_pins>; 6344 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 6345 clock-names = "pwm", "pclk"; 6346 status = "disabled"; 6347 }; 6348 6349 pwm15: pwm@febf0030 { 6350 compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm"; 6351 reg = <0x0 0xfebf0030 0x0 0x10>; 6352 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 6353 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>; 6354 #pwm-cells = <3>; 6355 pinctrl-names = "active"; 6356 pinctrl-0 = <&pwm15m0_pins>; 6357 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>; 6358 clock-names = "pwm", "pclk"; 6359 status = "disabled"; 6360 }; 6361 6362 tsadc: tsadc@fec00000 { 6363 compatible = "rockchip,rk3588-tsadc"; 6364 reg = <0x0 0xfec00000 0x0 0x400>; 6365 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; 6366 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>; 6367 clock-names = "tsadc", "apb_pclk"; 6368 assigned-clocks = <&cru CLK_TSADC>; 6369 assigned-clock-rates = <2000000>; 6370 resets = <&cru SRST_TSADC>, <&cru SRST_P_TSADC>; 6371 reset-names = "tsadc", "tsadc-apb"; 6372 #thermal-sensor-cells = <1>; 6373 rockchip,hw-tshut-temp = <120000>; 6374 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 6375 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 6376 pinctrl-names = "gpio", "otpout"; 6377 pinctrl-0 = <&tsadc_gpio_func>; 6378 pinctrl-1 = <&tsadc_shut>; 6379 status = "disabled"; 6380 }; 6381 6382 saradc: saradc@fec10000 { 6383 compatible = "rockchip,rk3588-saradc"; 6384 reg = <0x0 0xfec10000 0x0 0x10000>; 6385 interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>; 6386 #io-channel-cells = <1>; 6387 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 6388 clock-names = "saradc", "apb_pclk"; 6389 resets = <&cru SRST_P_SARADC>; 6390 reset-names = "saradc-apb"; 6391 status = "disabled"; 6392 }; 6393 6394 mailbox0: mailbox@fec60000 { 6395 compatible = "rockchip,rk3588-mailbox", 6396 "rockchip,rk3368-mailbox"; 6397 reg = <0x0 0xfec60000 0x0 0x200>; 6398 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 6399 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 6400 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 6401 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 6402 clocks = <&cru PCLK_MAILBOX0>; 6403 clock-names = "pclk_mailbox"; 6404 #mbox-cells = <1>; 6405 status = "disabled"; 6406 }; 6407 6408 mailbox1: mailbox@fec70000 { 6409 compatible = "rockchip,rk3588-mailbox", 6410 "rockchip,rk3368-mailbox"; 6411 reg = <0x0 0xfec70000 0x0 0x200>; 6412 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, 6413 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 6414 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 6415 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 6416 clocks = <&cru PCLK_MAILBOX1>; 6417 clock-names = "pclk_mailbox"; 6418 #mbox-cells = <1>; 6419 status = "disabled"; 6420 }; 6421 6422 i2c6: i2c@fec80000 { 6423 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 6424 reg = <0x0 0xfec80000 0x0 0x1000>; 6425 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 6426 clock-names = "i2c", "pclk"; 6427 interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>; 6428 pinctrl-names = "default"; 6429 pinctrl-0 = <&i2c6m0_xfer>; 6430 #address-cells = <1>; 6431 #size-cells = <0>; 6432 status = "disabled"; 6433 }; 6434 6435 i2c7: i2c@fec90000 { 6436 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 6437 reg = <0x0 0xfec90000 0x0 0x1000>; 6438 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 6439 clock-names = "i2c", "pclk"; 6440 interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>; 6441 pinctrl-names = "default"; 6442 pinctrl-0 = <&i2c7m0_xfer>; 6443 #address-cells = <1>; 6444 #size-cells = <0>; 6445 status = "disabled"; 6446 }; 6447 6448 i2c8: i2c@feca0000 { 6449 compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c"; 6450 reg = <0x0 0xfeca0000 0x0 0x1000>; 6451 clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>; 6452 clock-names = "i2c", "pclk"; 6453 interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>; 6454 pinctrl-names = "default"; 6455 pinctrl-0 = <&i2c8m0_xfer>; 6456 #address-cells = <1>; 6457 #size-cells = <0>; 6458 status = "disabled"; 6459 }; 6460 6461 spi4: spi@fecb0000 { 6462 compatible = "rockchip,rk3066-spi"; 6463 reg = <0x0 0xfecb0000 0x0 0x1000>; 6464 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 6465 #address-cells = <1>; 6466 #size-cells = <0>; 6467 clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>; 6468 clock-names = "spiclk", "apb_pclk"; 6469 dmas = <&dmac2 13>, <&dmac2 14>; 6470 dma-names = "tx", "rx"; 6471 pinctrl-names = "default"; 6472 pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>; 6473 num-cs = <2>; 6474 status = "disabled"; 6475 }; 6476 6477 otp: otp@fecc0000 { 6478 compatible = "rockchip,rk3588-otp"; 6479 reg = <0x0 0xfecc0000 0x0 0x400>; 6480 #address-cells = <1>; 6481 #size-cells = <1>; 6482 clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>, 6483 <&cru CLK_OTPC_ARB>, <&cru CLK_OTP_PHY_G>; 6484 clock-names = "otpc", "apb", "arb", "phy"; 6485 resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>, 6486 <&cru SRST_OTPC_ARB>; 6487 reset-names = "otpc", "apb", "arb"; 6488 6489 /* Data cells */ 6490 cpu_code: cpu-code@2 { 6491 reg = <0x02 0x2>; 6492 }; 6493 package_serial_number_high: package-serial-number-high@5 { 6494 reg = <0x05 0x1>; 6495 bits = <0 1>; 6496 }; 6497 package_serial_number_low: package-serial-number-low@6 { 6498 reg = <0x06 0x1>; 6499 bits = <5 3>; 6500 }; 6501 specification_serial_number: specification-serial-number@6 { 6502 reg = <0x06 0x1>; 6503 bits = <0 5>; 6504 }; 6505 otp_id: id@7 { 6506 reg = <0x07 0x10>; 6507 }; 6508 otp_cpu_version: cpu-version@1c { 6509 reg = <0x1c 0x1>; 6510 bits = <3 3>; 6511 }; 6512 cpub0_leakage: cpub0-leakage@17 { 6513 reg = <0x17 0x1>; 6514 }; 6515 cpub1_leakage: cpub1-leakage@18 { 6516 reg = <0x18 0x1>; 6517 }; 6518 cpul_leakage: cpul-leakage@19 { 6519 reg = <0x19 0x1>; 6520 }; 6521 log_leakage: log-leakage@1a { 6522 reg = <0x1a 0x1>; 6523 }; 6524 gpu_leakage: gpu-leakage@1b { 6525 reg = <0x1b 0x1>; 6526 }; 6527 npu_leakage: npu-leakage@28 { 6528 reg = <0x28 0x1>; 6529 }; 6530 codec_leakage: codec-leakage@29 { 6531 reg = <0x29 0x1>; 6532 }; 6533 cpul_opp_info: cpul-opp-info@3d { 6534 reg = <0x3d 0x6>; 6535 }; 6536 cpub01_opp_info: cpub01-opp-info@43 { 6537 reg = <0x43 0x6>; 6538 }; 6539 cpub23_opp_info: cpub23-opp-info@49 { 6540 reg = <0x49 0x6>; 6541 }; 6542 gpu_opp_info: gpu-opp-info@4f { 6543 reg = <0x4f 0x6>; 6544 }; 6545 npu_opp_info: npu-opp-info@55 { 6546 reg = <0x55 0x6>; 6547 }; 6548 dmc_opp_info: dmc-opp-info@5b { 6549 reg = <0x5b 0x6>; 6550 }; 6551 vop_opp_info: vop-opp-info@61 { 6552 reg = <0x61 0x6>; 6553 }; 6554 venc_opp_info: venc-opp-info@67 { 6555 reg = <0x67 0x6>; 6556 }; 6557 }; 6558 6559 mailbox2: mailbox@fece0000 { 6560 compatible = "rockchip,rk3588-mailbox", 6561 "rockchip,rk3368-mailbox"; 6562 reg = <0x0 0xfece0000 0x0 0x200>; 6563 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 6564 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, 6565 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 6566 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 6567 clocks = <&cru PCLK_MAILBOX2>; 6568 clock-names = "pclk_mailbox"; 6569 #mbox-cells = <1>; 6570 status = "disabled"; 6571 }; 6572 6573 dmac2: dma-controller@fed10000 { 6574 compatible = "arm,pl330", "arm,primecell"; 6575 reg = <0x0 0xfed10000 0x0 0x4000>; 6576 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 6577 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 6578 clocks = <&cru ACLK_DMAC2>; 6579 clock-names = "apb_pclk"; 6580 #dma-cells = <1>; 6581 arm,pl330-periph-burst; 6582 }; 6583 6584 hdptxphy0: phy@fed60000 { 6585 compatible = "rockchip,rk3588-hdptx-phy"; 6586 reg = <0x0 0xfed60000 0x0 0x2000>; 6587 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 6588 clock-names = "ref", "apb"; 6589 resets = <&cru SRST_P_HDPTX0>, <&cru SRST_HDPTX0_INIT>, 6590 <&cru SRST_HDPTX0_CMN>, <&cru SRST_HDPTX0_LANE>; 6591 reset-names = "apb", "init", "cmn", "lane"; 6592 rockchip,grf = <&hdptxphy0_grf>; 6593 #phy-cells = <0>; 6594 status = "disabled"; 6595 }; 6596 6597 hdptxphy_hdmi0: hdmiphy@fed60000 { 6598 compatible = "rockchip,rk3588-hdptx-phy-hdmi"; 6599 reg = <0x0 0xfed60000 0x0 0x2000>; 6600 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX0>; 6601 clock-names = "ref", "apb"; 6602 resets = <&cru SRST_HDPTX0>, <&cru SRST_P_HDPTX0>, 6603 <&cru SRST_HDPTX0_INIT>, <&cru SRST_HDPTX0_CMN>, 6604 <&cru SRST_HDPTX0_LANE>, <&cru SRST_HDPTX0_ROPLL>, 6605 <&cru SRST_HDPTX0_LCPLL>; 6606 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 6607 "lcpll"; 6608 rockchip,grf = <&hdptxphy0_grf>; 6609 #phy-cells = <0>; 6610 status = "disabled"; 6611 6612 hdptxphy_hdmi_clk0: clk-port { 6613 #clock-cells = <0>; 6614 status = "okay"; 6615 }; 6616 }; 6617 6618 usbdp_phy0: phy@fed80000 { 6619 compatible = "rockchip,rk3588-usbdp-phy"; 6620 reg = <0x0 0xfed80000 0x0 0x10000>; 6621 rockchip,u2phy-grf = <&usb2phy0_grf>; 6622 rockchip,usb-grf = <&usb_grf>; 6623 rockchip,usbdpphy-grf = <&usbdpphy0_grf>; 6624 rockchip,vo-grf = <&vo0_grf>; 6625 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 6626 <&cru CLK_USBDP_PHY0_IMMORTAL>, 6627 <&cru PCLK_USBDPPHY0>, 6628 <&u2phy0>; 6629 clock-names = "refclk", "immortal", "pclk", "utmi"; 6630 resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>, 6631 <&cru SRST_USBDP_COMBO_PHY0_CMN>, 6632 <&cru SRST_USBDP_COMBO_PHY0_LANE>, 6633 <&cru SRST_USBDP_COMBO_PHY0_PCS>, 6634 <&cru SRST_P_USBDPPHY0>; 6635 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 6636 status = "disabled"; 6637 6638 usbdp_phy0_dp: dp-port { 6639 #phy-cells = <0>; 6640 status = "disabled"; 6641 }; 6642 6643 usbdp_phy0_u3: u3-port { 6644 #phy-cells = <0>; 6645 status = "disabled"; 6646 }; 6647 }; 6648 6649 mipidcphy0: phy@feda0000 { 6650 compatible = "rockchip,rk3588-mipi-dcphy"; 6651 reg = <0x0 0xfeda0000 0x0 0x10000>; 6652 rockchip,grf = <&mipidcphy0_grf>; 6653 clocks = <&cru PCLK_MIPI_DCPHY0>, 6654 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 6655 clock-names = "pclk", "ref"; 6656 resets = <&cru SRST_M_MIPI_DCPHY0>, 6657 <&cru SRST_P_MIPI_DCPHY0>, 6658 <&cru SRST_P_MIPI_DCPHY0_GRF>, 6659 <&cru SRST_S_MIPI_DCPHY0>; 6660 reset-names = "m_phy", "apb", "grf", "s_phy"; 6661 #phy-cells = <0>; 6662 status = "okay"; 6663 }; 6664 6665 mipidcphy1: phy@fedb0000 { 6666 compatible = "rockchip,rk3588-mipi-dcphy"; 6667 reg = <0x0 0xfedb0000 0x0 0x10000>; 6668 rockchip,grf = <&mipidcphy1_grf>; 6669 clocks = <&cru PCLK_MIPI_DCPHY1>, 6670 <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>; 6671 clock-names = "pclk", "ref"; 6672 resets = <&cru SRST_M_MIPI_DCPHY1>, 6673 <&cru SRST_P_MIPI_DCPHY1>, 6674 <&cru SRST_P_MIPI_DCPHY1_GRF>, 6675 <&cru SRST_S_MIPI_DCPHY1>; 6676 reset-names = "m_phy", "apb", "grf", "s_phy"; 6677 #phy-cells = <0>; 6678 status = "okay"; 6679 }; 6680 6681 csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 { 6682 compatible = "rockchip,rk3588-csi2-dphy-hw"; 6683 reg = <0x0 0xfedc0000 0x0 0x8000>; 6684 clocks = <&cru PCLK_CSIPHY0>; 6685 clock-names = "pclk"; 6686 resets = <&cru SRST_CSIPHY0>, <&cru SRST_P_CSIPHY0>; 6687 reset-names = "srst_csiphy0", "srst_p_csiphy0"; 6688 rockchip,grf = <&mipidphy0_grf>; 6689 rockchip,sys_grf = <&sys_grf>; 6690 status = "okay"; 6691 }; 6692 6693 csi2_dphy1_hw: csi2-dphy1-hw@fedc8000 { 6694 compatible = "rockchip,rk3588-csi2-dphy-hw"; 6695 reg = <0x0 0xfedc8000 0x0 0x8000>; 6696 clocks = <&cru PCLK_CSIPHY1>; 6697 clock-names = "pclk"; 6698 resets = <&cru SRST_CSIPHY1>, <&cru SRST_P_CSIPHY1>; 6699 reset-names = "srst_csiphy1", "srst_p_csiphy1"; 6700 rockchip,grf = <&mipidphy1_grf>; 6701 rockchip,sys_grf = <&sys_grf>; 6702 status = "okay"; 6703 }; 6704 6705 combphy0_ps: phy@fee00000 { 6706 compatible = "rockchip,rk3588-naneng-combphy"; 6707 reg = <0x0 0xfee00000 0x0 0x100>; 6708 #phy-cells = <1>; 6709 clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>, 6710 <&cru PCLK_PHP_ROOT>; 6711 clock-names = "refclk", "apbclk", "phpclk"; 6712 assigned-clocks = <&cru CLK_REF_PIPE_PHY0>; 6713 assigned-clock-rates = <100000000>; 6714 resets = <&cru SRST_P_PCIE2_PHY0>, <&cru SRST_REF_PIPE_PHY0>; 6715 reset-names = "combphy-apb", "combphy"; 6716 rockchip,pipe-grf = <&php_grf>; 6717 rockchip,pipe-phy-grf = <&pipe_phy0_grf>; 6718 status = "disabled"; 6719 }; 6720 6721 combphy2_psu: phy@fee20000 { 6722 compatible = "rockchip,rk3588-naneng-combphy"; 6723 reg = <0x0 0xfee20000 0x0 0x100>; 6724 #phy-cells = <1>; 6725 clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>, 6726 <&cru PCLK_PHP_ROOT>; 6727 clock-names = "refclk", "apbclk", "phpclk"; 6728 assigned-clocks = <&cru CLK_REF_PIPE_PHY2>; 6729 assigned-clock-rates = <100000000>; 6730 resets = <&cru SRST_P_PCIE2_PHY2>, <&cru SRST_REF_PIPE_PHY2>; 6731 reset-names = "combphy-apb", "combphy"; 6732 rockchip,pipe-grf = <&php_grf>; 6733 rockchip,pipe-phy-grf = <&pipe_phy2_grf>; 6734 rockchip,pcie1ln-sel-bits = <0x100 1 1 0>; 6735 status = "disabled"; 6736 }; 6737 6738 syssram: sram@ff001000 { 6739 compatible = "mmio-sram"; 6740 reg = <0x0 0xff001000 0x0 0xef000>; 6741 6742 #address-cells = <1>; 6743 #size-cells = <1>; 6744 ranges = <0x0 0x0 0xff001000 0xef000>; 6745 /* start address and size should be 4k algin */ 6746 rkvdec0_sram: rkvdec-sram@0 { 6747 reg = <0x0 0x78000>; 6748 }; 6749 rkvdec1_sram: rkvdec-sram@78000 { 6750 reg = <0x78000 0x77000>; 6751 }; 6752 }; 6753 6754 pinctrl: pinctrl { 6755 compatible = "rockchip,rk3588-pinctrl"; 6756 rockchip,grf = <&ioc>; 6757 #address-cells = <2>; 6758 #size-cells = <2>; 6759 ranges; 6760 6761 gpio0: gpio@fd8a0000 { 6762 compatible = "rockchip,gpio-bank"; 6763 reg = <0x0 0xfd8a0000 0x0 0x100>; 6764 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 6765 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 6766 6767 gpio-controller; 6768 #gpio-cells = <2>; 6769 gpio-ranges = <&pinctrl 0 0 32>; 6770 interrupt-controller; 6771 #interrupt-cells = <2>; 6772 }; 6773 6774 gpio1: gpio@fec20000 { 6775 compatible = "rockchip,gpio-bank"; 6776 reg = <0x0 0xfec20000 0x0 0x100>; 6777 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 6778 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 6779 6780 gpio-controller; 6781 #gpio-cells = <2>; 6782 gpio-ranges = <&pinctrl 0 32 32>; 6783 interrupt-controller; 6784 #interrupt-cells = <2>; 6785 }; 6786 6787 gpio2: gpio@fec30000 { 6788 compatible = "rockchip,gpio-bank"; 6789 reg = <0x0 0xfec30000 0x0 0x100>; 6790 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; 6791 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 6792 6793 gpio-controller; 6794 #gpio-cells = <2>; 6795 gpio-ranges = <&pinctrl 0 64 32>; 6796 interrupt-controller; 6797 #interrupt-cells = <2>; 6798 }; 6799 6800 gpio3: gpio@fec40000 { 6801 compatible = "rockchip,gpio-bank"; 6802 reg = <0x0 0xfec40000 0x0 0x100>; 6803 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 6804 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 6805 6806 gpio-controller; 6807 #gpio-cells = <2>; 6808 gpio-ranges = <&pinctrl 0 96 32>; 6809 interrupt-controller; 6810 #interrupt-cells = <2>; 6811 }; 6812 6813 gpio4: gpio@fec50000 { 6814 compatible = "rockchip,gpio-bank"; 6815 reg = <0x0 0xfec50000 0x0 0x100>; 6816 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>; 6817 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 6818 6819 gpio-controller; 6820 #gpio-cells = <2>; 6821 gpio-ranges = <&pinctrl 0 128 32>; 6822 interrupt-controller; 6823 #interrupt-cells = <2>; 6824 }; 6825 }; 6826}; 6827 6828#include "rk3588s-pinctrl.dtsi" 6829
