1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/phy/phy-snps-pcie3.h> 7#include "rk3588s.dtsi" 8#include "rk3588-vccio3-pinctrl.dtsi" 9 10/ { 11 aliases { 12 dp0 = &dp0; 13 dp1 = &dp1; 14 edp0 = &edp0; 15 edp1 = &edp1; 16 ethernet0 = &gmac0; 17 hdptx0 = &hdptxphy0; 18 hdptx1 = &hdptxphy1; 19 hdptxhdmi0 = &hdptxphy_hdmi0; 20 hdptxhdmi1 = &hdptxphy_hdmi1; 21 hdmi0 = &hdmi0; 22 hdmi1 = &hdmi1; 23 hdmirx0 = &hdmirx_ctrler; 24 rkcif_mipi_lvds4= &rkcif_mipi_lvds4; 25 rkcif_mipi_lvds5= &rkcif_mipi_lvds5; 26 usbdp0 = &usbdp_phy0; 27 usbdp1 = &usbdp_phy1; 28 }; 29 30 rkcif_mipi_lvds4: rkcif-mipi-lvds4 { 31 compatible = "rockchip,rkcif-mipi-lvds"; 32 rockchip,hw = <&rkcif>; 33 iommus = <&rkcif_mmu>; 34 status = "disabled"; 35 }; 36 37 rkcif_mipi_lvds4_sditf: rkcif-mipi-lvds4-sditf { 38 compatible = "rockchip,rkcif-sditf"; 39 rockchip,cif = <&rkcif_mipi_lvds4>; 40 status = "disabled"; 41 }; 42 43 rkcif_mipi_lvds4_sditf_vir1: rkcif-mipi-lvds4-sditf-vir1 { 44 compatible = "rockchip,rkcif-sditf"; 45 rockchip,cif = <&rkcif_mipi_lvds4>; 46 status = "disabled"; 47 }; 48 49 rkcif_mipi_lvds4_sditf_vir2: rkcif-mipi-lvds4-sditf-vir2 { 50 compatible = "rockchip,rkcif-sditf"; 51 rockchip,cif = <&rkcif_mipi_lvds4>; 52 status = "disabled"; 53 }; 54 55 rkcif_mipi_lvds4_sditf_vir3: rkcif-mipi-lvds4-sditf-vir3 { 56 compatible = "rockchip,rkcif-sditf"; 57 rockchip,cif = <&rkcif_mipi_lvds4>; 58 status = "disabled"; 59 }; 60 61 rkcif_mipi_lvds5: rkcif-mipi-lvds5 { 62 compatible = "rockchip,rkcif-mipi-lvds"; 63 rockchip,hw = <&rkcif>; 64 iommus = <&rkcif_mmu>; 65 status = "disabled"; 66 }; 67 68 rkcif_mipi_lvds5_sditf: rkcif-mipi-lvds5-sditf { 69 compatible = "rockchip,rkcif-sditf"; 70 rockchip,cif = <&rkcif_mipi_lvds5>; 71 status = "disabled"; 72 }; 73 74 rkcif_mipi_lvds5_sditf_vir1: rkcif-mipi-lvds5-sditf-vir1 { 75 compatible = "rockchip,rkcif-sditf"; 76 rockchip,cif = <&rkcif_mipi_lvds5>; 77 status = "disabled"; 78 }; 79 80 rkcif_mipi_lvds5_sditf_vir2: rkcif-mipi-lvds5-sditf-vir2 { 81 compatible = "rockchip,rkcif-sditf"; 82 rockchip,cif = <&rkcif_mipi_lvds5>; 83 status = "disabled"; 84 }; 85 86 rkcif_mipi_lvds5_sditf_vir3: rkcif-mipi-lvds5-sditf-vir3 { 87 compatible = "rockchip,rkcif-sditf"; 88 rockchip,cif = <&rkcif_mipi_lvds5>; 89 status = "disabled"; 90 }; 91 92 usbdrd3_1: usbdrd3_1 { 93 compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3"; 94 clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>, 95 <&cru ACLK_USB3OTG1>; 96 clock-names = "ref", "suspend", "bus"; 97 #address-cells = <2>; 98 #size-cells = <2>; 99 ranges; 100 status = "disabled"; 101 102 usbdrd_dwc3_1: usb@fc400000 { 103 compatible = "snps,dwc3"; 104 reg = <0x0 0xfc400000 0x0 0x400000>; 105 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 106 power-domains = <&power RK3588_PD_USB>; 107 resets = <&cru SRST_A_USB3OTG1>; 108 reset-names = "usb3-otg"; 109 dr_mode = "host"; 110 phys = <&u2phy1_otg>, <&usbdp_phy1_u3>; 111 phy-names = "usb2-phy", "usb3-phy"; 112 phy_type = "utmi_wide"; 113 snps,dis_enblslpm_quirk; 114 snps,dis-u1-entry-quirk; 115 snps,dis-u2-entry-quirk; 116 snps,dis-u2-freeclk-exists-quirk; 117 snps,dis-del-phy-power-chg-quirk; 118 snps,dis-tx-ipgap-linecheck-quirk; 119 snps,parkmode-disable-ss-quirk; 120 status = "disabled"; 121 }; 122 }; 123 124 pcie30_phy_grf: syscon@fd5b8000 { 125 compatible = "rockchip,pcie30-phy-grf", "syscon"; 126 reg = <0x0 0xfd5b8000 0x0 0x10000>; 127 }; 128 129 pipe_phy1_grf: syscon@fd5c0000 { 130 compatible = "rockchip,pipe-phy-grf", "syscon"; 131 reg = <0x0 0xfd5c0000 0x0 0x100>; 132 }; 133 134 usbdpphy1_grf: syscon@fd5cc000 { 135 compatible = "rockchip,rk3588-usbdpphy-grf", "syscon"; 136 reg = <0x0 0xfd5cc000 0x0 0x4000>; 137 }; 138 139 usb2phy1_grf: syscon@fd5d4000 { 140 compatible = "rockchip,rk3588-usb2phy-grf", "syscon", 141 "simple-mfd"; 142 reg = <0x0 0xfd5d4000 0x0 0x4000>; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 146 u2phy1: usb2-phy@4000 { 147 compatible = "rockchip,rk3588-usb2phy"; 148 reg = <0x4000 0x10>; 149 interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>; 150 resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>; 151 reset-names = "phy", "apb"; 152 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>; 153 clock-names = "phyclk"; 154 clock-output-names = "usb480m_phy1"; 155 #clock-cells = <0>; 156 rockchip,usbctrl-grf = <&usb_grf>; 157 status = "disabled"; 158 159 u2phy1_otg: otg-port { 160 #phy-cells = <0>; 161 status = "disabled"; 162 }; 163 }; 164 }; 165 166 hdptxphy1_grf: syscon@fd5e4000 { 167 compatible = "rockchip,rk3588-hdptxphy-grf", "syscon"; 168 reg = <0x0 0xfd5e4000 0x0 0x100>; 169 }; 170 171 spdif_tx5: spdif-tx@fddb8000 { 172 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 173 reg = <0x0 0xfddb8000 0x0 0x1000>; 174 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 175 dmas = <&dmac1 22>; 176 dma-names = "tx"; 177 clock-names = "mclk", "hclk"; 178 clocks = <&cru MCLK_SPDIF5>, <&cru HCLK_SPDIF5_DP1>; 179 assigned-clocks = <&cru CLK_SPDIF5_DP1_SRC>; 180 assigned-clock-parents = <&cru PLL_AUPLL>; 181 power-domains = <&power RK3588_PD_VO0>; 182 #sound-dai-cells = <0>; 183 status = "disabled"; 184 }; 185 186 i2s8_8ch: i2s@fddc8000 { 187 compatible = "rockchip,rk3588-i2s-tdm"; 188 reg = <0x0 0xfddc8000 0x0 0x1000>; 189 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 190 clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>; 191 clock-names = "mclk_tx", "hclk"; 192 assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>; 193 assigned-clock-parents = <&cru PLL_AUPLL>; 194 dmas = <&dmac2 22>; 195 dma-names = "tx"; 196 power-domains = <&power RK3588_PD_VO0>; 197 resets = <&cru SRST_M_I2S8_8CH_TX>; 198 reset-names = "tx-m"; 199 rockchip,playback-only; 200 #sound-dai-cells = <0>; 201 status = "disabled"; 202 }; 203 204 spdif_tx4: spdif-tx@fdde8000 { 205 compatible = "rockchip,rk3588-spdif", "rockchip,rk3568-spdif"; 206 reg = <0x0 0xfdde8000 0x0 0x1000>; 207 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 208 dmas = <&dmac1 8>; 209 dma-names = "tx"; 210 clock-names = "mclk", "hclk"; 211 clocks = <&cru MCLK_SPDIF4>, <&cru HCLK_SPDIF4>; 212 assigned-clocks = <&cru CLK_SPDIF4_SRC>; 213 assigned-clock-parents = <&cru PLL_AUPLL>; 214 power-domains = <&power RK3588_PD_VO1>; 215 #sound-dai-cells = <0>; 216 status = "disabled"; 217 }; 218 219 i2s6_8ch: i2s@fddf4000 { 220 compatible = "rockchip,rk3588-i2s-tdm"; 221 reg = <0x0 0xfddf4000 0x0 0x1000>; 222 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>; 224 clock-names = "mclk_tx", "mclk_rx", "hclk"; 225 assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>; 226 assigned-clock-parents = <&cru PLL_GPLL>; 227 dmas = <&dmac2 4>; 228 dma-names = "tx"; 229 power-domains = <&power RK3588_PD_VO1>; 230 resets = <&cru SRST_M_I2S6_8CH_TX>; 231 reset-names = "tx-m"; 232 rockchip,always-on; 233 rockchip,hdmi-path; 234 rockchip,playback-only; 235 #sound-dai-cells = <0>; 236 status = "disabled"; 237 }; 238 239 i2s7_8ch: i2s@fddf8000 { 240 compatible = "rockchip,rk3588-i2s-tdm"; 241 reg = <0x0 0xfddf8000 0x0 0x1000>; 242 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>; 244 clock-names = "mclk_tx", "mclk_rx", "hclk"; 245 assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>; 246 assigned-clock-parents = <&cru PLL_AUPLL>; 247 dmas = <&dmac2 21>; 248 dma-names = "rx"; 249 power-domains = <&power RK3588_PD_VO1>; 250 resets = <&cru SRST_M_I2S7_8CH_RX>; 251 reset-names = "rx-m"; 252 rockchip,capture-only; 253 #sound-dai-cells = <0>; 254 status = "disabled"; 255 }; 256 257 i2s10_8ch: i2s@fde00000 { 258 compatible = "rockchip,rk3588-i2s-tdm"; 259 reg = <0x0 0xfde00000 0x0 0x1000>; 260 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 261 clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>; 262 clock-names = "mclk_tx", "mclk_rx", "hclk"; 263 assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>; 264 assigned-clock-parents = <&cru PLL_AUPLL>; 265 dmas = <&dmac2 24>; 266 dma-names = "rx"; 267 power-domains = <&power RK3588_PD_VO1>; 268 resets = <&cru SRST_M_I2S10_8CH_RX>; 269 reset-names = "rx-m"; 270 rockchip,capture-only; 271 #sound-dai-cells = <0>; 272 status = "disabled"; 273 }; 274 275 spdif_rx1: spdif-rx@fde10000 { 276 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 277 reg = <0x0 0xfde10000 0x0 0x1000>; 278 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&cru MCLK_SPDIFRX1>, <&cru HCLK_SPDIFRX1>; 280 clock-names = "mclk", "hclk"; 281 assigned-clocks = <&cru MCLK_SPDIFRX1>; 282 assigned-clock-parents = <&cru PLL_AUPLL>; 283 dmas = <&dmac0 22>; 284 dma-names = "rx"; 285 power-domains = <&power RK3588_PD_VO1>; 286 resets = <&cru SRST_M_SPDIFRX1>; 287 reset-names = "spdifrx-m"; 288 #sound-dai-cells = <0>; 289 status = "disabled"; 290 }; 291 292 spdif_rx2: spdif-rx@fde18000 { 293 compatible = "rockchip,rk3588-spdifrx", "rockchip,rk3308-spdifrx"; 294 reg = <0x0 0xfde18000 0x0 0x1000>; 295 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 296 clocks = <&cru MCLK_SPDIFRX2>, <&cru HCLK_SPDIFRX2>; 297 clock-names = "mclk", "hclk"; 298 assigned-clocks = <&cru MCLK_SPDIFRX2>; 299 assigned-clock-parents = <&cru PLL_AUPLL>; 300 dmas = <&dmac0 23>; 301 dma-names = "rx"; 302 power-domains = <&power RK3588_PD_VO1>; 303 resets = <&cru SRST_M_SPDIFRX2>; 304 reset-names = "spdifrx-m"; 305 #sound-dai-cells = <0>; 306 status = "disabled"; 307 }; 308 309 dp1: dp@fde60000 { 310 compatible = "rockchip,rk3588-dp"; 311 reg = <0x0 0xfde60000 0x0 0x4000>; 312 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 313 clocks = <&cru PCLK_DP1>, <&cru CLK_AUX16M_1>, 314 <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_SPDIF5_DP1>, 315 <&hclk_vo0>, <&cru CLK_DP1>; 316 clock-names = "apb", "aux", "i2s", "spdif", "hclk", "hdcp"; 317 assigned-clocks = <&cru CLK_AUX16M_1>; 318 assigned-clock-rates = <16000000>; 319 resets = <&cru SRST_DP1>; 320 phys = <&usbdp_phy1_dp>; 321 power-domains = <&power RK3588_PD_VO0>; 322 #sound-dai-cells = <1>; 323 status = "disabled"; 324 325 ports { 326 #address-cells = <1>; 327 #size-cells = <0>; 328 329 port@0 { 330 reg = <0>; 331 #address-cells = <1>; 332 #size-cells = <0>; 333 334 dp1_in_vp0: endpoint@0 { 335 reg = <0>; 336 remote-endpoint = <&vp0_out_dp1>; 337 status = "disabled"; 338 }; 339 340 dp1_in_vp1: endpoint@1 { 341 reg = <1>; 342 remote-endpoint = <&vp1_out_dp1>; 343 status = "disabled"; 344 }; 345 346 dp1_in_vp2: endpoint@2 { 347 reg = <2>; 348 remote-endpoint = <&vp2_out_dp1>; 349 status = "disabled"; 350 }; 351 }; 352 353 port@1 { 354 reg = <1>; 355 356 dp1_out: endpoint { }; 357 }; 358 }; 359 }; 360 361 hdmi1: hdmi@fdea0000 { 362 compatible = "rockchip,rk3588-dw-hdmi"; 363 reg = <0x0 0xfdea0000 0x0 0x20000>; 364 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 367 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 368 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&cru PCLK_HDMITX1>, 370 <&cru CLK_HDMIHDP1>, 371 <&cru CLK_HDMITX1_EARC>, 372 <&cru CLK_HDMITX1_REF>, 373 <&cru MCLK_I2S6_8CH_TX>, 374 <&cru DCLK_VOP0>, 375 <&cru DCLK_VOP1>, 376 <&cru DCLK_VOP2>, 377 <&cru DCLK_VOP3>, 378 <&hclk_vo1>, 379 <&hdptxphy_hdmi_clk1>; 380 clock-names = "pclk", 381 "hpd", 382 "earc", 383 "hdmitx_ref", 384 "aud", 385 "dclk_vp0", 386 "dclk_vp1", 387 "dclk_vp2", 388 "dclk_vp3", 389 "hclk_vo1", 390 "link_clk"; 391 resets = <&cru SRST_HDMITX1_REF>, <&cru SRST_HDMIHDP1>; 392 reset-names = "ref", "hdp"; 393 power-domains = <&power RK3588_PD_VO1>; 394 pinctrl-names = "default"; 395 pinctrl-0 = <&hdmim2_tx1_cec &hdmim0_tx1_hpd &hdmim1_tx1_scl &hdmim1_tx1_sda>; 396 reg-io-width = <4>; 397 rockchip,grf = <&sys_grf>; 398 rockchip,vo1_grf = <&vo1_grf>; 399 phys = <&hdptxphy_hdmi1>; 400 phy-names = "hdmi"; 401 #sound-dai-cells = <0>; 402 status = "disabled"; 403 404 ports { 405 #address-cells = <1>; 406 #size-cells = <0>; 407 408 hdmi1_in: port@0 { 409 reg = <0>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 413 hdmi1_in_vp0: endpoint@0 { 414 reg = <0>; 415 remote-endpoint = <&vp0_out_hdmi1>; 416 status = "disabled"; 417 }; 418 419 hdmi1_in_vp1: endpoint@1 { 420 reg = <1>; 421 remote-endpoint = <&vp1_out_hdmi1>; 422 status = "disabled"; 423 }; 424 425 hdmi1_in_vp2: endpoint@2 { 426 reg = <2>; 427 remote-endpoint = <&vp2_out_hdmi1>; 428 status = "disabled"; 429 }; 430 }; 431 }; 432 }; 433 434 edp1: edp@fded0000 { 435 compatible = "rockchip,rk3588-edp"; 436 reg = <0x0 0xfded0000 0x0 0x1000>; 437 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cru CLK_EDP1_24M>, <&cru PCLK_EDP1>, 439 <&cru CLK_EDP1_200M>, <&hclk_vo1>; 440 clock-names = "dp", "pclk", "spdif", "hclk"; 441 resets = <&cru SRST_EDP1_24M>, <&cru SRST_P_EDP1>; 442 reset-names = "dp", "apb"; 443 phys = <&hdptxphy1>; 444 phy-names = "dp"; 445 power-domains = <&power RK3588_PD_VO1>; 446 rockchip,grf = <&vo1_grf>; 447 status = "disabled"; 448 449 ports { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 453 port@0 { 454 reg = <0>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 458 edp1_in_vp0: endpoint@0 { 459 reg = <0>; 460 remote-endpoint = <&vp0_out_edp1>; 461 status = "disabled"; 462 }; 463 464 edp1_in_vp1: endpoint@1 { 465 reg = <1>; 466 remote-endpoint = <&vp1_out_edp1>; 467 status = "disabled"; 468 }; 469 470 edp1_in_vp2: endpoint@2 { 471 reg = <2>; 472 remote-endpoint = <&vp2_out_edp1>; 473 status = "disabled"; 474 }; 475 }; 476 477 port@1 { 478 reg = <1>; 479 480 edp1_out: endpoint { }; 481 }; 482 }; 483 }; 484 485 hdmirx_ctrler: hdmirx-controller@fdee0000 { 486 compatible = "rockchip,rk3588-hdmirx-ctrler", "rockchip,hdmirx-ctrler"; 487 reg = <0x0 0xfdee0000 0x0 0x6000>; 488 reg-names = "hdmirx_regs"; 489 power-domains = <&power RK3588_PD_VO1>; 490 rockchip,grf = <&sys_grf>; 491 rockchip,vo1_grf = <&vo1_grf>; 492 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 495 interrupt-names = "cec", "hdmi", "dma"; 496 clocks = <&cru ACLK_HDMIRX>, 497 <&cru CLK_HDMIRX_AUD>, 498 <&cru CLK_CR_PARA>, 499 <&cru PCLK_HDMIRX>, 500 <&cru CLK_HDMIRX_REF>, 501 <&cru PCLK_S_HDMIRX>, 502 <&hclk_vo1>; 503 clock-names = "aclk", 504 "audio", 505 "cr_para", 506 "pclk", 507 "ref", 508 "hclk_s_hdmirx", 509 "hclk_vo1"; 510 resets = <&cru SRST_A_HDMIRX>, <&cru SRST_P_HDMIRX>, 511 <&cru SRST_HDMIRX_REF>, <&cru SRST_A_HDMIRX_BIU>; 512 reset-names = "rst_a", "rst_p", "rst_ref", "rst_biu"; 513 pinctrl-0 = <&hdmim1_rx>; 514 pinctrl-names = "default"; 515 status = "disabled"; 516 }; 517 518 pcie3x4: pcie@fe150000 { 519 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 520 #address-cells = <3>; 521 #size-cells = <2>; 522 bus-range = <0x00 0x0f>; 523 clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>, 524 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>, 525 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>; 526 clock-names = "aclk_mst", "aclk_slv", 527 "aclk_dbi", "pclk", 528 "aux", "pipe"; 529 device_type = "pci"; 530 interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 533 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 534 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>; 535 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 536 #interrupt-cells = <1>; 537 interrupt-map-mask = <0 0 0 7>; 538 interrupt-map = <0 0 0 1 &pcie3x4_intc 0>, 539 <0 0 0 2 &pcie3x4_intc 1>, 540 <0 0 0 3 &pcie3x4_intc 2>, 541 <0 0 0 4 &pcie3x4_intc 3>; 542 linux,pci-domain = <0>; 543 num-ib-windows = <16>; 544 num-ob-windows = <16>; 545 num-viewport = <8>; 546 max-link-speed = <3>; 547 msi-map = <0x0000 &its1 0x0000 0x1000>; 548 num-lanes = <4>; 549 phys = <&pcie30phy>; 550 phy-names = "pcie-phy"; 551 power-domains = <&power RK3588_PD_PCIE>; 552 ranges = <0x00000800 0x0 0xf0000000 0x0 0xf0000000 0x0 0x100000 553 0x81000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x100000 554 0x82000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0xe00000 555 0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; 556 reg = <0x0 0xfe150000 0x0 0x10000>, 557 <0xa 0x40000000 0x0 0x400000>; 558 reg-names = "pcie-apb", "pcie-dbi"; 559 resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>; 560 reset-names = "pcie", "periph"; 561 rockchip,pipe-grf = <&php_grf>; 562 status = "disabled"; 563 564 pcie3x4_intc: legacy-interrupt-controller { 565 interrupt-controller; 566 #address-cells = <0>; 567 #interrupt-cells = <1>; 568 interrupt-parent = <&gic>; 569 interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING>; 570 }; 571 }; 572 573 pcie3x2: pcie@fe160000 { 574 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 575 #address-cells = <3>; 576 #size-cells = <2>; 577 bus-range = <0x10 0x1f>; 578 clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>, 579 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>, 580 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>; 581 clock-names = "aclk_mst", "aclk_slv", 582 "aclk_dbi", "pclk", 583 "aux", "pipe"; 584 device_type = "pci"; 585 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 590 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 591 #interrupt-cells = <1>; 592 interrupt-map-mask = <0 0 0 7>; 593 interrupt-map = <0 0 0 1 &pcie3x2_intc 0>, 594 <0 0 0 2 &pcie3x2_intc 1>, 595 <0 0 0 3 &pcie3x2_intc 2>, 596 <0 0 0 4 &pcie3x2_intc 3>; 597 linux,pci-domain = <1>; 598 num-ib-windows = <16>; 599 num-ob-windows = <16>; 600 num-viewport = <8>; 601 max-link-speed = <3>; 602 msi-map = <0x1000 &its1 0x1000 0x1000>; 603 num-lanes = <2>; 604 phys = <&pcie30phy>; 605 phy-names = "pcie-phy"; 606 power-domains = <&power RK3588_PD_PCIE>; 607 ranges = <0x00000800 0x0 0xf1000000 0x0 0xf1000000 0x0 0x100000 608 0x81000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x100000 609 0x82000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0xe00000 610 0xc3000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>; 611 reg = <0x0 0xfe160000 0x0 0x10000>, 612 <0xa 0x40400000 0x0 0x400000>; 613 reg-names = "pcie-apb", "pcie-dbi"; 614 resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>; 615 reset-names = "pcie", "periph"; 616 rockchip,pipe-grf = <&php_grf>; 617 status = "disabled"; 618 619 pcie3x2_intc: legacy-interrupt-controller { 620 interrupt-controller; 621 #address-cells = <0>; 622 #interrupt-cells = <1>; 623 interrupt-parent = <&gic>; 624 interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING>; 625 }; 626 }; 627 628 pcie2x1l0: pcie@fe170000 { 629 compatible = "rockchip,rk3588-pcie", "snps,dw-pcie"; 630 #address-cells = <3>; 631 #size-cells = <2>; 632 bus-range = <0x20 0x2f>; 633 clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>, 634 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>, 635 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>; 636 clock-names = "aclk_mst", "aclk_slv", 637 "aclk_dbi", "pclk", 638 "aux", "pipe"; 639 device_type = "pci"; 640 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 645 interrupt-names = "sys", "pmc", "msg", "legacy", "err"; 646 #interrupt-cells = <1>; 647 interrupt-map-mask = <0 0 0 7>; 648 interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>, 649 <0 0 0 2 &pcie2x1l0_intc 1>, 650 <0 0 0 3 &pcie2x1l0_intc 2>, 651 <0 0 0 4 &pcie2x1l0_intc 3>; 652 linux,pci-domain = <2>; 653 num-ib-windows = <8>; 654 num-ob-windows = <8>; 655 num-viewport = <4>; 656 max-link-speed = <2>; 657 msi-map = <0x2000 &its0 0x2000 0x1000>; 658 num-lanes = <1>; 659 phys = <&combphy1_ps PHY_TYPE_PCIE>; 660 phy-names = "pcie-phy"; 661 ranges = <0x00000800 0x0 0xf2000000 0x0 0xf2000000 0x0 0x100000 662 0x81000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x100000 663 0x82000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0xe00000 664 0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; 665 reg = <0x0 0xfe170000 0x0 0x10000>, 666 <0xa 0x40800000 0x0 0x400000>; 667 reg-names = "pcie-apb", "pcie-dbi"; 668 resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>; 669 reset-names = "pcie", "periph"; 670 rockchip,pipe-grf = <&php_grf>; 671 status = "disabled"; 672 673 pcie2x1l0_intc: legacy-interrupt-controller { 674 interrupt-controller; 675 #address-cells = <0>; 676 #interrupt-cells = <1>; 677 interrupt-parent = <&gic>; 678 interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING>; 679 }; 680 }; 681 682 gmac_uio0: uio@fe1b0000 { 683 compatible = "rockchip,uio-gmac"; 684 reg = <0x0 0xfe1b0000 0x0 0x10000>; 685 rockchip,ethernet = <&gmac0>; 686 status = "disabled"; 687 }; 688 689 gmac0: ethernet@fe1b0000 { 690 compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a"; 691 reg = <0x0 0xfe1b0000 0x0 0x10000>; 692 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 694 interrupt-names = "macirq", "eth_wake_irq"; 695 rockchip,grf = <&sys_grf>; 696 rockchip,php_grf = <&php_grf>; 697 clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>, 698 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>, 699 <&cru CLK_GMAC0_PTP_REF>; 700 clock-names = "stmmaceth", "clk_mac_ref", 701 "pclk_mac", "aclk_mac", 702 "ptp_ref"; 703 resets = <&cru SRST_A_GMAC0>; 704 reset-names = "stmmaceth"; 705 power-domains = <&power RK3588_PD_GMAC>; 706 707 snps,mixed-burst; 708 snps,tso; 709 710 snps,axi-config = <&gmac0_stmmac_axi_setup>; 711 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 712 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 713 status = "disabled"; 714 715 mdio0: mdio { 716 compatible = "snps,dwmac-mdio"; 717 #address-cells = <0x1>; 718 #size-cells = <0x0>; 719 }; 720 721 gmac0_stmmac_axi_setup: stmmac-axi-config { 722 snps,wr_osr_lmt = <4>; 723 snps,rd_osr_lmt = <8>; 724 snps,blen = <0 0 0 0 16 8 4>; 725 }; 726 727 gmac0_mtl_rx_setup: rx-queues-config { 728 snps,rx-queues-to-use = <1>; 729 queue0 {}; 730 }; 731 732 gmac0_mtl_tx_setup: tx-queues-config { 733 snps,tx-queues-to-use = <1>; 734 queue0 {}; 735 }; 736 }; 737 738 sata1: sata@fe220000 { 739 compatible = "rockchip,rk-ahci", "snps,dwc-ahci"; 740 reg = <0 0xfe220000 0 0x1000>; 741 clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>, 742 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>, 743 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>; 744 clock-names = "sata", "pmalive", "rxoob", "ref", "asic"; 745 interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>; 746 interrupt-names = "hostc"; 747 phys = <&combphy1_ps PHY_TYPE_SATA>; 748 phy-names = "sata-phy"; 749 ports-implemented = <0x1>; 750 status = "disabled"; 751 }; 752 753 hdptxphy1: phy@fed70000 { 754 compatible = "rockchip,rk3588-hdptx-phy"; 755 reg = <0x0 0xfed70000 0x0 0x2000>; 756 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; 757 clock-names = "ref", "apb"; 758 resets = <&cru SRST_P_HDPTX1>, <&cru SRST_HDPTX1_INIT>, 759 <&cru SRST_HDPTX1_CMN>, <&cru SRST_HDPTX1_LANE>; 760 reset-names = "apb", "init", "cmn", "lane"; 761 rockchip,grf = <&hdptxphy1_grf>; 762 #phy-cells = <0>; 763 status = "disabled"; 764 }; 765 766 hdptxphy_hdmi1: hdmiphy@fed70000 { 767 compatible = "rockchip,rk3588-hdptx-phy-hdmi"; 768 reg = <0x0 0xfed70000 0x0 0x2000>; 769 clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; 770 clock-names = "ref", "apb"; 771 resets = <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, 772 <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, 773 <&cru SRST_HDPTX1_LANE>, <&cru SRST_HDPTX1_ROPLL>, 774 <&cru SRST_HDPTX1_LCPLL>; 775 reset-names = "phy", "apb", "init", "cmn", "lane", "ropll", 776 "lcpll"; 777 rockchip,grf = <&hdptxphy1_grf>; 778 #phy-cells = <0>; 779 status = "disabled"; 780 781 hdptxphy_hdmi_clk1: clk-port { 782 #clock-cells = <0>; 783 status = "okay"; 784 }; 785 }; 786 787 788 usbdp_phy1: phy@fed90000 { 789 compatible = "rockchip,rk3588-usbdp-phy"; 790 reg = <0x0 0xfed90000 0x0 0x10000>; 791 rockchip,u2phy-grf = <&usb2phy1_grf>; 792 rockchip,usb-grf = <&usb_grf>; 793 rockchip,usbdpphy-grf = <&usbdpphy1_grf>; 794 rockchip,vo-grf = <&vo0_grf>; 795 clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>, 796 <&cru CLK_USBDP_PHY1_IMMORTAL>, 797 <&cru PCLK_USBDPPHY1>, 798 <&u2phy1>; 799 clock-names = "refclk", "immortal", "pclk", "utmi"; 800 resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>, 801 <&cru SRST_USBDP_COMBO_PHY1_CMN>, 802 <&cru SRST_USBDP_COMBO_PHY1_LANE>, 803 <&cru SRST_USBDP_COMBO_PHY1_PCS>, 804 <&cru SRST_P_USBDPPHY1>; 805 reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb"; 806 status = "disabled"; 807 808 usbdp_phy1_dp: dp-port { 809 #phy-cells = <0>; 810 status = "disabled"; 811 }; 812 813 usbdp_phy1_u3: u3-port { 814 #phy-cells = <0>; 815 status = "disabled"; 816 }; 817 }; 818 819 combphy1_ps: phy@fee10000 { 820 compatible = "rockchip,rk3588-naneng-combphy"; 821 reg = <0x0 0xfee10000 0x0 0x100>; 822 #phy-cells = <1>; 823 clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>, 824 <&cru PCLK_PHP_ROOT>; 825 clock-names = "refclk", "apbclk", "phpclk"; 826 assigned-clocks = <&cru CLK_REF_PIPE_PHY1>; 827 assigned-clock-rates = <100000000>; 828 resets = <&cru SRST_P_PCIE2_PHY1>, <&cru SRST_REF_PIPE_PHY1>; 829 reset-names = "combphy-apb", "combphy"; 830 rockchip,pipe-grf = <&php_grf>; 831 rockchip,pipe-phy-grf = <&pipe_phy1_grf>; 832 rockchip,pcie1ln-sel-bits = <0x100 0 0 0>; 833 status = "disabled"; 834 }; 835 836 pcie30phy: phy@fee80000 { 837 compatible = "rockchip,rk3588-pcie3-phy"; 838 reg = <0x0 0xfee80000 0x0 0x20000>; 839 #phy-cells = <0>; 840 clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>; 841 clock-names = "pclk"; 842 resets = <&cru SRST_PCIE30_PHY>; 843 reset-names = "phy"; 844 rockchip,pipe-grf = <&php_grf>; 845 rockchip,phy-grf = <&pcie30_phy_grf>; 846 status = "disabled"; 847 }; 848 849}; 850 851&display_subsystem { 852 route { 853 route_dp1: route-dp1 { 854 status = "disabled"; 855 logo,uboot = "logo.bmp"; 856 logo,kernel = "logo_kernel.bmp"; 857 logo,mode = "center"; 858 charge_logo,mode = "center"; 859 connect = <&vp1_out_dp1>; 860 }; 861 862 route_hdmi1: route-hdmi1 { 863 status = "disabled"; 864 logo,uboot = "logo.bmp"; 865 logo,kernel = "logo_kernel.bmp"; 866 logo,mode = "center"; 867 charge_logo,mode = "center"; 868 connect = <&vp1_out_hdmi1>; 869 }; 870 }; 871}; 872 873&vp0 { 874 vp0_out_dp1: endpoint@3 { 875 reg = <3>; 876 remote-endpoint = <&dp1_in_vp0>; 877 }; 878 879 vp0_out_edp1: endpoint@4 { 880 reg = <4>; 881 remote-endpoint = <&edp1_in_vp0>; 882 }; 883 884 vp0_out_hdmi1: endpoint@5 { 885 reg = <5>; 886 remote-endpoint = <&hdmi1_in_vp0>; 887 }; 888}; 889 890&vp1 { 891 vp1_out_dp1: endpoint@3 { 892 reg = <3>; 893 remote-endpoint = <&dp1_in_vp1>; 894 }; 895 896 vp1_out_edp1: endpoint@4 { 897 reg = <4>; 898 remote-endpoint = <&edp1_in_vp1>; 899 }; 900 901 vp1_out_hdmi1: endpoint@5 { 902 reg = <5>; 903 remote-endpoint = <&hdmi1_in_vp1>; 904 }; 905}; 906 907&vp2 { 908 vp2_out_dp1: endpoint@5 { 909 reg = <5>; 910 remote-endpoint = <&dp1_in_vp2>; 911 }; 912 913 vp2_out_edp1: endpoint@6 { 914 reg = <6>; 915 remote-endpoint = <&edp1_in_vp2>; 916 }; 917 918 vp2_out_hdmi1: endpoint@7 { 919 reg = <7>; 920 remote-endpoint = <&hdmi1_in_vp2>; 921 }; 922}; 923
