1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/ { 8*4882a593Smuzhiyun dummy_codec: dummy-codec { 9*4882a593Smuzhiyun compatible = "rockchip,dummy-codec"; 10*4882a593Smuzhiyun #sound-dai-cells = <0>; 11*4882a593Smuzhiyun status = "okay"; 12*4882a593Smuzhiyun }; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun sound0 { 15*4882a593Smuzhiyun compatible = "simple-audio-card"; 16*4882a593Smuzhiyun simple-audio-card,name = "rockchip,tdm"; 17*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 18*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 19*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&codec_master>; 20*4882a593Smuzhiyun simple-audio-card,frame-master = <&codec_master>; 21*4882a593Smuzhiyun status = "okay"; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun simple-audio-card,cpu { 24*4882a593Smuzhiyun sound-dai = <&i2s1_8ch>; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun codec_master: simple-audio-card,codec { 27*4882a593Smuzhiyun sound-dai = <&dummy_codec>; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun }; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun bt_codec: bt-codec { 32*4882a593Smuzhiyun compatible = "delta,dfbmcs320"; 33*4882a593Smuzhiyun #sound-dai-cells = <1>; 34*4882a593Smuzhiyun status = "okay"; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun sound1 { 38*4882a593Smuzhiyun compatible = "simple-audio-card"; 39*4882a593Smuzhiyun simple-audio-card,name = "rockchip,bt"; 40*4882a593Smuzhiyun simple-audio-card,format = "dsp_a"; 41*4882a593Smuzhiyun simple-audio-card,bitclock-inversion = <1>; 42*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 43*4882a593Smuzhiyun simple-audio-card,cpu { 44*4882a593Smuzhiyun sound-dai = <&i2s3_2ch>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun simple-audio-card,codec { 47*4882a593Smuzhiyun sound-dai = <&bt_codec 1>; 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun}; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun&i2s1_8ch { 53*4882a593Smuzhiyun pinctrl-0 = <&i2s1m0_lrck 54*4882a593Smuzhiyun &i2s1m0_sclk 55*4882a593Smuzhiyun &i2s1m0_sdi0 56*4882a593Smuzhiyun &i2s1m0_sdi1 57*4882a593Smuzhiyun &i2s1m0_sdo0 58*4882a593Smuzhiyun &i2s1m0_sdo1 59*4882a593Smuzhiyun &i2s1m0_sdo2>; 60*4882a593Smuzhiyun i2s-lrck-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 61*4882a593Smuzhiyun tdm-fsync-gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>; 62*4882a593Smuzhiyun rockchip,tdm-multi-lanes; 63*4882a593Smuzhiyun rockchip,tx-lanes = <3>; 64*4882a593Smuzhiyun rockchip,rx-lanes = <2>; 65*4882a593Smuzhiyun rockchip,clk-trcm = <1>; 66*4882a593Smuzhiyun status = "okay"; 67*4882a593Smuzhiyun}; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun&i2s3_2ch { 70*4882a593Smuzhiyun assigned-clocks = <&cru CLK_I2S3_2CH>; 71*4882a593Smuzhiyun assigned-clock-parents = <&mclkin_i2s3>; 72*4882a593Smuzhiyun pinctrl-0 = <&i2s3_sdi 73*4882a593Smuzhiyun &i2s3_sdo 74*4882a593Smuzhiyun &i2s3_mclk>; 75*4882a593Smuzhiyun status = "okay"; 76*4882a593Smuzhiyun}; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun&mclkin_i2s3 { 79*4882a593Smuzhiyun clock-frequency = <12288000>; 80*4882a593Smuzhiyun}; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun&spi3 { 83*4882a593Smuzhiyun status = "okay"; 84*4882a593Smuzhiyun assigned-clocks = <&cru CLK_SPI3>; 85*4882a593Smuzhiyun assigned-clock-rates = <200000000>; 86*4882a593Smuzhiyun num-cs = <2>; 87*4882a593Smuzhiyun pinctrl-0 = <&spi3m2_cs0 88*4882a593Smuzhiyun &spi3m2_cs1 89*4882a593Smuzhiyun &spi3m2_pins>; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun flash: is25lp032@1 { 92*4882a593Smuzhiyun compatible = "issi,is25lp032", "jedec,spi-nor"; 93*4882a593Smuzhiyun reg = <1>; 94*4882a593Smuzhiyun #address-cells = <1>; 95*4882a593Smuzhiyun #size-cells = <1>; 96*4882a593Smuzhiyun spi-max-frequency = <5000000>; 97*4882a593Smuzhiyun m25p,fast-read; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun}; 100