1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4 *
5 */
6
7/ {
8	dummy_codec: dummy-codec {
9		compatible = "rockchip,dummy-codec";
10		#sound-dai-cells = <0>;
11		status = "okay";
12	};
13
14	sound0 {
15		compatible = "simple-audio-card";
16		simple-audio-card,name = "rockchip,tdm";
17		simple-audio-card,format = "i2s";
18		simple-audio-card,mclk-fs = <256>;
19		simple-audio-card,bitclock-master = <&codec_master>;
20		simple-audio-card,frame-master = <&codec_master>;
21		status = "okay";
22
23		simple-audio-card,cpu {
24			sound-dai = <&i2s1_8ch>;
25		};
26		codec_master: simple-audio-card,codec {
27			sound-dai = <&dummy_codec>;
28		};
29	};
30
31	bt_codec: bt-codec {
32		compatible = "delta,dfbmcs320";
33		#sound-dai-cells = <1>;
34		status = "okay";
35	};
36
37	sound1 {
38		compatible = "simple-audio-card";
39		simple-audio-card,name = "rockchip,bt";
40		simple-audio-card,format = "dsp_a";
41		simple-audio-card,bitclock-inversion = <1>;
42		simple-audio-card,mclk-fs = <256>;
43		simple-audio-card,cpu {
44			sound-dai = <&i2s3_2ch>;
45		};
46		simple-audio-card,codec {
47			sound-dai = <&bt_codec 1>;
48		};
49	};
50};
51
52&i2s1_8ch {
53	pinctrl-0 = <&i2s1m0_lrck
54		     &i2s1m0_sclk
55		     &i2s1m0_sdi0
56		     &i2s1m0_sdi1
57		     &i2s1m0_sdo0
58		     &i2s1m0_sdo1
59		     &i2s1m0_sdo2>;
60	i2s-lrck-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
61	tdm-fsync-gpio = <&gpio4 RK_PA0 GPIO_ACTIVE_HIGH>;
62	rockchip,tdm-multi-lanes;
63	rockchip,tx-lanes = <3>;
64	rockchip,rx-lanes = <2>;
65	rockchip,clk-trcm = <1>;
66	status = "okay";
67};
68
69&i2s3_2ch {
70	assigned-clocks = <&cru CLK_I2S3_2CH>;
71	assigned-clock-parents = <&mclkin_i2s3>;
72	pinctrl-0 = <&i2s3_sdi
73		     &i2s3_sdo
74		     &i2s3_mclk>;
75	status = "okay";
76};
77
78&mclkin_i2s3 {
79	clock-frequency = <12288000>;
80};
81
82&spi3 {
83	status = "okay";
84	assigned-clocks = <&cru CLK_SPI3>;
85	assigned-clock-rates = <200000000>;
86	num-cs = <2>;
87	pinctrl-0 = <&spi3m2_cs0
88		     &spi3m2_cs1
89		     &spi3m2_pins>;
90
91	flash: is25lp032@1 {
92		compatible = "issi,is25lp032", "jedec,spi-nor";
93		reg = <1>;
94		#address-cells = <1>;
95		#size-cells = <1>;
96		spi-max-frequency = <5000000>;
97		m25p,fast-read;
98	};
99};
100