1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/pinctrl/rockchip.h> 7#include "rockchip-pinconf.dtsi" 8 9/* 10 * This file is auto generated by pin2dts tool, please keep these code 11 * by adding changes at end of this file. 12 */ 13&pinctrl { 14 clk32k { 15 /omit-if-no-ref/ 16 clk32k_out1: clk32k-out1 { 17 rockchip,pins = 18 /* clk32k_out1 */ 19 <2 RK_PC5 1 &pcfg_pull_none>; 20 }; 21 22 }; 23 24 eth0 { 25 /omit-if-no-ref/ 26 eth0_pins: eth0-pins { 27 rockchip,pins = 28 /* eth0_refclko_25m */ 29 <2 RK_PC3 1 &pcfg_pull_none>; 30 }; 31 32 }; 33 34 fspi { 35 /omit-if-no-ref/ 36 fspim1_pins: fspim1-pins { 37 rockchip,pins = 38 /* fspi_clk_m1 */ 39 <2 RK_PB3 3 &pcfg_pull_up_drv_level_2>, 40 /* fspi_cs0n_m1 */ 41 <2 RK_PB4 3 &pcfg_pull_up_drv_level_2>, 42 /* fspi_d0_m1 */ 43 <2 RK_PA6 3 &pcfg_pull_up_drv_level_2>, 44 /* fspi_d1_m1 */ 45 <2 RK_PA7 3 &pcfg_pull_up_drv_level_2>, 46 /* fspi_d2_m1 */ 47 <2 RK_PB0 3 &pcfg_pull_up_drv_level_2>, 48 /* fspi_d3_m1 */ 49 <2 RK_PB1 3 &pcfg_pull_up_drv_level_2>; 50 }; 51 52 /omit-if-no-ref/ 53 fspim1_cs1: fspim1-cs1 { 54 rockchip,pins = 55 /* fspi_cs1n_m1 */ 56 <2 RK_PB5 3 &pcfg_pull_up_drv_level_2>; 57 }; 58 }; 59 60 gmac0 { 61 /omit-if-no-ref/ 62 gmac0_miim: gmac0-miim { 63 rockchip,pins = 64 /* gmac0_mdc */ 65 <4 RK_PC4 1 &pcfg_pull_none>, 66 /* gmac0_mdio */ 67 <4 RK_PC5 1 &pcfg_pull_none>; 68 }; 69 70 /omit-if-no-ref/ 71 gmac0_clkinout: gmac0-clkinout { 72 rockchip,pins = 73 /* gmac0_mclkinout */ 74 <4 RK_PC3 1 &pcfg_pull_none>; 75 }; 76 77 /omit-if-no-ref/ 78 gmac0_rx_bus2: gmac0-rx-bus2 { 79 rockchip,pins = 80 /* gmac0_rxd0 */ 81 <2 RK_PC1 1 &pcfg_pull_none>, 82 /* gmac0_rxd1 */ 83 <2 RK_PC2 1 &pcfg_pull_none>, 84 /* gmac0_rxdv_crs */ 85 <4 RK_PC2 1 &pcfg_pull_none>; 86 }; 87 88 /omit-if-no-ref/ 89 gmac0_tx_bus2: gmac0-tx-bus2 { 90 rockchip,pins = 91 /* gmac0_txd0 */ 92 <2 RK_PB6 1 &pcfg_pull_none>, 93 /* gmac0_txd1 */ 94 <2 RK_PB7 1 &pcfg_pull_none>, 95 /* gmac0_txen */ 96 <2 RK_PC0 1 &pcfg_pull_none>; 97 }; 98 99 /omit-if-no-ref/ 100 gmac0_rgmii_clk: gmac0-rgmii-clk { 101 rockchip,pins = 102 /* gmac0_rxclk */ 103 <2 RK_PB0 1 &pcfg_pull_none>, 104 /* gmac0_txclk */ 105 <2 RK_PB3 1 &pcfg_pull_none>; 106 }; 107 108 /omit-if-no-ref/ 109 gmac0_rgmii_bus: gmac0-rgmii-bus { 110 rockchip,pins = 111 /* gmac0_rxd2 */ 112 <2 RK_PA6 1 &pcfg_pull_none>, 113 /* gmac0_rxd3 */ 114 <2 RK_PA7 1 &pcfg_pull_none>, 115 /* gmac0_txd2 */ 116 <2 RK_PB1 1 &pcfg_pull_none>, 117 /* gmac0_txd3 */ 118 <2 RK_PB2 1 &pcfg_pull_none>; 119 }; 120 121 /omit-if-no-ref/ 122 gmac0_ppsclk: gmac0-ppsclk { 123 rockchip,pins = 124 /* gmac0_ppsclk */ 125 <2 RK_PC4 1 &pcfg_pull_none>; 126 }; 127 128 /omit-if-no-ref/ 129 gmac0_ppstring: gmac0-ppstring { 130 rockchip,pins = 131 /* gmac0_ppstring */ 132 <2 RK_PB5 1 &pcfg_pull_none>; 133 }; 134 135 /omit-if-no-ref/ 136 gmac0_ptp_refclk: gmac0-ptp-refclk { 137 rockchip,pins = 138 /* gmac0_ptp_refclk */ 139 <2 RK_PB4 1 &pcfg_pull_none>; 140 }; 141 142 /omit-if-no-ref/ 143 gmac0_txer: gmac0-txer { 144 rockchip,pins = 145 /* gmac0_txer */ 146 <4 RK_PC6 1 &pcfg_pull_none>; 147 }; 148 149 }; 150 151 hdmi { 152 /omit-if-no-ref/ 153 hdmim0_tx1_cec: hdmim0-tx1-cec { 154 rockchip,pins = 155 /* hdmim0_tx1_cec */ 156 <2 RK_PC4 4 &pcfg_pull_none>; 157 }; 158 159 /omit-if-no-ref/ 160 hdmim0_tx1_scl: hdmim0-tx1-scl { 161 rockchip,pins = 162 /* hdmim0_tx1_scl */ 163 <2 RK_PB5 4 &pcfg_pull_none>; 164 }; 165 166 /omit-if-no-ref/ 167 hdmim0_tx1_sda: hdmim0-tx1-sda { 168 rockchip,pins = 169 /* hdmim0_tx1_sda */ 170 <2 RK_PB4 4 &pcfg_pull_none>; 171 }; 172 }; 173 174 i2c0 { 175 /omit-if-no-ref/ 176 i2c0m1_xfer: i2c0m1-xfer { 177 rockchip,pins = 178 /* i2c0_scl_m1 */ 179 <4 RK_PC5 9 &pcfg_pull_none_smt>, 180 /* i2c0_sda_m1 */ 181 <4 RK_PC6 9 &pcfg_pull_none_smt>; 182 }; 183 }; 184 185 i2c2 { 186 /omit-if-no-ref/ 187 i2c2m1_xfer: i2c2m1-xfer { 188 rockchip,pins = 189 /* i2c2_scl_m1 */ 190 <2 RK_PC1 9 &pcfg_pull_none_smt>, 191 /* i2c2_sda_m1 */ 192 <2 RK_PC0 9 &pcfg_pull_none_smt>; 193 }; 194 }; 195 196 i2c3 { 197 /omit-if-no-ref/ 198 i2c3m3_xfer: i2c3m3-xfer { 199 rockchip,pins = 200 /* i2c3_scl_m3 */ 201 <2 RK_PB2 9 &pcfg_pull_none_smt>, 202 /* i2c3_sda_m3 */ 203 <2 RK_PB3 9 &pcfg_pull_none_smt>; 204 }; 205 }; 206 207 i2c4 { 208 /omit-if-no-ref/ 209 i2c4m1_xfer: i2c4m1-xfer { 210 rockchip,pins = 211 /* i2c4_scl_m1 */ 212 <2 RK_PB5 9 &pcfg_pull_none_smt>, 213 /* i2c4_sda_m1 */ 214 <2 RK_PB4 9 &pcfg_pull_none_smt>; 215 }; 216 }; 217 218 i2c5 { 219 /omit-if-no-ref/ 220 i2c5m4_xfer: i2c5m4-xfer { 221 rockchip,pins = 222 /* i2c5_scl_m4 */ 223 <2 RK_PB6 9 &pcfg_pull_none_smt>, 224 /* i2c5_sda_m4 */ 225 <2 RK_PB7 9 &pcfg_pull_none_smt>; 226 }; 227 }; 228 229 i2c6 { 230 /omit-if-no-ref/ 231 i2c6m2_xfer: i2c6m2-xfer { 232 rockchip,pins = 233 /* i2c6_scl_m2 */ 234 <2 RK_PC3 9 &pcfg_pull_none_smt>, 235 /* i2c6_sda_m2 */ 236 <2 RK_PC2 9 &pcfg_pull_none_smt>; 237 }; 238 }; 239 240 i2c7 { 241 /omit-if-no-ref/ 242 i2c7m1_xfer: i2c7m1-xfer { 243 rockchip,pins = 244 /* i2c7_scl_m1 */ 245 <4 RK_PC3 9 &pcfg_pull_none_smt>, 246 /* i2c7_sda_m1 */ 247 <4 RK_PC4 9 &pcfg_pull_none_smt>; 248 }; 249 }; 250 251 i2c8 { 252 /omit-if-no-ref/ 253 i2c8m1_xfer: i2c8m1-xfer { 254 rockchip,pins = 255 /* i2c8_scl_m1 */ 256 <2 RK_PB0 9 &pcfg_pull_none_smt>, 257 /* i2c8_sda_m1 */ 258 <2 RK_PB1 9 &pcfg_pull_none_smt>; 259 }; 260 }; 261 262 i2s2 { 263 /omit-if-no-ref/ 264 i2s2m0_idle: i2s2m0-idle { 265 rockchip,pins = 266 /* i2s2m0_lrck_gpio */ 267 <2 RK_PC0 0 &pcfg_pull_none>, 268 /* i2s2m0_sclk_gpio */ 269 <2 RK_PB7 0 &pcfg_pull_none>; 270 }; 271 272 /omit-if-no-ref/ 273 i2s2m0_lrck: i2s2m0-lrck { 274 rockchip,pins = 275 /* i2s2m0_lrck */ 276 <2 RK_PC0 2 &pcfg_pull_none_smt>; 277 }; 278 279 /omit-if-no-ref/ 280 i2s2m0_mclk: i2s2m0-mclk { 281 rockchip,pins = 282 /* i2s2m0_mclk */ 283 <2 RK_PB6 2 &pcfg_pull_none_smt>; 284 }; 285 286 /omit-if-no-ref/ 287 i2s2m0_sclk: i2s2m0-sclk { 288 rockchip,pins = 289 /* i2s2m0_sclk */ 290 <2 RK_PB7 2 &pcfg_pull_none_smt>; 291 }; 292 293 /omit-if-no-ref/ 294 i2s2m0_sdi: i2s2m0-sdi { 295 rockchip,pins = 296 /* i2s2m0_sdi */ 297 <2 RK_PC3 2 &pcfg_pull_none>; 298 }; 299 300 /omit-if-no-ref/ 301 i2s2m0_sdo: i2s2m0-sdo { 302 rockchip,pins = 303 /* i2s2m0_sdo */ 304 <4 RK_PC3 2 &pcfg_pull_none>; 305 }; 306 }; 307 308 pwm2 { 309 /omit-if-no-ref/ 310 pwm2m2_pins: pwm2m2-pins { 311 rockchip,pins = 312 /* pwm2_m2 */ 313 <4 RK_PC2 11 &pcfg_pull_none>; 314 }; 315 }; 316 317 pwm4 { 318 /omit-if-no-ref/ 319 pwm4m1_pins: pwm4m1-pins { 320 rockchip,pins = 321 /* pwm4_m1 */ 322 <4 RK_PC3 11 &pcfg_pull_none>; 323 }; 324 }; 325 326 pwm5 { 327 /omit-if-no-ref/ 328 pwm5m2_pins: pwm5m2-pins { 329 rockchip,pins = 330 /* pwm5_m2 */ 331 <4 RK_PC4 11 &pcfg_pull_none>; 332 }; 333 }; 334 335 pwm6 { 336 /omit-if-no-ref/ 337 pwm6m2_pins: pwm6m2-pins { 338 rockchip,pins = 339 /* pwm6_m2 */ 340 <4 RK_PC5 11 &pcfg_pull_none>; 341 }; 342 }; 343 344 pwm7 { 345 /omit-if-no-ref/ 346 pwm7m3_pins: pwm7m3-pins { 347 rockchip,pins = 348 /* pwm7_ir_m3 */ 349 <4 RK_PC6 11 &pcfg_pull_none>; 350 }; 351 }; 352 353 sdio { 354 /omit-if-no-ref/ 355 sdiom0_pins: sdiom0-pins { 356 rockchip,pins = 357 /* sdio_clk_m0 */ 358 <2 RK_PB3 2 &pcfg_pull_none>, 359 /* sdio_cmd_m0 */ 360 <2 RK_PB2 2 &pcfg_pull_up>, 361 /* sdio_d0_m0 */ 362 <2 RK_PA6 2 &pcfg_pull_up>, 363 /* sdio_d1_m0 */ 364 <2 RK_PA7 2 &pcfg_pull_up>, 365 /* sdio_d2_m0 */ 366 <2 RK_PB0 2 &pcfg_pull_up>, 367 /* sdio_d3_m0 */ 368 <2 RK_PB1 2 &pcfg_pull_up>; 369 }; 370 }; 371 372 spi1 { 373 /omit-if-no-ref/ 374 spi1m0_pins: spi1m0-pins { 375 rockchip,pins = 376 /* spi1_clk_m0 */ 377 <2 RK_PC0 8 &pcfg_pull_up_drv_level_1>, 378 /* spi1_miso_m0 */ 379 <2 RK_PC1 8 &pcfg_pull_up_drv_level_1>, 380 /* spi1_mosi_m0 */ 381 <2 RK_PC2 8 &pcfg_pull_up_drv_level_1>; 382 }; 383 384 /omit-if-no-ref/ 385 spi1m0_cs0: spi1m0-cs0 { 386 rockchip,pins = 387 /* spi1_cs0_m0 */ 388 <2 RK_PC3 8 &pcfg_pull_up_drv_level_1>; 389 }; 390 391 /omit-if-no-ref/ 392 spi1m0_cs1: spi1m0-cs1 { 393 rockchip,pins = 394 /* spi1_cs1_m0 */ 395 <2 RK_PC4 8 &pcfg_pull_up_drv_level_1>; 396 }; 397 }; 398 399 spi3 { 400 /omit-if-no-ref/ 401 spi3m0_pins: spi3m0-pins { 402 rockchip,pins = 403 /* spi3_clk_m0 */ 404 <4 RK_PC6 8 &pcfg_pull_up_drv_level_1>, 405 /* spi3_miso_m0 */ 406 <4 RK_PC4 8 &pcfg_pull_up_drv_level_1>, 407 /* spi3_mosi_m0 */ 408 <4 RK_PC5 8 &pcfg_pull_up_drv_level_1>; 409 }; 410 411 /omit-if-no-ref/ 412 spi3m0_cs0: spi3m0-cs0 { 413 rockchip,pins = 414 /* spi3_cs0_m0 */ 415 <4 RK_PC2 8 &pcfg_pull_up_drv_level_1>; 416 }; 417 418 /omit-if-no-ref/ 419 spi3m0_cs1: spi3m0-cs1 { 420 rockchip,pins = 421 /* spi3_cs1_m0 */ 422 <4 RK_PC3 8 &pcfg_pull_up_drv_level_1>; 423 }; 424 }; 425 426 uart1 { 427 /omit-if-no-ref/ 428 uart1m0_xfer: uart1m0-xfer { 429 rockchip,pins = 430 /* uart1_rx_m0 */ 431 <2 RK_PB6 10 &pcfg_pull_up>, 432 /* uart1_tx_m0 */ 433 <2 RK_PB7 10 &pcfg_pull_up>; 434 }; 435 436 /omit-if-no-ref/ 437 uart1m0_ctsn: uart1m0-ctsn { 438 rockchip,pins = 439 /* uart1m0_ctsn */ 440 <2 RK_PC1 10 &pcfg_pull_none>; 441 }; 442 443 /omit-if-no-ref/ 444 uart1m0_rtsn: uart1m0-rtsn { 445 rockchip,pins = 446 /* uart1m0_rtsn */ 447 <2 RK_PC0 10 &pcfg_pull_none>; 448 }; 449 }; 450 451 uart6 { 452 /omit-if-no-ref/ 453 uart6m0_xfer: uart6m0-xfer { 454 rockchip,pins = 455 /* uart6_rx_m0 */ 456 <2 RK_PA6 10 &pcfg_pull_up>, 457 /* uart6_tx_m0 */ 458 <2 RK_PA7 10 &pcfg_pull_up>; 459 }; 460 461 /omit-if-no-ref/ 462 uart6m0_ctsn: uart6m0-ctsn { 463 rockchip,pins = 464 /* uart6m0_ctsn */ 465 <2 RK_PB1 10 &pcfg_pull_none>; 466 }; 467 468 /omit-if-no-ref/ 469 uart6m0_rtsn: uart6m0-rtsn { 470 rockchip,pins = 471 /* uart6m0_rtsn */ 472 <2 RK_PB0 10 &pcfg_pull_none>; 473 }; 474 }; 475 476 uart7 { 477 /omit-if-no-ref/ 478 uart7m0_xfer: uart7m0-xfer { 479 rockchip,pins = 480 /* uart7_rx_m0 */ 481 <2 RK_PB4 10 &pcfg_pull_up>, 482 /* uart7_tx_m0 */ 483 <2 RK_PB5 10 &pcfg_pull_up>; 484 }; 485 486 /omit-if-no-ref/ 487 uart7m0_ctsn: uart7m0-ctsn { 488 rockchip,pins = 489 /* uart7m0_ctsn */ 490 <4 RK_PC6 10 &pcfg_pull_none>; 491 }; 492 493 /omit-if-no-ref/ 494 uart7m0_rtsn: uart7m0-rtsn { 495 rockchip,pins = 496 /* uart7m0_rtsn */ 497 <4 RK_PC2 10 &pcfg_pull_none>; 498 }; 499 }; 500 501 uart9 { 502 /omit-if-no-ref/ 503 uart9m0_xfer: uart9m0-xfer { 504 rockchip,pins = 505 /* uart9_rx_m0 */ 506 <2 RK_PC4 10 &pcfg_pull_up>, 507 /* uart9_tx_m0 */ 508 <2 RK_PC2 10 &pcfg_pull_up>; 509 }; 510 511 /omit-if-no-ref/ 512 uart9m0_ctsn: uart9m0-ctsn { 513 rockchip,pins = 514 /* uart9m0_ctsn */ 515 <4 RK_PC5 10 &pcfg_pull_none>; 516 }; 517 518 /omit-if-no-ref/ 519 uart9m0_rtsn: uart9m0-rtsn { 520 rockchip,pins = 521 /* uart9m0_rtsn */ 522 <4 RK_PC4 10 &pcfg_pull_none>; 523 }; 524 }; 525}; 526