1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun#include "dt-bindings/usb/pd.h" 8*4882a593Smuzhiyun#include "rk3588.dtsi" 9*4882a593Smuzhiyun#include "rk3588-toybrick.dtsi" 10*4882a593Smuzhiyun#include "rk3588-rk806-single.dtsi" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun /* If hdmirx node is disabled, delete the reserved-memory node here. */ 14*4882a593Smuzhiyun reserved-memory { 15*4882a593Smuzhiyun #address-cells = <2>; 16*4882a593Smuzhiyun #size-cells = <2>; 17*4882a593Smuzhiyun ranges; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ 20*4882a593Smuzhiyun cma { 21*4882a593Smuzhiyun compatible = "shared-dma-pool"; 22*4882a593Smuzhiyun reusable; 23*4882a593Smuzhiyun reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; 24*4882a593Smuzhiyun linux,cma-default; 25*4882a593Smuzhiyun }; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun fan: pwm-fan { 29*4882a593Smuzhiyun compatible = "pwm-fan"; 30*4882a593Smuzhiyun #cooling-cells = <2>; 31*4882a593Smuzhiyun pwms = <&pwm9 0 50000 0>; 32*4882a593Smuzhiyun cooling-levels = <0 50 100 150 200 255>; 33*4882a593Smuzhiyun rockchip,temp-trips = < 34*4882a593Smuzhiyun 50000 1 35*4882a593Smuzhiyun 55000 2 36*4882a593Smuzhiyun 60000 3 37*4882a593Smuzhiyun 65000 4 38*4882a593Smuzhiyun 70000 5 39*4882a593Smuzhiyun >; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun hdmiin_dc: hdmiin-dc { 43*4882a593Smuzhiyun compatible = "rockchip,dummy-codec"; 44*4882a593Smuzhiyun #sound-dai-cells = <0>; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun es8388_sound: es8388-sound { 48*4882a593Smuzhiyun status = "okay"; 49*4882a593Smuzhiyun compatible = "rockchip,multicodecs-card"; 50*4882a593Smuzhiyun rockchip,card-name = "rockchip,es8388"; 51*4882a593Smuzhiyun hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 52*4882a593Smuzhiyun io-channels = <&saradc 3>; 53*4882a593Smuzhiyun io-channel-names = "adc-detect"; 54*4882a593Smuzhiyun keyup-threshold-microvolt = <1800000>; 55*4882a593Smuzhiyun poll-interval = <100>; 56*4882a593Smuzhiyun spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 57*4882a593Smuzhiyun hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; 58*4882a593Smuzhiyun rockchip,format = "i2s"; 59*4882a593Smuzhiyun rockchip,mclk-fs = <256>; 60*4882a593Smuzhiyun rockchip,cpu = <&i2s0_8ch>; 61*4882a593Smuzhiyun rockchip,codec = <&es8388>; 62*4882a593Smuzhiyun rockchip,audio-routing = 63*4882a593Smuzhiyun "Headphone", "LOUT1", 64*4882a593Smuzhiyun "Headphone", "ROUT1", 65*4882a593Smuzhiyun "Speaker", "LOUT2", 66*4882a593Smuzhiyun "Speaker", "ROUT2", 67*4882a593Smuzhiyun "Headphone", "Headphone Power", 68*4882a593Smuzhiyun "Headphone", "Headphone Power", 69*4882a593Smuzhiyun "Speaker", "Speaker Power", 70*4882a593Smuzhiyun "Speaker", "Speaker Power", 71*4882a593Smuzhiyun "LINPUT1", "Main Mic", 72*4882a593Smuzhiyun "LINPUT2", "Main Mic", 73*4882a593Smuzhiyun "RINPUT1", "Headset Mic", 74*4882a593Smuzhiyun "RINPUT2", "Headset Mic"; 75*4882a593Smuzhiyun pinctrl-names = "default"; 76*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 77*4882a593Smuzhiyun play-pause-key { 78*4882a593Smuzhiyun label = "playpause"; 79*4882a593Smuzhiyun linux,code = <KEY_PLAYPAUSE>; 80*4882a593Smuzhiyun press-threshold-microvolt = <2000>; 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun hdmiin-sound { 85*4882a593Smuzhiyun compatible = "simple-audio-card"; 86*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 87*4882a593Smuzhiyun simple-audio-card,name = "rockchip,hdmiin"; 88*4882a593Smuzhiyun simple-audio-card,bitclock-master = <&dailink0_master>; 89*4882a593Smuzhiyun simple-audio-card,frame-master = <&dailink0_master>; 90*4882a593Smuzhiyun status = "okay"; 91*4882a593Smuzhiyun simple-audio-card,cpu { 92*4882a593Smuzhiyun sound-dai = <&i2s7_8ch>; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun dailink0_master: simple-audio-card,codec { 95*4882a593Smuzhiyun sound-dai = <&hdmiin_dc>; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun pcie20_avdd0v85: pcie20-avdd0v85 { 100*4882a593Smuzhiyun compatible = "regulator-fixed"; 101*4882a593Smuzhiyun regulator-name = "pcie20_avdd0v85"; 102*4882a593Smuzhiyun regulator-boot-on; 103*4882a593Smuzhiyun regulator-always-on; 104*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 105*4882a593Smuzhiyun regulator-max-microvolt = <850000>; 106*4882a593Smuzhiyun vin-supply = <&vdd_0v85_s0>; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun pcie20_avdd1v8: pcie20-avdd1v8 { 110*4882a593Smuzhiyun compatible = "regulator-fixed"; 111*4882a593Smuzhiyun regulator-name = "pcie20_avdd1v8"; 112*4882a593Smuzhiyun regulator-boot-on; 113*4882a593Smuzhiyun regulator-always-on; 114*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 115*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 116*4882a593Smuzhiyun vin-supply = <&avcc_1v8_s0>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun pcie30_avdd0v75: pcie30-avdd0v75 { 120*4882a593Smuzhiyun compatible = "regulator-fixed"; 121*4882a593Smuzhiyun regulator-name = "pcie30_avdd0v75"; 122*4882a593Smuzhiyun regulator-boot-on; 123*4882a593Smuzhiyun regulator-always-on; 124*4882a593Smuzhiyun regulator-min-microvolt = <750000>; 125*4882a593Smuzhiyun regulator-max-microvolt = <750000>; 126*4882a593Smuzhiyun vin-supply = <&avdd_0v75_s0>; 127*4882a593Smuzhiyun }; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun pcie30_avdd1v8: pcie30-avdd1v8 { 130*4882a593Smuzhiyun compatible = "regulator-fixed"; 131*4882a593Smuzhiyun regulator-name = "pcie30_avdd1v8"; 132*4882a593Smuzhiyun regulator-boot-on; 133*4882a593Smuzhiyun regulator-always-on; 134*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 135*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 136*4882a593Smuzhiyun vin-supply = <&avcc_1v8_s0>; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun rk_headset: rk-headset { 140*4882a593Smuzhiyun status = "disabled"; 141*4882a593Smuzhiyun compatible = "rockchip_headset"; 142*4882a593Smuzhiyun headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 143*4882a593Smuzhiyun pinctrl-names = "default"; 144*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 145*4882a593Smuzhiyun io-channels = <&saradc 3>; 146*4882a593Smuzhiyun }; 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun vbus5v0_typec: vbus5v0-typec { 149*4882a593Smuzhiyun compatible = "regulator-fixed"; 150*4882a593Smuzhiyun regulator-name = "vbus5v0_typec"; 151*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 152*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 153*4882a593Smuzhiyun enable-active-high; 154*4882a593Smuzhiyun gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; 155*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 156*4882a593Smuzhiyun pinctrl-names = "default"; 157*4882a593Smuzhiyun pinctrl-0 = <&typec5v_pwren>; 158*4882a593Smuzhiyun }; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun vcc3v3_lcd_n: vcc3v3-lcd0-n { 161*4882a593Smuzhiyun compatible = "regulator-fixed"; 162*4882a593Smuzhiyun regulator-name = "vcc3v3_lcd0_n"; 163*4882a593Smuzhiyun regulator-boot-on; 164*4882a593Smuzhiyun enable-active-high; 165*4882a593Smuzhiyun gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; 166*4882a593Smuzhiyun vin-supply = <&vcc_1v8_s0>; 167*4882a593Smuzhiyun }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun vcc3v3_pcie30: vcc3v3-pcie30 { 170*4882a593Smuzhiyun compatible = "regulator-fixed"; 171*4882a593Smuzhiyun regulator-name = "vcc3v3_pcie30"; 172*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 173*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 174*4882a593Smuzhiyun enable-active-high; 175*4882a593Smuzhiyun gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; 176*4882a593Smuzhiyun startup-delay-us = <5000>; 177*4882a593Smuzhiyun vin-supply = <&vcc12v_dcin>; 178*4882a593Smuzhiyun }; 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun vcc5v0_host: vcc5v0-host { 181*4882a593Smuzhiyun compatible = "regulator-fixed"; 182*4882a593Smuzhiyun regulator-name = "vcc5v0_host"; 183*4882a593Smuzhiyun regulator-boot-on; 184*4882a593Smuzhiyun regulator-always-on; 185*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 186*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 187*4882a593Smuzhiyun enable-active-high; 188*4882a593Smuzhiyun gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 189*4882a593Smuzhiyun vin-supply = <&vcc5v0_usb>; 190*4882a593Smuzhiyun pinctrl-names = "default"; 191*4882a593Smuzhiyun pinctrl-0 = <&vcc5v0_host_en>; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun vcc_mipicsi0: vcc-mipicsi0-regulator { 195*4882a593Smuzhiyun compatible = "regulator-fixed"; 196*4882a593Smuzhiyun regulator-name = "vcc_mipicsi0"; 197*4882a593Smuzhiyun enable-active-high; 198*4882a593Smuzhiyun }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun vcc_mipicsi1: vcc-mipicsi1-regulator { 201*4882a593Smuzhiyun compatible = "regulator-fixed"; 202*4882a593Smuzhiyun regulator-name = "vcc_mipicsi1"; 203*4882a593Smuzhiyun enable-active-high; 204*4882a593Smuzhiyun }; 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun vcc_mipidcphy0: vcc-mipidcphy0-regulator { 207*4882a593Smuzhiyun compatible = "regulator-fixed"; 208*4882a593Smuzhiyun regulator-name = "vcc_mipicsi1"; 209*4882a593Smuzhiyun enable-active-high; 210*4882a593Smuzhiyun }; 211*4882a593Smuzhiyun 212*4882a593Smuzhiyun wireless_bluetooth: wireless-bluetooth { 213*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 214*4882a593Smuzhiyun clocks = <&hym8563>; 215*4882a593Smuzhiyun clock-names = "ext_clock"; 216*4882a593Smuzhiyun uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; 217*4882a593Smuzhiyun pinctrl-names = "default", "rts_gpio"; 218*4882a593Smuzhiyun pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 219*4882a593Smuzhiyun pinctrl-1 = <&uart8_gpios>; 220*4882a593Smuzhiyun BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 221*4882a593Smuzhiyun BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 222*4882a593Smuzhiyun BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; 223*4882a593Smuzhiyun status = "okay"; 224*4882a593Smuzhiyun }; 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun wireless_wlan: wireless-wlan { 227*4882a593Smuzhiyun compatible = "wlan-platdata"; 228*4882a593Smuzhiyun wifi_chip_type = "ap6255"; 229*4882a593Smuzhiyun pinctrl-names = "default"; 230*4882a593Smuzhiyun pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; 231*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; 232*4882a593Smuzhiyun WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 233*4882a593Smuzhiyun status = "okay"; 234*4882a593Smuzhiyun }; 235*4882a593Smuzhiyun}; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun&backlight { 238*4882a593Smuzhiyun pwms = <&pwm2 0 25000 0>; 239*4882a593Smuzhiyun status = "okay"; 240*4882a593Smuzhiyun}; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun&can2 { 243*4882a593Smuzhiyun status = "okay"; 244*4882a593Smuzhiyun}; 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun&combphy0_ps { 247*4882a593Smuzhiyun status = "okay"; 248*4882a593Smuzhiyun}; 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun&combphy1_ps { 251*4882a593Smuzhiyun status = "okay"; 252*4882a593Smuzhiyun}; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun&combphy2_psu { 255*4882a593Smuzhiyun status = "okay"; 256*4882a593Smuzhiyun}; 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun&dp0 { 259*4882a593Smuzhiyun status = "okay"; 260*4882a593Smuzhiyun}; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun&dp0_in_vp2 { 263*4882a593Smuzhiyun status = "okay"; 264*4882a593Smuzhiyun}; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun/* 267*4882a593Smuzhiyun * mipi_dcphy0 needs to be enabled 268*4882a593Smuzhiyun * when dsi0 is enabled 269*4882a593Smuzhiyun */ 270*4882a593Smuzhiyun&dsi0 { 271*4882a593Smuzhiyun status = "disabled"; 272*4882a593Smuzhiyun}; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun&dsi0_in_vp2 { 275*4882a593Smuzhiyun status = "disabled"; 276*4882a593Smuzhiyun}; 277*4882a593Smuzhiyun 278*4882a593Smuzhiyun&dsi0_in_vp3 { 279*4882a593Smuzhiyun status = "okay"; 280*4882a593Smuzhiyun}; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun&dsi0_panel { 283*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_n>; 284*4882a593Smuzhiyun reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 285*4882a593Smuzhiyun pinctrl-names = "default"; 286*4882a593Smuzhiyun pinctrl-0 = <&lcd_rst_gpio>; 287*4882a593Smuzhiyun}; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun/* 290*4882a593Smuzhiyun * mipi_dcphy1 needs to be enabled 291*4882a593Smuzhiyun * when dsi1 is enabled 292*4882a593Smuzhiyun */ 293*4882a593Smuzhiyun&dsi1 { 294*4882a593Smuzhiyun status = "disabled"; 295*4882a593Smuzhiyun}; 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun&dsi1_in_vp2 { 298*4882a593Smuzhiyun status = "disabled"; 299*4882a593Smuzhiyun}; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun&dsi1_in_vp3 { 302*4882a593Smuzhiyun status = "disabled"; 303*4882a593Smuzhiyun}; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun&dsi1_panel { 306*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_n>; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun /* 309*4882a593Smuzhiyun * because in hardware, the two screens share the reset pin, 310*4882a593Smuzhiyun * so reset-gpios need only in dsi1 enable and dsi0 disabled 311*4882a593Smuzhiyun * case. 312*4882a593Smuzhiyun */ 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 315*4882a593Smuzhiyun //pinctrl-names = "default"; 316*4882a593Smuzhiyun //pinctrl-0 = <&lcd_rst_gpio>; 317*4882a593Smuzhiyun}; 318*4882a593Smuzhiyun 319*4882a593Smuzhiyun&gmac0 { 320*4882a593Smuzhiyun /* Use rgmii-rxid mode to disable rx delay inside Soc */ 321*4882a593Smuzhiyun phy-mode = "rgmii-rxid"; 322*4882a593Smuzhiyun clock_in_out = "output"; 323*4882a593Smuzhiyun 324*4882a593Smuzhiyun snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; 325*4882a593Smuzhiyun snps,reset-active-low; 326*4882a593Smuzhiyun /* Reset time is 20ms, 100ms for rtl8211f */ 327*4882a593Smuzhiyun snps,reset-delays-us = <0 20000 100000>; 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun pinctrl-names = "default"; 330*4882a593Smuzhiyun pinctrl-0 = <&gmac0_miim 331*4882a593Smuzhiyun &gmac0_tx_bus2 332*4882a593Smuzhiyun &gmac0_rx_bus2 333*4882a593Smuzhiyun &gmac0_rgmii_clk 334*4882a593Smuzhiyun &gmac0_rgmii_bus>; 335*4882a593Smuzhiyun 336*4882a593Smuzhiyun tx_delay = <0x43>; 337*4882a593Smuzhiyun /* rx_delay = <0x3f>; */ 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun phy-handle = <&rgmii_phy>; 340*4882a593Smuzhiyun status = "okay"; 341*4882a593Smuzhiyun}; 342*4882a593Smuzhiyun 343*4882a593Smuzhiyun&hdmi0 { 344*4882a593Smuzhiyun enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 345*4882a593Smuzhiyun status = "okay"; 346*4882a593Smuzhiyun}; 347*4882a593Smuzhiyun 348*4882a593Smuzhiyun&hdmi0_in_vp0 { 349*4882a593Smuzhiyun status = "okay"; 350*4882a593Smuzhiyun}; 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun&hdmi0_sound { 353*4882a593Smuzhiyun status = "okay"; 354*4882a593Smuzhiyun}; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun/* Should work with at least 128MB cma reserved above. */ 357*4882a593Smuzhiyun&hdmirx_ctrler { 358*4882a593Smuzhiyun status = "okay"; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun /* Effective level used to trigger HPD: 0-low, 1-high */ 361*4882a593Smuzhiyun hpd-trigger-level = <1>; 362*4882a593Smuzhiyun hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 363*4882a593Smuzhiyun pinctrl-names = "default"; 364*4882a593Smuzhiyun pinctrl-0 = <&hdmim1_rx &hdmirx_det>; 365*4882a593Smuzhiyun}; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun&hdptxphy_hdmi0 { 368*4882a593Smuzhiyun status = "okay"; 369*4882a593Smuzhiyun}; 370*4882a593Smuzhiyun 371*4882a593Smuzhiyun&i2c0 { 372*4882a593Smuzhiyun status = "okay"; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 375*4882a593Smuzhiyun compatible = "rockchip,rk8602"; 376*4882a593Smuzhiyun reg = <0x42>; 377*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 378*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 379*4882a593Smuzhiyun regulator-name = "vdd_cpu_big0_s0"; 380*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 381*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 382*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 383*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 384*4882a593Smuzhiyun regulator-boot-on; 385*4882a593Smuzhiyun regulator-always-on; 386*4882a593Smuzhiyun regulator-state-mem { 387*4882a593Smuzhiyun regulator-off-in-suspend; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun }; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 392*4882a593Smuzhiyun compatible = "rockchip,rk8603"; 393*4882a593Smuzhiyun reg = <0x43>; 394*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 395*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 396*4882a593Smuzhiyun regulator-name = "vdd_cpu_big1_s0"; 397*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 398*4882a593Smuzhiyun regulator-max-microvolt = <1050000>; 399*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 400*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 401*4882a593Smuzhiyun regulator-boot-on; 402*4882a593Smuzhiyun regulator-always-on; 403*4882a593Smuzhiyun regulator-state-mem { 404*4882a593Smuzhiyun regulator-off-in-suspend; 405*4882a593Smuzhiyun }; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun}; 408*4882a593Smuzhiyun 409*4882a593Smuzhiyun&i2c2 { 410*4882a593Smuzhiyun status = "okay"; 411*4882a593Smuzhiyun clock-frequency = <400000>; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun usbc0: husb311@4e { 414*4882a593Smuzhiyun compatible = "hynetek,husb311"; 415*4882a593Smuzhiyun reg = <0x4e>; 416*4882a593Smuzhiyun interrupt-parent = <&gpio3>; 417*4882a593Smuzhiyun interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; 418*4882a593Smuzhiyun pinctrl-names = "default"; 419*4882a593Smuzhiyun pinctrl-0 = <&usbc0_int>; 420*4882a593Smuzhiyun vbus-supply = <&vbus5v0_typec>; 421*4882a593Smuzhiyun status = "okay"; 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun ports { 424*4882a593Smuzhiyun #address-cells = <1>; 425*4882a593Smuzhiyun #size-cells = <0>; 426*4882a593Smuzhiyun 427*4882a593Smuzhiyun port@0 { 428*4882a593Smuzhiyun reg = <0>; 429*4882a593Smuzhiyun usbc0_role_sw: endpoint@0 { 430*4882a593Smuzhiyun remote-endpoint = <&dwc3_0_role_switch>; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun }; 433*4882a593Smuzhiyun }; 434*4882a593Smuzhiyun 435*4882a593Smuzhiyun usb_con: connector { 436*4882a593Smuzhiyun compatible = "usb-c-connector"; 437*4882a593Smuzhiyun label = "USB-C"; 438*4882a593Smuzhiyun data-role = "dual"; 439*4882a593Smuzhiyun power-role = "dual"; 440*4882a593Smuzhiyun try-power-role = "sink"; 441*4882a593Smuzhiyun op-sink-microwatt = <1000000>; 442*4882a593Smuzhiyun sink-pdos = 443*4882a593Smuzhiyun <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 444*4882a593Smuzhiyun source-pdos = 445*4882a593Smuzhiyun <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 446*4882a593Smuzhiyun 447*4882a593Smuzhiyun altmodes { 448*4882a593Smuzhiyun #address-cells = <1>; 449*4882a593Smuzhiyun #size-cells = <0>; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun altmode@0 { 452*4882a593Smuzhiyun reg = <0>; 453*4882a593Smuzhiyun svid = <0xff01>; 454*4882a593Smuzhiyun vdo = <0xffffffff>; 455*4882a593Smuzhiyun }; 456*4882a593Smuzhiyun }; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun ports { 459*4882a593Smuzhiyun #address-cells = <1>; 460*4882a593Smuzhiyun #size-cells = <0>; 461*4882a593Smuzhiyun 462*4882a593Smuzhiyun port@0 { 463*4882a593Smuzhiyun reg = <0>; 464*4882a593Smuzhiyun usbc0_orien_sw: endpoint { 465*4882a593Smuzhiyun remote-endpoint = <&usbdp_phy0_orientation_switch>; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun }; 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun port@1 { 470*4882a593Smuzhiyun reg = <1>; 471*4882a593Smuzhiyun dp_altmode_mux: endpoint { 472*4882a593Smuzhiyun remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 473*4882a593Smuzhiyun }; 474*4882a593Smuzhiyun }; 475*4882a593Smuzhiyun }; 476*4882a593Smuzhiyun }; 477*4882a593Smuzhiyun }; 478*4882a593Smuzhiyun 479*4882a593Smuzhiyun hym8563: hym8563@51 { 480*4882a593Smuzhiyun compatible = "haoyu,hym8563"; 481*4882a593Smuzhiyun reg = <0x51>; 482*4882a593Smuzhiyun #clock-cells = <0>; 483*4882a593Smuzhiyun clock-frequency = <32768>; 484*4882a593Smuzhiyun clock-output-names = "hym8563"; 485*4882a593Smuzhiyun pinctrl-names = "default"; 486*4882a593Smuzhiyun pinctrl-0 = <&hym8563_int>; 487*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 488*4882a593Smuzhiyun interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun 491*4882a593Smuzhiyun vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 492*4882a593Smuzhiyun compatible = "rockchip,rk8602"; 493*4882a593Smuzhiyun reg = <0x42>; 494*4882a593Smuzhiyun vin-supply = <&vcc5v0_sys>; 495*4882a593Smuzhiyun regulator-compatible = "rk860x-reg"; 496*4882a593Smuzhiyun regulator-name = "vdd_npu_s0"; 497*4882a593Smuzhiyun regulator-min-microvolt = <550000>; 498*4882a593Smuzhiyun regulator-max-microvolt = <950000>; 499*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 500*4882a593Smuzhiyun rockchip,suspend-voltage-selector = <1>; 501*4882a593Smuzhiyun regulator-boot-on; 502*4882a593Smuzhiyun regulator-always-on; 503*4882a593Smuzhiyun regulator-state-mem { 504*4882a593Smuzhiyun regulator-off-in-suspend; 505*4882a593Smuzhiyun }; 506*4882a593Smuzhiyun }; 507*4882a593Smuzhiyun}; 508*4882a593Smuzhiyun 509*4882a593Smuzhiyun&i2c6 { 510*4882a593Smuzhiyun status = "disabled"; 511*4882a593Smuzhiyun gt1x: gt1x@14 { 512*4882a593Smuzhiyun compatible = "goodix,gt1x"; 513*4882a593Smuzhiyun reg = <0x14>; 514*4882a593Smuzhiyun pinctrl-names = "default"; 515*4882a593Smuzhiyun pinctrl-0 = <&touch_gpio>; 516*4882a593Smuzhiyun goodix,rst-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; 517*4882a593Smuzhiyun goodix,irq-gpio = <&gpio0 RK_PB0 IRQ_TYPE_LEVEL_LOW>; 518*4882a593Smuzhiyun power-supply = <&vcc3v3_lcd_n>; 519*4882a593Smuzhiyun }; 520*4882a593Smuzhiyun 521*4882a593Smuzhiyun gsl3673: gsl3673@40 { 522*4882a593Smuzhiyun compatible = "GSL,GSL3673"; 523*4882a593Smuzhiyun reg = <0x40>; 524*4882a593Smuzhiyun screen_max_x = <1536>; 525*4882a593Smuzhiyun screen_max_y = <2048>; 526*4882a593Smuzhiyun irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>; 527*4882a593Smuzhiyun rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; 528*4882a593Smuzhiyun }; 529*4882a593Smuzhiyun}; 530*4882a593Smuzhiyun 531*4882a593Smuzhiyun&i2c7 { 532*4882a593Smuzhiyun status = "okay"; 533*4882a593Smuzhiyun es8388: es8388@11 { 534*4882a593Smuzhiyun status = "okay"; 535*4882a593Smuzhiyun #sound-dai-cells = <0>; 536*4882a593Smuzhiyun compatible = "everest,es8388", "everest,es8323"; 537*4882a593Smuzhiyun reg = <0x11>; 538*4882a593Smuzhiyun clocks = <&mclkout_i2s0>; 539*4882a593Smuzhiyun clock-names = "mclk"; 540*4882a593Smuzhiyun assigned-clocks = <&mclkout_i2s0>; 541*4882a593Smuzhiyun assigned-clock-rates = <12288000>; 542*4882a593Smuzhiyun pinctrl-names = "default"; 543*4882a593Smuzhiyun pinctrl-0 = <&i2s0_mclk>; 544*4882a593Smuzhiyun }; 545*4882a593Smuzhiyun}; 546*4882a593Smuzhiyun 547*4882a593Smuzhiyun&i2s5_8ch { 548*4882a593Smuzhiyun status = "okay"; 549*4882a593Smuzhiyun}; 550*4882a593Smuzhiyun 551*4882a593Smuzhiyun&i2s7_8ch { 552*4882a593Smuzhiyun status = "okay"; 553*4882a593Smuzhiyun}; 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun&mdio0 { 556*4882a593Smuzhiyun rgmii_phy: phy@1 { 557*4882a593Smuzhiyun compatible = "ethernet-phy-ieee802.3-c22"; 558*4882a593Smuzhiyun reg = <0x1>; 559*4882a593Smuzhiyun }; 560*4882a593Smuzhiyun}; 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun&mipi_dcphy0 { 563*4882a593Smuzhiyun status = "okay"; 564*4882a593Smuzhiyun}; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun&mipi_dcphy1 { 567*4882a593Smuzhiyun status = "disabled"; 568*4882a593Smuzhiyun}; 569*4882a593Smuzhiyun 570*4882a593Smuzhiyun&pcie2x1l0 { 571*4882a593Smuzhiyun reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 572*4882a593Smuzhiyun rockchip,skip-scan-in-resume; 573*4882a593Smuzhiyun status = "okay"; 574*4882a593Smuzhiyun}; 575*4882a593Smuzhiyun 576*4882a593Smuzhiyun&pcie2x1l1 { 577*4882a593Smuzhiyun reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 578*4882a593Smuzhiyun pinctrl-names = "default"; 579*4882a593Smuzhiyun pinctrl-0 = <&rtl8111_isolate>; 580*4882a593Smuzhiyun status = "okay"; 581*4882a593Smuzhiyun}; 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun&pcie30phy { 584*4882a593Smuzhiyun rockchip,pcie30-phymode = <PHY_MODE_PCIE_NANBNB>; 585*4882a593Smuzhiyun status = "okay"; 586*4882a593Smuzhiyun}; 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun&pcie3x4 { 589*4882a593Smuzhiyun reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 590*4882a593Smuzhiyun vpcie3v3-supply = <&vcc3v3_pcie30>; 591*4882a593Smuzhiyun num-lanes=<2>; 592*4882a593Smuzhiyun status = "okay"; 593*4882a593Smuzhiyun}; 594*4882a593Smuzhiyun 595*4882a593Smuzhiyun&pinctrl { 596*4882a593Smuzhiyun hdmi { 597*4882a593Smuzhiyun hdmirx_det: hdmirx-det { 598*4882a593Smuzhiyun rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; 599*4882a593Smuzhiyun }; 600*4882a593Smuzhiyun }; 601*4882a593Smuzhiyun 602*4882a593Smuzhiyun headphone { 603*4882a593Smuzhiyun hp_det: hp-det { 604*4882a593Smuzhiyun rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 605*4882a593Smuzhiyun }; 606*4882a593Smuzhiyun }; 607*4882a593Smuzhiyun 608*4882a593Smuzhiyun hym8563 { 609*4882a593Smuzhiyun hym8563_int: hym8563-int { 610*4882a593Smuzhiyun rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 611*4882a593Smuzhiyun }; 612*4882a593Smuzhiyun }; 613*4882a593Smuzhiyun 614*4882a593Smuzhiyun lcd { 615*4882a593Smuzhiyun lcd_rst_gpio: lcd-rst-gpio { 616*4882a593Smuzhiyun rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 617*4882a593Smuzhiyun }; 618*4882a593Smuzhiyun }; 619*4882a593Smuzhiyun 620*4882a593Smuzhiyun rtl8111 { 621*4882a593Smuzhiyun rtl8111_isolate: rtl8111-isolate { 622*4882a593Smuzhiyun rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 623*4882a593Smuzhiyun }; 624*4882a593Smuzhiyun }; 625*4882a593Smuzhiyun 626*4882a593Smuzhiyun touch { 627*4882a593Smuzhiyun touch_gpio: touch-gpio { 628*4882a593Smuzhiyun rockchip,pins = 629*4882a593Smuzhiyun <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, 630*4882a593Smuzhiyun <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 631*4882a593Smuzhiyun }; 632*4882a593Smuzhiyun }; 633*4882a593Smuzhiyun 634*4882a593Smuzhiyun usb { 635*4882a593Smuzhiyun vcc5v0_host_en: vcc5v0-host-en { 636*4882a593Smuzhiyun rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 637*4882a593Smuzhiyun }; 638*4882a593Smuzhiyun }; 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun usb-typec { 641*4882a593Smuzhiyun usbc0_int: usbc0-int { 642*4882a593Smuzhiyun rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 643*4882a593Smuzhiyun }; 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun typec5v_pwren: typec5v-pwren { 646*4882a593Smuzhiyun rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 647*4882a593Smuzhiyun }; 648*4882a593Smuzhiyun }; 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun wireless-bluetooth { 651*4882a593Smuzhiyun uart8_gpios: uart8-gpios { 652*4882a593Smuzhiyun rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 653*4882a593Smuzhiyun }; 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun bt_reset_gpio: bt-reset-gpio { 656*4882a593Smuzhiyun rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 657*4882a593Smuzhiyun }; 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun bt_wake_gpio: bt-wake-gpio { 660*4882a593Smuzhiyun rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; 661*4882a593Smuzhiyun }; 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun bt_irq_gpio: bt-irq-gpio { 664*4882a593Smuzhiyun rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; 665*4882a593Smuzhiyun }; 666*4882a593Smuzhiyun }; 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun wireless-wlan { 669*4882a593Smuzhiyun wifi_host_wake_irq: wifi-host-wake-irq { 670*4882a593Smuzhiyun rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; 671*4882a593Smuzhiyun }; 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun wifi_poweren_gpio: wifi-poweren-gpio { 674*4882a593Smuzhiyun rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 675*4882a593Smuzhiyun }; 676*4882a593Smuzhiyun }; 677*4882a593Smuzhiyun}; 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun&pwm2 { 680*4882a593Smuzhiyun status = "okay"; 681*4882a593Smuzhiyun}; 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun&pwm9 { 684*4882a593Smuzhiyun pinctrl-0 = <&pwm9m1_pins>; 685*4882a593Smuzhiyun status = "okay"; 686*4882a593Smuzhiyun}; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun&sata0 { 689*4882a593Smuzhiyun status = "okay"; 690*4882a593Smuzhiyun}; 691*4882a593Smuzhiyun 692*4882a593Smuzhiyun&u2phy1_otg { 693*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 694*4882a593Smuzhiyun}; 695*4882a593Smuzhiyun 696*4882a593Smuzhiyun&u2phy2_host { 697*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 698*4882a593Smuzhiyun}; 699*4882a593Smuzhiyun 700*4882a593Smuzhiyun&u2phy3_host { 701*4882a593Smuzhiyun phy-supply = <&vcc5v0_host>; 702*4882a593Smuzhiyun}; 703*4882a593Smuzhiyun 704*4882a593Smuzhiyun&uart8 { 705*4882a593Smuzhiyun status = "okay"; 706*4882a593Smuzhiyun pinctrl-names = "default"; 707*4882a593Smuzhiyun pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; 708*4882a593Smuzhiyun}; 709*4882a593Smuzhiyun 710*4882a593Smuzhiyun&usbdp_phy0 { 711*4882a593Smuzhiyun orientation-switch; 712*4882a593Smuzhiyun svid = <0xff01>; 713*4882a593Smuzhiyun sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 714*4882a593Smuzhiyun sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 715*4882a593Smuzhiyun 716*4882a593Smuzhiyun port { 717*4882a593Smuzhiyun #address-cells = <1>; 718*4882a593Smuzhiyun #size-cells = <0>; 719*4882a593Smuzhiyun usbdp_phy0_orientation_switch: endpoint@0 { 720*4882a593Smuzhiyun reg = <0>; 721*4882a593Smuzhiyun remote-endpoint = <&usbc0_orien_sw>; 722*4882a593Smuzhiyun }; 723*4882a593Smuzhiyun 724*4882a593Smuzhiyun usbdp_phy0_dp_altmode_mux: endpoint@1 { 725*4882a593Smuzhiyun reg = <1>; 726*4882a593Smuzhiyun remote-endpoint = <&dp_altmode_mux>; 727*4882a593Smuzhiyun }; 728*4882a593Smuzhiyun }; 729*4882a593Smuzhiyun}; 730*4882a593Smuzhiyun 731*4882a593Smuzhiyun&usbdp_phy1 { 732*4882a593Smuzhiyun rockchip,dp-lane-mux = <2 3>; 733*4882a593Smuzhiyun}; 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun&usbdrd_dwc3_0 { 736*4882a593Smuzhiyun dr_mode = "otg"; 737*4882a593Smuzhiyun usb-role-switch; 738*4882a593Smuzhiyun port { 739*4882a593Smuzhiyun #address-cells = <1>; 740*4882a593Smuzhiyun #size-cells = <0>; 741*4882a593Smuzhiyun dwc3_0_role_switch: endpoint@0 { 742*4882a593Smuzhiyun reg = <0>; 743*4882a593Smuzhiyun remote-endpoint = <&usbc0_role_sw>; 744*4882a593Smuzhiyun }; 745*4882a593Smuzhiyun }; 746*4882a593Smuzhiyun}; 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun&usbhost3_0 { 749*4882a593Smuzhiyun status = "disabled"; 750*4882a593Smuzhiyun}; 751*4882a593Smuzhiyun 752*4882a593Smuzhiyun&usbhost_dwc3_0 { 753*4882a593Smuzhiyun status = "disabled"; 754*4882a593Smuzhiyun}; 755