1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "dt-bindings/usb/pd.h" 8#include "rk3588.dtsi" 9#include "rk3588-toybrick.dtsi" 10#include "rk3588-rk806-single.dtsi" 11 12/ { 13 /* If hdmirx node is disabled, delete the reserved-memory node here. */ 14 reserved-memory { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 ranges; 18 19 /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ 20 cma { 21 compatible = "shared-dma-pool"; 22 reusable; 23 reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; 24 linux,cma-default; 25 }; 26 }; 27 28 fan: pwm-fan { 29 compatible = "pwm-fan"; 30 #cooling-cells = <2>; 31 pwms = <&pwm9 0 50000 0>; 32 cooling-levels = <0 50 100 150 200 255>; 33 rockchip,temp-trips = < 34 50000 1 35 55000 2 36 60000 3 37 65000 4 38 70000 5 39 >; 40 }; 41 42 hdmiin_dc: hdmiin-dc { 43 compatible = "rockchip,dummy-codec"; 44 #sound-dai-cells = <0>; 45 }; 46 47 es8388_sound: es8388-sound { 48 status = "okay"; 49 compatible = "rockchip,multicodecs-card"; 50 rockchip,card-name = "rockchip,es8388"; 51 hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 52 io-channels = <&saradc 3>; 53 io-channel-names = "adc-detect"; 54 keyup-threshold-microvolt = <1800000>; 55 poll-interval = <100>; 56 spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 57 hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; 58 rockchip,format = "i2s"; 59 rockchip,mclk-fs = <256>; 60 rockchip,cpu = <&i2s0_8ch>; 61 rockchip,codec = <&es8388>; 62 rockchip,audio-routing = 63 "Headphone", "LOUT1", 64 "Headphone", "ROUT1", 65 "Speaker", "LOUT2", 66 "Speaker", "ROUT2", 67 "Headphone", "Headphone Power", 68 "Headphone", "Headphone Power", 69 "Speaker", "Speaker Power", 70 "Speaker", "Speaker Power", 71 "LINPUT1", "Main Mic", 72 "LINPUT2", "Main Mic", 73 "RINPUT1", "Headset Mic", 74 "RINPUT2", "Headset Mic"; 75 pinctrl-names = "default"; 76 pinctrl-0 = <&hp_det>; 77 play-pause-key { 78 label = "playpause"; 79 linux,code = <KEY_PLAYPAUSE>; 80 press-threshold-microvolt = <2000>; 81 }; 82 }; 83 84 hdmiin-sound { 85 compatible = "simple-audio-card"; 86 simple-audio-card,format = "i2s"; 87 simple-audio-card,name = "rockchip,hdmiin"; 88 simple-audio-card,bitclock-master = <&dailink0_master>; 89 simple-audio-card,frame-master = <&dailink0_master>; 90 status = "okay"; 91 simple-audio-card,cpu { 92 sound-dai = <&i2s7_8ch>; 93 }; 94 dailink0_master: simple-audio-card,codec { 95 sound-dai = <&hdmiin_dc>; 96 }; 97 }; 98 99 pcie20_avdd0v85: pcie20-avdd0v85 { 100 compatible = "regulator-fixed"; 101 regulator-name = "pcie20_avdd0v85"; 102 regulator-boot-on; 103 regulator-always-on; 104 regulator-min-microvolt = <850000>; 105 regulator-max-microvolt = <850000>; 106 vin-supply = <&vdd_0v85_s0>; 107 }; 108 109 pcie20_avdd1v8: pcie20-avdd1v8 { 110 compatible = "regulator-fixed"; 111 regulator-name = "pcie20_avdd1v8"; 112 regulator-boot-on; 113 regulator-always-on; 114 regulator-min-microvolt = <1800000>; 115 regulator-max-microvolt = <1800000>; 116 vin-supply = <&avcc_1v8_s0>; 117 }; 118 119 pcie30_avdd0v75: pcie30-avdd0v75 { 120 compatible = "regulator-fixed"; 121 regulator-name = "pcie30_avdd0v75"; 122 regulator-boot-on; 123 regulator-always-on; 124 regulator-min-microvolt = <750000>; 125 regulator-max-microvolt = <750000>; 126 vin-supply = <&avdd_0v75_s0>; 127 }; 128 129 pcie30_avdd1v8: pcie30-avdd1v8 { 130 compatible = "regulator-fixed"; 131 regulator-name = "pcie30_avdd1v8"; 132 regulator-boot-on; 133 regulator-always-on; 134 regulator-min-microvolt = <1800000>; 135 regulator-max-microvolt = <1800000>; 136 vin-supply = <&avcc_1v8_s0>; 137 }; 138 139 rk_headset: rk-headset { 140 status = "disabled"; 141 compatible = "rockchip_headset"; 142 headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 143 pinctrl-names = "default"; 144 pinctrl-0 = <&hp_det>; 145 io-channels = <&saradc 3>; 146 }; 147 148 vbus5v0_typec: vbus5v0-typec { 149 compatible = "regulator-fixed"; 150 regulator-name = "vbus5v0_typec"; 151 regulator-min-microvolt = <5000000>; 152 regulator-max-microvolt = <5000000>; 153 enable-active-high; 154 gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; 155 vin-supply = <&vcc5v0_usb>; 156 pinctrl-names = "default"; 157 pinctrl-0 = <&typec5v_pwren>; 158 }; 159 160 vcc3v3_lcd_n: vcc3v3-lcd0-n { 161 compatible = "regulator-fixed"; 162 regulator-name = "vcc3v3_lcd0_n"; 163 regulator-boot-on; 164 enable-active-high; 165 gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; 166 vin-supply = <&vcc_1v8_s0>; 167 }; 168 169 vcc3v3_pcie30: vcc3v3-pcie30 { 170 compatible = "regulator-fixed"; 171 regulator-name = "vcc3v3_pcie30"; 172 regulator-min-microvolt = <3300000>; 173 regulator-max-microvolt = <3300000>; 174 enable-active-high; 175 gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; 176 startup-delay-us = <5000>; 177 vin-supply = <&vcc12v_dcin>; 178 }; 179 180 vcc5v0_host: vcc5v0-host { 181 compatible = "regulator-fixed"; 182 regulator-name = "vcc5v0_host"; 183 regulator-boot-on; 184 regulator-always-on; 185 regulator-min-microvolt = <5000000>; 186 regulator-max-microvolt = <5000000>; 187 enable-active-high; 188 gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 189 vin-supply = <&vcc5v0_usb>; 190 pinctrl-names = "default"; 191 pinctrl-0 = <&vcc5v0_host_en>; 192 }; 193 194 vcc_mipicsi0: vcc-mipicsi0-regulator { 195 compatible = "regulator-fixed"; 196 regulator-name = "vcc_mipicsi0"; 197 enable-active-high; 198 }; 199 200 vcc_mipicsi1: vcc-mipicsi1-regulator { 201 compatible = "regulator-fixed"; 202 regulator-name = "vcc_mipicsi1"; 203 enable-active-high; 204 }; 205 206 vcc_mipidcphy0: vcc-mipidcphy0-regulator { 207 compatible = "regulator-fixed"; 208 regulator-name = "vcc_mipicsi1"; 209 enable-active-high; 210 }; 211 212 wireless_bluetooth: wireless-bluetooth { 213 compatible = "bluetooth-platdata"; 214 clocks = <&hym8563>; 215 clock-names = "ext_clock"; 216 uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; 217 pinctrl-names = "default", "rts_gpio"; 218 pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 219 pinctrl-1 = <&uart8_gpios>; 220 BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 221 BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 222 BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; 223 status = "okay"; 224 }; 225 226 wireless_wlan: wireless-wlan { 227 compatible = "wlan-platdata"; 228 wifi_chip_type = "ap6255"; 229 pinctrl-names = "default"; 230 pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; 231 WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; 232 WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 233 status = "okay"; 234 }; 235}; 236 237&backlight { 238 pwms = <&pwm2 0 25000 0>; 239 status = "okay"; 240}; 241 242&can2 { 243 status = "okay"; 244}; 245 246&combphy0_ps { 247 status = "okay"; 248}; 249 250&combphy1_ps { 251 status = "okay"; 252}; 253 254&combphy2_psu { 255 status = "okay"; 256}; 257 258&dp0 { 259 status = "okay"; 260}; 261 262&dp0_in_vp2 { 263 status = "okay"; 264}; 265 266/* 267 * mipi_dcphy0 needs to be enabled 268 * when dsi0 is enabled 269 */ 270&dsi0 { 271 status = "disabled"; 272}; 273 274&dsi0_in_vp2 { 275 status = "disabled"; 276}; 277 278&dsi0_in_vp3 { 279 status = "okay"; 280}; 281 282&dsi0_panel { 283 power-supply = <&vcc3v3_lcd_n>; 284 reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 285 pinctrl-names = "default"; 286 pinctrl-0 = <&lcd_rst_gpio>; 287}; 288 289/* 290 * mipi_dcphy1 needs to be enabled 291 * when dsi1 is enabled 292 */ 293&dsi1 { 294 status = "disabled"; 295}; 296 297&dsi1_in_vp2 { 298 status = "disabled"; 299}; 300 301&dsi1_in_vp3 { 302 status = "disabled"; 303}; 304 305&dsi1_panel { 306 power-supply = <&vcc3v3_lcd_n>; 307 308 /* 309 * because in hardware, the two screens share the reset pin, 310 * so reset-gpios need only in dsi1 enable and dsi0 disabled 311 * case. 312 */ 313 314 //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 315 //pinctrl-names = "default"; 316 //pinctrl-0 = <&lcd_rst_gpio>; 317}; 318 319&gmac0 { 320 /* Use rgmii-rxid mode to disable rx delay inside Soc */ 321 phy-mode = "rgmii-rxid"; 322 clock_in_out = "output"; 323 324 snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; 325 snps,reset-active-low; 326 /* Reset time is 20ms, 100ms for rtl8211f */ 327 snps,reset-delays-us = <0 20000 100000>; 328 329 pinctrl-names = "default"; 330 pinctrl-0 = <&gmac0_miim 331 &gmac0_tx_bus2 332 &gmac0_rx_bus2 333 &gmac0_rgmii_clk 334 &gmac0_rgmii_bus>; 335 336 tx_delay = <0x43>; 337 /* rx_delay = <0x3f>; */ 338 339 phy-handle = <&rgmii_phy>; 340 status = "okay"; 341}; 342 343&hdmi0 { 344 enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 345 status = "okay"; 346}; 347 348&hdmi0_in_vp0 { 349 status = "okay"; 350}; 351 352&hdmi0_sound { 353 status = "okay"; 354}; 355 356/* Should work with at least 128MB cma reserved above. */ 357&hdmirx_ctrler { 358 status = "okay"; 359 360 /* Effective level used to trigger HPD: 0-low, 1-high */ 361 hpd-trigger-level = <1>; 362 hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 363 pinctrl-names = "default"; 364 pinctrl-0 = <&hdmim1_rx &hdmirx_det>; 365}; 366 367&hdptxphy_hdmi0 { 368 status = "okay"; 369}; 370 371&i2c0 { 372 status = "okay"; 373 374 vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 375 compatible = "rockchip,rk8602"; 376 reg = <0x42>; 377 vin-supply = <&vcc5v0_sys>; 378 regulator-compatible = "rk860x-reg"; 379 regulator-name = "vdd_cpu_big0_s0"; 380 regulator-min-microvolt = <550000>; 381 regulator-max-microvolt = <1050000>; 382 regulator-ramp-delay = <2300>; 383 rockchip,suspend-voltage-selector = <1>; 384 regulator-boot-on; 385 regulator-always-on; 386 regulator-state-mem { 387 regulator-off-in-suspend; 388 }; 389 }; 390 391 vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 392 compatible = "rockchip,rk8603"; 393 reg = <0x43>; 394 vin-supply = <&vcc5v0_sys>; 395 regulator-compatible = "rk860x-reg"; 396 regulator-name = "vdd_cpu_big1_s0"; 397 regulator-min-microvolt = <550000>; 398 regulator-max-microvolt = <1050000>; 399 regulator-ramp-delay = <2300>; 400 rockchip,suspend-voltage-selector = <1>; 401 regulator-boot-on; 402 regulator-always-on; 403 regulator-state-mem { 404 regulator-off-in-suspend; 405 }; 406 }; 407}; 408 409&i2c2 { 410 status = "okay"; 411 clock-frequency = <400000>; 412 413 usbc0: husb311@4e { 414 compatible = "hynetek,husb311"; 415 reg = <0x4e>; 416 interrupt-parent = <&gpio3>; 417 interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; 418 pinctrl-names = "default"; 419 pinctrl-0 = <&usbc0_int>; 420 vbus-supply = <&vbus5v0_typec>; 421 status = "okay"; 422 423 ports { 424 #address-cells = <1>; 425 #size-cells = <0>; 426 427 port@0 { 428 reg = <0>; 429 usbc0_role_sw: endpoint@0 { 430 remote-endpoint = <&dwc3_0_role_switch>; 431 }; 432 }; 433 }; 434 435 usb_con: connector { 436 compatible = "usb-c-connector"; 437 label = "USB-C"; 438 data-role = "dual"; 439 power-role = "dual"; 440 try-power-role = "sink"; 441 op-sink-microwatt = <1000000>; 442 sink-pdos = 443 <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 444 source-pdos = 445 <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 446 447 altmodes { 448 #address-cells = <1>; 449 #size-cells = <0>; 450 451 altmode@0 { 452 reg = <0>; 453 svid = <0xff01>; 454 vdo = <0xffffffff>; 455 }; 456 }; 457 458 ports { 459 #address-cells = <1>; 460 #size-cells = <0>; 461 462 port@0 { 463 reg = <0>; 464 usbc0_orien_sw: endpoint { 465 remote-endpoint = <&usbdp_phy0_orientation_switch>; 466 }; 467 }; 468 469 port@1 { 470 reg = <1>; 471 dp_altmode_mux: endpoint { 472 remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 473 }; 474 }; 475 }; 476 }; 477 }; 478 479 hym8563: hym8563@51 { 480 compatible = "haoyu,hym8563"; 481 reg = <0x51>; 482 #clock-cells = <0>; 483 clock-frequency = <32768>; 484 clock-output-names = "hym8563"; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&hym8563_int>; 487 interrupt-parent = <&gpio0>; 488 interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; 489 }; 490 491 vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 492 compatible = "rockchip,rk8602"; 493 reg = <0x42>; 494 vin-supply = <&vcc5v0_sys>; 495 regulator-compatible = "rk860x-reg"; 496 regulator-name = "vdd_npu_s0"; 497 regulator-min-microvolt = <550000>; 498 regulator-max-microvolt = <950000>; 499 regulator-ramp-delay = <2300>; 500 rockchip,suspend-voltage-selector = <1>; 501 regulator-boot-on; 502 regulator-always-on; 503 regulator-state-mem { 504 regulator-off-in-suspend; 505 }; 506 }; 507}; 508 509&i2c6 { 510 status = "disabled"; 511 gt1x: gt1x@14 { 512 compatible = "goodix,gt1x"; 513 reg = <0x14>; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&touch_gpio>; 516 goodix,rst-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; 517 goodix,irq-gpio = <&gpio0 RK_PB0 IRQ_TYPE_LEVEL_LOW>; 518 power-supply = <&vcc3v3_lcd_n>; 519 }; 520 521 gsl3673: gsl3673@40 { 522 compatible = "GSL,GSL3673"; 523 reg = <0x40>; 524 screen_max_x = <1536>; 525 screen_max_y = <2048>; 526 irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>; 527 rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; 528 }; 529}; 530 531&i2c7 { 532 status = "okay"; 533 es8388: es8388@11 { 534 status = "okay"; 535 #sound-dai-cells = <0>; 536 compatible = "everest,es8388", "everest,es8323"; 537 reg = <0x11>; 538 clocks = <&mclkout_i2s0>; 539 clock-names = "mclk"; 540 assigned-clocks = <&mclkout_i2s0>; 541 assigned-clock-rates = <12288000>; 542 pinctrl-names = "default"; 543 pinctrl-0 = <&i2s0_mclk>; 544 }; 545}; 546 547&i2s5_8ch { 548 status = "okay"; 549}; 550 551&i2s7_8ch { 552 status = "okay"; 553}; 554 555&mdio0 { 556 rgmii_phy: phy@1 { 557 compatible = "ethernet-phy-ieee802.3-c22"; 558 reg = <0x1>; 559 }; 560}; 561 562&mipi_dcphy0 { 563 status = "okay"; 564}; 565 566&mipi_dcphy1 { 567 status = "disabled"; 568}; 569 570&pcie2x1l0 { 571 reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 572 rockchip,skip-scan-in-resume; 573 status = "okay"; 574}; 575 576&pcie2x1l1 { 577 reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 578 pinctrl-names = "default"; 579 pinctrl-0 = <&rtl8111_isolate>; 580 status = "okay"; 581}; 582 583&pcie30phy { 584 rockchip,pcie30-phymode = <PHY_MODE_PCIE_NANBNB>; 585 status = "okay"; 586}; 587 588&pcie3x4 { 589 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 590 vpcie3v3-supply = <&vcc3v3_pcie30>; 591 num-lanes=<2>; 592 status = "okay"; 593}; 594 595&pinctrl { 596 hdmi { 597 hdmirx_det: hdmirx-det { 598 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; 599 }; 600 }; 601 602 headphone { 603 hp_det: hp-det { 604 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 605 }; 606 }; 607 608 hym8563 { 609 hym8563_int: hym8563-int { 610 rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 611 }; 612 }; 613 614 lcd { 615 lcd_rst_gpio: lcd-rst-gpio { 616 rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 617 }; 618 }; 619 620 rtl8111 { 621 rtl8111_isolate: rtl8111-isolate { 622 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 623 }; 624 }; 625 626 touch { 627 touch_gpio: touch-gpio { 628 rockchip,pins = 629 <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, 630 <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 631 }; 632 }; 633 634 usb { 635 vcc5v0_host_en: vcc5v0-host-en { 636 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 637 }; 638 }; 639 640 usb-typec { 641 usbc0_int: usbc0-int { 642 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 643 }; 644 645 typec5v_pwren: typec5v-pwren { 646 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 647 }; 648 }; 649 650 wireless-bluetooth { 651 uart8_gpios: uart8-gpios { 652 rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 653 }; 654 655 bt_reset_gpio: bt-reset-gpio { 656 rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 657 }; 658 659 bt_wake_gpio: bt-wake-gpio { 660 rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; 661 }; 662 663 bt_irq_gpio: bt-irq-gpio { 664 rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; 665 }; 666 }; 667 668 wireless-wlan { 669 wifi_host_wake_irq: wifi-host-wake-irq { 670 rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; 671 }; 672 673 wifi_poweren_gpio: wifi-poweren-gpio { 674 rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 675 }; 676 }; 677}; 678 679&pwm2 { 680 status = "okay"; 681}; 682 683&pwm9 { 684 pinctrl-0 = <&pwm9m1_pins>; 685 status = "okay"; 686}; 687 688&sata0 { 689 status = "okay"; 690}; 691 692&u2phy1_otg { 693 phy-supply = <&vcc5v0_host>; 694}; 695 696&u2phy2_host { 697 phy-supply = <&vcc5v0_host>; 698}; 699 700&u2phy3_host { 701 phy-supply = <&vcc5v0_host>; 702}; 703 704&uart8 { 705 status = "okay"; 706 pinctrl-names = "default"; 707 pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; 708}; 709 710&usbdp_phy0 { 711 orientation-switch; 712 svid = <0xff01>; 713 sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 714 sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 715 716 port { 717 #address-cells = <1>; 718 #size-cells = <0>; 719 usbdp_phy0_orientation_switch: endpoint@0 { 720 reg = <0>; 721 remote-endpoint = <&usbc0_orien_sw>; 722 }; 723 724 usbdp_phy0_dp_altmode_mux: endpoint@1 { 725 reg = <1>; 726 remote-endpoint = <&dp_altmode_mux>; 727 }; 728 }; 729}; 730 731&usbdp_phy1 { 732 rockchip,dp-lane-mux = <2 3>; 733}; 734 735&usbdrd_dwc3_0 { 736 dr_mode = "otg"; 737 usb-role-switch; 738 port { 739 #address-cells = <1>; 740 #size-cells = <0>; 741 dwc3_0_role_switch: endpoint@0 { 742 reg = <0>; 743 remote-endpoint = <&usbc0_role_sw>; 744 }; 745 }; 746}; 747 748&usbhost3_0 { 749 status = "disabled"; 750}; 751 752&usbhost_dwc3_0 { 753 status = "disabled"; 754}; 755