1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "dt-bindings/usb/pd.h" 8#include "rk3588.dtsi" 9#include "rk3588-toybrick.dtsi" 10#include "rk3588-rk806-single.dtsi" 11 12/ { 13 es8388_sound: es8388-sound { 14 status = "okay"; 15 compatible = "simple-audio-card"; 16 simple-audio-card,format = "i2s"; 17 simple-audio-card,mclk-fs = <256>; 18 simple-audio-card,name = "rockchip,es8388-codec"; 19 simple-audio-card,dai-link@0 { 20 format = "i2s"; 21 cpu { 22 sound-dai = <&i2s0_8ch>; 23 }; 24 codec { 25 sound-dai = <&es8388>; 26 }; 27 }; 28 }; 29 30 pcie20_avdd0v85: pcie20-avdd0v85 { 31 compatible = "regulator-fixed"; 32 regulator-name = "pcie20_avdd0v85"; 33 regulator-boot-on; 34 regulator-min-microvolt = <850000>; 35 regulator-max-microvolt = <850000>; 36 vin-supply = <&vdd_0v85_s0>;//csq 37 }; 38 39 pcie20_avdd1v8: pcie20-avdd1v8 { 40 compatible = "regulator-fixed"; 41 regulator-name = "pcie20_avdd1v8"; 42 regulator-boot-on; 43 regulator-min-microvolt = <1800000>; 44 regulator-max-microvolt = <1800000>; 45 vin-supply = <&avcc_1v8_s0>; 46 }; 47 48 pcie30_avdd0v75: pcie30-avdd0v75 { 49 compatible = "regulator-fixed"; 50 regulator-name = "pcie30_avdd0v75"; 51 regulator-boot-on; 52 regulator-min-microvolt = <750000>; 53 regulator-max-microvolt = <750000>; 54 vin-supply = <&avdd_0v75_s0>; 55 }; 56 57 pcie30_avdd1v8: pcie30-avdd1v8 { 58 compatible = "regulator-fixed"; 59 regulator-name = "pcie30_avdd1v8"; 60 regulator-boot-on; 61 regulator-min-microvolt = <1800000>; 62 regulator-max-microvolt = <1800000>; 63 vin-supply = <&avcc_1v8_s0>; 64 }; 65 66 rk_headset: rk-headset { 67 status = "okay"; 68 compatible = "rockchip_headset"; 69 headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 70 pinctrl-names = "default"; 71 pinctrl-0 = <&hp_det>; 72 io-channels = <&saradc 3>; 73 }; 74 75 vbus5v0_typec: vbus5v0-typec { 76 compatible = "regulator-fixed"; 77 regulator-name = "vbus5v0_typec"; 78 regulator-min-microvolt = <5000000>; 79 regulator-max-microvolt = <5000000>; 80 enable-active-high; 81 gpio = <&gpio4 RK_PD0 GPIO_ACTIVE_HIGH>; 82 vin-supply = <&vcc5v0_usb>; 83 pinctrl-names = "default"; 84 pinctrl-0 = <&typec5v_pwren>; 85 }; 86 87 vcc3v3_lcd_n: vcc3v3-lcd0-n { 88 compatible = "regulator-fixed"; 89 regulator-name = "vcc3v3_lcd0_n"; 90 regulator-boot-on; 91 enable-active-high; 92 gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>; 93 vin-supply = <&vcc_1v8_s0>; 94 }; 95 96 vcc3v3_pcie30: vcc3v3-pcie30 { 97 compatible = "regulator-fixed"; 98 regulator-name = "vcc3v3_pcie30"; 99 regulator-min-microvolt = <3300000>; 100 regulator-max-microvolt = <3300000>; 101 enable-active-high; 102 gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; 103 startup-delay-us = <5000>; 104 vin-supply = <&vcc12v_dcin>; 105 }; 106 107 vcc5v0_host: vcc5v0-host { 108 compatible = "regulator-fixed"; 109 regulator-name = "vcc5v0_host"; 110 regulator-boot-on; 111 regulator-always-on; 112 regulator-min-microvolt = <5000000>; 113 regulator-max-microvolt = <5000000>; 114 enable-active-high; 115 gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&vcc5v0_usb>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&vcc5v0_host_en>; 119 }; 120 121 vcc_mipicsi0: vcc-mipicsi0-regulator { 122 compatible = "regulator-fixed"; 123 gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 124 pinctrl-names = "default"; 125 pinctrl-0 = <&mipicsi0_pwr>; 126 regulator-name = "vcc_mipicsi0"; 127 enable-active-high; 128 }; 129 130 vcc_mipicsi1: vcc-mipicsi1-regulator { 131 compatible = "regulator-fixed"; 132 gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 133 pinctrl-names = "default"; 134 pinctrl-0 = <&mipicsi1_pwr>; 135 regulator-name = "vcc_mipicsi1"; 136 enable-active-high; 137 }; 138 139 vcc_mipidcphy0: vcc-mipidcphy0-regulator { 140 compatible = "regulator-fixed"; 141 gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&mipidcphy0_pwr>; 144 regulator-name = "vcc_mipicsi1"; 145 enable-active-high; 146 }; 147 148 wireless_bluetooth: wireless-bluetooth { 149 compatible = "bluetooth-platdata"; 150 clocks = <&hym8563>; 151 clock-names = "ext_clock"; 152 uart_rts_gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; 153 pinctrl-names = "default", "rts_gpio"; 154 pinctrl-0 = <&uart8m1_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 155 pinctrl-1 = <&uart8_gpios>; 156 BT,reset_gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 157 BT,wake_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 158 BT,wake_host_irq = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; 159 status = "okay"; 160 }; 161 162 wireless_wlan: wireless-wlan { 163 compatible = "wlan-platdata"; 164 wifi_chip_type = "ap6255"; 165 pinctrl-names = "default"; 166 pinctrl-0 = <&wifi_host_wake_irq>, <&wifi_poweren_gpio>; 167 WIFI,host_wake_irq = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>; 168 WIFI,poweren_gpio = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>; 169 status = "okay"; 170 }; 171 172 panel-edp { 173 compatible = "innolux,p120zdg-bf4", "simple-panel"; 174 backlight = <&backlight>; 175 power-supply = <&vcc3v3_lcd_edp>; 176 prepare-delay-ms = <120>; 177 enable-delay-ms = <120>; 178 unprepare-delay-ms = <500>; 179 disable-delay-ms = <120>; 180 width-mm = <254>; 181 height-mm = <169>; 182 panel-timing { 183 clock-frequency = <200000000>; 184 hactive = <1536>; 185 vactive = <2048>; 186 hfront-porch = <12>; 187 hsync-len = <16>; 188 hback-porch = <48>; 189 vfront-porch = <8>; 190 vsync-len = <4>; 191 vback-porch = <8>; 192 hsync-active = <0>; 193 vsync-active = <0>; 194 de-active = <0>; 195 pixelclk-active = <0>; 196 }; 197 198 port { 199 panel_in_edp: endpoint { 200 remote-endpoint = <&edp_out_panel>; 201 }; 202 }; 203 }; 204 205 vcc3v3_lcd_edp: vcc3v3-lcd-edp { 206 compatible = "regulator-fixed"; 207 regulator-name = "vcc3v3_lcd_edp"; 208 gpio = <&gpio1 RK_PA5 GPIO_ACTIVE_HIGH>; 209 enable-active-high; 210 vin-supply = <&vcc_3v3_s3>; 211 }; 212}; 213 214&backlight { 215 pwms = <&pwm2 0 25000 0>; 216 status = "okay"; 217}; 218 219&combphy0_ps { 220 status = "okay"; 221}; 222 223&combphy1_ps { 224 status = "okay"; 225}; 226 227&combphy2_psu { 228 status = "okay"; 229}; 230 231&dp0 { 232 status = "disabled"; 233}; 234 235&dp0_in_vp2 { 236 status = "disabled"; 237}; 238 239&dp1 { 240 pinctrl-names = "default"; 241 pinctrl-0 = <&dp1_hpd>; 242 hpd-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; 243 status = "disabled"; 244}; 245 246&dp1_in_vp2 { 247 status = "disabled"; 248}; 249 250/* 251 * mipi_dcphy0 needs to be enabled 252 * when dsi0 is enabled 253 */ 254&dsi0 { 255 status = "disabled"; 256}; 257 258&dsi0_in_vp2 { 259 status = "disabled"; 260}; 261 262&dsi0_in_vp3 { 263 status = "disabled"; 264}; 265 266&edp1 { 267 force-hpd; 268 status = "okay"; 269 ports { 270 port@1 { 271 reg = <1>; 272 edp_out_panel: endpoint { 273 remote-endpoint = <&panel_in_edp>; 274 }; 275 }; 276 }; 277}; 278 279&edp1_in_vp2 { 280 status = "okay"; 281}; 282 283&hdptxphy1 { 284 status = "okay"; 285}; 286 287&dsi0_panel { 288 power-supply = <&vcc3v3_lcd_n>; 289 reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 290 pinctrl-names = "default"; 291 pinctrl-0 = <&lcd_rst_gpio>; 292}; 293 294/* 295 * mipi_dcphy1 needs to be enabled 296 * when dsi1 is enabled 297 */ 298&dsi1 { 299 status = "disabled"; 300}; 301 302&dsi1_in_vp2 { 303 status = "disabled"; 304}; 305 306&dsi1_in_vp3 { 307 status = "disabled"; 308}; 309 310&dsi1_panel { 311 power-supply = <&vcc3v3_lcd_n>; 312 313 /* 314 * because in hardware, the two screens share the reset pin, 315 * so reset-gpios need only in dsi1 enable and dsi0 disabled 316 * case. 317 */ 318 319 //reset-gpios = <&gpio2 RK_PB4 GPIO_ACTIVE_LOW>; 320 //pinctrl-names = "default"; 321 //pinctrl-0 = <&lcd_rst_gpio>; 322}; 323 324&gmac0 { 325 /* Use rgmii-rxid mode to disable rx delay inside Soc */ 326 phy-mode = "rgmii-rxid"; 327 clock_in_out = "output"; 328 329 snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; 330 snps,reset-active-low; 331 /* Reset time is 20ms, 100ms for rtl8211f */ 332 snps,reset-delays-us = <0 20000 100000>; 333 334 pinctrl-names = "default"; 335 pinctrl-0 = <&gmac0_miim 336 &gmac0_tx_bus2 337 &gmac0_rx_bus2 338 &gmac0_rgmii_clk 339 &gmac0_rgmii_bus>; 340 341 tx_delay = <0x43>; 342 /* rx_delay = <0x3f>; */ 343 344 phy-handle = <&rgmii_phy>; 345 status = "okay"; 346}; 347 348&hdmi0 { 349 enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 350 status = "okay"; 351}; 352 353&hdmi0_in_vp0 { 354 status = "okay"; 355}; 356 357&hdmi0_sound { 358 status = "okay"; 359}; 360 361&hdptxphy_hdmi0 { 362 status = "okay"; 363}; 364 365&i2c0 { 366 status = "okay"; 367 368 vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 369 compatible = "rockchip,rk8602"; 370 reg = <0x42>; 371 vin-supply = <&vcc5v0_sys>; 372 regulator-compatible = "rk860x-reg"; 373 regulator-name = "vdd_cpu_big0_s0"; 374 regulator-min-microvolt = <550000>; 375 regulator-max-microvolt = <1050000>; 376 regulator-ramp-delay = <2300>; 377 rockchip,suspend-voltage-selector = <1>; 378 regulator-boot-on; 379 regulator-always-on; 380 regulator-state-mem { 381 regulator-off-in-suspend; 382 }; 383 }; 384 385 vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 386 compatible = "rockchip,rk8603"; 387 reg = <0x43>; 388 vin-supply = <&vcc5v0_sys>; 389 regulator-compatible = "rk860x-reg"; 390 regulator-name = "vdd_cpu_big1_s0"; 391 regulator-min-microvolt = <550000>; 392 regulator-max-microvolt = <1050000>; 393 regulator-ramp-delay = <2300>; 394 rockchip,suspend-voltage-selector = <1>; 395 regulator-boot-on; 396 regulator-always-on; 397 regulator-state-mem { 398 regulator-off-in-suspend; 399 }; 400 }; 401}; 402 403&i2c2 { 404 status = "okay"; 405 406 usbc0: fusb302@22 { 407 compatible = "fcs,fusb302"; 408 reg = <0x22>; 409 interrupt-parent = <&gpio3>; 410 interrupts = <RK_PB4 IRQ_TYPE_LEVEL_LOW>; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&usbc0_int>; 413 vbus-supply = <&vbus5v0_typec>; 414 status = "okay"; 415 416 ports { 417 #address-cells = <1>; 418 #size-cells = <0>; 419 420 port@0 { 421 reg = <0>; 422 usbc0_role_sw: endpoint@0 { 423 remote-endpoint = <&dwc3_0_role_switch>; 424 }; 425 }; 426 }; 427 428 usb_con: connector { 429 compatible = "usb-c-connector"; 430 label = "USB-C"; 431 data-role = "dual"; 432 power-role = "dual"; 433 try-power-role = "sink"; 434 op-sink-microwatt = <1000000>; 435 sink-pdos = 436 <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>; 437 source-pdos = 438 <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 439 440 altmodes { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 444 altmode@0 { 445 reg = <0>; 446 svid = <0xff01>; 447 vdo = <0xffffffff>; 448 }; 449 }; 450 451 ports { 452 #address-cells = <1>; 453 #size-cells = <0>; 454 455 port@0 { 456 reg = <0>; 457 usbc0_orien_sw: endpoint { 458 remote-endpoint = <&usbdp_phy0_orientation_switch>; 459 }; 460 }; 461 462 port@1 { 463 reg = <1>; 464 dp_altmode_mux: endpoint { 465 remote-endpoint = <&usbdp_phy0_dp_altmode_mux>; 466 }; 467 }; 468 }; 469 }; 470 }; 471 472 hym8563: hym8563@51 { 473 compatible = "haoyu,hym8563"; 474 reg = <0x51>; 475 #clock-cells = <0>; 476 clock-frequency = <32768>; 477 clock-output-names = "hym8563"; 478 pinctrl-names = "default"; 479 pinctrl-0 = <&hym8563_int>; 480 interrupt-parent = <&gpio0>; 481 interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>; 482 }; 483 484 vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 485 compatible = "rockchip,rk8602"; 486 reg = <0x42>; 487 vin-supply = <&vcc5v0_sys>; 488 regulator-compatible = "rk860x-reg"; 489 regulator-name = "vdd_npu_s0"; 490 regulator-min-microvolt = <550000>; 491 regulator-max-microvolt = <950000>; 492 regulator-ramp-delay = <2300>; 493 rockchip,suspend-voltage-selector = <1>; 494 regulator-boot-on; 495 regulator-always-on; 496 regulator-state-mem { 497 regulator-off-in-suspend; 498 }; 499 }; 500}; 501 502&i2c6 { 503 status = "okay"; 504 gt1x: gt1x@14 { 505 compatible = "goodix,gt1x"; 506 reg = <0x14>; 507 pinctrl-names = "default"; 508 pinctrl-0 = <&touch_gpio>; 509 goodix,rst-gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>; 510 goodix,irq-gpio = <&gpio0 RK_PB0 IRQ_TYPE_LEVEL_LOW>; 511 }; 512 513 gsl3673: gsl3673@40 { 514 compatible = "GSL,GSL3673"; 515 reg = <0x40>; 516 screen_max_x = <1536>; 517 screen_max_y = <2048>; 518 irq_gpio_number = <&gpio1 RK_PA6 IRQ_TYPE_LEVEL_LOW>; 519 rst_gpio_number = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>; 520 }; 521}; 522 523&i2c7 { 524 status = "okay"; 525 es8388: es8388@11 { 526 status = "okay"; 527 #sound-dai-cells = <0>; 528 compatible = "everest,es8388", "everest,es8323"; 529 reg = <0x11>; 530 clocks = <&mclkout_i2s0>; 531 clock-names = "mclk"; 532 assigned-clocks = <&mclkout_i2s0>; 533 assigned-clock-rates = <12288000>; 534 pinctrl-names = "default"; 535 pinctrl-0 = <&i2s0_mclk>; 536 spk-con-gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 537 hp-con-gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; 538 extcon = <&rk_headset>; 539 }; 540}; 541 542&hdmirx_ctrler { 543 status = "okay"; 544 hdmirx-det-gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&hdmim1_rx &hdmirx_det>; 547}; 548 549&i2s5_8ch { 550 status = "okay"; 551}; 552 553&mdio0 { 554 rgmii_phy: phy@1 { 555 compatible = "ethernet-phy-ieee802.3-c22"; 556 reg = <0x1>; 557 }; 558}; 559 560&mipi_dcphy0 { 561 status = "okay"; 562}; 563 564&mipi_dcphy1 { 565 status = "disabled"; 566}; 567 568&pcie2x1l0 { 569 reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 570 status = "okay"; 571}; 572 573&pcie2x1l1 { 574 reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 575 pinctrl-names = "default"; 576 pinctrl-0 = <&rtl8111_isolate>; 577 status = "okay"; 578}; 579 580&pcie30phy { 581 rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>; 582 status = "okay"; 583}; 584 585&pcie3x4 { 586 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 587 vpcie3v3-supply = <&vcc3v3_pcie30>; 588 status = "disabled"; 589}; 590 591&pinctrl { 592 cam { 593 mipicsi0_pwr: mipicsi0-pwr { 594 rockchip,pins = 595 /* camera power en */ 596 <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 597 }; 598 mipicsi1_pwr: mipicsi1-pwr { 599 rockchip,pins = 600 /* camera power en */ 601 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 602 }; 603 mipidcphy0_pwr: mipidcphy0-pwr { 604 rockchip,pins = 605 /* camera power en */ 606 <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 607 }; 608 }; 609 610 dp { 611 dp1_hpd: dp1-hpd { 612 rockchip,pins = <1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 613 }; 614 }; 615 616 hdmi { 617 hdmirx_det: hdmirx-det { 618 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>; 619 }; 620 }; 621 622 headphone { 623 hp_det: hp-det { 624 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 625 }; 626 }; 627 628 hym8563 { 629 hym8563_int: hym8563-int { 630 rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>; 631 }; 632 }; 633 634 lcd { 635 lcd_rst_gpio: lcd-rst-gpio { 636 rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 637 }; 638 }; 639 640 rtl8111 { 641 rtl8111_isolate: rtl8111-isolate { 642 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 643 }; 644 }; 645 646 touch { 647 touch_gpio: touch-gpio { 648 rockchip,pins = 649 <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, 650 <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 651 }; 652 }; 653 654 usb { 655 vcc5v0_host_en: vcc5v0-host-en { 656 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 657 }; 658 }; 659 660 usb-typec { 661 usbc0_int: usbc0-int { 662 rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>; 663 }; 664 665 typec5v_pwren: typec5v-pwren { 666 rockchip,pins = <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; 667 }; 668 }; 669 670 wireless-bluetooth { 671 uart8_gpios: uart8-gpios { 672 rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 673 }; 674 675 bt_reset_gpio: bt-reset-gpio { 676 rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 677 }; 678 679 bt_wake_gpio: bt-wake-gpio { 680 rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; 681 }; 682 683 bt_irq_gpio: bt-irq-gpio { 684 rockchip,pins = <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; 685 }; 686 }; 687 688 wireless-wlan { 689 wifi_host_wake_irq: wifi-host-wake-irq { 690 rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>; 691 }; 692 693 wifi_poweren_gpio: wifi-poweren-gpio { 694 rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; 695 }; 696 }; 697}; 698 699&pwm2 { 700 status = "okay"; 701}; 702 703&sata0 { 704 status = "okay"; 705}; 706 707&u2phy1_otg { 708 phy-supply = <&vcc5v0_host>; 709}; 710 711&u2phy2_host { 712 phy-supply = <&vcc5v0_host>; 713}; 714 715&u2phy3_host { 716 phy-supply = <&vcc5v0_host>; 717}; 718 719&uart8 { 720 status = "okay"; 721 pinctrl-names = "default"; 722 pinctrl-0 = <&uart8m1_xfer &uart8m1_ctsn>; 723}; 724 725&usbdp_phy0 { 726 orientation-switch; 727 svid = <0xff01>; 728 sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 729 sbu2-dc-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 730 731 port { 732 #address-cells = <1>; 733 #size-cells = <0>; 734 usbdp_phy0_orientation_switch: endpoint@0 { 735 reg = <0>; 736 remote-endpoint = <&usbc0_orien_sw>; 737 }; 738 739 usbdp_phy0_dp_altmode_mux: endpoint@1 { 740 reg = <1>; 741 remote-endpoint = <&dp_altmode_mux>; 742 }; 743 }; 744}; 745 746&usbdp_phy1 { 747 rockchip,dp-lane-mux = <2 3>; 748}; 749 750&usbdrd_dwc3_0 { 751 dr_mode = "otg"; 752 usb-role-switch; 753 port { 754 #address-cells = <1>; 755 #size-cells = <0>; 756 dwc3_0_role_switch: endpoint@0 { 757 reg = <0>; 758 remote-endpoint = <&usbc0_role_sw>; 759 }; 760 }; 761}; 762 763&usbhost3_0 { 764 status = "disabled"; 765}; 766 767&usbhost_dwc3_0 { 768 status = "disabled"; 769}; 770 771