1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9 10&spi2 { 11 status = "okay"; 12 assigned-clocks = <&cru CLK_SPI2>; 13 assigned-clock-rates = <200000000>; 14 num-cs = <2>; 15 16 rk806master: rk806master@0 { 17 compatible = "rockchip,rk806"; 18 spi-max-frequency = <1000000>; 19 reg = <0x0>; 20 21 interrupt-parent = <&gpio0>; 22 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 23 24 pinctrl-names = "default", "pmic-power-off"; 25 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; 26 pinctrl-1 = <&rk806_dvs1_pwrdn>; 27 28 /* 2800mv-3500mv */ 29 low_voltage_threshold = <3000>; 30 /* 2700mv-3400mv */ 31 shutdown_voltage_threshold = <2700>; 32 /* 140 160 */ 33 shutdown_temperture_threshold = <160>; 34 hotdie_temperture_threshold = <115>; 35 36 /* 0: restart PMU; 37 * 1: reset all the power off reset registers, 38 * forcing the state to switch to ACTIVE mode; 39 * 2: Reset all the power off reset registers, 40 * forcing the state to switch to ACTIVE mode, 41 * and simultaneously pull down the RESETB PIN for 5mS before releasing 42 */ 43 pmic-reset-func = <1>; 44 45 vcc1-supply = <&vcc5v0_sys>; 46 vcc2-supply = <&vcc5v0_sys>; 47 vcc3-supply = <&vcc5v0_sys>; 48 vcc4-supply = <&vcc5v0_sys>; 49 vcc5-supply = <&vcc5v0_sys>; 50 vcc6-supply = <&vcc5v0_sys>; 51 vcc7-supply = <&vcc5v0_sys>; 52 vcc8-supply = <&vcc5v0_sys>; 53 vcc9-supply = <&vcc5v0_sys>; 54 vcc10-supply = <&vcc5v0_sys>; 55 vcc11-supply = <&vcc_2v0_pldo_s3>; 56 vcc12-supply = <&vcc5v0_sys>; 57 vcc13-supply = <&vcc_1v1_nldo_s3>; 58 vcc14-supply = <&vcc_1v1_nldo_s3>; 59 vcca-supply = <&vcc5v0_sys>; 60 61 pwrkey { 62 status = "okay"; 63 }; 64 65 pinctrl_rk806: pinctrl_rk806 { 66 gpio-controller; 67 #gpio-cells = <2>; 68 69 rk806_dvs1_null: rk806_dvs1_null { 70 pins = "gpio_pwrctrl2"; 71 function = "pin_fun0"; 72 }; 73 74 rk806_dvs1_slp: rk806_dvs1_slp { 75 pins = "gpio_pwrctrl1"; 76 function = "pin_fun1"; 77 }; 78 79 rk806_dvs1_pwrdn: rk806_dvs1_pwrdn { 80 pins = "gpio_pwrctrl1"; 81 function = "pin_fun2"; 82 }; 83 84 rk806_dvs1_rst: rk806_dvs1_rst { 85 pins = "gpio_pwrctrl1"; 86 function = "pin_fun3"; 87 }; 88 89 rk806_dvs2_null: rk806_dvs2_null { 90 pins = "gpio_pwrctrl2"; 91 function = "pin_fun0"; 92 }; 93 94 rk806_dvs2_slp: rk806_dvs2_slp { 95 pins = "gpio_pwrctrl2"; 96 function = "pin_fun1"; 97 }; 98 99 rk806_dvs2_pwrdn: rk806_dvs2_pwrdn { 100 pins = "gpio_pwrctrl2"; 101 function = "pin_fun2"; 102 }; 103 104 rk806_dvs2_rst: rk806_dvs2_rst { 105 pins = "gpio_pwrctrl2"; 106 function = "pin_fun3"; 107 }; 108 109 rk806_dvs2_dvs: rk806_dvs2_dvs { 110 pins = "gpio_pwrctrl2"; 111 function = "pin_fun4"; 112 }; 113 114 rk806_dvs2_gpio: rk806_dvs2_gpio { 115 pins = "gpio_pwrctrl2"; 116 function = "pin_fun5"; 117 }; 118 119 rk806_dvs3_null: rk806_dvs3_null { 120 pins = "gpio_pwrctrl3"; 121 function = "pin_fun0"; 122 }; 123 124 rk806_dvs3_slp: rk806_dvs3_slp { 125 pins = "gpio_pwrctrl3"; 126 function = "pin_fun1"; 127 }; 128 129 rk806_dvs3_pwrdn: rk806_dvs3_pwrdn { 130 pins = "gpio_pwrctrl3"; 131 function = "pin_fun2"; 132 }; 133 134 rk806_dvs3_rst: rk806_dvs3_rst { 135 pins = "gpio_pwrctrl3"; 136 function = "pin_fun3"; 137 }; 138 139 rk806_dvs3_dvs: rk806_dvs3_dvs { 140 pins = "gpio_pwrctrl3"; 141 function = "pin_fun4"; 142 }; 143 144 rk806_dvs3_gpio: rk806_dvs3_gpio { 145 pins = "gpio_pwrctrl3"; 146 function = "pin_fun5"; 147 }; 148 }; 149 150 regulators { 151 vdd_gpu_s0: DCDC_REG1 { 152 regulator-boot-on; 153 regulator-min-microvolt = <550000>; 154 regulator-max-microvolt = <950000>; 155 regulator-ramp-delay = <12500>; 156 regulator-name = "vdd_gpu_s0"; 157 regulator-enable-ramp-delay = <400>; 158 regulator-state-mem { 159 regulator-off-in-suspend; 160 }; 161 }; 162 163 vdd_npu_s0: DCDC_REG2 { 164 regulator-always-on; 165 regulator-boot-on; 166 regulator-min-microvolt = <550000>; 167 regulator-max-microvolt = <950000>; 168 regulator-ramp-delay = <12500>; 169 regulator-name = "vdd_npu_s0"; 170 regulator-state-mem { 171 regulator-off-in-suspend; 172 }; 173 }; 174 175 vdd_log_s0: DCDC_REG3 { 176 regulator-always-on; 177 regulator-boot-on; 178 regulator-min-microvolt = <675000>; 179 regulator-max-microvolt = <750000>; 180 regulator-ramp-delay = <12500>; 181 regulator-name = "vdd_log_s0"; 182 regulator-state-mem { 183 regulator-off-in-suspend; 184 regulator-suspend-microvolt = <750000>; 185 }; 186 }; 187 188 vdd_vdenc_s0: DCDC_REG4 { 189 regulator-always-on; 190 regulator-boot-on; 191 regulator-min-microvolt = <550000>; 192 regulator-max-microvolt = <950000>; 193 regulator-ramp-delay = <12500>; 194 regulator-name = "vdd_vdenc_s0"; 195 regulator-state-mem { 196 regulator-off-in-suspend; 197 }; 198 }; 199 200 vdd_gpu_mem_s0: DCDC_REG5 { 201 regulator-boot-on; 202 regulator-min-microvolt = <675000>; 203 regulator-max-microvolt = <950000>; 204 regulator-ramp-delay = <12500>; 205 regulator-enable-ramp-delay = <400>; 206 regulator-name = "vdd_gpu_mem_s0"; 207 regulator-state-mem { 208 regulator-off-in-suspend; 209 }; 210 }; 211 212 vdd_npu_mem_s0: DCDC_REG6 { 213 regulator-always-on; 214 regulator-boot-on; 215 regulator-min-microvolt = <675000>; 216 regulator-max-microvolt = <950000>; 217 regulator-ramp-delay = <12500>; 218 regulator-name = "vdd_npu_mem_s0"; 219 regulator-state-mem { 220 regulator-off-in-suspend; 221 }; 222 }; 223 224 vcc_2v0_pldo_s3: DCDC_REG7 { 225 regulator-always-on; 226 regulator-boot-on; 227 regulator-min-microvolt = <2000000>; 228 regulator-max-microvolt = <2000000>; 229 regulator-ramp-delay = <12500>; 230 regulator-name = "vdd_2v0_pldo_s3"; 231 regulator-state-mem { 232 regulator-on-in-suspend; 233 regulator-suspend-microvolt = <2000000>; 234 }; 235 }; 236 237 vdd_vdenc_mem_s0: DCDC_REG8 { 238 regulator-always-on; 239 regulator-boot-on; 240 regulator-min-microvolt = <675000>; 241 regulator-max-microvolt = <950000>; 242 regulator-ramp-delay = <12500>; 243 regulator-name = "vdd_vdenc_mem_s0"; 244 regulator-state-mem { 245 regulator-off-in-suspend; 246 }; 247 }; 248 249 vdd2_ddr_s3: DCDC_REG9 { 250 regulator-always-on; 251 regulator-boot-on; 252 regulator-name = "vdd2_ddr_s3"; 253 regulator-state-mem { 254 regulator-on-in-suspend; 255 }; 256 }; 257 258 vcc_1v1_nldo_s3: DCDC_REG10 { 259 regulator-always-on; 260 regulator-boot-on; 261 regulator-min-microvolt = <1100000>; 262 regulator-max-microvolt = <1100000>; 263 regulator-ramp-delay = <12500>; 264 regulator-name = "vcc_1v1_nldo_s3"; 265 regulator-state-mem { 266 regulator-on-in-suspend; 267 regulator-suspend-microvolt = <1100000>; 268 }; 269 }; 270 271 avcc_1v8_s0: PLDO_REG1 { 272 regulator-always-on; 273 regulator-boot-on; 274 regulator-min-microvolt = <1800000>; 275 regulator-max-microvolt = <1800000>; 276 regulator-ramp-delay = <12500>; 277 regulator-name = "avcc_1v8_s0"; 278 regulator-state-mem { 279 regulator-off-in-suspend; 280 }; 281 }; 282 283 vdd1_1v8_ddr_s3: PLDO_REG2 { 284 regulator-always-on; 285 regulator-boot-on; 286 regulator-min-microvolt = <1800000>; 287 regulator-max-microvolt = <1800000>; 288 regulator-ramp-delay = <12500>; 289 regulator-name = "vdd1_1v8_ddr_s3"; 290 regulator-state-mem { 291 regulator-on-in-suspend; 292 regulator-suspend-microvolt = <1800000>; 293 }; 294 }; 295 296 avcc_1v8_codec_s0: PLDO_REG3 { 297 regulator-always-on; 298 regulator-boot-on; 299 regulator-min-microvolt = <1800000>; 300 regulator-max-microvolt = <1800000>; 301 regulator-ramp-delay = <12500>; 302 regulator-name = "avcc_1v8_codec_s0"; 303 regulator-state-mem { 304 regulator-off-in-suspend; 305 }; 306 }; 307 308 vcc_3v3_s3: PLDO_REG4 { 309 regulator-always-on; 310 regulator-boot-on; 311 regulator-min-microvolt = <3300000>; 312 regulator-max-microvolt = <3300000>; 313 regulator-ramp-delay = <12500>; 314 regulator-name = "vcc_3v3_s3"; 315 regulator-state-mem { 316 regulator-on-in-suspend; 317 regulator-suspend-microvolt = <3300000>; 318 }; 319 }; 320 321 vccio_sd_s0: PLDO_REG5 { 322 regulator-always-on; 323 regulator-boot-on; 324 regulator-min-microvolt = <1800000>; 325 regulator-max-microvolt = <3300000>; 326 regulator-ramp-delay = <12500>; 327 regulator-name = "vccio_sd_s0"; 328 regulator-state-mem { 329 regulator-off-in-suspend; 330 }; 331 }; 332 333 vccio_1v8_s3: PLDO_REG6 { 334 regulator-always-on; 335 regulator-boot-on; 336 regulator-min-microvolt = <1800000>; 337 regulator-max-microvolt = <1800000>; 338 regulator-ramp-delay = <12500>; 339 regulator-name = "vccio_1v8_s3"; 340 regulator-state-mem { 341 regulator-on-in-suspend; 342 regulator-suspend-microvolt = <1800000>; 343 }; 344 }; 345 346 vdd_0v75_s3: NLDO_REG1 { 347 regulator-always-on; 348 regulator-boot-on; 349 regulator-min-microvolt = <750000>; 350 regulator-max-microvolt = <750000>; 351 regulator-ramp-delay = <12500>; 352 regulator-name = "vdd_0v75_s3"; 353 regulator-state-mem { 354 regulator-on-in-suspend; 355 regulator-suspend-microvolt = <750000>; 356 }; 357 }; 358 359 vdd2l_0v9_ddr_s3: NLDO_REG2 { 360 regulator-always-on; 361 regulator-boot-on; 362 regulator-min-microvolt = <900000>; 363 regulator-max-microvolt = <900000>; 364 regulator-name = "vdd2l_0v9_ddr_s3"; 365 regulator-state-mem { 366 regulator-on-in-suspend; 367 regulator-suspend-microvolt = <900000>; 368 }; 369 }; 370 371 vdd_0v75_hdmi_edp_s0: NLDO_REG3 { 372 regulator-always-on; 373 regulator-boot-on; 374 regulator-min-microvolt = <837500>; 375 regulator-max-microvolt = <837500>; 376 regulator-name = "vdd_0v75_hdmi_edp_s0"; 377 regulator-state-mem { 378 regulator-off-in-suspend; 379 }; 380 }; 381 382 avdd_0v75_s0: NLDO_REG4 { 383 regulator-always-on; 384 regulator-boot-on; 385 regulator-min-microvolt = <750000>; 386 regulator-max-microvolt = <750000>; 387 regulator-name = "avdd_0v75_s0"; 388 regulator-state-mem { 389 regulator-off-in-suspend; 390 }; 391 }; 392 393 vdd_0v85_s0: NLDO_REG5 { 394 regulator-always-on; 395 regulator-boot-on; 396 regulator-min-microvolt = <850000>; 397 regulator-max-microvolt = <850000>; 398 regulator-name = "vdd_0v85_s0"; 399 regulator-state-mem { 400 regulator-off-in-suspend; 401 }; 402 }; 403 }; 404 }; 405 406 rk806slave: rk806slave@1 { 407 compatible = "rockchip,rk806"; 408 spi-max-frequency = <1000000>; 409 reg = <0x01>; 410 411 interrupt-parent = <&gpio0>; 412 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 413 414 pinctrl-names = "default"; 415 pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>; 416 417 /* 0: restart PMU; 418 * 1: reset all the power off reset registers, 419 * forcing the state to switch to ACTIVE mode; 420 * 2: Reset all the power off reset registers, 421 * forcing the state to switch to ACTIVE mode, 422 * and simultaneously pull down the RESETB PIN for 5mS before releasing 423 */ 424 pmic-reset-func = <1>; 425 426 vcc1-supply = <&vcc5v0_sys>; 427 vcc2-supply = <&vcc5v0_sys>; 428 vcc3-supply = <&vcc5v0_sys>; 429 vcc4-supply = <&vcc5v0_sys>; 430 vcc5-supply = <&vcc5v0_sys>; 431 vcc6-supply = <&vcc5v0_sys>; 432 vcc7-supply = <&vcc5v0_sys>; 433 vcc8-supply = <&vcc5v0_sys>; 434 vcc9-supply = <&vcc5v0_sys>; 435 vcc10-supply = <&vcc5v0_sys>; 436 vcc11-supply = <&vcc_2v0_pldo_s3>; 437 vcc12-supply = <&vcc5v0_sys>; 438 vcc13-supply = <&vcc_1v1_nldo_s3>; 439 vcc14-supply = <&vcc_2v0_pldo_s3>; 440 vcca-supply = <&vcc5v0_sys>; 441 442 pwrkey { 443 status = "disabled"; 444 }; 445 446 pinctrl_slave_rk806: pinctrl_slave_rk806 { 447 gpio-controller; 448 #gpio-cells = <2>; 449 450 rk806_slave_dvs1_null: rk806_slave_dvs1_null { 451 pins = "gpio_pwrctrl2"; 452 function = "pin_fun0"; 453 }; 454 455 rk806_slave_dvs1_slp: rk806_slave_dvs1_slp { 456 pins = "gpio_pwrctrl1"; 457 function = "pin_fun1"; 458 }; 459 460 rk806_slave_dvs1_pwrdn: rk806_slave_dvs1_pwrdn { 461 pins = "gpio_pwrctrl1"; 462 function = "pin_fun2"; 463 }; 464 465 rk806_slave_dvs1_rst: rk806_slave_dvs1_rst { 466 pins = "gpio_pwrctrl1"; 467 function = "pin_fun3"; 468 }; 469 470 rk806_slave_dvs2_null: rk806_slave_dvs2_null { 471 pins = "gpio_pwrctrl2"; 472 function = "pin_fun0"; 473 }; 474 475 rk806_slave_dvs2_slp: rk806_slave_dvs2_slp { 476 pins = "gpio_pwrctrl2"; 477 function = "pin_fun1"; 478 }; 479 480 rk806_slave_dvs2_pwrdn: rk806_slave_dvs2_pwrdn { 481 pins = "gpio_pwrctrl2"; 482 function = "pin_fun2"; 483 }; 484 485 rk806_slave_dvs2_rst: rk806_slave_dvs2_rst { 486 pins = "gpio_pwrctrl2"; 487 function = "pin_fun3"; 488 }; 489 490 rk806_slave_dvs2_dvs: rk806_slave_dvs2_dvs { 491 pins = "gpio_pwrctrl2"; 492 function = "pin_fun4"; 493 }; 494 495 rk806_slave_dvs2_gpio: rk806_slave_dvs2_gpio { 496 pins = "gpio_pwrctrl2"; 497 function = "pin_fun5"; 498 }; 499 500 rk806_slave_dvs3_null: rk806_slave_dvs3_null { 501 pins = "gpio_pwrctrl3"; 502 function = "pin_fun0"; 503 }; 504 505 rk806_slave_dvs3_slp: rk806_slave_dvs3_slp { 506 pins = "gpio_pwrctrl3"; 507 function = "pin_fun1"; 508 }; 509 510 rk806_slave_dvs3_pwrdn: rk806_slave_dvs3_pwrdn { 511 pins = "gpio_pwrctrl3"; 512 function = "pin_fun2"; 513 }; 514 515 rk806_slave_dvs3_rst: rk806_slave_dvs3_rst { 516 pins = "gpio_pwrctrl3"; 517 function = "pin_fun3"; 518 }; 519 520 rk806_slave_dvs3_dvs: rk806_slave_dvs3_dvs { 521 pins = "gpio_pwrctrl3"; 522 function = "pin_fun4"; 523 }; 524 525 rk806_slave_dvs3_gpio: rk806_slave_dvs3_gpio { 526 pins = "gpio_pwrctrl3"; 527 function = "pin_fun5"; 528 }; 529 }; 530 531 regulators { 532 vdd_cpu_big1_s0: DCDC_REG1 { 533 regulator-always-on; 534 regulator-boot-on; 535 regulator-min-microvolt = <550000>; 536 regulator-max-microvolt = <1050000>; 537 regulator-ramp-delay = <12500>; 538 regulator-name = "vdd_cpu_big1_s0"; 539 regulator-state-mem { 540 regulator-off-in-suspend; 541 }; 542 }; 543 544 vdd_cpu_big0_s0: DCDC_REG2 { 545 regulator-always-on; 546 regulator-boot-on; 547 regulator-min-microvolt = <550000>; 548 regulator-max-microvolt = <1050000>; 549 regulator-ramp-delay = <12500>; 550 regulator-name = "vdd_cpu_big0_s0"; 551 regulator-state-mem { 552 regulator-off-in-suspend; 553 }; 554 }; 555 556 vdd_cpu_lit_s0: DCDC_REG3 { 557 regulator-always-on; 558 regulator-boot-on; 559 regulator-min-microvolt = <550000>; 560 regulator-max-microvolt = <950000>; 561 regulator-ramp-delay = <12500>; 562 regulator-name = "vdd_cpu_lit_s0"; 563 regulator-state-mem { 564 regulator-off-in-suspend; 565 }; 566 }; 567 568 vcc_3v3_s0: DCDC_REG4 { 569 regulator-always-on; 570 regulator-boot-on; 571 regulator-min-microvolt = <3300000>; 572 regulator-max-microvolt = <3300000>; 573 regulator-ramp-delay = <12500>; 574 regulator-name = "vcc_3v3_s0"; 575 regulator-state-mem { 576 regulator-off-in-suspend; 577 }; 578 }; 579 580 vdd_cpu_big1_mem_s0: DCDC_REG5 { 581 regulator-always-on; 582 regulator-boot-on; 583 regulator-min-microvolt = <675000>; 584 regulator-max-microvolt = <1050000>; 585 regulator-ramp-delay = <12500>; 586 regulator-name = "vdd_cpu_big1_mem_s0"; 587 regulator-state-mem { 588 regulator-off-in-suspend; 589 }; 590 }; 591 592 593 vdd_cpu_big0_mem_s0: DCDC_REG6 { 594 regulator-always-on; 595 regulator-boot-on; 596 regulator-min-microvolt = <675000>; 597 regulator-max-microvolt = <1050000>; 598 regulator-ramp-delay = <12500>; 599 regulator-name = "vdd_cpu_big0_mem_s0"; 600 regulator-state-mem { 601 regulator-off-in-suspend; 602 }; 603 }; 604 605 vcc_1v8_s0: DCDC_REG7 { 606 regulator-always-on; 607 regulator-boot-on; 608 regulator-min-microvolt = <1800000>; 609 regulator-max-microvolt = <1800000>; 610 regulator-ramp-delay = <12500>; 611 regulator-name = "vcc_1v8_s0"; 612 regulator-state-mem { 613 regulator-off-in-suspend; 614 }; 615 }; 616 617 vdd_cpu_lit_mem_s0: DCDC_REG8 { 618 regulator-always-on; 619 regulator-boot-on; 620 regulator-min-microvolt = <675000>; 621 regulator-max-microvolt = <950000>; 622 regulator-ramp-delay = <12500>; 623 regulator-name = "vdd_cpu_lit_mem_s0"; 624 regulator-state-mem { 625 regulator-off-in-suspend; 626 }; 627 }; 628 629 vddq_ddr_s0: DCDC_REG9 { 630 regulator-always-on; 631 regulator-boot-on; 632 regulator-name = "vddq_ddr_s0"; 633 regulator-state-mem { 634 regulator-off-in-suspend; 635 }; 636 }; 637 638 vdd_ddr_s0: DCDC_REG10 { 639 regulator-always-on; 640 regulator-boot-on; 641 regulator-min-microvolt = <675000>; 642 regulator-max-microvolt = <900000>; 643 regulator-ramp-delay = <12500>; 644 regulator-name = "vdd_ddr_s0"; 645 regulator-state-mem { 646 regulator-off-in-suspend; 647 }; 648 }; 649 650 vcc_1v8_cam_s0: PLDO_REG1 { 651 regulator-always-on; 652 regulator-boot-on; 653 regulator-min-microvolt = <1800000>; 654 regulator-max-microvolt = <1800000>; 655 regulator-ramp-delay = <12500>; 656 regulator-name = "vcc_1v8_cam_s0"; 657 regulator-state-mem { 658 regulator-off-in-suspend; 659 }; 660 }; 661 662 avdd1v8_ddr_pll_s0: PLDO_REG2 { 663 regulator-always-on; 664 regulator-boot-on; 665 regulator-min-microvolt = <1800000>; 666 regulator-max-microvolt = <1800000>; 667 regulator-ramp-delay = <12500>; 668 regulator-name = "avdd1v8_ddr_pll_s0"; 669 regulator-state-mem { 670 regulator-off-in-suspend; 671 }; 672 }; 673 674 vdd_1v8_pll_s0: PLDO_REG3 { 675 regulator-always-on; 676 regulator-boot-on; 677 regulator-min-microvolt = <1800000>; 678 regulator-max-microvolt = <1800000>; 679 regulator-ramp-delay = <12500>; 680 regulator-name = "vdd_1v8_pll_s0"; 681 regulator-state-mem { 682 regulator-off-in-suspend; 683 }; 684 }; 685 686 vcc_3v3_sd_s0: PLDO_REG4 { 687 regulator-always-on; 688 regulator-boot-on; 689 regulator-min-microvolt = <3300000>; 690 regulator-max-microvolt = <3300000>; 691 regulator-ramp-delay = <12500>; 692 regulator-name = "vcc_3v3_sd_s0"; 693 regulator-state-mem { 694 regulator-off-in-suspend; 695 }; 696 }; 697 698 vcc_2v8_cam_s0: PLDO_REG5 { 699 regulator-always-on; 700 regulator-boot-on; 701 regulator-min-microvolt = <2800000>; 702 regulator-max-microvolt = <2800000>; 703 regulator-ramp-delay = <12500>; 704 regulator-name = "vcc_2v8_cam_s0"; 705 regulator-state-mem { 706 regulator-off-in-suspend; 707 }; 708 }; 709 710 pldo6_s3: PLDO_REG6 { 711 regulator-always-on; 712 regulator-boot-on; 713 regulator-min-microvolt = <1800000>; 714 regulator-max-microvolt = <1800000>; 715 regulator-name = "pldo6_s3"; 716 regulator-state-mem { 717 regulator-on-in-suspend; 718 regulator-suspend-microvolt = <1800000>; 719 }; 720 }; 721 722 vdd_0v75_pll_s0: NLDO_REG1 { 723 regulator-always-on; 724 regulator-boot-on; 725 regulator-min-microvolt = <750000>; 726 regulator-max-microvolt = <750000>; 727 regulator-ramp-delay = <12500>; 728 regulator-name = "vdd_0v75_pll_s0"; 729 regulator-state-mem { 730 regulator-off-in-suspend; 731 }; 732 }; 733 734 vdd_ddr_pll_s0: NLDO_REG2 { 735 regulator-always-on; 736 regulator-boot-on; 737 regulator-min-microvolt = <850000>; 738 regulator-max-microvolt = <850000>; 739 regulator-name = "vdd_ddr_pll_s0"; 740 regulator-state-mem { 741 regulator-off-in-suspend; 742 }; 743 }; 744 745 avdd_0v85_s0: NLDO_REG3 { 746 regulator-always-on; 747 regulator-boot-on; 748 regulator-min-microvolt = <850000>; 749 regulator-max-microvolt = <850000>; 750 regulator-ramp-delay = <12500>; 751 regulator-name = "avdd_0v85_s0"; 752 regulator-state-mem { 753 regulator-off-in-suspend; 754 }; 755 }; 756 757 avdd_1v2_cam_s0: NLDO_REG4 { 758 regulator-always-on; 759 regulator-boot-on; 760 regulator-min-microvolt = <1200000>; 761 regulator-max-microvolt = <1200000>; 762 regulator-ramp-delay = <12500>; 763 regulator-name = "avdd_1v2_cam_s0"; 764 regulator-state-mem { 765 regulator-off-in-suspend; 766 }; 767 }; 768 769 avdd_1v2_s0: NLDO_REG5 { 770 regulator-always-on; 771 regulator-boot-on; 772 regulator-min-microvolt = <1200000>; 773 regulator-max-microvolt = <1200000>; 774 regulator-ramp-delay = <12500>; 775 regulator-name = "avdd_1v2_s0"; 776 regulator-state-mem { 777 regulator-off-in-suspend; 778 }; 779 }; 780 }; 781 }; 782}; 783