1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pwm/pwm.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include <dt-bindings/input/rk-input.h> 11#include <dt-bindings/display/drm_mipi_dsi.h> 12#include <dt-bindings/display/rockchip_vop.h> 13#include <dt-bindings/sensor-dev.h> 14#include "rk3588-cpu-swap.dtsi" 15 16/ { 17 adc_keys: adc-keys { 18 compatible = "adc-keys"; 19 io-channels = <&saradc 1>; 20 io-channel-names = "buttons"; 21 keyup-threshold-microvolt = <1800000>; 22 poll-interval = <100>; 23 24 vol-up-key { 25 label = "volume up"; 26 linux,code = <KEY_VOLUMEUP>; 27 press-threshold-microvolt = <1750>; 28 }; 29 }; 30 31 dp0_sound: dp0-sound { 32 status = "disabled"; 33 compatible = "rockchip,hdmi"; 34 rockchip,card-name= "rockchip-dp0"; 35 rockchip,mclk-fs = <512>; 36 rockchip,cpu = <&spdif_tx2>; 37 rockchip,codec = <&dp0 1>; 38 rockchip,jack-det; 39 }; 40 41 dp1_sound: dp1-sound { 42 status = "disabled"; 43 compatible = "rockchip,hdmi"; 44 rockchip,card-name= "rockchip-dp1"; 45 rockchip,mclk-fs = <512>; 46 rockchip,cpu = <&spdif_tx5>; 47 rockchip,codec = <&dp1 1>; 48 rockchip,jack-det; 49 }; 50 51 hdmi0_sound: hdmi0-sound { 52 status = "disabled"; 53 compatible = "rockchip,hdmi"; 54 rockchip,mclk-fs = <128>; 55 rockchip,card-name = "rockchip-hdmi0"; 56 rockchip,cpu = <&i2s5_8ch>; 57 rockchip,codec = <&hdmi0>; 58 rockchip,jack-det; 59 }; 60 61 hdmi1_sound: hdmi1-sound { 62 status = "disabled"; 63 compatible = "rockchip,hdmi"; 64 rockchip,mclk-fs = <128>; 65 rockchip,card-name = "rockchip-hdmi1"; 66 rockchip,cpu = <&i2s6_8ch>; 67 rockchip,codec = <&hdmi1>; 68 rockchip,jack-det; 69 }; 70 71 test-power { 72 status = "okay"; 73 }; 74}; 75 76&av1d_mmu { 77 status = "okay"; 78}; 79 80&CPU_SLEEP { 81 status = "disabled"; 82}; 83 84&cluster0_opp_table { 85 /delete-node/ opp-408000000; 86 /delete-node/ opp-600000000; 87 /delete-node/ opp-816000000; 88 /delete-node/ opp-1008000000; 89}; 90 91&cluster1_opp_table { 92 /delete-node/ opp-408000000; 93 /delete-node/ opp-600000000; 94 /delete-node/ opp-816000000; 95 /delete-node/ opp-1008000000; 96 /delete-node/ opp-2256000000; 97 /delete-node/ opp-2304000000; 98 /delete-node/ opp-2352000000; 99 /delete-node/ opp-2400000000; 100}; 101 102&cluster2_opp_table { 103 /delete-node/ opp-408000000; 104 /delete-node/ opp-600000000; 105 /delete-node/ opp-816000000; 106 /delete-node/ opp-1008000000; 107 /delete-node/ opp-2256000000; 108 /delete-node/ opp-2304000000; 109 /delete-node/ opp-2352000000; 110 /delete-node/ opp-2400000000; 111}; 112 113&cpu_l0 { 114 cpu-supply = <&vdd_cpu_lit_s0>; 115 mem-supply = <&vdd_cpu_lit_mem_s0>; 116}; 117 118&cpu_b0 { 119 cpu-supply = <&vdd_cpu_big0_s0>; 120 mem-supply = <&vdd_cpu_big0_mem_s0>; 121}; 122 123&cpu_b2 { 124 cpu-supply = <&vdd_cpu_big1_s0>; 125 mem-supply = <&vdd_cpu_big1_mem_s0>; 126}; 127 128&display_subsystem { 129 clocks = <&hdptxphy_hdmi_clk0>, <&hdptxphy_hdmi_clk1>; 130 clock-names = "hdmi0_phy_pll", "hdmi1_phy_pll"; 131}; 132 133&gpu_opp_table { 134 /delete-node/ opp-198000000; 135 /delete-node/ opp-297000000; 136 /delete-node/ opp-396000000; 137 /delete-node/ opp-500000000; 138 /delete-node/ opp-1000000000; 139 140}; 141 142&gpu { 143 mali-supply = <&vdd_gpu_s0>; 144 mem-supply = <&vdd_gpu_mem_s0>; 145 status = "okay"; 146}; 147 148&hdptxphy_hdmi_clk0 { 149 status = "okay"; 150}; 151 152&hdptxphy_hdmi_clk1 { 153 status = "okay"; 154}; 155 156&iep { 157 status = "okay"; 158}; 159 160&iep_mmu { 161 status = "okay"; 162}; 163 164&jpegd { 165 status = "okay"; 166}; 167 168&jpegd_mmu { 169 status = "okay"; 170}; 171 172&jpege_ccu { 173 status = "okay"; 174}; 175 176&jpege0 { 177 status = "okay"; 178}; 179 180&jpege0_mmu { 181 status = "okay"; 182}; 183 184&jpege1 { 185 status = "okay"; 186}; 187 188&jpege1_mmu { 189 status = "okay"; 190}; 191 192&jpege2 { 193 status = "okay"; 194}; 195 196&jpege2_mmu { 197 status = "okay"; 198}; 199 200&jpege3 { 201 status = "okay"; 202}; 203 204&jpege3_mmu { 205 status = "okay"; 206}; 207 208&mpp_srv { 209 status = "okay"; 210}; 211 212&rga3_core0 { 213 status = "okay"; 214}; 215 216&rga3_0_mmu { 217 status = "okay"; 218}; 219 220&rga3_core1 { 221 status = "okay"; 222}; 223 224&rga3_1_mmu { 225 status = "okay"; 226}; 227 228&rga2 { 229 status = "okay"; 230}; 231 232&rknpu { 233 rknpu-supply = <&vdd_npu_s0>; 234 mem-supply = <&vdd_npu_mem_s0>; 235 status = "okay"; 236}; 237 238&rknpu_mmu { 239 status = "okay"; 240}; 241 242&rkvdec_ccu { 243 status = "okay"; 244}; 245 246&rkvdec0 { 247 status = "okay"; 248}; 249 250&rkvdec0_mmu { 251 status = "okay"; 252}; 253 254&rkvdec1 { 255 status = "okay"; 256}; 257 258&rkvdec1_mmu { 259 status = "okay"; 260}; 261 262&rkvenc_ccu { 263 status = "okay"; 264}; 265 266&rkvenc0 { 267 venc-supply = <&vdd_vdenc_s0>; 268 mem-supply = <&vdd_vdenc_mem_s0>; 269 status = "okay"; 270}; 271 272&rkvenc0_mmu { 273 status = "okay"; 274}; 275 276&rkvenc1 { 277 venc-supply = <&vdd_vdenc_s0>; 278 mem-supply = <&vdd_vdenc_mem_s0>; 279 status = "okay"; 280}; 281 282&rkvenc1_mmu { 283 status = "okay"; 284}; 285 286&saradc { 287 status = "okay"; 288 vref-supply = <&avcc_1v8_s0>; 289}; 290 291&tsadc { 292 status = "okay"; 293}; 294 295&vdpu { 296 status = "okay"; 297}; 298 299&vdpu_mmu { 300 status = "okay"; 301}; 302 303&vepu { 304 status = "okay"; 305}; 306 307&vop { 308 assigned-clocks = <&cru ACLK_VOP>; 309 assigned-clock-rates = <800000000>; 310 status = "okay"; 311}; 312 313&vop_mmu { 314 status = "okay"; 315}; 316 317/* vp0 & vp1 splice for 8K output */ 318&vp0 { 319 rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER0 | 1 << ROCKCHIP_VOP2_ESMART0)>; 320 rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART0>; 321}; 322 323&vp1 { 324 rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER1 | 1 << ROCKCHIP_VOP2_ESMART1)>; 325 rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART1>; 326}; 327 328&vp2 { 329 rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER2 | 1 << ROCKCHIP_VOP2_ESMART2)>; 330 rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART2>; 331}; 332 333&vp3 { 334 rockchip,plane-mask = <(1 << ROCKCHIP_VOP2_CLUSTER3 | 1 << ROCKCHIP_VOP2_ESMART3)>; 335 rockchip,primary-plane = <ROCKCHIP_VOP2_ESMART3>; 336}; 337