xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3588-nvr-demo.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include "rk3588.dtsi"
8*4882a593Smuzhiyun#include "rk3588-nvr.dtsi"
9*4882a593Smuzhiyun#include "rk3588-rk806-single.dtsi"
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun/ {
12*4882a593Smuzhiyun	i2s0_sound: i2s0-sound {
13*4882a593Smuzhiyun		status = "okay";
14*4882a593Smuzhiyun		compatible = "simple-audio-card";
15*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
16*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
17*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,es8311";
18*4882a593Smuzhiyun		simple-audio-card,dai-link@0 {
19*4882a593Smuzhiyun			format = "i2s";
20*4882a593Smuzhiyun			cpu {
21*4882a593Smuzhiyun				sound-dai = <&i2s0_8ch>;
22*4882a593Smuzhiyun			};
23*4882a593Smuzhiyun			codec {
24*4882a593Smuzhiyun				sound-dai = <&es8311>;
25*4882a593Smuzhiyun			};
26*4882a593Smuzhiyun		};
27*4882a593Smuzhiyun	};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun	leds: leds {
30*4882a593Smuzhiyun		compatible = "gpio-leds";
31*4882a593Smuzhiyun		hdd_led: hdd-led {
32*4882a593Smuzhiyun			gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
33*4882a593Smuzhiyun			default-state = "off";
34*4882a593Smuzhiyun		};
35*4882a593Smuzhiyun		net_led: net-led {
36*4882a593Smuzhiyun			gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
37*4882a593Smuzhiyun			default-state = "off";
38*4882a593Smuzhiyun		};
39*4882a593Smuzhiyun		work_led: work-led {
40*4882a593Smuzhiyun			gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
41*4882a593Smuzhiyun			linux,default-trigger = "heartbeat";
42*4882a593Smuzhiyun		};
43*4882a593Smuzhiyun	};
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun	pcie30_avdd0v75: pcie30-avdd0v75 {
46*4882a593Smuzhiyun		compatible = "regulator-fixed";
47*4882a593Smuzhiyun		regulator-name = "pcie30_avdd0v75";
48*4882a593Smuzhiyun		regulator-boot-on;
49*4882a593Smuzhiyun		regulator-always-on;
50*4882a593Smuzhiyun		regulator-min-microvolt = <750000>;
51*4882a593Smuzhiyun		regulator-max-microvolt = <750000>;
52*4882a593Smuzhiyun		vin-supply = <&vdd_0v75_s0>;
53*4882a593Smuzhiyun	};
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun	pcie30_avdd1v8: pcie30-avdd1v8 {
56*4882a593Smuzhiyun		compatible = "regulator-fixed";
57*4882a593Smuzhiyun		regulator-name = "pcie30_avdd1v8";
58*4882a593Smuzhiyun		regulator-boot-on;
59*4882a593Smuzhiyun		regulator-always-on;
60*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
61*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
62*4882a593Smuzhiyun		vin-supply = <&avcc_1v8_s0>;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	vcc12v_dcin: vcc12v-dcin {
66*4882a593Smuzhiyun		compatible = "regulator-fixed";
67*4882a593Smuzhiyun		regulator-name = "vcc12v_dcin";
68*4882a593Smuzhiyun		regulator-always-on;
69*4882a593Smuzhiyun		regulator-boot-on;
70*4882a593Smuzhiyun		regulator-min-microvolt = <12000000>;
71*4882a593Smuzhiyun		regulator-max-microvolt = <12000000>;
72*4882a593Smuzhiyun	};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun	vcc3v3_pcie30: vcc3v3-pcie30 {
75*4882a593Smuzhiyun		compatible = "regulator-fixed";
76*4882a593Smuzhiyun		regulator-name = "vcc3v3_pcie30";
77*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
78*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
79*4882a593Smuzhiyun		enable-active-high;
80*4882a593Smuzhiyun		gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>;
81*4882a593Smuzhiyun		startup-delay-us = <7500>;
82*4882a593Smuzhiyun		vin-supply = <&vcc12v_dcin>;
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	vcc5v0_sys: vcc5v0-sys {
86*4882a593Smuzhiyun		compatible = "regulator-fixed";
87*4882a593Smuzhiyun		regulator-name = "vcc5v0_sys";
88*4882a593Smuzhiyun		regulator-always-on;
89*4882a593Smuzhiyun		regulator-boot-on;
90*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
91*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
92*4882a593Smuzhiyun		vin-supply = <&vcc12v_dcin>;
93*4882a593Smuzhiyun	};
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host-regulator {
96*4882a593Smuzhiyun		compatible = "regulator-fixed";
97*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
98*4882a593Smuzhiyun		regulator-boot-on;
99*4882a593Smuzhiyun		regulator-always-on;
100*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
101*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
102*4882a593Smuzhiyun		enable-active-high;
103*4882a593Smuzhiyun		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
104*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
105*4882a593Smuzhiyun		pinctrl-names = "default";
106*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
107*4882a593Smuzhiyun	};
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun	vcc5v0_otg: vcc5v0-otg-regulator {
110*4882a593Smuzhiyun		compatible = "regulator-fixed";
111*4882a593Smuzhiyun		regulator-name = "vcc5v0_otg";
112*4882a593Smuzhiyun		regulator-min-microvolt = <5000000>;
113*4882a593Smuzhiyun		regulator-max-microvolt = <5000000>;
114*4882a593Smuzhiyun		enable-active-high;
115*4882a593Smuzhiyun		gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
116*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
117*4882a593Smuzhiyun		pinctrl-names = "default";
118*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_otg_en>;
119*4882a593Smuzhiyun	};
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
122*4882a593Smuzhiyun		compatible = "regulator-fixed";
123*4882a593Smuzhiyun		regulator-name = "vcc_1v1_nldo_s3";
124*4882a593Smuzhiyun		regulator-always-on;
125*4882a593Smuzhiyun		regulator-boot-on;
126*4882a593Smuzhiyun		regulator-min-microvolt = <1100000>;
127*4882a593Smuzhiyun		regulator-max-microvolt = <1100000>;
128*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
129*4882a593Smuzhiyun	};
130*4882a593Smuzhiyun};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun&combphy0_ps {
133*4882a593Smuzhiyun	pinctrl-names = "default";
134*4882a593Smuzhiyun	pinctrl-0 = <&sata0_pm_reset>;
135*4882a593Smuzhiyun	status = "okay";
136*4882a593Smuzhiyun};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun&combphy1_ps {
139*4882a593Smuzhiyun	pinctrl-names = "default";
140*4882a593Smuzhiyun	pinctrl-0 = <&sata1_pm_reset>;
141*4882a593Smuzhiyun	status = "okay";
142*4882a593Smuzhiyun};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun&combphy2_psu {
145*4882a593Smuzhiyun	status = "okay";
146*4882a593Smuzhiyun};
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun&dp0 {
149*4882a593Smuzhiyun	pinctrl-0 = <&dp0m2_pins>;
150*4882a593Smuzhiyun	pinctrl-names = "default";
151*4882a593Smuzhiyun	status = "okay";
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&dp0_in_vp0 {
155*4882a593Smuzhiyun	status = "okay";
156*4882a593Smuzhiyun};
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun&dp0_in_vp1 {
159*4882a593Smuzhiyun	status = "okay";
160*4882a593Smuzhiyun};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun&dp0_in_vp2 {
163*4882a593Smuzhiyun	status = "okay";
164*4882a593Smuzhiyun};
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun&dp1 {
167*4882a593Smuzhiyun	pinctrl-0 = <&dp1m2_pins &dp1_hdmi_ctl>;
168*4882a593Smuzhiyun	pinctrl-names = "default";
169*4882a593Smuzhiyun	status = "okay";
170*4882a593Smuzhiyun};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun&dp1_in_vp0 {
173*4882a593Smuzhiyun	status = "okay";
174*4882a593Smuzhiyun};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun&dp1_in_vp1 {
177*4882a593Smuzhiyun	status = "okay";
178*4882a593Smuzhiyun};
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun&dp1_in_vp2 {
181*4882a593Smuzhiyun	status = "okay";
182*4882a593Smuzhiyun};
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun&dp1_sound {
185*4882a593Smuzhiyun	status = "okay";
186*4882a593Smuzhiyun};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun&gmac0 {
189*4882a593Smuzhiyun	/* Use rgmii-rxid mode to disable rx delay inside Soc */
190*4882a593Smuzhiyun	phy-mode = "rgmii-rxid";
191*4882a593Smuzhiyun	clock_in_out = "output";
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun	snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
194*4882a593Smuzhiyun	snps,reset-active-low;
195*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
196*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun	pinctrl-names = "default";
199*4882a593Smuzhiyun	pinctrl-0 = <&gmac0_miim
200*4882a593Smuzhiyun		     &gmac0_tx_bus2
201*4882a593Smuzhiyun		     &gmac0_rx_bus2
202*4882a593Smuzhiyun		     &gmac0_rgmii_clk
203*4882a593Smuzhiyun		     &gmac0_rgmii_bus>;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun	tx_delay = <0x44>;
206*4882a593Smuzhiyun	/* rx_delay = <0x4f>; */
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun	phy-handle = <&rgmii_phy0>;
209*4882a593Smuzhiyun	status = "okay";
210*4882a593Smuzhiyun};
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun&gmac1 {
213*4882a593Smuzhiyun	/* Use rgmii-rxid mode to disable rx delay inside Soc */
214*4882a593Smuzhiyun	phy-mode = "rgmii-rxid";
215*4882a593Smuzhiyun	clock_in_out = "output";
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun	snps,reset-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
218*4882a593Smuzhiyun	snps,reset-active-low;
219*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
220*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun	pinctrl-names = "default";
223*4882a593Smuzhiyun	pinctrl-0 = <&gmac1_miim
224*4882a593Smuzhiyun		     &gmac1_tx_bus2
225*4882a593Smuzhiyun		     &gmac1_rx_bus2
226*4882a593Smuzhiyun		     &gmac1_rgmii_clk
227*4882a593Smuzhiyun		     &gmac1_rgmii_bus>;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun	tx_delay = <0x42>;
230*4882a593Smuzhiyun	/* rx_delay = <0x4f>; */
231*4882a593Smuzhiyun
232*4882a593Smuzhiyun	phy-handle = <&rgmii_phy1>;
233*4882a593Smuzhiyun	status = "okay";
234*4882a593Smuzhiyun};
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun&hdmi0 {
237*4882a593Smuzhiyun	enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>;
238*4882a593Smuzhiyun	status = "okay";
239*4882a593Smuzhiyun};
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun&hdmi0_in_vp0 {
242*4882a593Smuzhiyun	status = "okay";
243*4882a593Smuzhiyun};
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun&hdmi0_in_vp1 {
246*4882a593Smuzhiyun	status = "okay";
247*4882a593Smuzhiyun};
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun&hdmi0_in_vp2 {
250*4882a593Smuzhiyun	status = "okay";
251*4882a593Smuzhiyun};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun&hdmi0_sound {
254*4882a593Smuzhiyun	status = "okay";
255*4882a593Smuzhiyun};
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun&hdmi1 {
258*4882a593Smuzhiyun	enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
259*4882a593Smuzhiyun	status = "okay";
260*4882a593Smuzhiyun};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun&hdmi1_in_vp0 {
263*4882a593Smuzhiyun	status = "okay";
264*4882a593Smuzhiyun};
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun&hdmi1_in_vp1 {
267*4882a593Smuzhiyun	status = "okay";
268*4882a593Smuzhiyun};
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun&hdmi1_in_vp2 {
271*4882a593Smuzhiyun	status = "okay";
272*4882a593Smuzhiyun};
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun&hdmi1_sound {
275*4882a593Smuzhiyun	status = "okay";
276*4882a593Smuzhiyun};
277*4882a593Smuzhiyun
278*4882a593Smuzhiyun&hdptxphy_hdmi0 {
279*4882a593Smuzhiyun	status = "okay";
280*4882a593Smuzhiyun};
281*4882a593Smuzhiyun
282*4882a593Smuzhiyun&hdptxphy_hdmi1 {
283*4882a593Smuzhiyun	status = "okay";
284*4882a593Smuzhiyun};
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun&i2c0 {
287*4882a593Smuzhiyun	status = "okay";
288*4882a593Smuzhiyun	pinctrl-names = "default";
289*4882a593Smuzhiyun	pinctrl-0 = <&i2c0m2_xfer>;
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun	vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 {
292*4882a593Smuzhiyun		compatible = "rockchip,rk8602";
293*4882a593Smuzhiyun		reg = <0x42>;
294*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
295*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
296*4882a593Smuzhiyun		regulator-name = "vdd_cpu_big0_s0";
297*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
298*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
299*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
300*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
301*4882a593Smuzhiyun		regulator-boot-on;
302*4882a593Smuzhiyun		regulator-always-on;
303*4882a593Smuzhiyun		regulator-state-mem {
304*4882a593Smuzhiyun			regulator-off-in-suspend;
305*4882a593Smuzhiyun		};
306*4882a593Smuzhiyun	};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun	vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 {
309*4882a593Smuzhiyun		compatible = "rockchip,rk8603";
310*4882a593Smuzhiyun		reg = <0x43>;
311*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
312*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
313*4882a593Smuzhiyun		regulator-name = "vdd_cpu_big1_s0";
314*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
315*4882a593Smuzhiyun		regulator-max-microvolt = <1050000>;
316*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
317*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
318*4882a593Smuzhiyun		regulator-boot-on;
319*4882a593Smuzhiyun		regulator-always-on;
320*4882a593Smuzhiyun		regulator-state-mem {
321*4882a593Smuzhiyun			regulator-off-in-suspend;
322*4882a593Smuzhiyun		};
323*4882a593Smuzhiyun	};
324*4882a593Smuzhiyun};
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun&i2c2 {
327*4882a593Smuzhiyun	status = "okay";
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun	vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 {
330*4882a593Smuzhiyun		compatible = "rockchip,rk8602";
331*4882a593Smuzhiyun		reg = <0x42>;
332*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
333*4882a593Smuzhiyun		regulator-compatible = "rk860x-reg";
334*4882a593Smuzhiyun		regulator-name = "vdd_npu_s0";
335*4882a593Smuzhiyun		regulator-min-microvolt = <550000>;
336*4882a593Smuzhiyun		regulator-max-microvolt = <950000>;
337*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
338*4882a593Smuzhiyun		rockchip,suspend-voltage-selector = <1>;
339*4882a593Smuzhiyun		regulator-boot-on;
340*4882a593Smuzhiyun		regulator-always-on;
341*4882a593Smuzhiyun		regulator-state-mem {
342*4882a593Smuzhiyun			regulator-off-in-suspend;
343*4882a593Smuzhiyun		};
344*4882a593Smuzhiyun	};
345*4882a593Smuzhiyun};
346*4882a593Smuzhiyun
347*4882a593Smuzhiyun&i2c3 {
348*4882a593Smuzhiyun	status = "okay";
349*4882a593Smuzhiyun	es8311: es8311@18 {
350*4882a593Smuzhiyun		status = "okay";
351*4882a593Smuzhiyun		compatible = "everest,es8311";
352*4882a593Smuzhiyun		reg = <0x18>;
353*4882a593Smuzhiyun		#sound-dai-cells = <0>;
354*4882a593Smuzhiyun		adc-pga-gain = <6>;     /* 18dB */
355*4882a593Smuzhiyun		adc-volume = <0xbf>;    /* 0dB */
356*4882a593Smuzhiyun		dac-volume = <0xbf>;    /* 0dB */
357*4882a593Smuzhiyun		aec-mode = "adc left, adc right";
358*4882a593Smuzhiyun		clocks = <&mclkout_i2s0>;
359*4882a593Smuzhiyun		clock-names = "mclk";
360*4882a593Smuzhiyun		assigned-clocks = <&mclkout_i2s0>;
361*4882a593Smuzhiyun		assigned-clock-rates = <12288000>;
362*4882a593Smuzhiyun		pinctrl-names = "default";
363*4882a593Smuzhiyun		pinctrl-0 = <&i2s0_mclk>;
364*4882a593Smuzhiyun	};
365*4882a593Smuzhiyun};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun&i2c4 {
368*4882a593Smuzhiyun	status = "okay";
369*4882a593Smuzhiyun	pinctrl-names = "default";
370*4882a593Smuzhiyun	pinctrl-0 = <&i2c4m3_xfer>;
371*4882a593Smuzhiyun};
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun&i2c5 {
374*4882a593Smuzhiyun	status = "okay";
375*4882a593Smuzhiyun};
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun&i2c6 {
378*4882a593Smuzhiyun	status = "okay";
379*4882a593Smuzhiyun	hym8563: hym8563@51 {
380*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
381*4882a593Smuzhiyun		reg = <0x51>;
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun		pinctrl-names = "default";
384*4882a593Smuzhiyun		pinctrl-0 = <&rtc_int>;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
387*4882a593Smuzhiyun		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
388*4882a593Smuzhiyun		wakeup-source;
389*4882a593Smuzhiyun	};
390*4882a593Smuzhiyun};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun&i2s0_8ch {
393*4882a593Smuzhiyun	status = "okay";
394*4882a593Smuzhiyun	pinctrl-0 = <&i2s0_lrck
395*4882a593Smuzhiyun		     &i2s0_sclk
396*4882a593Smuzhiyun		     &i2s0_sdi0
397*4882a593Smuzhiyun		     &i2s0_sdo0>;
398*4882a593Smuzhiyun};
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun&i2s5_8ch {
401*4882a593Smuzhiyun	status = "okay";
402*4882a593Smuzhiyun};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun&i2s6_8ch {
405*4882a593Smuzhiyun	status = "okay";
406*4882a593Smuzhiyun};
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun&mdio0 {
409*4882a593Smuzhiyun	rgmii_phy0: phy@1 {
410*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
411*4882a593Smuzhiyun		reg = <0x1>;
412*4882a593Smuzhiyun	};
413*4882a593Smuzhiyun};
414*4882a593Smuzhiyun
415*4882a593Smuzhiyun&mdio1 {
416*4882a593Smuzhiyun	rgmii_phy1: phy@1 {
417*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
418*4882a593Smuzhiyun		reg = <0x1>;
419*4882a593Smuzhiyun	};
420*4882a593Smuzhiyun};
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun&pcie30phy {
423*4882a593Smuzhiyun	status = "okay";
424*4882a593Smuzhiyun};
425*4882a593Smuzhiyun
426*4882a593Smuzhiyun&pcie3x4 {
427*4882a593Smuzhiyun	reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
428*4882a593Smuzhiyun	vpcie3v3-supply = <&vcc3v3_pcie30>;
429*4882a593Smuzhiyun	pinctrl-names = "default";
430*4882a593Smuzhiyun	pinctrl-0 = <&pcie30x4_clkreqn_m1>;
431*4882a593Smuzhiyun	status = "okay";
432*4882a593Smuzhiyun};
433*4882a593Smuzhiyun
434*4882a593Smuzhiyun&pwm3 {
435*4882a593Smuzhiyun	compatible = "rockchip,remotectl-pwm";
436*4882a593Smuzhiyun	pinctrl-names = "default";
437*4882a593Smuzhiyun	pinctrl-0 = <&pwm3m0_pins>;
438*4882a593Smuzhiyun	remote_pwm_id = <3>;
439*4882a593Smuzhiyun	handle_cpu_id = <1>;
440*4882a593Smuzhiyun	remote_support_psci = <0>;
441*4882a593Smuzhiyun	status = "okay";
442*4882a593Smuzhiyun
443*4882a593Smuzhiyun	ir_key1 {
444*4882a593Smuzhiyun		rockchip,usercode = <0x4040>;
445*4882a593Smuzhiyun		rockchip,key_table =
446*4882a593Smuzhiyun			<0xf2	KEY_REPLY>,
447*4882a593Smuzhiyun			<0xba	KEY_BACK>,
448*4882a593Smuzhiyun			<0xf4	KEY_UP>,
449*4882a593Smuzhiyun			<0xf1	KEY_DOWN>,
450*4882a593Smuzhiyun			<0xef	KEY_LEFT>,
451*4882a593Smuzhiyun			<0xee	KEY_RIGHT>,
452*4882a593Smuzhiyun			<0xbd	KEY_HOME>,
453*4882a593Smuzhiyun			<0xea	KEY_VOLUMEUP>,
454*4882a593Smuzhiyun			<0xe3	KEY_VOLUMEDOWN>,
455*4882a593Smuzhiyun			<0xe2	KEY_SEARCH>,
456*4882a593Smuzhiyun			<0xb2	KEY_POWER>,
457*4882a593Smuzhiyun			<0xbc	KEY_MUTE>,
458*4882a593Smuzhiyun			<0xec	KEY_MENU>,
459*4882a593Smuzhiyun			<0xbf	0x190>,
460*4882a593Smuzhiyun			<0xe0	0x191>,
461*4882a593Smuzhiyun			<0xe1	0x192>,
462*4882a593Smuzhiyun			<0xe9	183>,
463*4882a593Smuzhiyun			<0xe6	248>,
464*4882a593Smuzhiyun			<0xe8	185>,
465*4882a593Smuzhiyun			<0xe7	186>,
466*4882a593Smuzhiyun			<0xf0	388>,
467*4882a593Smuzhiyun			<0xbe	0x175>;
468*4882a593Smuzhiyun	};
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun	ir_key2 {
471*4882a593Smuzhiyun		rockchip,usercode = <0xff00>;
472*4882a593Smuzhiyun		rockchip,key_table =
473*4882a593Smuzhiyun			<0xf9	KEY_HOME>,
474*4882a593Smuzhiyun			<0xbf	KEY_BACK>,
475*4882a593Smuzhiyun			<0xfb	KEY_MENU>,
476*4882a593Smuzhiyun			<0xaa	KEY_REPLY>,
477*4882a593Smuzhiyun			<0xb9	KEY_UP>,
478*4882a593Smuzhiyun			<0xe9	KEY_DOWN>,
479*4882a593Smuzhiyun			<0xb8	KEY_LEFT>,
480*4882a593Smuzhiyun			<0xea	KEY_RIGHT>,
481*4882a593Smuzhiyun			<0xeb	KEY_VOLUMEDOWN>,
482*4882a593Smuzhiyun			<0xef	KEY_VOLUMEUP>,
483*4882a593Smuzhiyun			<0xf7	KEY_MUTE>,
484*4882a593Smuzhiyun			<0xe7	KEY_POWER>,
485*4882a593Smuzhiyun			<0xfc	KEY_POWER>,
486*4882a593Smuzhiyun			<0xa9	KEY_VOLUMEDOWN>,
487*4882a593Smuzhiyun			<0xa8	KEY_PLAYPAUSE>,
488*4882a593Smuzhiyun			<0xe0	KEY_VOLUMEDOWN>,
489*4882a593Smuzhiyun			<0xa5	KEY_VOLUMEDOWN>,
490*4882a593Smuzhiyun			<0xab	183>,
491*4882a593Smuzhiyun			<0xb7	388>,
492*4882a593Smuzhiyun			<0xe8	388>,
493*4882a593Smuzhiyun			<0xf8	184>,
494*4882a593Smuzhiyun			<0xaf	185>,
495*4882a593Smuzhiyun			<0xed	KEY_VOLUMEDOWN>,
496*4882a593Smuzhiyun			<0xee	186>,
497*4882a593Smuzhiyun			<0xb3	KEY_VOLUMEDOWN>,
498*4882a593Smuzhiyun			<0xf1	KEY_VOLUMEDOWN>,
499*4882a593Smuzhiyun			<0xf2	KEY_VOLUMEDOWN>,
500*4882a593Smuzhiyun			<0xf3	KEY_SEARCH>,
501*4882a593Smuzhiyun			<0xb4	KEY_VOLUMEDOWN>,
502*4882a593Smuzhiyun			<0xa4	KEY_SETUP>,
503*4882a593Smuzhiyun			<0xbe	KEY_SEARCH>;
504*4882a593Smuzhiyun	};
505*4882a593Smuzhiyun
506*4882a593Smuzhiyun	ir_key3 {
507*4882a593Smuzhiyun		rockchip,usercode = <0x1dcc>;
508*4882a593Smuzhiyun		rockchip,key_table =
509*4882a593Smuzhiyun			<0xee	KEY_REPLY>,
510*4882a593Smuzhiyun			<0xf0	KEY_BACK>,
511*4882a593Smuzhiyun			<0xf8	KEY_UP>,
512*4882a593Smuzhiyun			<0xbb	KEY_DOWN>,
513*4882a593Smuzhiyun			<0xef	KEY_LEFT>,
514*4882a593Smuzhiyun			<0xed	KEY_RIGHT>,
515*4882a593Smuzhiyun			<0xfc	KEY_HOME>,
516*4882a593Smuzhiyun			<0xf1	KEY_VOLUMEUP>,
517*4882a593Smuzhiyun			<0xfd	KEY_VOLUMEDOWN>,
518*4882a593Smuzhiyun			<0xb7	KEY_SEARCH>,
519*4882a593Smuzhiyun			<0xff	KEY_POWER>,
520*4882a593Smuzhiyun			<0xf3	KEY_MUTE>,
521*4882a593Smuzhiyun			<0xbf	KEY_MENU>,
522*4882a593Smuzhiyun			<0xf9	0x191>,
523*4882a593Smuzhiyun			<0xf5	0x192>,
524*4882a593Smuzhiyun			<0xb3	388>,
525*4882a593Smuzhiyun			<0xbe	KEY_1>,
526*4882a593Smuzhiyun			<0xba	KEY_2>,
527*4882a593Smuzhiyun			<0xb2	KEY_3>,
528*4882a593Smuzhiyun			<0xbd	KEY_4>,
529*4882a593Smuzhiyun			<0xf9	KEY_5>,
530*4882a593Smuzhiyun			<0xb1	KEY_6>,
531*4882a593Smuzhiyun			<0xfc	KEY_7>,
532*4882a593Smuzhiyun			<0xf8	KEY_8>,
533*4882a593Smuzhiyun			<0xb0	KEY_9>,
534*4882a593Smuzhiyun			<0xb6	KEY_0>,
535*4882a593Smuzhiyun			<0xb5	KEY_BACKSPACE>;
536*4882a593Smuzhiyun	};
537*4882a593Smuzhiyun};
538*4882a593Smuzhiyun
539*4882a593Smuzhiyun&rk806single {
540*4882a593Smuzhiyun	pinctrl-names = "default", "pmic-power-off";
541*4882a593Smuzhiyun	pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
542*4882a593Smuzhiyun	pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
543*4882a593Smuzhiyun
544*4882a593Smuzhiyun	regulators {
545*4882a593Smuzhiyun		avcc_1v8_s0: PLDO_REG1 {
546*4882a593Smuzhiyun			regulator-always-on;
547*4882a593Smuzhiyun			regulator-boot-on;
548*4882a593Smuzhiyun			regulator-min-microvolt = <1800000>;
549*4882a593Smuzhiyun			regulator-max-microvolt = <1800000>;
550*4882a593Smuzhiyun			regulator-name = "avcc_1v8_s0";
551*4882a593Smuzhiyun			regulator-state-mem {
552*4882a593Smuzhiyun				regulator-on-in-suspend;
553*4882a593Smuzhiyun				regulator-suspend-microvolt = <1800000>;
554*4882a593Smuzhiyun			};
555*4882a593Smuzhiyun		};
556*4882a593Smuzhiyun	};
557*4882a593Smuzhiyun};
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun&rockchip_suspend {
560*4882a593Smuzhiyun	status = "okay";
561*4882a593Smuzhiyun	rockchip,sleep-debug-en = <1>;
562*4882a593Smuzhiyun	rockchip,virtual-poweroff = <1>;
563*4882a593Smuzhiyun	rockchip,sleep-mode-config = <
564*4882a593Smuzhiyun		(0
565*4882a593Smuzhiyun		| RKPM_SLP_ARMOFF_DDRPD
566*4882a593Smuzhiyun		)
567*4882a593Smuzhiyun	>;
568*4882a593Smuzhiyun	rockchip,wakeup-config = <
569*4882a593Smuzhiyun		(0
570*4882a593Smuzhiyun		| RKPM_CPU0_WKUP_EN
571*4882a593Smuzhiyun		| RKPM_GPIO_WKUP_EN
572*4882a593Smuzhiyun		)
573*4882a593Smuzhiyun	>;
574*4882a593Smuzhiyun};
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun&route_dp0 {
577*4882a593Smuzhiyun	status = "okay";
578*4882a593Smuzhiyun	force-output;
579*4882a593Smuzhiyun	connect = <&vp2_out_dp0>;
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun	force_timing {
582*4882a593Smuzhiyun		clock-frequency = <65000000>;
583*4882a593Smuzhiyun		hactive = <1024>;
584*4882a593Smuzhiyun		vactive = <768>;
585*4882a593Smuzhiyun		hfront-porch = <24>;
586*4882a593Smuzhiyun		hsync-len = <136>;
587*4882a593Smuzhiyun		hback-porch = <160>;
588*4882a593Smuzhiyun		vfront-porch = <3>;
589*4882a593Smuzhiyun		vsync-len = <6>;
590*4882a593Smuzhiyun		vback-porch = <29>;
591*4882a593Smuzhiyun		hsync-active = <0>;
592*4882a593Smuzhiyun		vsync-active = <0>;
593*4882a593Smuzhiyun		de-active = <0>;
594*4882a593Smuzhiyun		pixelclk-active = <0>;
595*4882a593Smuzhiyun	};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun};
598*4882a593Smuzhiyun
599*4882a593Smuzhiyun&route_dp1 {
600*4882a593Smuzhiyun	status = "okay";
601*4882a593Smuzhiyun	force-output;
602*4882a593Smuzhiyun	connect = <&vp2_out_dp1>;
603*4882a593Smuzhiyun
604*4882a593Smuzhiyun	force_timing {
605*4882a593Smuzhiyun		clock-frequency = <65000000>;
606*4882a593Smuzhiyun		hactive = <1024>;
607*4882a593Smuzhiyun		vactive = <768>;
608*4882a593Smuzhiyun		hfront-porch = <24>;
609*4882a593Smuzhiyun		hsync-len = <136>;
610*4882a593Smuzhiyun		hback-porch = <160>;
611*4882a593Smuzhiyun		vfront-porch = <3>;
612*4882a593Smuzhiyun		vsync-len = <6>;
613*4882a593Smuzhiyun		vback-porch = <29>;
614*4882a593Smuzhiyun		hsync-active = <0>;
615*4882a593Smuzhiyun		vsync-active = <0>;
616*4882a593Smuzhiyun		de-active = <0>;
617*4882a593Smuzhiyun		pixelclk-active = <0>;
618*4882a593Smuzhiyun	};
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun};
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun&route_hdmi0 {
623*4882a593Smuzhiyun	status = "okay";
624*4882a593Smuzhiyun	force-output;
625*4882a593Smuzhiyun	connect = <&vp2_out_hdmi0>;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun	force_timing {
628*4882a593Smuzhiyun		clock-frequency = <65000000>;
629*4882a593Smuzhiyun		hactive = <1024>;
630*4882a593Smuzhiyun		vactive = <768>;
631*4882a593Smuzhiyun		hfront-porch = <24>;
632*4882a593Smuzhiyun		hsync-len = <136>;
633*4882a593Smuzhiyun		hback-porch = <160>;
634*4882a593Smuzhiyun		vfront-porch = <3>;
635*4882a593Smuzhiyun		vsync-len = <6>;
636*4882a593Smuzhiyun		vback-porch = <29>;
637*4882a593Smuzhiyun		hsync-active = <0>;
638*4882a593Smuzhiyun		vsync-active = <0>;
639*4882a593Smuzhiyun		de-active = <0>;
640*4882a593Smuzhiyun		pixelclk-active = <0>;
641*4882a593Smuzhiyun	};
642*4882a593Smuzhiyun
643*4882a593Smuzhiyun};
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun&route_hdmi1 {
646*4882a593Smuzhiyun	status = "okay";
647*4882a593Smuzhiyun	force-output;
648*4882a593Smuzhiyun	connect = <&vp2_out_hdmi1>;
649*4882a593Smuzhiyun
650*4882a593Smuzhiyun	force_timing {
651*4882a593Smuzhiyun		clock-frequency = <65000000>;
652*4882a593Smuzhiyun		hactive = <1024>;
653*4882a593Smuzhiyun		vactive = <768>;
654*4882a593Smuzhiyun		hfront-porch = <24>;
655*4882a593Smuzhiyun		hsync-len = <136>;
656*4882a593Smuzhiyun		hback-porch = <160>;
657*4882a593Smuzhiyun		vfront-porch = <3>;
658*4882a593Smuzhiyun		vsync-len = <6>;
659*4882a593Smuzhiyun		vback-porch = <29>;
660*4882a593Smuzhiyun		hsync-active = <0>;
661*4882a593Smuzhiyun		vsync-active = <0>;
662*4882a593Smuzhiyun		de-active = <0>;
663*4882a593Smuzhiyun		pixelclk-active = <0>;
664*4882a593Smuzhiyun	};
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun};
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun&sata0 {
669*4882a593Smuzhiyun	status = "okay";
670*4882a593Smuzhiyun};
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun&sata1 {
673*4882a593Smuzhiyun	status = "okay";
674*4882a593Smuzhiyun};
675*4882a593Smuzhiyun
676*4882a593Smuzhiyun&sdhci {
677*4882a593Smuzhiyun	bus-width = <8>;
678*4882a593Smuzhiyun	no-sdio;
679*4882a593Smuzhiyun	no-sd;
680*4882a593Smuzhiyun	non-removable;
681*4882a593Smuzhiyun	max-frequency = <200000000>;
682*4882a593Smuzhiyun	mmc-hs400-1_8v;
683*4882a593Smuzhiyun	mmc-hs400-enhanced-strobe;
684*4882a593Smuzhiyun	status = "okay";
685*4882a593Smuzhiyun};
686*4882a593Smuzhiyun
687*4882a593Smuzhiyun&spdif_tx5 {
688*4882a593Smuzhiyun	status = "okay";
689*4882a593Smuzhiyun};
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun&pinctrl {
692*4882a593Smuzhiyun	dp {
693*4882a593Smuzhiyun		dp1_hdmi_ctl: dp-hdmi-ctl {
694*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>,
695*4882a593Smuzhiyun					<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
696*4882a593Smuzhiyun		};
697*4882a593Smuzhiyun	};
698*4882a593Smuzhiyun
699*4882a593Smuzhiyun	pcie30x4 {
700*4882a593Smuzhiyun		pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 {
701*4882a593Smuzhiyun			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
702*4882a593Smuzhiyun		};
703*4882a593Smuzhiyun	};
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun
706*4882a593Smuzhiyun	rtc {
707*4882a593Smuzhiyun		rtc_int: rtc-int {
708*4882a593Smuzhiyun			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
709*4882a593Smuzhiyun		};
710*4882a593Smuzhiyun	};
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun	usb {
713*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
714*4882a593Smuzhiyun			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
715*4882a593Smuzhiyun		};
716*4882a593Smuzhiyun
717*4882a593Smuzhiyun		vcc5v0_otg_en: vcc5v0-otg-en {
718*4882a593Smuzhiyun			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
719*4882a593Smuzhiyun		};
720*4882a593Smuzhiyun	};
721*4882a593Smuzhiyun
722*4882a593Smuzhiyun	sata {
723*4882a593Smuzhiyun		sata0_pm_reset: sata0-pm-reset {
724*4882a593Smuzhiyun			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>;
725*4882a593Smuzhiyun		};
726*4882a593Smuzhiyun		sata1_pm_reset: sata1-pm-reset {
727*4882a593Smuzhiyun			rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>;
728*4882a593Smuzhiyun		};
729*4882a593Smuzhiyun	};
730*4882a593Smuzhiyun};
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun&u2phy0 {
733*4882a593Smuzhiyun	status = "okay";
734*4882a593Smuzhiyun};
735*4882a593Smuzhiyun
736*4882a593Smuzhiyun&u2phy1 {
737*4882a593Smuzhiyun	status = "okay";
738*4882a593Smuzhiyun};
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun&u2phy2 {
741*4882a593Smuzhiyun	status = "okay";
742*4882a593Smuzhiyun};
743*4882a593Smuzhiyun
744*4882a593Smuzhiyun&u2phy3 {
745*4882a593Smuzhiyun	status = "okay";
746*4882a593Smuzhiyun};
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun&u2phy0_otg {
749*4882a593Smuzhiyun	vbus-supply = <&vcc5v0_otg>;
750*4882a593Smuzhiyun	status = "okay";
751*4882a593Smuzhiyun};
752*4882a593Smuzhiyun
753*4882a593Smuzhiyun&u2phy1_otg {
754*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
755*4882a593Smuzhiyun	status = "okay";
756*4882a593Smuzhiyun};
757*4882a593Smuzhiyun
758*4882a593Smuzhiyun&u2phy2_host {
759*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
760*4882a593Smuzhiyun	status = "okay";
761*4882a593Smuzhiyun};
762*4882a593Smuzhiyun
763*4882a593Smuzhiyun&u2phy3_host {
764*4882a593Smuzhiyun	phy-supply = <&vcc5v0_host>;
765*4882a593Smuzhiyun	status = "okay";
766*4882a593Smuzhiyun};
767*4882a593Smuzhiyun
768*4882a593Smuzhiyun&usb_host0_ehci {
769*4882a593Smuzhiyun	status = "okay";
770*4882a593Smuzhiyun};
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun&usb_host0_ohci {
773*4882a593Smuzhiyun	status = "okay";
774*4882a593Smuzhiyun};
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun&usb_host1_ehci {
777*4882a593Smuzhiyun	status = "okay";
778*4882a593Smuzhiyun};
779*4882a593Smuzhiyun
780*4882a593Smuzhiyun&usb_host1_ohci {
781*4882a593Smuzhiyun	status = "okay";
782*4882a593Smuzhiyun};
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun&usbdp_phy0 {
785*4882a593Smuzhiyun	rockchip,dp-lane-mux = < 2 3 >;
786*4882a593Smuzhiyun	status = "okay";
787*4882a593Smuzhiyun};
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun&usbdp_phy0_dp {
790*4882a593Smuzhiyun	status = "okay";
791*4882a593Smuzhiyun};
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun&usbdp_phy0_u3 {
794*4882a593Smuzhiyun	status = "okay";
795*4882a593Smuzhiyun};
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun&usbdp_phy1 {
798*4882a593Smuzhiyun	rockchip,dp-lane-mux = < 0 1 2 3 >;
799*4882a593Smuzhiyun	status = "okay";
800*4882a593Smuzhiyun};
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun&usbdp_phy1_dp {
803*4882a593Smuzhiyun	status = "okay";
804*4882a593Smuzhiyun};
805*4882a593Smuzhiyun
806*4882a593Smuzhiyun&usbdp_phy1_u3 {
807*4882a593Smuzhiyun	maximum-speed = "high-speed";
808*4882a593Smuzhiyun	status = "okay";
809*4882a593Smuzhiyun};
810*4882a593Smuzhiyun
811*4882a593Smuzhiyun&usbdrd3_0 {
812*4882a593Smuzhiyun	status = "okay";
813*4882a593Smuzhiyun};
814*4882a593Smuzhiyun
815*4882a593Smuzhiyun&usbdrd3_1 {
816*4882a593Smuzhiyun	status = "okay";
817*4882a593Smuzhiyun};
818*4882a593Smuzhiyun
819*4882a593Smuzhiyun&usbdrd_dwc3_0 {
820*4882a593Smuzhiyun	dr_mode = "peripheral";
821*4882a593Smuzhiyun	status = "okay";
822*4882a593Smuzhiyun};
823*4882a593Smuzhiyun
824*4882a593Smuzhiyun&usbdrd_dwc3_1 {
825*4882a593Smuzhiyun	dr_mode = "host";
826*4882a593Smuzhiyun	maximum-speed = "high-speed";
827*4882a593Smuzhiyun	status = "okay";
828*4882a593Smuzhiyun};
829*4882a593Smuzhiyun
830*4882a593Smuzhiyun&usbhost3_0 {
831*4882a593Smuzhiyun	status = "okay";
832*4882a593Smuzhiyun};
833*4882a593Smuzhiyun
834*4882a593Smuzhiyun&usbhost_dwc3_0 {
835*4882a593Smuzhiyun	dr_mode = "host";
836*4882a593Smuzhiyun	status = "okay";
837*4882a593Smuzhiyun};
838*4882a593Smuzhiyun
839*4882a593Smuzhiyun&vdd_log_s0 {
840*4882a593Smuzhiyun	regulator-state-mem {
841*4882a593Smuzhiyun		regulator-on-in-suspend;
842*4882a593Smuzhiyun		regulator-suspend-microvolt = <750000>;
843*4882a593Smuzhiyun	};
844*4882a593Smuzhiyun};
845*4882a593Smuzhiyun
846*4882a593Smuzhiyun&vdd_vdenc_s0 {
847*4882a593Smuzhiyun	regulator-init-microvolt = <750000>;
848*4882a593Smuzhiyun};
849*4882a593Smuzhiyun
850