1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "rk3588.dtsi" 8#include "rk3588-nvr.dtsi" 9#include "rk3588-rk806-single.dtsi" 10 11/ { 12 i2s0_sound: i2s0-sound { 13 status = "okay"; 14 compatible = "simple-audio-card"; 15 simple-audio-card,format = "i2s"; 16 simple-audio-card,mclk-fs = <256>; 17 simple-audio-card,name = "rockchip,es8311"; 18 simple-audio-card,dai-link@0 { 19 format = "i2s"; 20 cpu { 21 sound-dai = <&i2s0_8ch>; 22 }; 23 codec { 24 sound-dai = <&es8311>; 25 }; 26 }; 27 }; 28 29 leds: leds { 30 compatible = "gpio-leds"; 31 hdd_led: hdd-led { 32 gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; 33 default-state = "off"; 34 }; 35 net_led: net-led { 36 gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>; 37 default-state = "off"; 38 }; 39 work_led: work-led { 40 gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>; 41 linux,default-trigger = "heartbeat"; 42 }; 43 }; 44 45 pcie30_avdd0v75: pcie30-avdd0v75 { 46 compatible = "regulator-fixed"; 47 regulator-name = "pcie30_avdd0v75"; 48 regulator-boot-on; 49 regulator-always-on; 50 regulator-min-microvolt = <750000>; 51 regulator-max-microvolt = <750000>; 52 vin-supply = <&vdd_0v75_s0>; 53 }; 54 55 pcie30_avdd1v8: pcie30-avdd1v8 { 56 compatible = "regulator-fixed"; 57 regulator-name = "pcie30_avdd1v8"; 58 regulator-boot-on; 59 regulator-always-on; 60 regulator-min-microvolt = <1800000>; 61 regulator-max-microvolt = <1800000>; 62 vin-supply = <&avcc_1v8_s0>; 63 }; 64 65 vcc12v_dcin: vcc12v-dcin { 66 compatible = "regulator-fixed"; 67 regulator-name = "vcc12v_dcin"; 68 regulator-always-on; 69 regulator-boot-on; 70 regulator-min-microvolt = <12000000>; 71 regulator-max-microvolt = <12000000>; 72 }; 73 74 vcc3v3_pcie30: vcc3v3-pcie30 { 75 compatible = "regulator-fixed"; 76 regulator-name = "vcc3v3_pcie30"; 77 regulator-min-microvolt = <3300000>; 78 regulator-max-microvolt = <3300000>; 79 enable-active-high; 80 gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_HIGH>; 81 startup-delay-us = <7500>; 82 vin-supply = <&vcc12v_dcin>; 83 }; 84 85 vcc5v0_sys: vcc5v0-sys { 86 compatible = "regulator-fixed"; 87 regulator-name = "vcc5v0_sys"; 88 regulator-always-on; 89 regulator-boot-on; 90 regulator-min-microvolt = <5000000>; 91 regulator-max-microvolt = <5000000>; 92 vin-supply = <&vcc12v_dcin>; 93 }; 94 95 vcc5v0_host: vcc5v0-host-regulator { 96 compatible = "regulator-fixed"; 97 regulator-name = "vcc5v0_host"; 98 regulator-boot-on; 99 regulator-always-on; 100 regulator-min-microvolt = <5000000>; 101 regulator-max-microvolt = <5000000>; 102 enable-active-high; 103 gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 104 vin-supply = <&vcc5v0_sys>; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&vcc5v0_host_en>; 107 }; 108 109 vcc5v0_otg: vcc5v0-otg-regulator { 110 compatible = "regulator-fixed"; 111 regulator-name = "vcc5v0_otg"; 112 regulator-min-microvolt = <5000000>; 113 regulator-max-microvolt = <5000000>; 114 enable-active-high; 115 gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 116 vin-supply = <&vcc5v0_sys>; 117 pinctrl-names = "default"; 118 pinctrl-0 = <&vcc5v0_otg_en>; 119 }; 120 121 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { 122 compatible = "regulator-fixed"; 123 regulator-name = "vcc_1v1_nldo_s3"; 124 regulator-always-on; 125 regulator-boot-on; 126 regulator-min-microvolt = <1100000>; 127 regulator-max-microvolt = <1100000>; 128 vin-supply = <&vcc5v0_sys>; 129 }; 130}; 131 132&combphy0_ps { 133 pinctrl-names = "default"; 134 pinctrl-0 = <&sata0_pm_reset>; 135 status = "okay"; 136}; 137 138&combphy1_ps { 139 pinctrl-names = "default"; 140 pinctrl-0 = <&sata1_pm_reset>; 141 status = "okay"; 142}; 143 144&combphy2_psu { 145 status = "okay"; 146}; 147 148&dp0 { 149 pinctrl-0 = <&dp0m2_pins>; 150 pinctrl-names = "default"; 151 status = "okay"; 152}; 153 154&dp0_in_vp0 { 155 status = "okay"; 156}; 157 158&dp0_in_vp1 { 159 status = "okay"; 160}; 161 162&dp0_in_vp2 { 163 status = "okay"; 164}; 165 166&dp1 { 167 pinctrl-0 = <&dp1m2_pins &dp1_hdmi_ctl>; 168 pinctrl-names = "default"; 169 status = "okay"; 170}; 171 172&dp1_in_vp0 { 173 status = "okay"; 174}; 175 176&dp1_in_vp1 { 177 status = "okay"; 178}; 179 180&dp1_in_vp2 { 181 status = "okay"; 182}; 183 184&dp1_sound { 185 status = "okay"; 186}; 187 188&gmac0 { 189 /* Use rgmii-rxid mode to disable rx delay inside Soc */ 190 phy-mode = "rgmii-rxid"; 191 clock_in_out = "output"; 192 193 snps,reset-gpio = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>; 194 snps,reset-active-low; 195 /* Reset time is 20ms, 100ms for rtl8211f */ 196 snps,reset-delays-us = <0 20000 100000>; 197 198 pinctrl-names = "default"; 199 pinctrl-0 = <&gmac0_miim 200 &gmac0_tx_bus2 201 &gmac0_rx_bus2 202 &gmac0_rgmii_clk 203 &gmac0_rgmii_bus>; 204 205 tx_delay = <0x44>; 206 /* rx_delay = <0x4f>; */ 207 208 phy-handle = <&rgmii_phy0>; 209 status = "okay"; 210}; 211 212&gmac1 { 213 /* Use rgmii-rxid mode to disable rx delay inside Soc */ 214 phy-mode = "rgmii-rxid"; 215 clock_in_out = "output"; 216 217 snps,reset-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>; 218 snps,reset-active-low; 219 /* Reset time is 20ms, 100ms for rtl8211f */ 220 snps,reset-delays-us = <0 20000 100000>; 221 222 pinctrl-names = "default"; 223 pinctrl-0 = <&gmac1_miim 224 &gmac1_tx_bus2 225 &gmac1_rx_bus2 226 &gmac1_rgmii_clk 227 &gmac1_rgmii_bus>; 228 229 tx_delay = <0x42>; 230 /* rx_delay = <0x4f>; */ 231 232 phy-handle = <&rgmii_phy1>; 233 status = "okay"; 234}; 235 236&hdmi0 { 237 enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 238 status = "okay"; 239}; 240 241&hdmi0_in_vp0 { 242 status = "okay"; 243}; 244 245&hdmi0_in_vp1 { 246 status = "okay"; 247}; 248 249&hdmi0_in_vp2 { 250 status = "okay"; 251}; 252 253&hdmi0_sound { 254 status = "okay"; 255}; 256 257&hdmi1 { 258 enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 259 status = "okay"; 260}; 261 262&hdmi1_in_vp0 { 263 status = "okay"; 264}; 265 266&hdmi1_in_vp1 { 267 status = "okay"; 268}; 269 270&hdmi1_in_vp2 { 271 status = "okay"; 272}; 273 274&hdmi1_sound { 275 status = "okay"; 276}; 277 278&hdptxphy_hdmi0 { 279 status = "okay"; 280}; 281 282&hdptxphy_hdmi1 { 283 status = "okay"; 284}; 285 286&i2c0 { 287 status = "okay"; 288 pinctrl-names = "default"; 289 pinctrl-0 = <&i2c0m2_xfer>; 290 291 vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 292 compatible = "rockchip,rk8602"; 293 reg = <0x42>; 294 vin-supply = <&vcc5v0_sys>; 295 regulator-compatible = "rk860x-reg"; 296 regulator-name = "vdd_cpu_big0_s0"; 297 regulator-min-microvolt = <550000>; 298 regulator-max-microvolt = <1050000>; 299 regulator-ramp-delay = <2300>; 300 rockchip,suspend-voltage-selector = <1>; 301 regulator-boot-on; 302 regulator-always-on; 303 regulator-state-mem { 304 regulator-off-in-suspend; 305 }; 306 }; 307 308 vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 309 compatible = "rockchip,rk8603"; 310 reg = <0x43>; 311 vin-supply = <&vcc5v0_sys>; 312 regulator-compatible = "rk860x-reg"; 313 regulator-name = "vdd_cpu_big1_s0"; 314 regulator-min-microvolt = <550000>; 315 regulator-max-microvolt = <1050000>; 316 regulator-ramp-delay = <2300>; 317 rockchip,suspend-voltage-selector = <1>; 318 regulator-boot-on; 319 regulator-always-on; 320 regulator-state-mem { 321 regulator-off-in-suspend; 322 }; 323 }; 324}; 325 326&i2c2 { 327 status = "okay"; 328 329 vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 330 compatible = "rockchip,rk8602"; 331 reg = <0x42>; 332 vin-supply = <&vcc5v0_sys>; 333 regulator-compatible = "rk860x-reg"; 334 regulator-name = "vdd_npu_s0"; 335 regulator-min-microvolt = <550000>; 336 regulator-max-microvolt = <950000>; 337 regulator-ramp-delay = <2300>; 338 rockchip,suspend-voltage-selector = <1>; 339 regulator-boot-on; 340 regulator-always-on; 341 regulator-state-mem { 342 regulator-off-in-suspend; 343 }; 344 }; 345}; 346 347&i2c3 { 348 status = "okay"; 349 es8311: es8311@18 { 350 status = "okay"; 351 compatible = "everest,es8311"; 352 reg = <0x18>; 353 #sound-dai-cells = <0>; 354 adc-pga-gain = <6>; /* 18dB */ 355 adc-volume = <0xbf>; /* 0dB */ 356 dac-volume = <0xbf>; /* 0dB */ 357 aec-mode = "adc left, adc right"; 358 clocks = <&mclkout_i2s0>; 359 clock-names = "mclk"; 360 assigned-clocks = <&mclkout_i2s0>; 361 assigned-clock-rates = <12288000>; 362 pinctrl-names = "default"; 363 pinctrl-0 = <&i2s0_mclk>; 364 }; 365}; 366 367&i2c4 { 368 status = "okay"; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&i2c4m3_xfer>; 371}; 372 373&i2c5 { 374 status = "okay"; 375}; 376 377&i2c6 { 378 status = "okay"; 379 hym8563: hym8563@51 { 380 compatible = "haoyu,hym8563"; 381 reg = <0x51>; 382 383 pinctrl-names = "default"; 384 pinctrl-0 = <&rtc_int>; 385 386 interrupt-parent = <&gpio0>; 387 interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>; 388 wakeup-source; 389 }; 390}; 391 392&i2s0_8ch { 393 status = "okay"; 394 pinctrl-0 = <&i2s0_lrck 395 &i2s0_sclk 396 &i2s0_sdi0 397 &i2s0_sdo0>; 398}; 399 400&i2s5_8ch { 401 status = "okay"; 402}; 403 404&i2s6_8ch { 405 status = "okay"; 406}; 407 408&mdio0 { 409 rgmii_phy0: phy@1 { 410 compatible = "ethernet-phy-ieee802.3-c22"; 411 reg = <0x1>; 412 }; 413}; 414 415&mdio1 { 416 rgmii_phy1: phy@1 { 417 compatible = "ethernet-phy-ieee802.3-c22"; 418 reg = <0x1>; 419 }; 420}; 421 422&pcie30phy { 423 status = "okay"; 424}; 425 426&pcie3x4 { 427 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 428 vpcie3v3-supply = <&vcc3v3_pcie30>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&pcie30x4_clkreqn_m1>; 431 status = "okay"; 432}; 433 434&pwm3 { 435 compatible = "rockchip,remotectl-pwm"; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&pwm3m0_pins>; 438 remote_pwm_id = <3>; 439 handle_cpu_id = <1>; 440 remote_support_psci = <0>; 441 status = "okay"; 442 443 ir_key1 { 444 rockchip,usercode = <0x4040>; 445 rockchip,key_table = 446 <0xf2 KEY_REPLY>, 447 <0xba KEY_BACK>, 448 <0xf4 KEY_UP>, 449 <0xf1 KEY_DOWN>, 450 <0xef KEY_LEFT>, 451 <0xee KEY_RIGHT>, 452 <0xbd KEY_HOME>, 453 <0xea KEY_VOLUMEUP>, 454 <0xe3 KEY_VOLUMEDOWN>, 455 <0xe2 KEY_SEARCH>, 456 <0xb2 KEY_POWER>, 457 <0xbc KEY_MUTE>, 458 <0xec KEY_MENU>, 459 <0xbf 0x190>, 460 <0xe0 0x191>, 461 <0xe1 0x192>, 462 <0xe9 183>, 463 <0xe6 248>, 464 <0xe8 185>, 465 <0xe7 186>, 466 <0xf0 388>, 467 <0xbe 0x175>; 468 }; 469 470 ir_key2 { 471 rockchip,usercode = <0xff00>; 472 rockchip,key_table = 473 <0xf9 KEY_HOME>, 474 <0xbf KEY_BACK>, 475 <0xfb KEY_MENU>, 476 <0xaa KEY_REPLY>, 477 <0xb9 KEY_UP>, 478 <0xe9 KEY_DOWN>, 479 <0xb8 KEY_LEFT>, 480 <0xea KEY_RIGHT>, 481 <0xeb KEY_VOLUMEDOWN>, 482 <0xef KEY_VOLUMEUP>, 483 <0xf7 KEY_MUTE>, 484 <0xe7 KEY_POWER>, 485 <0xfc KEY_POWER>, 486 <0xa9 KEY_VOLUMEDOWN>, 487 <0xa8 KEY_PLAYPAUSE>, 488 <0xe0 KEY_VOLUMEDOWN>, 489 <0xa5 KEY_VOLUMEDOWN>, 490 <0xab 183>, 491 <0xb7 388>, 492 <0xe8 388>, 493 <0xf8 184>, 494 <0xaf 185>, 495 <0xed KEY_VOLUMEDOWN>, 496 <0xee 186>, 497 <0xb3 KEY_VOLUMEDOWN>, 498 <0xf1 KEY_VOLUMEDOWN>, 499 <0xf2 KEY_VOLUMEDOWN>, 500 <0xf3 KEY_SEARCH>, 501 <0xb4 KEY_VOLUMEDOWN>, 502 <0xa4 KEY_SETUP>, 503 <0xbe KEY_SEARCH>; 504 }; 505 506 ir_key3 { 507 rockchip,usercode = <0x1dcc>; 508 rockchip,key_table = 509 <0xee KEY_REPLY>, 510 <0xf0 KEY_BACK>, 511 <0xf8 KEY_UP>, 512 <0xbb KEY_DOWN>, 513 <0xef KEY_LEFT>, 514 <0xed KEY_RIGHT>, 515 <0xfc KEY_HOME>, 516 <0xf1 KEY_VOLUMEUP>, 517 <0xfd KEY_VOLUMEDOWN>, 518 <0xb7 KEY_SEARCH>, 519 <0xff KEY_POWER>, 520 <0xf3 KEY_MUTE>, 521 <0xbf KEY_MENU>, 522 <0xf9 0x191>, 523 <0xf5 0x192>, 524 <0xb3 388>, 525 <0xbe KEY_1>, 526 <0xba KEY_2>, 527 <0xb2 KEY_3>, 528 <0xbd KEY_4>, 529 <0xf9 KEY_5>, 530 <0xb1 KEY_6>, 531 <0xfc KEY_7>, 532 <0xf8 KEY_8>, 533 <0xb0 KEY_9>, 534 <0xb6 KEY_0>, 535 <0xb5 KEY_BACKSPACE>; 536 }; 537}; 538 539&rk806single { 540 pinctrl-names = "default", "pmic-power-off"; 541 pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; 542 pinctrl-1 = <&rk806_dvs1_slp>, <&rk806_dvs2_null>, <&rk806_dvs3_null>; 543 544 regulators { 545 avcc_1v8_s0: PLDO_REG1 { 546 regulator-always-on; 547 regulator-boot-on; 548 regulator-min-microvolt = <1800000>; 549 regulator-max-microvolt = <1800000>; 550 regulator-name = "avcc_1v8_s0"; 551 regulator-state-mem { 552 regulator-on-in-suspend; 553 regulator-suspend-microvolt = <1800000>; 554 }; 555 }; 556 }; 557}; 558 559&rockchip_suspend { 560 status = "okay"; 561 rockchip,sleep-debug-en = <1>; 562 rockchip,virtual-poweroff = <1>; 563 rockchip,sleep-mode-config = < 564 (0 565 | RKPM_SLP_ARMOFF_DDRPD 566 ) 567 >; 568 rockchip,wakeup-config = < 569 (0 570 | RKPM_CPU0_WKUP_EN 571 | RKPM_GPIO_WKUP_EN 572 ) 573 >; 574}; 575 576&route_dp0 { 577 status = "okay"; 578 force-output; 579 connect = <&vp2_out_dp0>; 580 581 force_timing { 582 clock-frequency = <65000000>; 583 hactive = <1024>; 584 vactive = <768>; 585 hfront-porch = <24>; 586 hsync-len = <136>; 587 hback-porch = <160>; 588 vfront-porch = <3>; 589 vsync-len = <6>; 590 vback-porch = <29>; 591 hsync-active = <0>; 592 vsync-active = <0>; 593 de-active = <0>; 594 pixelclk-active = <0>; 595 }; 596 597}; 598 599&route_dp1 { 600 status = "okay"; 601 force-output; 602 connect = <&vp2_out_dp1>; 603 604 force_timing { 605 clock-frequency = <65000000>; 606 hactive = <1024>; 607 vactive = <768>; 608 hfront-porch = <24>; 609 hsync-len = <136>; 610 hback-porch = <160>; 611 vfront-porch = <3>; 612 vsync-len = <6>; 613 vback-porch = <29>; 614 hsync-active = <0>; 615 vsync-active = <0>; 616 de-active = <0>; 617 pixelclk-active = <0>; 618 }; 619 620}; 621 622&route_hdmi0 { 623 status = "okay"; 624 force-output; 625 connect = <&vp2_out_hdmi0>; 626 627 force_timing { 628 clock-frequency = <65000000>; 629 hactive = <1024>; 630 vactive = <768>; 631 hfront-porch = <24>; 632 hsync-len = <136>; 633 hback-porch = <160>; 634 vfront-porch = <3>; 635 vsync-len = <6>; 636 vback-porch = <29>; 637 hsync-active = <0>; 638 vsync-active = <0>; 639 de-active = <0>; 640 pixelclk-active = <0>; 641 }; 642 643}; 644 645&route_hdmi1 { 646 status = "okay"; 647 force-output; 648 connect = <&vp2_out_hdmi1>; 649 650 force_timing { 651 clock-frequency = <65000000>; 652 hactive = <1024>; 653 vactive = <768>; 654 hfront-porch = <24>; 655 hsync-len = <136>; 656 hback-porch = <160>; 657 vfront-porch = <3>; 658 vsync-len = <6>; 659 vback-porch = <29>; 660 hsync-active = <0>; 661 vsync-active = <0>; 662 de-active = <0>; 663 pixelclk-active = <0>; 664 }; 665 666}; 667 668&sata0 { 669 status = "okay"; 670}; 671 672&sata1 { 673 status = "okay"; 674}; 675 676&sdhci { 677 bus-width = <8>; 678 no-sdio; 679 no-sd; 680 non-removable; 681 max-frequency = <200000000>; 682 mmc-hs400-1_8v; 683 mmc-hs400-enhanced-strobe; 684 status = "okay"; 685}; 686 687&spdif_tx5 { 688 status = "okay"; 689}; 690 691&pinctrl { 692 dp { 693 dp1_hdmi_ctl: dp-hdmi-ctl { 694 rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>, 695 <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; 696 }; 697 }; 698 699 pcie30x4 { 700 pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { 701 rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; 702 }; 703 }; 704 705 706 rtc { 707 rtc_int: rtc-int { 708 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; 709 }; 710 }; 711 712 usb { 713 vcc5v0_host_en: vcc5v0-host-en { 714 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 715 }; 716 717 vcc5v0_otg_en: vcc5v0-otg-en { 718 rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>; 719 }; 720 }; 721 722 sata { 723 sata0_pm_reset: sata0-pm-reset { 724 rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_output_high>; 725 }; 726 sata1_pm_reset: sata1-pm-reset { 727 rockchip,pins = <4 RK_PA1 RK_FUNC_GPIO &pcfg_output_high>; 728 }; 729 }; 730}; 731 732&u2phy0 { 733 status = "okay"; 734}; 735 736&u2phy1 { 737 status = "okay"; 738}; 739 740&u2phy2 { 741 status = "okay"; 742}; 743 744&u2phy3 { 745 status = "okay"; 746}; 747 748&u2phy0_otg { 749 vbus-supply = <&vcc5v0_otg>; 750 status = "okay"; 751}; 752 753&u2phy1_otg { 754 phy-supply = <&vcc5v0_host>; 755 status = "okay"; 756}; 757 758&u2phy2_host { 759 phy-supply = <&vcc5v0_host>; 760 status = "okay"; 761}; 762 763&u2phy3_host { 764 phy-supply = <&vcc5v0_host>; 765 status = "okay"; 766}; 767 768&usb_host0_ehci { 769 status = "okay"; 770}; 771 772&usb_host0_ohci { 773 status = "okay"; 774}; 775 776&usb_host1_ehci { 777 status = "okay"; 778}; 779 780&usb_host1_ohci { 781 status = "okay"; 782}; 783 784&usbdp_phy0 { 785 rockchip,dp-lane-mux = < 2 3 >; 786 status = "okay"; 787}; 788 789&usbdp_phy0_dp { 790 status = "okay"; 791}; 792 793&usbdp_phy0_u3 { 794 status = "okay"; 795}; 796 797&usbdp_phy1 { 798 rockchip,dp-lane-mux = < 0 1 2 3 >; 799 status = "okay"; 800}; 801 802&usbdp_phy1_dp { 803 status = "okay"; 804}; 805 806&usbdp_phy1_u3 { 807 maximum-speed = "high-speed"; 808 status = "okay"; 809}; 810 811&usbdrd3_0 { 812 status = "okay"; 813}; 814 815&usbdrd3_1 { 816 status = "okay"; 817}; 818 819&usbdrd_dwc3_0 { 820 dr_mode = "peripheral"; 821 status = "okay"; 822}; 823 824&usbdrd_dwc3_1 { 825 dr_mode = "host"; 826 maximum-speed = "high-speed"; 827 status = "okay"; 828}; 829 830&usbhost3_0 { 831 status = "okay"; 832}; 833 834&usbhost_dwc3_0 { 835 dr_mode = "host"; 836 status = "okay"; 837}; 838 839&vdd_log_s0 { 840 regulator-state-mem { 841 regulator-on-in-suspend; 842 regulator-suspend-microvolt = <750000>; 843 }; 844}; 845 846&vdd_vdenc_s0 { 847 regulator-init-microvolt = <750000>; 848}; 849 850