1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6/ { 7 vcc_mipicsi0: vcc-mipicsi0-regulator { 8 compatible = "regulator-fixed"; 9 gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 10 pinctrl-names = "default"; 11 pinctrl-0 = <&mipicsi0_pwr>; 12 regulator-name = "vcc_mipicsi0"; 13 enable-active-high; 14 }; 15 16 vcc_mipicsi1: vcc-mipicsi1-regulator { 17 compatible = "regulator-fixed"; 18 gpio = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 19 pinctrl-names = "default"; 20 pinctrl-0 = <&mipicsi1_pwr>; 21 regulator-name = "vcc_mipicsi1"; 22 enable-active-high; 23 }; 24}; 25 26&pinctrl { 27 cam { 28 mipicsi0_pwr: mipicsi0-pwr { 29 rockchip,pins = 30 <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 31 }; 32 33 mipicsi1_pwr: mipicsi1-pwr { 34 rockchip,pins = 35 <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 36 }; 37 }; 38}; 39 40&csi2_dphy0_hw { 41 status = "okay"; 42}; 43 44&csi2_dphy1_hw { 45 status = "okay"; 46}; 47 48&csi2_dphy1 { 49 status = "okay"; 50 51 ports { 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 port@0 { 56 reg = <0>; 57 #address-cells = <1>; 58 #size-cells = <0>; 59 60 mipi_in_ucam2: endpoint@1 { 61 reg = <1>; 62 remote-endpoint = <&imx464_out2>; 63 data-lanes = <1 2>; 64 }; 65 }; 66 67 port@1 { 68 reg = <1>; 69 #address-cells = <1>; 70 #size-cells = <0>; 71 72 csidphy1_out: endpoint@0 { 73 reg = <0>; 74 remote-endpoint = <&mipi2_csi2_input>; 75 }; 76 }; 77 }; 78}; 79 80&csi2_dphy2 { 81 status = "okay"; 82 83 ports { 84 #address-cells = <1>; 85 #size-cells = <0>; 86 87 port@0 { 88 reg = <0>; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 92 mipi_in_ucam3: endpoint@1 { 93 reg = <1>; 94 remote-endpoint = <&imx464_out3>; 95 data-lanes = <1 2>; 96 }; 97 }; 98 99 port@1 { 100 reg = <1>; 101 #address-cells = <1>; 102 #size-cells = <0>; 103 104 csidphy2_out: endpoint@0 { 105 reg = <0>; 106 remote-endpoint = <&mipi3_csi2_input>; 107 }; 108 }; 109 }; 110}; 111 112&csi2_dphy4 { 113 status = "okay"; 114 115 ports { 116 #address-cells = <1>; 117 #size-cells = <0>; 118 119 port@0 { 120 reg = <0>; 121 #address-cells = <1>; 122 #size-cells = <0>; 123 124 mipi_in_ucam4: endpoint@1 { 125 reg = <1>; 126 remote-endpoint = <&imx464_out4>; 127 data-lanes = <1 2>; 128 }; 129 }; 130 131 port@1 { 132 reg = <1>; 133 #address-cells = <1>; 134 #size-cells = <0>; 135 136 csidphy4_out: endpoint@0 { 137 reg = <0>; 138 remote-endpoint = <&mipi4_csi2_input>; 139 }; 140 }; 141 }; 142}; 143 144&csi2_dphy5 { 145 status = "okay"; 146 147 ports { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 151 port@0 { 152 reg = <0>; 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 mipi_in_ucam5: endpoint@1 { 157 reg = <1>; 158 remote-endpoint = <&imx464_out5>; 159 data-lanes = <1 2>; 160 }; 161 }; 162 163 port@1 { 164 reg = <1>; 165 #address-cells = <1>; 166 #size-cells = <0>; 167 168 csidphy5_out: endpoint@0 { 169 reg = <0>; 170 remote-endpoint = <&mipi5_csi2_input>; 171 }; 172 }; 173 }; 174}; 175 176&i2c5 { 177 status = "okay"; 178 179 pinctrl-0 = <&i2c5m3_xfer>; 180 /* module 77/79 0x1a 78/80 0x36 */ 181 imx464_2: imx464-2@1a { 182 compatible = "sony,imx464"; 183 status = "okay"; 184 reg = <0x1a>; 185 clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; 186 clock-names = "xvclk"; 187 power-domains = <&power RK3588_PD_VI>; 188 pinctrl-names = "default"; 189 pinctrl-0 = <&mipim0_camera3_clk>; 190 avdd-supply = <&vcc_mipicsi0>; 191 reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; 192 pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; 193 rockchip,camera-module-sync-mode = "internal_master"; 194 rockchip,camera-module-index = <2>; 195 rockchip,camera-module-facing = "back"; 196 rockchip,camera-module-name = "CMK-OT1980-PX1"; 197 rockchip,camera-module-lens-name = "SHG102"; 198 port { 199 imx464_out2: endpoint { 200 remote-endpoint = <&mipi_in_ucam2>; 201 data-lanes = <1 2>; 202 }; 203 }; 204 }; 205 206 imx464_3: imx464-3@36 { 207 compatible = "sony,imx464"; 208 status = "okay"; 209 reg = <0x36>; 210 clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; 211 clock-names = "xvclk"; 212 power-domains = <&power RK3588_PD_VI>; 213 avdd-supply = <&vcc_mipicsi0>; 214 pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; 215 rockchip,camera-module-sync-mode = "external_master"; 216 rockchip,camera-module-index = <3>; 217 rockchip,camera-module-facing = "back"; 218 rockchip,camera-module-name = "CMK-OT1980-PX1"; 219 rockchip,camera-module-lens-name = "SHG102"; 220 port { 221 imx464_out3: endpoint { 222 remote-endpoint = <&mipi_in_ucam3>; 223 data-lanes = <1 2>; 224 }; 225 }; 226 }; 227}; 228 229&i2c4 { 230 status = "okay"; 231 232 pinctrl-0 = <&i2c4m3_xfer>; 233 /* 77/79 0x1a 78/80 0x36 */ 234 imx464_4: imx464-4@1a { 235 compatible = "sony,imx464"; 236 status = "okay"; 237 reg = <0x1a>; 238 clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; 239 clock-names = "xvclk"; 240 power-domains = <&power RK3588_PD_VI>; 241 pinctrl-names = "default"; 242 pinctrl-0 = <&mipim0_camera4_clk>; 243 avdd-supply = <&vcc_mipicsi1>; 244 reset-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; 245 pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; 246 rockchip,camera-module-sync-mode = "external_master"; 247 rockchip,camera-module-index = <0>; 248 rockchip,camera-module-facing = "back"; 249 rockchip,camera-module-name = "CMK-OT1980-PX1"; 250 rockchip,camera-module-lens-name = "SHG102"; 251 port { 252 imx464_out4: endpoint { 253 remote-endpoint = <&mipi_in_ucam4>; 254 data-lanes = <1 2>; 255 }; 256 }; 257 }; 258 259 imx464_5: imx464-5@36 { 260 compatible = "sony,imx464"; 261 status = "okay"; 262 reg = <0x36>; 263 clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; 264 clock-names = "xvclk"; 265 power-domains = <&power RK3588_PD_VI>; 266 avdd-supply = <&vcc_mipicsi1>; 267 pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; 268 rockchip,camera-module-sync-mode = "external_master"; 269 rockchip,camera-module-index = <1>; 270 rockchip,camera-module-facing = "back"; 271 rockchip,camera-module-name = "CMK-OT1980-PX1"; 272 rockchip,camera-module-lens-name = "SHG102"; 273 port { 274 imx464_out5: endpoint { 275 remote-endpoint = <&mipi_in_ucam5>; 276 data-lanes = <1 2>; 277 }; 278 }; 279 }; 280}; 281 282&mipi2_csi2 { 283 status = "okay"; 284 285 ports { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 289 port@0 { 290 reg = <0>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 294 mipi2_csi2_input: endpoint@1 { 295 reg = <1>; 296 remote-endpoint = <&csidphy1_out>; 297 }; 298 }; 299 300 port@1 { 301 reg = <1>; 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 mipi2_csi2_output: endpoint@0 { 306 reg = <0>; 307 remote-endpoint = <&cif_mipi_in2>; 308 }; 309 }; 310 }; 311}; 312 313&mipi3_csi2 { 314 status = "okay"; 315 316 ports { 317 #address-cells = <1>; 318 #size-cells = <0>; 319 320 port@0 { 321 reg = <0>; 322 #address-cells = <1>; 323 #size-cells = <0>; 324 325 mipi3_csi2_input: endpoint@1 { 326 reg = <1>; 327 remote-endpoint = <&csidphy2_out>; 328 }; 329 }; 330 331 port@1 { 332 reg = <1>; 333 #address-cells = <1>; 334 #size-cells = <0>; 335 336 mipi3_csi2_output: endpoint@0 { 337 reg = <0>; 338 remote-endpoint = <&cif_mipi_in3>; 339 }; 340 }; 341 }; 342}; 343 344&mipi4_csi2 { 345 status = "okay"; 346 347 ports { 348 #address-cells = <1>; 349 #size-cells = <0>; 350 351 port@0 { 352 reg = <0>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 356 mipi4_csi2_input: endpoint@1 { 357 reg = <1>; 358 remote-endpoint = <&csidphy4_out>; 359 }; 360 }; 361 362 port@1 { 363 reg = <1>; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 367 mipi4_csi2_output: endpoint@0 { 368 reg = <0>; 369 remote-endpoint = <&cif_mipi_in4>; 370 }; 371 }; 372 }; 373}; 374 375&mipi5_csi2 { 376 status = "okay"; 377 378 ports { 379 #address-cells = <1>; 380 #size-cells = <0>; 381 382 port@0 { 383 reg = <0>; 384 #address-cells = <1>; 385 #size-cells = <0>; 386 387 mipi5_csi2_input: endpoint@1 { 388 reg = <1>; 389 remote-endpoint = <&csidphy5_out>; 390 }; 391 }; 392 393 port@1 { 394 reg = <1>; 395 #address-cells = <1>; 396 #size-cells = <0>; 397 398 mipi5_csi2_output: endpoint@0 { 399 reg = <0>; 400 remote-endpoint = <&cif_mipi_in5>; 401 }; 402 }; 403 }; 404}; 405 406&rkcif { 407 status = "okay"; 408}; 409 410&rkcif_mipi_lvds2 { 411 status = "okay"; 412 413 port { 414 cif_mipi_in2: endpoint { 415 remote-endpoint = <&mipi2_csi2_output>; 416 }; 417 }; 418}; 419 420&rkcif_mipi_lvds2_sditf { 421 status = "okay"; 422 423 port { 424 mipi2_lvds_sditf: endpoint { 425 remote-endpoint = <&isp0_vir0>; 426 }; 427 }; 428}; 429 430&rkcif_mipi_lvds3 { 431 status = "okay"; 432 433 port { 434 cif_mipi_in3: endpoint { 435 remote-endpoint = <&mipi3_csi2_output>; 436 }; 437 }; 438}; 439 440&rkcif_mipi_lvds3_sditf { 441 status = "okay"; 442 443 port { 444 mipi3_lvds_sditf: endpoint { 445 remote-endpoint = <&isp1_vir0>; 446 }; 447 }; 448}; 449 450&rkcif_mipi_lvds4 { 451 status = "okay"; 452 453 port { 454 cif_mipi_in4: endpoint { 455 remote-endpoint = <&mipi4_csi2_output>; 456 }; 457 }; 458}; 459 460&rkcif_mipi_lvds4_sditf { 461 status = "okay"; 462 463 port { 464 mipi4_lvds_sditf: endpoint { 465 remote-endpoint = <&isp0_vir1>; 466 }; 467 }; 468}; 469 470&rkcif_mipi_lvds5 { 471 status = "okay"; 472 473 port { 474 cif_mipi_in5: endpoint { 475 remote-endpoint = <&mipi5_csi2_output>; 476 }; 477 }; 478}; 479 480&rkcif_mipi_lvds5_sditf { 481 status = "okay"; 482 483 port { 484 mipi5_lvds_sditf: endpoint { 485 remote-endpoint = <&isp1_vir1>; 486 }; 487 }; 488}; 489 490&rkcif_mmu { 491 status = "okay"; 492}; 493 494&rkisp0 { 495 status = "okay"; 496}; 497 498&isp0_mmu { 499 status = "okay"; 500}; 501 502&rkisp0_vir0 { 503 status = "okay"; 504 505 port { 506 #address-cells = <1>; 507 #size-cells = <0>; 508 509 isp0_vir0: endpoint@0 { 510 reg = <0>; 511 remote-endpoint = <&mipi2_lvds_sditf>; 512 }; 513 }; 514}; 515 516&rkisp0_vir1 { 517 status = "okay"; 518 519 port { 520 #address-cells = <1>; 521 #size-cells = <0>; 522 523 isp0_vir1: endpoint@0 { 524 reg = <0>; 525 remote-endpoint = <&mipi4_lvds_sditf>; 526 }; 527 }; 528}; 529 530&rkisp1 { 531 status = "okay"; 532}; 533 534&isp1_mmu { 535 status = "okay"; 536}; 537 538&rkisp1_vir0 { 539 status = "okay"; 540 541 port { 542 #address-cells = <1>; 543 #size-cells = <0>; 544 545 isp1_vir0: endpoint@0 { 546 reg = <0>; 547 remote-endpoint = <&mipi3_lvds_sditf>; 548 }; 549 }; 550}; 551 552&rkisp1_vir1 { 553 status = "okay"; 554 555 port { 556 #address-cells = <1>; 557 #size-cells = <0>; 558 559 isp1_vir1: endpoint@0 { 560 reg = <0>; 561 remote-endpoint = <&mipi5_lvds_sditf>; 562 }; 563 }; 564}; 565 566