1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "dt-bindings/usb/pd.h" 8#include "rk3588.dtsi" 9#include "rk3588-evb.dtsi" 10#include "rk3588-rk806-single.dtsi" 11 12/ { 13 /* If hdmirx node is disabled, delete the reserved-memory node here. */ 14 reserved-memory { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 ranges; 18 19 /* Reserve 128MB memory for hdmirx-controller@fdee0000 */ 20 cma { 21 compatible = "shared-dma-pool"; 22 reusable; 23 reg = <0x0 (256 * 0x100000) 0x0 (128 * 0x100000)>; 24 linux,cma-default; 25 }; 26 }; 27 28 es8388_sound: es8388-sound { 29 status = "okay"; 30 compatible = "rockchip,multicodecs-card"; 31 rockchip,card-name = "rockchip-es8388"; 32 hp-det-gpio = <&gpio1 RK_PC4 GPIO_ACTIVE_LOW>; 33 io-channels = <&saradc 3>; 34 io-channel-names = "adc-detect"; 35 keyup-threshold-microvolt = <1800000>; 36 poll-interval = <100>; 37 spk-con-gpio = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 38 hp-con-gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 39 rockchip,format = "i2s"; 40 rockchip,mclk-fs = <256>; 41 rockchip,cpu = <&i2s0_8ch>; 42 rockchip,codec = <&es8388>; 43 rockchip,audio-routing = 44 "Headphone", "LOUT1", 45 "Headphone", "ROUT1", 46 "Speaker", "LOUT2", 47 "Speaker", "ROUT2", 48 "Headphone", "Headphone Power", 49 "Headphone", "Headphone Power", 50 "Speaker", "Speaker Power", 51 "Speaker", "Speaker Power", 52 "LINPUT1", "Main Mic", 53 "LINPUT2", "Main Mic", 54 "RINPUT1", "Headset Mic", 55 "RINPUT2", "Headset Mic"; 56 pinctrl-names = "default"; 57 pinctrl-0 = <&hp_det>; 58 play-pause-key { 59 label = "playpause"; 60 linux,code = <KEY_PLAYPAUSE>; 61 press-threshold-microvolt = <2000>; 62 }; 63 }; 64 65 fan: pwm-fan { 66 compatible = "pwm-fan"; 67 #cooling-cells = <2>; 68 pwms = <&pwm3 0 50000 0>; 69 cooling-levels = <0 50 100 150 200 255>; 70 rockchip,temp-trips = < 71 50000 1 72 55000 2 73 60000 3 74 65000 4 75 70000 5 76 >; 77 }; 78 79 hdmiin-sound { 80 compatible = "rockchip,hdmi"; 81 rockchip,mclk-fs = <128>; 82 rockchip,format = "i2s"; 83 rockchip,bitclock-master = <&hdmirx_ctrler>; 84 rockchip,frame-master = <&hdmirx_ctrler>; 85 rockchip,card-name = "rockchip,hdmiin"; 86 rockchip,cpu = <&i2s7_8ch>; 87 rockchip,codec = <&hdmirx_ctrler 0>; 88 rockchip,jack-det; 89 }; 90 91 pcie20_avdd0v85: pcie20-avdd0v85 { 92 compatible = "regulator-fixed"; 93 regulator-name = "pcie20_avdd0v85"; 94 regulator-boot-on; 95 regulator-always-on; 96 regulator-min-microvolt = <850000>; 97 regulator-max-microvolt = <850000>; 98 vin-supply = <&vdd_0v85_s0>; 99 }; 100 101 pcie20_avdd1v8: pcie20-avdd1v8 { 102 compatible = "regulator-fixed"; 103 regulator-name = "pcie20_avdd1v8"; 104 regulator-boot-on; 105 regulator-always-on; 106 regulator-min-microvolt = <1800000>; 107 regulator-max-microvolt = <1800000>; 108 vin-supply = <&avcc_1v8_s0>; 109 }; 110 111 pcie30_avdd0v75: pcie30-avdd0v75 { 112 compatible = "regulator-fixed"; 113 regulator-name = "pcie30_avdd0v75"; 114 regulator-boot-on; 115 regulator-always-on; 116 regulator-min-microvolt = <750000>; 117 regulator-max-microvolt = <750000>; 118 vin-supply = <&avdd_0v75_s0>; 119 }; 120 121 pcie30_avdd1v8: pcie30-avdd1v8 { 122 compatible = "regulator-fixed"; 123 regulator-name = "pcie30_avdd1v8"; 124 regulator-boot-on; 125 regulator-always-on; 126 regulator-min-microvolt = <1800000>; 127 regulator-max-microvolt = <1800000>; 128 vin-supply = <&avcc_1v8_s0>; 129 }; 130 131 sdio_pwrseq: sdio-pwrseq { 132 compatible = "mmc-pwrseq-simple"; 133 clocks = <&hym8563>; 134 clock-names = "ext_clock"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&wifi_enable_h>; 137 /* 138 * On the module itself this is one of these (depending 139 * on the actual card populated): 140 * - SDIO_RESET_L_WL_REG_ON 141 * - PDN (power down when low) 142 */ 143 post-power-on-delay-ms = <200>; 144 reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; 145 }; 146 147 rk_headset: rk-headset { 148 status = "disabled"; 149 compatible = "rockchip_headset"; 150 headset_gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 151 pinctrl-names = "default"; 152 pinctrl-0 = <&hp_det>; 153 io-channels = <&saradc 3>; 154 }; 155 156 157 vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 { 158 compatible = "regulator-fixed"; 159 regulator-name = "vcc_1v1_nldo_s3"; 160 regulator-always-on; 161 regulator-boot-on; 162 regulator-min-microvolt = <1100000>; 163 regulator-max-microvolt = <1100000>; 164 vin-supply = <&vcc5v0_sys>; 165 }; 166 167 vcc3v3_lcd_n: vcc3v3-lcd0-n { 168 compatible = "regulator-fixed"; 169 regulator-name = "vcc3v3_lcd0_n"; 170 regulator-boot-on; 171 enable-active-high; 172 gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 173 vin-supply = <&vcc_1v8_s0>; 174 }; 175 176 vcc3v3_pcie30: vcc3v3-pcie30 { 177 compatible = "regulator-fixed"; 178 regulator-name = "vcc3v3_pcie30"; 179 regulator-min-microvolt = <3300000>; 180 regulator-max-microvolt = <3300000>; 181 enable-active-high; 182 gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; 183 startup-delay-us = <5000>; 184 vin-supply = <&vcc12v_dcin>; 185 }; 186 187 vcc5v0_host: vcc5v0-host { 188 compatible = "regulator-fixed"; 189 regulator-name = "vcc5v0_host"; 190 regulator-boot-on; 191 regulator-always-on; 192 regulator-min-microvolt = <5000000>; 193 regulator-max-microvolt = <5000000>; 194 enable-active-high; 195 gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 196 vin-supply = <&vcc5v0_usb>; 197 pinctrl-names = "default"; 198 pinctrl-0 = <&vcc5v0_host_en>; 199 }; 200 201 vcc_mipicsi0: vcc-mipicsi0-regulator { 202 compatible = "regulator-fixed"; 203 gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>; 204 pinctrl-names = "default"; 205 pinctrl-0 = <&mipicsi0_pwr>; 206 regulator-name = "vcc_mipicsi0"; 207 enable-active-high; 208 }; 209 210 vcc_mipicsi1: vcc-mipicsi1-regulator { 211 compatible = "regulator-fixed"; 212 gpio = <&gpio1 RK_PD3 GPIO_ACTIVE_HIGH>; 213 pinctrl-names = "default"; 214 pinctrl-0 = <&mipicsi1_pwr>; 215 regulator-name = "vcc_mipicsi1"; 216 enable-active-high; 217 }; 218 219 vcc_mipidcphy0: vcc-mipidcphy0-regulator { 220 compatible = "regulator-fixed"; 221 gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>; 222 pinctrl-names = "default"; 223 pinctrl-0 = <&mipidcphy0_pwr>; 224 regulator-name = "vcc_mipidcphy0"; 225 enable-active-high; 226 }; 227 228 vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator { 229 compatible = "regulator-fixed"; 230 gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 231 pinctrl-names = "default"; 232 pinctrl-0 = <&sd_s0_pwr>; 233 regulator-name = "vcc_3v3_sd_s0"; 234 enable-active-high; 235 }; 236 237 wireless_bluetooth: wireless-bluetooth { 238 compatible = "bluetooth-platdata"; 239 clocks = <&hym8563>; 240 clock-names = "ext_clock"; 241 uart_rts_gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_LOW>; 242 pinctrl-names = "default", "rts_gpio"; 243 pinctrl-0 = <&uart9m0_rtsn>, <&bt_reset_gpio>, <&bt_wake_gpio>, <&bt_irq_gpio>; 244 pinctrl-1 = <&uart9_gpios>; 245 BT,reset_gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 246 BT,wake_gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 247 BT,wake_host_irq = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 248 status = "okay"; 249 }; 250 251 wireless_wlan: wireless-wlan { 252 compatible = "wlan-platdata"; 253 wifi_chip_type = "ap6398s"; 254 pinctrl-names = "default"; 255 pinctrl-0 = <&wifi_host_wake_irq>; 256 WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; 257 WIFI,poweren_gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>; 258 status = "okay"; 259 }; 260}; 261 262&backlight { 263 pwms = <&pwm1 0 25000 0>; 264 status = "okay"; 265}; 266 267&combphy0_ps { 268 status = "okay"; 269}; 270 271&combphy1_ps { 272 status = "okay"; 273}; 274 275&combphy2_psu { 276 status = "okay"; 277}; 278 279&dp0 { 280 pinctrl-names = "default"; 281 pinctrl-0 = <&vga_hpdin_l>; 282 hpd-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 283 status = "okay"; 284}; 285 286&dp0_in_vp2 { 287 status = "okay"; 288}; 289 290&dp1 { 291 pinctrl-names = "default"; 292 pinctrl-0 = <&dp1m0_pins>; 293 status = "okay"; 294}; 295 296&dp1_in_vp2 { 297 status = "okay"; 298}; 299 300/* 301 * mipi_dcphy0 needs to be enabled 302 * when dsi0 is enabled 303 */ 304&dsi0 { 305 status = "okay"; 306}; 307 308&dsi0_in_vp2 { 309 status = "disabled"; 310}; 311 312&dsi0_in_vp3 { 313 status = "okay"; 314}; 315 316&dsi0_panel { 317 power-supply = <&vcc3v3_lcd_n>; 318 reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; 319 pinctrl-names = "default"; 320 pinctrl-0 = <&lcd_rst_gpio>; 321}; 322 323/* 324 * mipi_dcphy1 needs to be enabled 325 * when dsi1 is enabled 326 */ 327&dsi1 { 328 status = "disabled"; 329}; 330 331&dsi1_in_vp2 { 332 status = "disabled"; 333}; 334 335&dsi1_in_vp3 { 336 status = "disabled"; 337}; 338 339&dsi1_panel { 340 power-supply = <&vcc3v3_lcd_n>; 341 342 /* 343 * because in hardware, the two screens share the reset pin, 344 * so reset-gpios need only in dsi1 enable and dsi0 disabled 345 * case. 346 */ 347 348 //reset-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_LOW>; 349 //pinctrl-names = "default"; 350 //pinctrl-0 = <&lcd_rst_gpio>; 351}; 352 353&gmac1 { 354 /* Use rgmii-rxid mode to disable rx delay inside Soc */ 355 phy-mode = "rgmii-rxid"; 356 clock_in_out = "output"; 357 358 snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 359 snps,reset-active-low; 360 /* Reset time is 20ms, 100ms for rtl8211f */ 361 snps,reset-delays-us = <0 20000 100000>; 362 363 pinctrl-names = "default"; 364 pinctrl-0 = <&gmac1_miim 365 &gmac1_tx_bus2 366 &gmac1_rx_bus2 367 &gmac1_rgmii_clk 368 &gmac1_rgmii_bus>; 369 370 tx_delay = <0x43>; 371 /* rx_delay = <0x3f>; */ 372 373 phy-handle = <&rgmii_phy>; 374 status = "okay"; 375}; 376 377&hdmi0 { 378 enable-gpios = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 379 status = "okay"; 380}; 381 382&hdmi0_in_vp0 { 383 status = "okay"; 384}; 385 386&hdmi0_sound { 387 status = "okay"; 388}; 389 390&hdmi1 { 391 enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 392 status = "okay"; 393}; 394 395&hdmi1_in_vp1 { 396 status = "okay"; 397}; 398 399&hdmi1_sound { 400 status = "okay"; 401}; 402 403/* Should work with at least 128MB cma reserved above. */ 404&hdmirx_ctrler { 405 status = "okay"; 406 407 #sound-dai-cells = <1>; 408 /* Effective level used to trigger HPD: 0-low, 1-high */ 409 hpd-trigger-level = <1>; 410 hdmirx-det-gpios = <&gpio1 RK_PD5 GPIO_ACTIVE_LOW>; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&hdmim1_rx &hdmirx_det>; 413}; 414 415&hdptxphy_hdmi0 { 416 status = "okay"; 417}; 418 419&hdptxphy_hdmi1 { 420 status = "okay"; 421}; 422 423&i2c0 { 424 status = "okay"; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&i2c0m2_xfer>; 427 428 vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: rk8602@42 { 429 compatible = "rockchip,rk8602"; 430 reg = <0x42>; 431 vin-supply = <&vcc5v0_sys>; 432 regulator-compatible = "rk860x-reg"; 433 regulator-name = "vdd_cpu_big0_s0"; 434 regulator-min-microvolt = <550000>; 435 regulator-max-microvolt = <1050000>; 436 regulator-ramp-delay = <2300>; 437 rockchip,suspend-voltage-selector = <1>; 438 regulator-boot-on; 439 regulator-always-on; 440 regulator-state-mem { 441 regulator-off-in-suspend; 442 }; 443 }; 444 445 vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: rk8603@43 { 446 compatible = "rockchip,rk8603"; 447 reg = <0x43>; 448 vin-supply = <&vcc5v0_sys>; 449 regulator-compatible = "rk860x-reg"; 450 regulator-name = "vdd_cpu_big1_s0"; 451 regulator-min-microvolt = <550000>; 452 regulator-max-microvolt = <1050000>; 453 regulator-ramp-delay = <2300>; 454 rockchip,suspend-voltage-selector = <1>; 455 regulator-boot-on; 456 regulator-always-on; 457 regulator-state-mem { 458 regulator-off-in-suspend; 459 }; 460 }; 461}; 462 463&i2c1 { 464 status = "okay"; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&i2c1m2_xfer>; 467 468 vdd_npu_s0: vdd_npu_mem_s0: rk8602@42 { 469 compatible = "rockchip,rk8602"; 470 reg = <0x42>; 471 vin-supply = <&vcc5v0_sys>; 472 regulator-compatible = "rk860x-reg"; 473 regulator-name = "vdd_npu_s0"; 474 regulator-min-microvolt = <550000>; 475 regulator-max-microvolt = <950000>; 476 regulator-ramp-delay = <2300>; 477 rockchip,suspend-voltage-selector = <1>; 478 regulator-boot-on; 479 regulator-always-on; 480 regulator-state-mem { 481 regulator-off-in-suspend; 482 }; 483 }; 484}; 485 486&i2c4 { 487 status = "okay"; 488 pinctrl-0 = <&i2c4m1_xfer>; 489 490 ls_stk3332: light@47 { 491 compatible = "ls_stk3332"; 492 status = "disabled"; 493 reg = <0x47>; 494 type = <SENSOR_TYPE_LIGHT>; 495 irq_enable = <0>; 496 als_threshold_high = <100>; 497 als_threshold_low = <10>; 498 als_ctrl_gain = <2>; /* 0:x1 1:x4 2:x16 3:x64 */ 499 poll_delay_ms = <100>; 500 }; 501 502 ps_stk3332: proximity@47 { 503 compatible = "ps_stk3332"; 504 status = "disabled"; 505 reg = <0x47>; 506 type = <SENSOR_TYPE_PROXIMITY>; 507 //pinctrl-names = "default"; 508 //pinctrl-0 = <&gpio3_c6>; 509 //irq-gpio = <&gpio3 RK_PC6 IRQ_TYPE_LEVEL_LOW>; 510 //irq_enable = <1>; 511 ps_threshold_high = <0x200>; 512 ps_threshold_low = <0x100>; 513 ps_ctrl_gain = <3>; /* 0:x1 1:x2 2:x5 3:x8 */ 514 ps_led_current = <4>; /* 0:3.125mA 1:6.25mA 2:12.5mA 3:25mA 4:50mA 5:100mA*/ 515 poll_delay_ms = <100>; 516 }; 517 518 icm42607_acc: icm_acc@68 { 519 status = "okay"; 520 compatible = "icm42607_acc"; 521 reg = <0x68>; 522 irq-gpio = <&gpio4 RK_PC2 IRQ_TYPE_EDGE_RISING>; 523 irq_enable = <0>; 524 poll_delay_ms = <30>; 525 type = <SENSOR_TYPE_ACCEL>; 526 layout = <0>; 527 }; 528 529 icm42607_gyro: icm_gyro@68 { 530 status = "okay"; 531 compatible = "icm42607_gyro"; 532 reg = <0x68>; 533 poll_delay_ms = <30>; 534 type = <SENSOR_TYPE_GYROSCOPE>; 535 layout = <0>; 536 }; 537}; 538 539&i2c5 { 540 status = "okay"; 541 gt1x: gt1x@14 { 542 compatible = "goodix,gt1x"; 543 reg = <0x14>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&touch_gpio>; 546 goodix,rst-gpio = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>; 547 goodix,irq-gpio = <&gpio3 RK_PC0 IRQ_TYPE_LEVEL_LOW>; 548 power-supply = <&vcc3v3_lcd_n>; 549 }; 550}; 551 552&i2c6 { 553 status = "okay"; 554 555 hym8563: hym8563@51 { 556 compatible = "haoyu,hym8563"; 557 reg = <0x51>; 558 #clock-cells = <0>; 559 clock-frequency = <32768>; 560 clock-output-names = "hym8563"; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&hym8563_int>; 563 interrupt-parent = <&gpio0>; 564 interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>; 565 wakeup-source; 566 }; 567}; 568 569&i2c7 { 570 status = "okay"; 571 es8388: es8388@11 { 572 status = "okay"; 573 #sound-dai-cells = <0>; 574 compatible = "everest,es8388", "everest,es8323"; 575 reg = <0x11>; 576 clocks = <&mclkout_i2s0>; 577 clock-names = "mclk"; 578 assigned-clocks = <&mclkout_i2s0>; 579 assigned-clock-rates = <12288000>; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&i2s0_mclk>; 582 }; 583}; 584 585&i2s2_2ch { 586 pinctrl-0 = <&i2s2m0_sclk &i2s2m0_lrck &i2s2m0_sdi &i2s2m0_sdo>; 587 status = "disabled"; 588}; 589 590&i2s5_8ch { 591 status = "okay"; 592}; 593 594&i2s6_8ch { 595 status = "okay"; 596}; 597 598&i2s7_8ch { 599 status = "okay"; 600}; 601 602&mdio1 { 603 rgmii_phy: phy@1 { 604 compatible = "ethernet-phy-ieee802.3-c22"; 605 reg = <0x1>; 606 }; 607}; 608 609&mipi_dcphy0 { 610 status = "okay"; 611}; 612 613&mipi_dcphy1 { 614 status = "disabled"; 615}; 616 617&pcie2x1l0 { 618 reset-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; 619 status = "okay"; 620}; 621 622&pcie30phy { 623 rockchip,pcie30-phymode = <PHY_MODE_PCIE_AGGREGATION>; 624 status = "okay"; 625}; 626 627&pcie3x4 { 628 reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_HIGH>; 629 vpcie3v3-supply = <&vcc3v3_pcie30>; 630 pinctrl-names = "default"; 631 pinctrl-0 = <&pcie30x4_clkreqn_m1>; 632 status = "okay"; 633}; 634 635&pinctrl { 636 cam { 637 mipicsi0_pwr: mipicsi0-pwr { 638 rockchip,pins = 639 /* camera power en */ 640 <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; 641 }; 642 mipicsi1_pwr: mipicsi1-pwr { 643 rockchip,pins = 644 /* camera power en */ 645 <1 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 646 }; 647 mipidcphy0_pwr: mipidcphy0-pwr { 648 rockchip,pins = 649 /* camera power en */ 650 <2 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 651 }; 652 }; 653 654 vga { 655 vga_hpdin_l: vga-hpdin-l { 656 rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 657 }; 658 }; 659 660 hdmi { 661 hdmirx_det: hdmirx-det { 662 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; 663 }; 664 }; 665 666 headphone { 667 hp_det: hp-det { 668 rockchip,pins = <1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 669 }; 670 }; 671 672 hym8563 { 673 hym8563_int: hym8563-int { 674 rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>; 675 }; 676 }; 677 678 lcd { 679 lcd_rst_gpio: lcd-rst-gpio { 680 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 681 }; 682 }; 683 684 pcie30x4 { 685 pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { 686 rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; 687 }; 688 }; 689 690 sdio-pwrseq { 691 wifi_enable_h: wifi-enable-h { 692 rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; 693 }; 694 }; 695 696 sdmmc { 697 sd_s0_pwr: sd-s0-pwr { 698 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>; 699 }; 700 }; 701 702 touch { 703 touch_gpio: touch-gpio { 704 rockchip,pins = 705 <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>, 706 <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>; 707 }; 708 }; 709 710 usb { 711 vcc5v0_host_en: vcc5v0-host-en { 712 rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>; 713 }; 714 }; 715 716 717 wireless-bluetooth { 718 uart9_gpios: uart9-gpios { 719 rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>; 720 }; 721 722 bt_reset_gpio: bt-reset-gpio { 723 rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 724 }; 725 726 bt_wake_gpio: bt-wake-gpio { 727 rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 728 }; 729 730 bt_irq_gpio: bt-irq-gpio { 731 rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; 732 }; 733 }; 734 735 wireless-wlan { 736 wifi_host_wake_irq: wifi-host-wake-irq { 737 rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 738 }; 739 }; 740}; 741 742&pwm1 { 743 status = "okay"; 744}; 745 746&pwm3 { 747 pinctrl-0 = <&pwm3m1_pins>; 748 status = "okay"; 749}; 750 751&route_dsi0 { 752 status = "okay"; 753 connect = <&vp3_out_dsi0>; 754}; 755 756&route_dsi1 { 757 status = "disabled"; 758 connect = <&vp3_out_dsi1>; 759}; 760 761&route_hdmi0 { 762 status = "okay"; 763}; 764 765&route_hdmi1 { 766 status = "okay"; 767}; 768 769&sata0 { 770 status = "okay"; 771}; 772 773&sdio { 774 max-frequency = <150000000>; 775 no-sd; 776 no-mmc; 777 bus-width = <4>; 778 disable-wp; 779 cap-sd-highspeed; 780 cap-sdio-irq; 781 keep-power-in-suspend; 782 mmc-pwrseq = <&sdio_pwrseq>; 783 non-removable; 784 pinctrl-names = "default"; 785 pinctrl-0 = <&sdiom0_pins>; 786 sd-uhs-sdr104; 787 status = "okay"; 788}; 789 790&sdmmc { 791 status = "okay"; 792 vmmc-supply = <&vcc_3v3_sd_s0>; 793}; 794 795&uart9 { 796 status = "okay"; 797 pinctrl-names = "default"; 798 pinctrl-0 = <&uart9m0_xfer &uart9m0_ctsn>; 799}; 800 801&u2phy0_otg { 802 status = "okay"; 803}; 804 805&u2phy1_otg { 806 phy-supply = <&vcc5v0_host>; 807}; 808 809&u2phy2_host { 810 phy-supply = <&vcc5v0_host>; 811}; 812 813&u2phy3_host { 814 phy-supply = <&vcc5v0_host>; 815}; 816 817&usbdp_phy0 { 818 rockchip,dp-lane-mux = <2 3>; 819 status = "okay"; 820}; 821 822&usbdp_phy0_dp { 823 status = "okay"; 824}; 825 826&usbdp_phy0_u3 { 827 status = "okay"; 828}; 829 830&usbdp_phy1 { 831 rockchip,dp-lane-mux = <3 2 1 0>; 832 status = "okay"; 833}; 834 835&usbdp_phy1_dp { 836 status = "okay"; 837}; 838 839&usbdp_phy1_u3 { 840 maximum-speed = "high-speed"; 841 status = "okay"; 842}; 843 844&usbdrd_dwc3_0 { 845 dr_mode = "otg"; 846 extcon = <&u2phy0>; 847 status = "okay"; 848}; 849 850&usbdrd_dwc3_1 { 851 dr_mode = "host"; 852 maximum-speed = "high-speed"; 853 status = "okay"; 854}; 855