1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include "rk3588.dtsi" 8#include "rk3588-evb.dtsi" 9#include "rk3588-rk806-dual.dtsi" 10 11/ { 12 dsm_sound: dsm-sound { 13 compatible = "simple-audio-card"; 14 simple-audio-card,format = "i2s"; 15 simple-audio-card,mclk-fs = <256>; 16 simple-audio-card,name = "rockchip,dsm-sound"; 17 simple-audio-card,bitclock-master = <&sndcodec>; 18 simple-audio-card,frame-master = <&sndcodec>; 19 sndcpu: simple-audio-card,cpu { 20 sound-dai = <&i2s3_2ch>; 21 }; 22 sndcodec: simple-audio-card,codec { 23 sound-dai = <&acdcdig_dsm>; 24 }; 25 }; 26 27 fan: pwm-fan { 28 compatible = "pwm-fan"; 29 #cooling-cells = <2>; 30 pwms = <&pwm9 0 50000 0>; 31 cooling-levels = <0 50 100 150 200 255>; 32 rockchip,temp-trips = < 33 50000 1 34 55000 2 35 60000 3 36 65000 4 37 70000 5 38 >; 39 }; 40 41 hdmiin_dc: hdmiin-dc { 42 compatible = "rockchip,dummy-codec"; 43 #sound-dai-cells = <0>; 44 }; 45 46 hdmiin-sound { 47 compatible = "simple-audio-card"; 48 simple-audio-card,format = "i2s"; 49 simple-audio-card,name = "rockchip,hdmiin"; 50 simple-audio-card,bitclock-master = <&dailink0_master>; 51 simple-audio-card,frame-master = <&dailink0_master>; 52 status = "okay"; 53 simple-audio-card,cpu { 54 sound-dai = <&i2s7_8ch>; 55 }; 56 dailink0_master: simple-audio-card,codec { 57 sound-dai = <&hdmiin_dc>; 58 }; 59 }; 60 61 pcie20_avdd0v85: pcie20-avdd0v85 { 62 compatible = "regulator-fixed"; 63 regulator-name = "pcie20_avdd0v85"; 64 regulator-boot-on; 65 regulator-always-on; 66 regulator-min-microvolt = <850000>; 67 regulator-max-microvolt = <850000>; 68 vin-supply = <&avdd_0v85_s0>; 69 }; 70 71 pcie20_avdd1v8: pcie20-avdd1v8 { 72 compatible = "regulator-fixed"; 73 regulator-name = "pcie20_avdd1v8"; 74 regulator-boot-on; 75 regulator-always-on; 76 regulator-min-microvolt = <1800000>; 77 regulator-max-microvolt = <1800000>; 78 vin-supply = <&avcc_1v8_s0>; 79 }; 80 81 pcie30_avdd0v75: pcie30-avdd0v75 { 82 compatible = "regulator-fixed"; 83 regulator-name = "pcie30_avdd0v75"; 84 regulator-boot-on; 85 regulator-always-on; 86 regulator-min-microvolt = <750000>; 87 regulator-max-microvolt = <750000>; 88 vin-supply = <&avdd_0v75_s0>; 89 }; 90 91 pcie30_avdd1v8: pcie30-avdd1v8 { 92 compatible = "regulator-fixed"; 93 regulator-name = "pcie30_avdd1v8"; 94 regulator-boot-on; 95 regulator-always-on; 96 regulator-min-microvolt = <1800000>; 97 regulator-max-microvolt = <1800000>; 98 vin-supply = <&avcc_1v8_s0>; 99 }; 100 101 vcc3v3_pcie30: vcc3v3-pcie30 { 102 compatible = "regulator-fixed"; 103 regulator-name = "vcc3v3_pcie30"; 104 regulator-min-microvolt = <3300000>; 105 regulator-max-microvolt = <3300000>; 106 enable-active-high; 107 gpios = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>; 108 startup-delay-us = <5000>; 109 vin-supply = <&vcc12v_dcin>; 110 }; 111}; 112 113&acdcdig_dsm { 114 status = "okay"; 115}; 116 117&combphy0_ps { 118 status = "okay"; 119}; 120 121&combphy1_ps { 122 status = "okay"; 123}; 124 125&combphy2_psu { 126 status = "okay"; 127}; 128 129/* 130 * mipi_dcphy0 needs to be enabled 131 * when dsi0 is enabled 132 */ 133&dsi0 { 134 status = "disabled"; 135}; 136 137&dsi0_in_vp2 { 138 status = "disabled"; 139}; 140 141&dsi0_in_vp3 { 142 status = "okay"; 143}; 144 145/* 146 * mipi_dcphy1 needs to be enabled 147 * when dsi1 is enabled 148 */ 149&dsi1 { 150 status = "disabled"; 151}; 152 153&dsi1_in_vp2 { 154 status = "disabled"; 155}; 156 157&dsi1_in_vp3 { 158 status = "disabled"; 159}; 160 161&hdmi1 { 162 enable-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 163 status = "okay"; 164}; 165 166&hdmi1_in_vp0 { 167 status = "okay"; 168}; 169 170&hdmi1_sound { 171 status = "okay"; 172}; 173 174&hdptxphy_hdmi1 { 175 status = "okay"; 176}; 177 178&i2s3_2ch { 179 status = "okay"; 180 /delete-property/ pinctrl-names; 181 /delete-property/ pinctrl-0; 182}; 183 184&i2s6_8ch { 185 status = "okay"; 186}; 187 188&i2s7_8ch { 189 status = "okay"; 190}; 191 192&mipi_dcphy0 { 193 status = "disabled"; 194}; 195 196&mipi_dcphy1 { 197 status = "disabled"; 198}; 199 200&pcie2x1l0 { 201 reset-gpios = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 202 vpcie3v3-supply = <&vcc3v3_pcie30>; 203 status = "okay"; 204}; 205 206&pcie2x1l1 { 207 reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; 208 vpcie3v3-supply = <&vcc3v3_pcie30>; 209 status = "okay"; 210}; 211 212&pcie2x1l2 { 213 reset-gpios = <&gpio4 RK_PC1 GPIO_ACTIVE_HIGH>; 214 vpcie3v3-supply = <&vcc3v3_pcie30>; 215 status = "okay"; 216}; 217 218&pcie30phy { 219 rockchip,pcie30-phymode = <PHY_MODE_PCIE_NANBNB>; 220 status = "okay"; 221}; 222 223&pcie3x2 { 224 reset-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>; 225 vpcie3v3-supply = <&vcc3v3_pcie30>; 226 status = "okay"; 227}; 228 229&pcie3x4 { 230 num-lanes = <2>; 231 reset-gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>; 232 vpcie3v3-supply = <&vcc3v3_pcie30>; 233 pinctrl-names = "default"; 234 pinctrl-0 = <&pcie30x4_clkreqn_m1>; 235 status = "okay"; 236}; 237 238&pinctrl { 239 pcie30x4 { 240 pcie30x4_clkreqn_m1: pcie30x4-clkreqn-m1 { 241 rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>; 242 }; 243 }; 244}; 245 246&pwm9 { 247 pinctrl-0 = <&pwm9m2_pins>; 248 status = "okay"; 249}; 250 251&route_dsi0 { 252 status = "okay"; 253 connect = <&vp3_out_dsi0>; 254}; 255 256&route_dsi1 { 257 status = "disabled"; 258 connect = <&vp3_out_dsi1>; 259}; 260 261&spdif_tx1 { 262 status = "okay"; 263 pinctrl-names = "default"; 264 pinctrl-0 = <&spdif1m0_tx>; 265}; 266 267&spdif_tx1_dc { 268 status = "okay"; 269}; 270 271&spdif_tx1_sound { 272 status = "okay"; 273}; 274 275&usbdp_phy0 { 276 status = "disabled"; 277}; 278 279&usbdp_phy0_dp { 280 status = "disabled"; 281}; 282 283&usbdp_phy0_u3 { 284 status = "disabled"; 285}; 286 287&usbdrd_dwc3_0 { 288 dr_mode = "peripheral"; 289 phys = <&u2phy0_otg>; 290 phy-names = "usb2-phy"; 291 maximum-speed = "high-speed"; 292}; 293 294&usbhost3_0 { 295 status = "disabled"; 296}; 297 298&usbhost_dwc3_0 { 299 status = "disabled"; 300}; 301