1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/ { 8 cam_ircut0: cam_ircut { 9 status = "okay"; 10 compatible = "rockchip,ircut"; 11 ircut-open-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 12 ircut-close-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>; 13 rockchip,camera-module-index = <0>; 14 rockchip,camera-module-facing = "back"; 15 }; 16 vcc_mipidphy0: vcc-mipidcphy0-regulator { 17 compatible = "regulator-fixed"; 18 gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 19 pinctrl-names = "default"; 20 pinctrl-0 = <&mipidphy0_pwr>; 21 regulator-name = "vcc_mipidphy0"; 22 enable-active-high; 23 }; 24}; 25 26&csi2_dphy0 { 27 status = "okay"; 28 29 ports { 30 #address-cells = <1>; 31 #size-cells = <0>; 32 port@0 { 33 reg = <0>; 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 mipidphy0_in_ucam0: endpoint@1 { 38 reg = <1>; 39 remote-endpoint = <&imx415_out0>; 40 data-lanes = <1 2 3 4>; 41 }; 42 }; 43 port@1 { 44 reg = <1>; 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 csidphy0_out: endpoint@0 { 49 reg = <0>; 50 remote-endpoint = <&mipi2_csi2_input>; 51 }; 52 }; 53 }; 54}; 55 56&csi2_dphy0_hw { 57 status = "okay"; 58}; 59 60&i2c3 { 61 status = "okay"; 62 63 imx415: imx415@1a { 64 compatible = "sony,imx415"; 65 reg = <0x1a>; 66 clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; 67 clock-names = "xvclk"; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&mipim0_camera3_clk>; 70 power-domains = <&power RK3588_PD_VI>; 71 pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; 72 avdd-supply = <&vcc_mipidphy0>; 73 rockchip,camera-module-index = <0>; 74 rockchip,camera-module-facing = "back"; 75 rockchip,camera-module-name = "CMK-OT2022-PX1"; 76 rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20"; 77 lens-focus = <&cam_ircut0>; 78 port { 79 imx415_out0: endpoint { 80 remote-endpoint = <&mipidphy0_in_ucam0>; 81 data-lanes = <1 2 3 4>; 82 }; 83 }; 84 }; 85}; 86 87&mipi2_csi2 { 88 status = "okay"; 89 90 ports { 91 #address-cells = <1>; 92 #size-cells = <0>; 93 94 port@0 { 95 reg = <0>; 96 #address-cells = <1>; 97 #size-cells = <0>; 98 99 mipi2_csi2_input: endpoint@1 { 100 reg = <1>; 101 remote-endpoint = <&csidphy0_out>; 102 }; 103 }; 104 105 port@1 { 106 reg = <1>; 107 #address-cells = <1>; 108 #size-cells = <0>; 109 110 mipi2_csi2_output: endpoint@0 { 111 reg = <0>; 112 remote-endpoint = <&cif_mipi2_in0>; 113 }; 114 }; 115 }; 116}; 117 118&pinctrl { 119 cam { 120 mipidphy0_pwr: mipidphy0-pwr { 121 rockchip,pins = 122 /* camera power en */ 123 <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 124 }; 125 }; 126}; 127 128&rkcif { 129 status = "okay"; 130}; 131 132&rkcif_mipi_lvds2 { 133 status = "okay"; 134 135 port { 136 cif_mipi2_in0: endpoint { 137 remote-endpoint = <&mipi2_csi2_output>; 138 }; 139 }; 140}; 141 142&rkcif_mipi_lvds2_sditf { 143 status = "okay"; 144 145 port { 146 mipi_lvds2_sditf: endpoint { 147 remote-endpoint = <&isp0_vir0>; 148 }; 149 }; 150}; 151 152&rkcif_mmu { 153 status = "okay"; 154}; 155 156&rkisp0 { 157 status = "okay"; 158}; 159 160&isp0_mmu { 161 status = "okay"; 162}; 163 164&rkisp0_vir0 { 165 status = "okay"; 166 167 port { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 isp0_vir0: endpoint@0 { 172 reg = <0>; 173 remote-endpoint = <&mipi_lvds2_sditf>; 174 }; 175 }; 176}; 177