1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4 *
5 */
6/dts-v1/;
7
8#include "rk3588-evb1-lp4.dtsi"
9#include "rk3588-android.dtsi"
10
11/ {
12	model = "Rockchip RK3588 EVB1 LP4 V10 Board + Rockchip RK3588 EVB V10 Extboard";
13	compatible = "rockchip,rk3588-evb1-lp4-v10-lt6911uxe", "rockchip,rk3588";
14
15	vcc_mipicsi0: vcc-mipicsi0-regulator {
16		compatible = "regulator-fixed";
17		gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
18		pinctrl-names = "default";
19		pinctrl-0 = <&mipicsi0_pwr>;
20		regulator-name = "vcc_mipicsi0";
21		enable-active-high;
22		regulator-boot-on;
23		regulator-always-on;
24	};
25
26	vcc_mipidcphy0: vcc-mipidcphy0-regulator {
27		compatible = "regulator-fixed";
28		gpio = <&gpio2 RK_PC4 GPIO_ACTIVE_HIGH>;
29		pinctrl-names = "default";
30		pinctrl-0 = <&mipidcphy0_pwr>;
31		regulator-name = "vcc_mipidcphy0";
32		enable-active-high;
33		regulator-boot-on;
34		regulator-always-on;
35	};
36
37	ext_cam_clk: external-camera-clock {
38		compatible = "fixed-clock";
39		clock-frequency = <24000000>;
40		clock-output-names = "CLK_CAMERA_24MHZ";
41		#clock-cells = <0>;
42	};
43};
44
45&csi2_dphy0 {
46	status = "okay";
47
48	ports {
49		#address-cells = <1>;
50		#size-cells = <0>;
51		port@0 {
52			reg = <0>;
53			#address-cells = <1>;
54			#size-cells = <0>;
55
56			hdmi_mipi2_in: endpoint@1 {
57				reg = <1>;
58				remote-endpoint = <&lt6911uxe_out1>;
59				data-lanes = <1 2 3 4>;
60			};
61		};
62		port@1 {
63			reg = <1>;
64			#address-cells = <1>;
65			#size-cells = <0>;
66
67			csidphy0_out: endpoint@0 {
68				reg = <0>;
69				remote-endpoint = <&mipi2_csi2_input>;
70			};
71		};
72	};
73};
74
75&csi2_dphy0_hw {
76	status = "okay";
77};
78
79&csi2_dcphy0 {
80	status = "okay";
81
82	ports {
83		#address-cells = <1>;
84		#size-cells = <0>;
85		port@0 {
86			reg = <0>;
87			#address-cells = <1>;
88			#size-cells = <0>;
89
90			hdmi_mipi0_in: endpoint@1 {
91				reg = <1>;
92				remote-endpoint = <&lt6911uxe_out0>;
93				data-lanes = <1 2 3 4>;
94			};
95		};
96		port@1 {
97			reg = <1>;
98			#address-cells = <1>;
99			#size-cells = <0>;
100
101			csidcphy0_out: endpoint@0 {
102				reg = <0>;
103				remote-endpoint = <&mipi0_csi2_input>;
104			};
105		};
106	};
107};
108
109&i2c3 {
110	status = "okay";
111
112	lt6911uxe_1: lt6911uxe_1@2b {
113		compatible = "lontium,lt6911uxe";
114		status = "okay";
115		reg = <0x2b>;
116		clocks = <&ext_cam_clk>;
117		clock-names = "xvclk";
118		power-domains = <&power RK3588_PD_VI>;
119		pinctrl-names = "default";
120		pinctrl-0 = <&lt6911uxe_pin_1>;
121		interrupt-parent = <&gpio1>;
122		interrupts = <RK_PB3 IRQ_TYPE_LEVEL_LOW>;
123		// reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
124		// power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
125		plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
126		rockchip,camera-module-index = <0>;
127		rockchip,camera-module-facing = "back";
128		rockchip,camera-module-name = "HDMI-MIPI2";
129		rockchip,camera-module-lens-name = "LT6911UXE-2";
130		port {
131			lt6911uxe_out1: endpoint {
132				remote-endpoint = <&hdmi_mipi2_in>;
133				data-lanes = <1 2 3 4>;
134			};
135		};
136	};
137};
138
139&i2c5 {
140	status = "okay";
141
142	lt6911uxe: lt6911uxe@2b {
143		compatible = "lontium,lt6911uxe";
144		status = "okay";
145		reg = <0x2b>;
146		clocks = <&ext_cam_clk>;
147		clock-names = "xvclk";
148		power-domains = <&power RK3588_PD_VI>;
149		pinctrl-names = "default";
150		pinctrl-0 = <&lt6911uxe_pin>;
151		interrupt-parent = <&gpio1>;
152		interrupts = <RK_PA0 IRQ_TYPE_LEVEL_LOW>;
153		// reset-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_LOW>;
154		// power-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
155		// plugin-det-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
156		plugin-det-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>;
157		rockchip,camera-module-index = <1>;
158		rockchip,camera-module-facing = "front";
159		rockchip,camera-module-name = "HDMI-MIPI0";
160		rockchip,camera-module-lens-name = "LT6911UXC-0";
161
162		port {
163			lt6911uxe_out0: endpoint {
164				remote-endpoint = <&hdmi_mipi0_in>;
165				data-lanes = <1 2 3 4>;
166			};
167		};
168	};
169};
170
171&mipi_dcphy0 {
172	status = "okay";
173};
174
175&mipi0_csi2 {
176	status = "okay";
177
178	ports {
179		#address-cells = <1>;
180		#size-cells = <0>;
181
182		port@0 {
183			reg = <0>;
184			#address-cells = <1>;
185			#size-cells = <0>;
186
187			mipi0_csi2_input: endpoint@1 {
188				reg = <1>;
189				remote-endpoint = <&csidcphy0_out>;
190			};
191		};
192
193		port@1 {
194			reg = <1>;
195			#address-cells = <1>;
196			#size-cells = <0>;
197
198			mipi0_csi2_output: endpoint@0 {
199				reg = <0>;
200				remote-endpoint = <&cif_mipi_in0>;
201			};
202		};
203	};
204};
205
206&mipi2_csi2 {
207	status = "okay";
208
209	ports {
210		#address-cells = <1>;
211		#size-cells = <0>;
212
213		port@0 {
214			reg = <0>;
215			#address-cells = <1>;
216			#size-cells = <0>;
217
218			mipi2_csi2_input: endpoint@1 {
219				reg = <1>;
220				remote-endpoint = <&csidphy0_out>;
221			};
222		};
223
224		port@1 {
225			reg = <1>;
226			#address-cells = <1>;
227			#size-cells = <0>;
228
229			mipi2_csi2_output: endpoint@0 {
230				reg = <0>;
231				remote-endpoint = <&cif_mipi_in2>;
232			};
233		};
234	};
235};
236
237&rkcif {
238	status = "okay";
239};
240
241&rkcif_mipi_lvds {
242	status = "okay";
243
244	port {
245		cif_mipi_in0: endpoint {
246			remote-endpoint = <&mipi0_csi2_output>;
247		};
248	};
249};
250
251&rkcif_mipi_lvds2 {
252	status = "okay";
253
254	port {
255		cif_mipi_in2: endpoint {
256			remote-endpoint = <&mipi2_csi2_output>;
257		};
258	};
259};
260
261&rkcif_mmu {
262	status = "okay";
263};
264
265&pinctrl {
266	hdmiin {
267		lt6911uxe_pin: lt6911uxe-pin {
268			rockchip,pins = <1 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>,
269					<1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
270		};
271
272		lt6911uxe_pin_1: lt6911uxe-pin-1 {
273			rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>,
274					<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
275		};
276	};
277};
278