1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8 9#include "rk3588-evb1-lp4.dtsi" 10#include "rk3588-evb1-imx415.dtsi" 11#include "rk3588-android.dtsi" 12 13/ { 14 model = "Rockchip RK3588 EVB1 LP4 V10 Board + DSI DSC PANEL MV2100UZ1 DISPLAY Ext Board"; 15 compatible = "rockchip,rk3588-evb1-lp4-v10-dsi-dsc-MV2100UZ1", "rockchip,rk3588"; 16}; 17 18&backlight { 19 status = "okay"; 20 default-brightness-level = <20>; 21}; 22 23&dsi0 { 24 status = "okay"; 25 rockchip,lane-rate = <1200000>; 26 27 dsi0_panel: panel@0 { 28 status = "okay"; 29 compatible = "simple-panel-dsi"; 30 reg = <0>; 31 backlight = <&backlight>; 32 reset-delay-ms = <50>; 33 enable-delay-ms = <50>; 34 init-delay-ms = <20>; 35 prepare-delay-ms = <50>; 36 unprepare-delay-ms = <20>; 37 disable-delay-ms = <20>; 38 dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST)>; 39 40 dsi,format = <MIPI_DSI_FMT_RGB888>; 41 dsi,lanes = <4>; 42 43 compressed-data; 44 slice-width = <1140>; 45 slice-height = <2280>; 46 version-major = <1>; 47 version-minor = <1>; 48 49 panel-init-sequence = [ 50 /* PPS Setting */ 51 0A 00 58 11 00 00 89 30 80 08 E8 08 E8 08 E8 04 74 04 74 02 00 03 C9 00 20 F7 C5 00 0F 00 0F 00 0E 00 06 18 00 10 F0 03 0C 20 00 06 0B 0B 33 0E 1C 2A 38 46 54 62 69 70 77 79 7B 7D 7E 01 02 01 00 09 40 09 BE 19 FC 19 FA 19 F8 1A 38 1A 78 1A B6 2A F6 2B 34 2B 74 3B 74 6B F4 52 39 00 02 FF 20 53 39 00 02 E0 10 54 39 00 02 7A 07 55 39 00 02 7D 0C 56 39 00 02 7E 0C 57 39 00 02 FB 01 58 59 39 00 02 FF E0 60 39 00 02 66 00 61 39 00 02 23 07 62 39 00 02 FB 01 63 64 /* CMD2 page 5 */ 65 39 00 02 FF 25 66 67 /* OSC TRACE for MIPI H 4.748us */ 68 39 00 02 2F 20 69 39 00 02 0D 07 70 39 00 02 0E 6B 71 39 00 02 11 11 72 39 00 02 13 00 73 39 00 02 14 01 74 39 00 02 25 20 75 39 00 02 0F 09 76 39 00 02 10 A5 77 39 00 02 12 17 78 39 00 02 15 01 79 39 00 02 0C 01 80 39 00 02 09 10 81 39 00 02 38 03 82 39 00 02 0A 00 83 39 00 02 07 02 84 85 /* MIPI VFP */ 86 39 00 02 BC FF 87 39 00 02 BD FF 88 39 00 02 BE FF 89 39 00 02 BF FF 90 39 00 02 C0 FF 91 39 00 02 C1 FF 92 39 00 02 C2 FF 93 39 00 02 C3 FF 94 95 39 00 02 FB 01 96 97 39 00 02 FF 10 98 39 00 05 2A 00 00 08 E7 99 39 00 05 2B 00 00 08 E7 100 39 00 02 03 01 101 39 00 02 BB 13 102 39 00 02 C0 03 103 39 00 11 C1 89 28 08 E8 F2 00 03 C9 F7 C5 00 0F 00 0E 00 06 104 39 00 03 C2 10 F0 105 39 00 02 35 00 106 39 00 03 44 00 00 107 39 00 02 51 FF 108 39 00 02 53 24 109 39 00 02 FB 01 110 111 15 64 01 11 112 15 14 01 29 113 ]; 114 115 panel-exit-sequence = [ 116 05 00 01 28 117 05 00 01 10 118 ]; 119 120 disp_timings0: display-timings { 121 native-mode = <&dsi0_timing0>; 122 dsi0_timing0: timing0 { 123 clock-frequency = <506000000>; 124 hactive = <2280>; 125 vactive = <2280>; 126 hfront-porch = <52>; 127 hsync-len = <20>; 128 hback-porch = <52>; 129 vfront-porch = <44>; 130 vsync-len = <2>; 131 vback-porch = <14>; 132 hsync-active = <0>; 133 vsync-active = <0>; 134 de-active = <0>; 135 pixelclk-active = <0>; 136 }; 137 }; 138 139 ports { 140 #address-cells = <1>; 141 #size-cells = <0>; 142 143 port@0 { 144 reg = <0>; 145 panel_in_dsi: endpoint { 146 remote-endpoint = <&dsi_out_panel>; 147 }; 148 }; 149 }; 150 }; 151 152 ports { 153 #address-cells = <1>; 154 #size-cells = <0>; 155 156 port@1 { 157 reg = <1>; 158 dsi_out_panel: endpoint { 159 remote-endpoint = <&panel_in_dsi>; 160 }; 161 }; 162 }; 163}; 164 165&dp0 { 166 status = "disabled"; 167}; 168 169&dp1 { 170 status = "disabled"; 171}; 172 173&dp0_in_vp2 { 174 status = "disabled"; 175}; 176 177&dp1_in_vp2 { 178 status = "disabled"; 179}; 180 181&dsi0_in_vp2 { 182 status = "okay"; 183}; 184 185&dsi0_in_vp3 { 186 status = "disabled"; 187}; 188 189&dsi1_in_vp2 { 190 status = "disabled"; 191}; 192 193&mipi_dcphy0 { 194 status = "okay"; 195}; 196 197&route_dsi0 { 198 status = "okay"; 199 connect = <&vp2_out_dsi0>; 200}; 201