1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7&csi2_dcphy0 { 8 status = "okay"; 9 10 ports { 11 #address-cells = <1>; 12 #size-cells = <0>; 13 port@0 { 14 reg = <0>; 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 mipi_in_ucam0: endpoint@1 { 19 reg = <1>; 20 remote-endpoint = <&imx464_out0>; 21 data-lanes = <1 2>; 22 }; 23 }; 24 port@1 { 25 reg = <1>; 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 csidcphy0_out: endpoint@0 { 30 reg = <0>; 31 remote-endpoint = <&mipi0_csi2_input>; 32 }; 33 }; 34 }; 35}; 36 37&csi2_dcphy1 { 38 status = "okay"; 39 40 ports { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 port@0 { 44 reg = <0>; 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 mipi_in_ucam1: endpoint@1 { 49 reg = <1>; 50 remote-endpoint = <&imx464_out1>; 51 data-lanes = <1 2>; 52 }; 53 }; 54 port@1 { 55 reg = <1>; 56 #address-cells = <1>; 57 #size-cells = <0>; 58 59 csidcphy1_out: endpoint@0 { 60 reg = <0>; 61 remote-endpoint = <&mipi1_csi2_input>; 62 }; 63 }; 64 }; 65}; 66 67&csi2_dphy0_hw { 68 status = "okay"; 69}; 70 71&csi2_dphy1_hw { 72 status = "okay"; 73}; 74 75&csi2_dphy1 { 76 status = "okay"; 77 78 ports { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 port@0 { 82 reg = <0>; 83 #address-cells = <1>; 84 #size-cells = <0>; 85 86 mipi_in_ucam2: endpoint@1 { 87 reg = <1>; 88 remote-endpoint = <&imx464_out2>; 89 data-lanes = <1 2>; 90 }; 91 }; 92 port@1 { 93 reg = <1>; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 csidphy1_out: endpoint@0 { 98 reg = <0>; 99 remote-endpoint = <&mipi2_csi2_input>; 100 }; 101 }; 102 }; 103}; 104 105&csi2_dphy2 { 106 status = "okay"; 107 108 ports { 109 #address-cells = <1>; 110 #size-cells = <0>; 111 port@0 { 112 reg = <0>; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 116 mipi_in_ucam3: endpoint@1 { 117 reg = <1>; 118 remote-endpoint = <&imx464_out3>; 119 data-lanes = <1 2>; 120 }; 121 }; 122 port@1 { 123 reg = <1>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 csidphy2_out: endpoint@0 { 128 reg = <0>; 129 remote-endpoint = <&mipi3_csi2_input>; 130 }; 131 }; 132 }; 133}; 134 135&csi2_dphy4 { 136 status = "okay"; 137 138 ports { 139 #address-cells = <1>; 140 #size-cells = <0>; 141 port@0 { 142 reg = <0>; 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 mipi_in_ucam4: endpoint@1 { 147 reg = <1>; 148 remote-endpoint = <&imx464_out4>; 149 data-lanes = <1 2>; 150 }; 151 }; 152 port@1 { 153 reg = <1>; 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 csidphy4_out: endpoint@0 { 158 reg = <0>; 159 remote-endpoint = <&mipi4_csi2_input>; 160 }; 161 }; 162 }; 163}; 164 165&csi2_dphy5 { 166 status = "okay"; 167 168 ports { 169 #address-cells = <1>; 170 #size-cells = <0>; 171 port@0 { 172 reg = <0>; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 176 mipi_in_ucam5: endpoint@1 { 177 reg = <1>; 178 remote-endpoint = <&imx464_out5>; 179 data-lanes = <1 2>; 180 }; 181 }; 182 port@1 { 183 reg = <1>; 184 #address-cells = <1>; 185 #size-cells = <0>; 186 187 csidphy5_out: endpoint@0 { 188 reg = <0>; 189 remote-endpoint = <&mipi5_csi2_input>; 190 }; 191 }; 192 }; 193}; 194 195&i2c3 { 196 status = "okay"; 197 198 /* module 77/79 0x1a 78/80 0x36 */ 199 imx464_2: imx464-2@1a { 200 compatible = "sony,imx464"; 201 status = "okay"; 202 reg = <0x1a>; 203 clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; 204 clock-names = "xvclk"; 205 power-domains = <&power RK3588_PD_VI>; 206 pinctrl-names = "default"; 207 pinctrl-0 = <&mipim0_camera3_clk>; 208 avdd-supply = <&vcc_mipicsi0>; 209 pwdn-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>; 210 rockchip,camera-module-index = <2>; 211 rockchip,camera-module-facing = "back"; 212 rockchip,camera-module-name = "CMK-OT1980-PX1"; 213 rockchip,camera-module-lens-name = "SHG102"; 214 port { 215 imx464_out2: endpoint { 216 remote-endpoint = <&mipi_in_ucam2>; 217 data-lanes = <1 2>; 218 }; 219 }; 220 }; 221 222 imx464_3: imx464-3@36 { 223 compatible = "sony,imx464"; 224 status = "okay"; 225 reg = <0x36>; 226 clocks = <&cru CLK_MIPI_CAMARAOUT_M3>; 227 clock-names = "xvclk"; 228 power-domains = <&power RK3588_PD_VI>; 229 avdd-supply = <&vcc_mipicsi0>; 230 pwdn-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>; 231 rockchip,camera-module-index = <3>; 232 rockchip,camera-module-facing = "back"; 233 rockchip,camera-module-name = "CMK-OT1980-PX1"; 234 rockchip,camera-module-lens-name = "SHG102"; 235 port { 236 imx464_out3: endpoint { 237 remote-endpoint = <&mipi_in_ucam3>; 238 data-lanes = <1 2>; 239 }; 240 }; 241 }; 242}; 243 244&i2c4 { 245 status = "okay"; 246 pinctrl-0 = <&i2c4m3_xfer>; 247 248 /* 77/79 0x1a 78/80 0x36 */ 249 imx464_4: imx464-4@1a { 250 compatible = "sony,imx464"; 251 status = "okay"; 252 reg = <0x1a>; 253 clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; 254 clock-names = "xvclk"; 255 power-domains = <&power RK3588_PD_VI>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&mipim0_camera4_clk>; 258 avdd-supply = <&vcc_mipicsi1>; 259 pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; 260 rockchip,camera-module-index = <0>; 261 rockchip,camera-module-facing = "back"; 262 rockchip,camera-module-name = "CMK-OT1980-PX1"; 263 rockchip,camera-module-lens-name = "SHG102"; 264 port { 265 imx464_out4: endpoint { 266 remote-endpoint = <&mipi_in_ucam4>; 267 data-lanes = <1 2>; 268 }; 269 }; 270 }; 271 272 imx464_5: imx464-5@36 { 273 compatible = "sony,imx464"; 274 status = "okay"; 275 reg = <0x36>; 276 clocks = <&cru CLK_MIPI_CAMARAOUT_M4>; 277 clock-names = "xvclk"; 278 power-domains = <&power RK3588_PD_VI>; 279 avdd-supply = <&vcc_mipicsi1>; 280 pwdn-gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>; 281 rockchip,camera-module-index = <1>; 282 rockchip,camera-module-facing = "back"; 283 rockchip,camera-module-name = "CMK-OT1980-PX1"; 284 rockchip,camera-module-lens-name = "SHG102"; 285 port { 286 imx464_out5: endpoint { 287 remote-endpoint = <&mipi_in_ucam5>; 288 data-lanes = <1 2>; 289 }; 290 }; 291 }; 292}; 293 294&i2c5 { 295 status = "okay"; 296 297 /* 77/79 0x1a 78/80 0x36 */ 298 imx464_0: imx464-0@1a { 299 compatible = "sony,imx464"; 300 status = "okay"; 301 reg = <0x1a>; 302 clocks = <&cru CLK_MIPI_CAMARAOUT_M1>; 303 clock-names = "xvclk"; 304 power-domains = <&power RK3588_PD_VI>; 305 pwdn-gpios = <&gpio1 RK_PA0 GPIO_ACTIVE_HIGH>; 306 pinctrl-names = "default"; 307 pinctrl-0 = <&mipim0_camera1_clk>; 308 avdd-supply = <&vcc_mipidcphy0>; 309 rockchip,camera-module-index = <4>; 310 rockchip,camera-module-facing = "back"; 311 rockchip,camera-module-name = "CMK-OT1980-PX1"; 312 rockchip,camera-module-lens-name = "SHG102"; 313 port { 314 imx464_out0: endpoint { 315 remote-endpoint = <&mipi_in_ucam0>; 316 data-lanes = <1 2>; 317 }; 318 }; 319 }; 320 321 imx464_1: imx464-1@36 { 322 compatible = "sony,imx464"; 323 status = "okay"; 324 reg = <0x36>; 325 clocks = <&cru CLK_MIPI_CAMARAOUT_M2>; 326 clock-names = "xvclk"; 327 power-domains = <&power RK3588_PD_VI>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&mipim0_camera2_clk>; 330 pwdn-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; 331 avdd-supply = <&vcc_mipidcphy0>; 332 rockchip,camera-module-index = <5>; 333 rockchip,camera-module-facing = "back"; 334 rockchip,camera-module-name = "CMK-OT1980-PX1"; 335 rockchip,camera-module-lens-name = "SHG102"; 336 port { 337 imx464_out1: endpoint { 338 remote-endpoint = <&mipi_in_ucam1>; 339 data-lanes = <1 2>; 340 }; 341 }; 342 }; 343}; 344 345&mipi_dcphy0 { 346 status = "okay"; 347}; 348 349&mipi_dcphy1 { 350 status = "okay"; 351}; 352 353&mipi0_csi2 { 354 status = "okay"; 355 356 ports { 357 #address-cells = <1>; 358 #size-cells = <0>; 359 360 port@0 { 361 reg = <0>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 365 mipi0_csi2_input: endpoint@1 { 366 reg = <1>; 367 remote-endpoint = <&csidcphy0_out>; 368 }; 369 }; 370 371 port@1 { 372 reg = <1>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 376 mipi0_csi2_output: endpoint@0 { 377 reg = <0>; 378 remote-endpoint = <&cif_mipi_in0>; 379 }; 380 }; 381 }; 382}; 383 384&mipi1_csi2 { 385 status = "okay"; 386 387 ports { 388 #address-cells = <1>; 389 #size-cells = <0>; 390 391 port@0 { 392 reg = <0>; 393 #address-cells = <1>; 394 #size-cells = <0>; 395 396 mipi1_csi2_input: endpoint@1 { 397 reg = <1>; 398 remote-endpoint = <&csidcphy1_out>; 399 }; 400 }; 401 402 port@1 { 403 reg = <1>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 407 mipi1_csi2_output: endpoint@0 { 408 reg = <0>; 409 remote-endpoint = <&cif_mipi_in1>; 410 }; 411 }; 412 }; 413}; 414 415&mipi2_csi2 { 416 status = "okay"; 417 418 ports { 419 #address-cells = <1>; 420 #size-cells = <0>; 421 422 port@0 { 423 reg = <0>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 427 mipi2_csi2_input: endpoint@1 { 428 reg = <1>; 429 remote-endpoint = <&csidphy1_out>; 430 }; 431 }; 432 433 port@1 { 434 reg = <1>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 438 mipi2_csi2_output: endpoint@0 { 439 reg = <0>; 440 remote-endpoint = <&cif_mipi_in2>; 441 }; 442 }; 443 }; 444}; 445 446&mipi3_csi2 { 447 status = "okay"; 448 449 ports { 450 #address-cells = <1>; 451 #size-cells = <0>; 452 453 port@0 { 454 reg = <0>; 455 #address-cells = <1>; 456 #size-cells = <0>; 457 458 mipi3_csi2_input: endpoint@1 { 459 reg = <1>; 460 remote-endpoint = <&csidphy2_out>; 461 }; 462 }; 463 464 port@1 { 465 reg = <1>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 469 mipi3_csi2_output: endpoint@0 { 470 reg = <0>; 471 remote-endpoint = <&cif_mipi_in3>; 472 }; 473 }; 474 }; 475}; 476 477&mipi4_csi2 { 478 status = "okay"; 479 480 ports { 481 #address-cells = <1>; 482 #size-cells = <0>; 483 484 port@0 { 485 reg = <0>; 486 #address-cells = <1>; 487 #size-cells = <0>; 488 489 mipi4_csi2_input: endpoint@1 { 490 reg = <1>; 491 remote-endpoint = <&csidphy4_out>; 492 }; 493 }; 494 495 port@1 { 496 reg = <1>; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 500 mipi4_csi2_output: endpoint@0 { 501 reg = <0>; 502 remote-endpoint = <&cif_mipi_in4>; 503 }; 504 }; 505 }; 506}; 507 508&mipi5_csi2 { 509 status = "okay"; 510 511 ports { 512 #address-cells = <1>; 513 #size-cells = <0>; 514 515 port@0 { 516 reg = <0>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 520 mipi5_csi2_input: endpoint@1 { 521 reg = <1>; 522 remote-endpoint = <&csidphy5_out>; 523 }; 524 }; 525 526 port@1 { 527 reg = <1>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 531 mipi5_csi2_output: endpoint@0 { 532 reg = <0>; 533 remote-endpoint = <&cif_mipi_in5>; 534 }; 535 }; 536 }; 537}; 538 539&rkcif { 540 status = "okay"; 541}; 542 543&rkcif_mipi_lvds { 544 status = "okay"; 545 546 port { 547 cif_mipi_in0: endpoint { 548 remote-endpoint = <&mipi0_csi2_output>; 549 }; 550 }; 551}; 552 553&rkcif_mipi_lvds_sditf { 554 status = "okay"; 555 556 port { 557 mipi_lvds_sditf: endpoint { 558 remote-endpoint = <&isp0_vir0>; 559 }; 560 }; 561}; 562 563&rkcif_mipi_lvds1 { 564 status = "okay"; 565 566 port { 567 cif_mipi_in1: endpoint { 568 remote-endpoint = <&mipi1_csi2_output>; 569 }; 570 }; 571}; 572 573&rkcif_mipi_lvds1_sditf { 574 status = "okay"; 575 576 port { 577 mipi1_lvds_sditf: endpoint { 578 remote-endpoint = <&isp1_vir0>; 579 }; 580 }; 581}; 582 583&rkcif_mipi_lvds2 { 584 status = "okay"; 585 586 port { 587 cif_mipi_in2: endpoint { 588 remote-endpoint = <&mipi2_csi2_output>; 589 }; 590 }; 591}; 592 593&rkcif_mipi_lvds2_sditf { 594 status = "okay"; 595 596 port { 597 mipi2_lvds_sditf: endpoint { 598 remote-endpoint = <&isp0_vir1>; 599 }; 600 }; 601}; 602 603&rkcif_mipi_lvds3 { 604 status = "okay"; 605 606 port { 607 cif_mipi_in3: endpoint { 608 remote-endpoint = <&mipi3_csi2_output>; 609 }; 610 }; 611}; 612 613&rkcif_mipi_lvds3_sditf { 614 status = "okay"; 615 616 port { 617 mipi3_lvds_sditf: endpoint { 618 remote-endpoint = <&isp1_vir1>; 619 }; 620 }; 621}; 622 623&rkcif_mipi_lvds4 { 624 status = "okay"; 625 626 port { 627 cif_mipi_in4: endpoint { 628 remote-endpoint = <&mipi4_csi2_output>; 629 }; 630 }; 631}; 632 633&rkcif_mipi_lvds4_sditf { 634 status = "okay"; 635 636 port { 637 mipi4_lvds_sditf: endpoint { 638 remote-endpoint = <&isp0_vir2>; 639 }; 640 }; 641}; 642 643&rkcif_mipi_lvds5 { 644 status = "okay"; 645 646 port { 647 cif_mipi_in5: endpoint { 648 remote-endpoint = <&mipi5_csi2_output>; 649 }; 650 }; 651}; 652 653&rkcif_mipi_lvds5_sditf { 654 status = "okay"; 655 656 port { 657 mipi5_lvds_sditf: endpoint { 658 remote-endpoint = <&isp1_vir2>; 659 }; 660 }; 661}; 662 663&rkcif_mmu { 664 status = "okay"; 665}; 666 667&rkisp0 { 668 status = "okay"; 669}; 670 671&isp0_mmu { 672 status = "okay"; 673}; 674 675&rkisp0_vir0 { 676 status = "okay"; 677 678 port { 679 #address-cells = <1>; 680 #size-cells = <0>; 681 682 isp0_vir0: endpoint@0 { 683 reg = <0>; 684 remote-endpoint = <&mipi_lvds_sditf>; 685 }; 686 }; 687}; 688 689&rkisp0_vir1 { 690 status = "okay"; 691 692 port { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 696 isp0_vir1: endpoint@0 { 697 reg = <0>; 698 remote-endpoint = <&mipi2_lvds_sditf>; 699 }; 700 }; 701}; 702 703&rkisp0_vir2 { 704 status = "okay"; 705 706 port { 707 #address-cells = <1>; 708 #size-cells = <0>; 709 710 isp0_vir2: endpoint@0 { 711 reg = <0>; 712 remote-endpoint = <&mipi4_lvds_sditf>; 713 }; 714 }; 715}; 716 717&rkisp1 { 718 status = "okay"; 719}; 720 721&isp1_mmu { 722 status = "okay"; 723}; 724 725&rkisp1_vir0 { 726 status = "okay"; 727 728 port { 729 #address-cells = <1>; 730 #size-cells = <0>; 731 732 isp1_vir0: endpoint@0 { 733 reg = <0>; 734 remote-endpoint = <&mipi1_lvds_sditf>; 735 }; 736 }; 737}; 738 739&rkisp1_vir1 { 740 status = "okay"; 741 742 port { 743 #address-cells = <1>; 744 #size-cells = <0>; 745 746 isp1_vir1: endpoint@0 { 747 reg = <0>; 748 remote-endpoint = <&mipi3_lvds_sditf>; 749 }; 750 }; 751}; 752 753 754&rkisp1_vir2 { 755 status = "okay"; 756 757 port { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 761 isp1_vir2: endpoint@0 { 762 reg = <0>; 763 remote-endpoint = <&mipi5_lvds_sditf>; 764 }; 765 }; 766}; 767