1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include "rk3568.dtsi" 10#include "rk3568-toybrick.dtsi" 11 12/delete-node/ &adc_keys; 13 14/ { 15 compatible = "rockchip,rk3568-toybrick", "rockchip,rk3568"; 16 adc-keys { 17 compatible = "adc-keys"; 18 io-channels = <&saradc 0>; 19 io-channel-names = "buttons"; 20 poll-interval = <100>; 21 keyup-threshold-microvolt = <1800000>; 22 23 menu-key { 24 linux,code = <KEY_MENU>; 25 label = "menu"; 26 press-threshold-microvolt = <1250000>; 27 }; 28 29 mute-key { 30 linux,code = <KEY_MUTE>; 31 label = "mute"; 32 press-threshold-microvolt = <850000>; 33 }; 34 35 vol-down-key { 36 linux,code = <KEY_VOLUMEDOWN>; 37 label = "volume down"; 38 press-threshold-microvolt = <400000>; 39 }; 40 41 vol-up-key { 42 linux,code = <KEY_VOLUMEUP>; 43 label = "volume up"; 44 press-threshold-microvolt = <20000>; 45 }; 46 }; 47 48 gpio_leds: gpio-leds { 49 compatible = "gpio-leds"; 50 led@1 { 51 gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>; 52 label = "blue"; // Blue LED 53 retain-state-suspended; 54 }; 55 56 led@2 { 57 gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>; 58 label = "red"; // Red LED 59 retain-state-suspended; 60 }; 61 62 led@3 { 63 gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_HIGH>; 64 label = "green"; // Green LED 65 retain-state-suspended; 66 }; 67 }; 68 69 pcie20_3v3: gpio-regulator { 70 compatible = "regulator-gpio"; 71 regulator-name = "pcie20_3v3"; 72 regulator-min-microvolt = <100000>; 73 regulator-max-microvolt = <3300000>; 74 gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; 75 gpios-states = <0x1>; 76 states = <100000 0x0 77 3300000 0x1>; 78 }; 79 80 pcie30_avdd0v9: pcie30-avdd0v9 { 81 compatible = "regulator-fixed"; 82 regulator-name = "pcie30_avdd0v9"; 83 regulator-always-on; 84 regulator-boot-on; 85 regulator-min-microvolt = <900000>; 86 regulator-max-microvolt = <900000>; 87 vin-supply = <&vcc3v3_sys>; 88 }; 89 90 pcie30_avdd1v8: pcie30-avdd1v8 { 91 compatible = "regulator-fixed"; 92 regulator-name = "pcie30_avdd1v8"; 93 regulator-always-on; 94 regulator-boot-on; 95 regulator-min-microvolt = <1800000>; 96 regulator-max-microvolt = <1800000>; 97 vin-supply = <&vcc3v3_sys>; 98 }; 99 100 pcie30_3v3: gpio-regulator { 101 compatible = "regulator-gpio"; 102 regulator-name = "pcie30_3v3"; 103 regulator-min-microvolt = <100000>; 104 regulator-max-microvolt = <3300000>; 105 gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>; 106 gpios-states = <0x1>; 107 states = <100000 0x0 108 3300000 0x1>; 109 }; 110 111 rk_headset: rk-headset { 112 compatible = "rockchip_headset"; 113 headset_gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_LOW>; 114 pinctrl-names = "default"; 115 pinctrl-0 = <&hp_det>; 116 io-channels = <&saradc 1>; 117 }; 118 119 rk809_sound_micarray: rk809-sound-micarray { 120 status = "disabled"; 121 compatible = "simple-audio-card"; 122 simple-audio-card,format = "i2s"; 123 simple-audio-card,name = "rockchip,rk809-codec"; 124 simple-audio-card,mclk-fs = <256>; 125 126 simple-audio-card,dai-link@0 { 127 format = "i2s"; 128 cpu { 129 sound-dai = <&i2s1_8ch>; 130 }; 131 codec { 132 sound-dai = <&rk809_codec 0>; 133 }; 134 }; 135 simple-audio-card,dai-link@1 { 136 format = "i2s"; 137 cpu { 138 sound-dai = <&i2s1_8ch>; 139 }; 140 codec { 141 sound-dai = <&es7210>; 142 }; 143 }; 144 }; 145 146 rt5672-sound { 147 compatible = "rockchip-rt5670"; 148 status = "disabled"; 149 dais { 150 dai0 { 151 audio-codec = <&rt5670>; 152 audio-controller = <&i2s1_8ch>; 153 format = "i2s"; 154 }; 155 dai1 { 156 audio-codec = <&rt5670>; 157 audio-controller = <&i2s1_8ch>; 158 format = "i2s"; 159 }; 160 dai2 { 161 audio-codec = <&es7210>; 162 audio-controller = <&i2s1_8ch>; 163 format = "i2s"; 164 }; 165 }; 166 }; 167 168 vcc2v5_sys: vcc2v5-ddr { 169 compatible = "regulator-fixed"; 170 regulator-name = "vcc2v5-sys"; 171 regulator-always-on; 172 regulator-boot-on; 173 regulator-min-microvolt = <2500000>; 174 regulator-max-microvolt = <2500000>; 175 vin-supply = <&vcc3v3_sys>; 176 }; 177 178 vcc_camera: vcc-camera-regulator { 179 compatible = "regulator-fixed"; 180 gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&camera_pwr>; 183 regulator-name = "vcc_camera"; 184 enable-active-high; 185 regulator-always-on; 186 regulator-boot-on; 187 }; 188 189 vcc3v3_bu: vcc3v3-bu { 190 compatible = "regulator-fixed"; 191 regulator-name = "vcc3v3_bu"; 192 regulator-always-on; 193 regulator-boot-on; 194 regulator-min-microvolt = <3300000>; 195 regulator-max-microvolt = <3300000>; 196 vin-supply = <&vcc5v0_sys>; 197 }; 198}; 199 200&combphy0_us { 201 status = "okay"; 202}; 203 204&combphy1_usq { 205 status = "okay"; 206}; 207 208&combphy2_psq { 209 status = "okay"; 210}; 211 212&csi2_dphy_hw { 213 status = "okay"; 214}; 215 216&csi2_dphy0 { 217 status = "okay"; 218 219 ports { 220 #address-cells = <1>; 221 #size-cells = <0>; 222 port@0 { 223 reg = <0>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 mipi_in_ucam0: endpoint@1 { 228 reg = <1>; 229 remote-endpoint = <&ucam_out0>; 230 data-lanes = <1 2>; 231 }; 232 mipi_in_ucam1: endpoint@2 { 233 reg = <2>; 234 remote-endpoint = <&gc8034_out>; 235 data-lanes = <1 2 3 4>; 236 }; 237 mipi_in_ucam2: endpoint@3 { 238 reg = <3>; 239 remote-endpoint = <&ov5695_out>; 240 data-lanes = <1 2>; 241 }; 242 }; 243 port@1 { 244 reg = <1>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 248 csidphy_out: endpoint@0 { 249 reg = <0>; 250 remote-endpoint = <&isp0_in>; 251 }; 252 }; 253 }; 254}; 255 256&gmac0 { 257 phy-mode = "rgmii"; 258 clock_in_out = "output"; 259 260 snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>; 261 snps,reset-active-low; 262 /* Reset time is 20ms, 100ms for rtl8211f */ 263 snps,reset-delays-us = <0 20000 100000>; 264 265 assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>; 266 assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>; 267 assigned-clock-rates = <0>, <125000000>; 268 269 pinctrl-names = "default"; 270 pinctrl-0 = <&gmac0_miim 271 &gmac0_tx_bus2 272 &gmac0_rx_bus2 273 &gmac0_rgmii_clk 274 &gmac0_rgmii_bus>; 275 276 tx_delay = <0x37>; 277 rx_delay = <0x2e>; 278 279 phy-handle = <&rgmii_phy0>; 280 status = "okay"; 281}; 282 283&gmac1 { 284 phy-mode = "rgmii"; 285 clock_in_out = "output"; 286 287 snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 288 snps,reset-active-low; 289 /* Reset time is 20ms, 100ms for rtl8211f */ 290 snps,reset-delays-us = <0 20000 100000>; 291 292 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 293 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; 294 assigned-clock-rates = <0>, <125000000>; 295 296 pinctrl-names = "default"; 297 pinctrl-0 = <&gmac1m1_miim 298 &gmac1m1_tx_bus2 299 &gmac1m1_rx_bus2 300 &gmac1m1_rgmii_clk 301 &gmac1m1_rgmii_bus>; 302 303 tx_delay = <0x47>; 304 rx_delay = <0x28>; 305 306 phy-handle = <&rgmii_phy1>; 307 status = "okay"; 308}; 309 310&i2c3 { 311 status = "okay"; 312 rt5670: rt5670@1c { 313 status = "okay"; 314 #sound-dai-cell = <0>; 315 compatible = "realtek,rt5670"; 316 reg = <0x1c>; 317 }; 318 319 es7210: es7210@40 { 320 #sound-dai-cells = <0>; 321 compatible = "MicArray_0"; 322 reg = <0x40>; 323 clocks = <&cru I2S1_MCLKOUT_RX>;//csqerr 324 clock-names = "mclk"; 325 }; 326 327 es7210_1: es7210@42 { 328 compatible = "MicArray_1"; 329 reg = <0x42>; 330 }; 331}; 332 333&i2c4 { 334 status = "okay"; 335 336 gc8034: gc8034@37 { 337 compatible = "galaxycore,gc8034"; 338 reg = <0x37>; 339 clocks = <&cru CLK_CIF_OUT>;//CLK_CAM0_OUT>; 340 clock-names = "xvclk"; 341 power-domains = <&power RK3568_PD_VI>; 342 pinctrl-names = "default"; 343 pinctrl-0 = <&cif_clk>; 344 reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; 345 pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; 346 rockchip,grf = <&grf>; 347 rockchip,camera-module-index = <0>; 348 rockchip,camera-module-facing = "back"; 349 rockchip,camera-module-name = "RK-CMK-8M-2-v1"; 350 rockchip,camera-module-lens-name = "CK8401"; 351 port { 352 gc8034_out: endpoint { 353 remote-endpoint = <&mipi_in_ucam1>; 354 data-lanes = <1 2 3 4>; 355 }; 356 }; 357 }; 358 359 ov9750_1: ov9750_1@36 { 360 compatible = "ovti,ov9750"; 361 reg = <0x36>; 362 clocks = <&cru CLK_CIF_OUT>; 363 clock-names = "xvclk"; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&cif_clk>; 366 power-domains = <&power RK3568_PD_VI>; 367 reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>; 368 pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>; 369 rockchip,camera-module-index = <0>; 370 rockchip,camera-module-facing = "back"; 371 rockchip,camera-module-name = "CMK-OT0854-FV1"; 372 rockchip,camera-module-lens-name = "CHT-842B-MD"; 373 port { 374 ucam_out0: endpoint { 375 remote-endpoint = <&mipi_in_ucam0>; 376 data-lanes = <1 2>; 377 }; 378 }; 379 }; 380 381 ov5695: ov5695@36 { 382 status = "okay"; 383 compatible = "ovti,ov5695"; 384 reg = <0x36>; 385 clocks = <&cru CLK_CIF_OUT>; 386 clock-names = "xvclk"; 387 power-domains = <&power RK3568_PD_VI>; 388 pinctrl-names = "default"; 389 pinctrl-0 = <&cif_clk>; 390 reset-gpios = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; 391 pwdn-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_LOW>; 392 rockchip,camera-module-index = <0>; 393 rockchip,camera-module-facing = "back"; 394 rockchip,camera-module-name = "TongJu"; 395 rockchip,camera-module-lens-name = "CHT842-MD"; 396 port { 397 ov5695_out: endpoint { 398 remote-endpoint = <&mipi_in_ucam2>; 399 data-lanes = <1 2>; 400 }; 401 }; 402 }; 403}; 404 405&i2c5 { 406 status = "okay"; 407 408 gs_mxc6655xa: gs_mxc6655xa@15 { 409 status = "okay"; 410 compatible = "gs_mxc6655xa"; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&mxc6655xa_irq_pin>; 413 reg = <0x15>; 414 irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; 415 irq_enable = <0>; 416 poll_delay_ms = <30>; 417 type = <SENSOR_TYPE_ACCEL>; 418 power-off-in-suspend = <1>; 419 layout = <1>; 420 }; 421 422 mxc6655xa: mxc6655xa@15 { 423 status = "disabled"; 424 compatible = "gs_mxc6655xa"; 425 pinctrl-names = "default"; 426 pinctrl-0 = <&mxc6655xa_irq_pin>; 427 reg = <0x15>; 428 irq-gpio = <&gpio3 RK_PC1 IRQ_TYPE_LEVEL_LOW>; 429 irq_enable = <0>; 430 poll_delay_ms = <30>; 431 type = <SENSOR_TYPE_ACCEL>; 432 power-off-in-suspend = <1>; 433 layout = <1>; 434 }; 435 436 hym8563: hym8563@51 { 437 compatible = "haoyu,hym8563"; 438 reg = <0x51>; 439 pinctrl-names = "default"; 440 pinctrl-0 = <&rtc_int>; 441 442 interrupt-parent = <&gpio0>; 443 interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; 444 }; 445}; 446 447&i2s1_8ch { 448 status = "okay"; 449 #sound-dai-cells = <0>; 450 rockchip,clk-trcm = <1>; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&i2s1m0_sclktx 453 &i2s1m0_sclkrx 454 &i2s1m0_lrcktx 455 &i2s1m0_sclkrx 456 &i2s1m0_lrckrx 457 &i2s1m0_sdo0 458 &i2s1m0_sdi0 459 &i2s1m0_sdi1 460 &i2s1m0_sdi2 461 &i2s1m0_sdi3>; 462}; 463 464&mdio0 { 465 rgmii_phy0: phy@0 { 466 compatible = "ethernet-phy-ieee802.3-c22"; 467 reg = <0x0>; 468 }; 469}; 470 471&mdio1 { 472 rgmii_phy1: phy@0 { 473 compatible = "ethernet-phy-ieee802.3-c22"; 474 reg = <0x0>; 475 }; 476}; 477 478&pcie30phy { 479 status = "okay"; 480}; 481 482&pcie3x2 { 483 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; 484 vpcie3v3-supply = <&pcie30_3v3>; 485 status = "okay"; 486}; 487 488&pwm7 { 489 status = "okay"; 490}; 491 492&rk809_sound { 493 status = "okay"; 494}; 495 496&rkisp { 497 status = "okay"; 498}; 499 500&rkisp_mmu { 501 status = "okay"; 502}; 503 504&rkisp_vir0 { 505 status = "okay"; 506 507 port { 508 #address-cells = <1>; 509 #size-cells = <0>; 510 511 isp0_in: endpoint@0 { 512 reg = <0>; 513 remote-endpoint = <&csidphy_out>; 514 }; 515 }; 516}; 517 518&sata2 { 519 status = "okay"; 520}; 521 522&sdio_pwrseq { 523 compatible = "mmc-pwrseq-simple"; 524 clocks = <&rk809 1>; 525 clock-names = "ext_clock"; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&wifi_enable_h>; 528 529 /* 530 * On the module itself this is one of these (depending 531 * on the actual card populated): 532 * - SDIO_RESET_L_WL_REG_ON 533 * - PDN (power down when low) 534 */ 535 reset-gpios = <&gpio3 RK_PD5 GPIO_ACTIVE_LOW>; 536 post-power-on-delay-ms = <20>; 537 status = "okay"; 538}; 539 540&sdmmc1 { 541 status = "disabled"; 542}; 543 544&sdmmc2 { 545 max-frequency = <150000000>; 546 supports-sdio; 547 bus-width = <4>; 548 disable-wp; 549 cap-sd-highspeed; 550 cap-sdio-irq; 551 keep-power-in-suspend; 552 mmc-pwrseq = <&sdio_pwrseq>; 553 non-removable; 554 pinctrl-names = "default"; 555 pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; 556 sd-uhs-sdr104; 557 status = "okay"; 558}; 559 560&uart1 { 561 status = "disabled"; 562 pinctrl-names = "default"; 563 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; 564}; 565 566&uart8 { 567 status = "okay"; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&uart8m0_xfer &uart8m0_ctsn>; 570}; 571 572&vcc3v3_lcd0_n { 573 gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 574 enable-active-high; 575}; 576 577&vcc3v3_lcd1_n { 578 gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 579 enable-active-high; 580}; 581 582&video_phy0 { 583 status = "okay"; 584}; 585 586&video_phy1 { 587 status = "disabled"; 588}; 589 590&wireless_wlan { 591 pinctrl-names = "default"; 592 pinctrl-0 = <&wifi_host_wake_irq>; 593 WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; 594}; 595 596&wireless_bluetooth { 597 compatible = "bluetooth-platdata"; 598 clocks = <&rk809 1>; 599 clock-names = "ext_clock"; 600 //wifi-bt-power-toggle; 601 uart_rts_gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 602 pinctrl-names = "default", "rts_gpio"; 603 pinctrl-0 = <&uart8m0_rtsn>; 604 pinctrl-1 = <&uart8_pin>; 605 BT,reset_gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_HIGH>; 606 BT,wake_gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>; 607 BT,wake_host_irq = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>; 608 status = "okay"; 609}; 610 611&pinctrl { 612 cam { 613 camera_pwr: camera-pwr { 614 rockchip,pins = 615 /* camera power en */ 616 <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 617 }; 618 }; 619 620 headphone { 621 hp_det: hp-det { 622 rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_down>; 623 }; 624 }; 625 626 i2s1 { 627 /omit-if-no-ref/ 628 i2s1m0_lrckrx: i2s1m0-lrckrx { 629 rockchip,pins = 630 /* i2s1m0_lrckrx */ 631 <1 RK_PA6 1 &pcfg_pull_up_drv_level_4>; 632 }; 633 /omit-if-no-ref/ 634 i2s1m0_lrcktx: i2s1m0-lrcktx { 635 rockchip,pins = 636 /* i2s1m0_lrcktx */ 637 <1 RK_PA5 1 &pcfg_pull_up_drv_level_4>; 638 }; 639 /omit-if-no-ref/ 640 i2s1m0_mclk: i2s1m0-mclk { 641 rockchip,pins = 642 /* i2s1m0_mclk */ 643 <1 RK_PA2 1 &pcfg_pull_up_drv_level_4>; 644 }; 645 /omit-if-no-ref/ 646 i2s1m0_sclkrx: i2s1m0-sclkrx { 647 rockchip,pins = 648 /* i2s1m0_sclkrx */ 649 <1 RK_PA4 1 &pcfg_pull_up_drv_level_4>; 650 }; 651 /omit-if-no-ref/ 652 i2s1m0_sclktx: i2s1m0-sclktx { 653 rockchip,pins = 654 /* i2s1m0_sclktx */ 655 <1 RK_PA3 1 &pcfg_pull_up_drv_level_4>; 656 }; 657 /omit-if-no-ref/ 658 i2s1m0_sdi0: i2s1m0-sdi0 { 659 rockchip,pins = 660 /* i2s1m0_sdi0 */ 661 <1 RK_PB3 1 &pcfg_pull_up_drv_level_4>; 662 }; 663 /omit-if-no-ref/ 664 i2s1m0_sdi1: i2s1m0-sdi1 { 665 rockchip,pins = 666 /* i2s1m0_sdi1 */ 667 <1 RK_PB2 2 &pcfg_pull_up_drv_level_4>; 668 }; 669 /omit-if-no-ref/ 670 i2s1m0_sdi2: i2s1m0-sdi2 { 671 rockchip,pins = 672 /* i2s1m0_sdi2 */ 673 <1 RK_PB1 2 &pcfg_pull_up_drv_level_4>; 674 }; 675 /omit-if-no-ref/ 676 i2s1m0_sdi3: i2s1m0-sdi3 { 677 rockchip,pins = 678 /* i2s1m0_sdi3 */ 679 <1 RK_PB0 2 &pcfg_pull_up_drv_level_4>; 680 }; 681 /omit-if-no-ref/ 682 i2s1m0_sdo0: i2s1m0-sdo0 { 683 rockchip,pins = 684 /* i2s1m0_sdo0 */ 685 <1 RK_PA7 1 &pcfg_pull_up_drv_level_4>; 686 }; 687 }; 688 689 leds_pin: leds-pin { 690 rockchip,pins = 691 <4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>, 692 <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_up>, 693 <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 694 }; 695 696 mxc6655xa { 697 mxc6655xa_irq_pin: mxc6655xa_irq_pin { 698 rockchip,pins = <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 699 }; 700 }; 701 702 rtc { 703 rtc_int: rtc-int { 704 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; 705 }; 706 }; 707 708 sdio-pwrseq { 709 wifi_enable_h: wifi-enable-h { 710 rockchip,pins = <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>; 711 }; 712 }; 713 714 wireless-wlan { 715 wifi_host_wake_irq: wifi-host-wake-irq { 716 rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; 717 }; 718 }; 719 720 wireless-bluetooth { 721 uart8_pin: uart8-pin { 722 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 723 }; 724 }; 725}; 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