xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3568-toybrick-sd0.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
8*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
9*4882a593Smuzhiyun#include "rk3568.dtsi"
10*4882a593Smuzhiyun#include "rk3568-toybrick.dtsi"
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun/delete-node/ &adc_keys;
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun/ {
15*4882a593Smuzhiyun	compatible = "rockchip,rk3568-toybrick-sd0", "rockchip,rk3568";
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	bt-sound {
18*4882a593Smuzhiyun		status = "okay";
19*4882a593Smuzhiyun		compatible = "simple-audio-card";
20*4882a593Smuzhiyun		simple-audio-card,format = "dsp_a";
21*4882a593Smuzhiyun		simple-audio-card,bitclock-inversion = <1>;
22*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <512>;
23*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,bt";
24*4882a593Smuzhiyun		#simple-audio-card,bitclock-master = <&sound2_master>;
25*4882a593Smuzhiyun		#simple-audio-card,frame-master = <&sound2_master>;
26*4882a593Smuzhiyun		simple-audio-card,cpu {
27*4882a593Smuzhiyun			sound-dai = <&i2s2_2ch>;
28*4882a593Smuzhiyun		};
29*4882a593Smuzhiyun		sound2_master:simple-audio-card,codec {
30*4882a593Smuzhiyun			#sound-dai-cells = <0>;
31*4882a593Smuzhiyun			sound-dai = <&bt_sco>;
32*4882a593Smuzhiyun		};
33*4882a593Smuzhiyun	};
34*4882a593Smuzhiyun	pcie30_avdd0v9: pcie30-avdd0v9 {
35*4882a593Smuzhiyun		compatible = "regulator-fixed";
36*4882a593Smuzhiyun		regulator-name = "pcie30_avdd0v9";
37*4882a593Smuzhiyun		regulator-always-on;
38*4882a593Smuzhiyun		regulator-boot-on;
39*4882a593Smuzhiyun		regulator-min-microvolt = <900000>;
40*4882a593Smuzhiyun		regulator-max-microvolt = <900000>;
41*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
42*4882a593Smuzhiyun	};
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun	pcie30_avdd1v8: pcie30-avdd1v8 {
45*4882a593Smuzhiyun		compatible = "regulator-fixed";
46*4882a593Smuzhiyun		regulator-name = "pcie30_avdd1v8";
47*4882a593Smuzhiyun		regulator-always-on;
48*4882a593Smuzhiyun		regulator-boot-on;
49*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
50*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
51*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
52*4882a593Smuzhiyun	};
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun	pcie30_3v3: gpio-regulator {
55*4882a593Smuzhiyun		compatible = "regulator-gpio";
56*4882a593Smuzhiyun		regulator-name = "pcie30_3v3";
57*4882a593Smuzhiyun		regulator-min-microvolt = <100000>;
58*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
59*4882a593Smuzhiyun		gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>;
60*4882a593Smuzhiyun		gpios-states = <0x1>;
61*4882a593Smuzhiyun		states = <100000 0x0
62*4882a593Smuzhiyun				3300000 0x1>;
63*4882a593Smuzhiyun	};
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun	rk_headset: rk-headset {
66*4882a593Smuzhiyun		compatible = "rockchip_headset";
67*4882a593Smuzhiyun		headset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>;
68*4882a593Smuzhiyun		pinctrl-names = "default";
69*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
70*4882a593Smuzhiyun		io-channels = <&saradc 2>;
71*4882a593Smuzhiyun	};
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun	vcc2v5_sys: vcc2v5-ddr {
74*4882a593Smuzhiyun		compatible = "regulator-fixed";
75*4882a593Smuzhiyun		regulator-name = "vcc2v5-sys";
76*4882a593Smuzhiyun		regulator-always-on;
77*4882a593Smuzhiyun		regulator-boot-on;
78*4882a593Smuzhiyun		regulator-min-microvolt = <2500000>;
79*4882a593Smuzhiyun		regulator-max-microvolt = <2500000>;
80*4882a593Smuzhiyun		vin-supply = <&vcc3v3_sys>;
81*4882a593Smuzhiyun	};
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun	vcc3v3_pcie: gpio-regulator {
84*4882a593Smuzhiyun		compatible = "regulator-fixed";
85*4882a593Smuzhiyun		regulator-name = "vcc3v3_pcie";
86*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
87*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
88*4882a593Smuzhiyun		enable-active-high;
89*4882a593Smuzhiyun		startup-delay-us = <5000>;
90*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
91*4882a593Smuzhiyun	};
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun	vcc3v3_bu: vcc3v3-bu {
94*4882a593Smuzhiyun		compatible = "regulator-fixed";
95*4882a593Smuzhiyun		regulator-name = "vcc3v3_bu";
96*4882a593Smuzhiyun		regulator-always-on;
97*4882a593Smuzhiyun		regulator-boot-on;
98*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
99*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
100*4882a593Smuzhiyun		vin-supply = <&vcc5v0_sys>;
101*4882a593Smuzhiyun	};
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun    vcc_camera: vcc-camera-regulator {
104*4882a593Smuzhiyun		compatible = "regulator-fixed";
105*4882a593Smuzhiyun		gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
106*4882a593Smuzhiyun		pinctrl-names = "default";
107*4882a593Smuzhiyun		pinctrl-0 = <&camera_pwr>;
108*4882a593Smuzhiyun		regulator-name = "vcc_camera";
109*4882a593Smuzhiyun		enable-active-high;
110*4882a593Smuzhiyun		regulator-always-on;
111*4882a593Smuzhiyun		regulator-boot-on;
112*4882a593Smuzhiyun	};
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun	vcc5v0_host: vcc5v0-host-regulator {
115*4882a593Smuzhiyun		compatible = "regulator-fixed";
116*4882a593Smuzhiyun		enable-active-high;
117*4882a593Smuzhiyun		gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
118*4882a593Smuzhiyun		pinctrl-names = "default";
119*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_host_en>;
120*4882a593Smuzhiyun		regulator-name = "vcc5v0_host";
121*4882a593Smuzhiyun		regulator-always-on;
122*4882a593Smuzhiyun	};
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun	vcc5v0_otg: vcc5v0-otg-regulator {
125*4882a593Smuzhiyun		compatible = "regulator-fixed";
126*4882a593Smuzhiyun		enable-active-high;
127*4882a593Smuzhiyun		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
128*4882a593Smuzhiyun		pinctrl-names = "default";
129*4882a593Smuzhiyun		pinctrl-0 = <&vcc5v0_otg_en>;
130*4882a593Smuzhiyun		regulator-name = "vcc5v0_otg";
131*4882a593Smuzhiyun	};
132*4882a593Smuzhiyun};
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun&bus_npu {
135*4882a593Smuzhiyun	status = "okay";
136*4882a593Smuzhiyun};
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun&combphy0_us {
139*4882a593Smuzhiyun	status = "okay";
140*4882a593Smuzhiyun};
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun&combphy1_usq {
143*4882a593Smuzhiyun	status = "okay";
144*4882a593Smuzhiyun};
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun&combphy2_psq {
147*4882a593Smuzhiyun	status = "okay";
148*4882a593Smuzhiyun};
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun&csi2_dphy_hw {
151*4882a593Smuzhiyun	status = "okay";
152*4882a593Smuzhiyun};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun&csi2_dphy0 {
155*4882a593Smuzhiyun	status = "okay";
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun	ports {
158*4882a593Smuzhiyun		#address-cells = <1>;
159*4882a593Smuzhiyun		#size-cells = <0>;
160*4882a593Smuzhiyun		port@0 {
161*4882a593Smuzhiyun			reg = <0>;
162*4882a593Smuzhiyun			#address-cells = <1>;
163*4882a593Smuzhiyun			#size-cells = <0>;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
166*4882a593Smuzhiyun				reg = <1>;
167*4882a593Smuzhiyun				remote-endpoint = <&imx415_out>;
168*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
169*4882a593Smuzhiyun			};
170*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@2 {
171*4882a593Smuzhiyun				reg = <2>;
172*4882a593Smuzhiyun				remote-endpoint = <&ov50c40_out>;
173*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
174*4882a593Smuzhiyun			};
175*4882a593Smuzhiyun		};
176*4882a593Smuzhiyun		port@1 {
177*4882a593Smuzhiyun			reg = <1>;
178*4882a593Smuzhiyun			#address-cells = <1>;
179*4882a593Smuzhiyun			#size-cells = <0>;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun			csidphy_out: endpoint@0 {
182*4882a593Smuzhiyun				reg = <0>;
183*4882a593Smuzhiyun				remote-endpoint = <&isp0_in>;
184*4882a593Smuzhiyun			};
185*4882a593Smuzhiyun		};
186*4882a593Smuzhiyun	};
187*4882a593Smuzhiyun};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun&gmac1 {
190*4882a593Smuzhiyun	phy-mode = "rgmii";
191*4882a593Smuzhiyun	clock_in_out = "output";
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun	snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>;
194*4882a593Smuzhiyun	snps,reset-active-low;
195*4882a593Smuzhiyun	/* Reset time is 20ms, 100ms for rtl8211f */
196*4882a593Smuzhiyun	snps,reset-delays-us = <0 20000 100000>;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>;
199*4882a593Smuzhiyun	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
200*4882a593Smuzhiyun	assigned-clock-rates = <0>, <125000000>, <25000000>;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun	pinctrl-names = "default";
203*4882a593Smuzhiyun	pinctrl-0 = <&gmac1m1_miim
204*4882a593Smuzhiyun		     &gmac1m1_tx_bus2
205*4882a593Smuzhiyun		     &gmac1m1_rx_bus2
206*4882a593Smuzhiyun		     &gmac1m1_rgmii_clk
207*4882a593Smuzhiyun		     &gmac1m1_rgmii_bus
208*4882a593Smuzhiyun		     &eth1m1_pins>;
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun	tx_delay = <0x47>;
211*4882a593Smuzhiyun	rx_delay = <0x28>;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun	phy-handle = <&rgmii_phy1>;
214*4882a593Smuzhiyun	status = "okay";
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&i2s2_2ch {
218*4882a593Smuzhiyun	status = "okay";
219*4882a593Smuzhiyun	#sound-dai-cells = <0>;
220*4882a593Smuzhiyun};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun&i2c0 {
223*4882a593Smuzhiyun	status = "okay";
224*4882a593Smuzhiyun	rk809: pmic@20 {
225*4882a593Smuzhiyun		compatible = "rockchip,rk809";
226*4882a593Smuzhiyun		reg = <0x20>;
227*4882a593Smuzhiyun		regulators {
228*4882a593Smuzhiyun			vccio_acodec: LDO_REG4 {
229*4882a593Smuzhiyun				regulator-always-on;
230*4882a593Smuzhiyun				regulator-boot-on;
231*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
232*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
233*4882a593Smuzhiyun				regulator-name = "vccio_acodec";
234*4882a593Smuzhiyun				regulator-state-mem {
235*4882a593Smuzhiyun					regulator-off-in-suspend;
236*4882a593Smuzhiyun				};
237*4882a593Smuzhiyun			};
238*4882a593Smuzhiyun		};
239*4882a593Smuzhiyun	};
240*4882a593Smuzhiyun};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun&i2s1_8ch {
243*4882a593Smuzhiyun	status = "okay";
244*4882a593Smuzhiyun	#sound-dai-cells = <0>;
245*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
246*4882a593Smuzhiyun	pinctrl-names = "default";
247*4882a593Smuzhiyun	pinctrl-0 = <&i2s1m0_sclktx
248*4882a593Smuzhiyun		     &i2s1m0_lrcktx
249*4882a593Smuzhiyun		     &i2s1m0_sdo0
250*4882a593Smuzhiyun		     &i2s1m0_sdi0>;
251*4882a593Smuzhiyun};
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun&i2c5 {
254*4882a593Smuzhiyun	status = "okay";
255*4882a593Smuzhiyun	hym8563: hym8563@51 {
256*4882a593Smuzhiyun		compatible = "haoyu,hym8563";
257*4882a593Smuzhiyun		reg = <0x51>;
258*4882a593Smuzhiyun		#clock-cells = <0>;
259*4882a593Smuzhiyun		clock-frequency = <32768>;
260*4882a593Smuzhiyun		clock-output-names = "hym8563";
261*4882a593Smuzhiyun		pinctrl-names = "default";
262*4882a593Smuzhiyun		pinctrl-0 = <&rtc_int>;
263*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
264*4882a593Smuzhiyun		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
265*4882a593Smuzhiyun	};
266*4882a593Smuzhiyun};
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun&i2c2 {
269*4882a593Smuzhiyun	status = "okay";
270*4882a593Smuzhiyun	pinctrl-names = "default";
271*4882a593Smuzhiyun	pinctrl-0 = <&i2c2m1_xfer>;
272*4882a593Smuzhiyun	imx415: imx415@1a {
273*4882a593Smuzhiyun		compatible = "sony,imx415";
274*4882a593Smuzhiyun		reg = <0x1a>;
275*4882a593Smuzhiyun		clocks = <&cru CLK_CIF_OUT>;
276*4882a593Smuzhiyun		clock-names = "xvclk";
277*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
278*4882a593Smuzhiyun		pinctrl-names = "default";
279*4882a593Smuzhiyun		pinctrl-0 = <&cif_clk>;
280*4882a593Smuzhiyun		// must be high at last
281*4882a593Smuzhiyun		power-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
282*4882a593Smuzhiyun		// must be high at last  do at vcc_camera
283*4882a593Smuzhiyun		//reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
284*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
285*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
286*4882a593Smuzhiyun		rockchip,camera-module-name = "CMK-OT2022-PX1";
287*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20-RK3568";
288*4882a593Smuzhiyun		//lens-focus = <&cam_ircut0>;
289*4882a593Smuzhiyun		port {
290*4882a593Smuzhiyun			imx415_out: endpoint {
291*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
292*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
293*4882a593Smuzhiyun			};
294*4882a593Smuzhiyun		};
295*4882a593Smuzhiyun	};
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun	aw8601: aw8601@c {
298*4882a593Smuzhiyun		compatible = "awinic,aw8601";
299*4882a593Smuzhiyun		status = "okay";
300*4882a593Smuzhiyun		reg = <0x0c>;
301*4882a593Smuzhiyun		rockchip,vcm-start-current = <56>;
302*4882a593Smuzhiyun		rockchip,vcm-rated-current = <96>;
303*4882a593Smuzhiyun		rockchip,vcm-step-mode = <4>;
304*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
305*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
306*4882a593Smuzhiyun	};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun	otp_eeprom: otp_eeprom@50 {
309*4882a593Smuzhiyun		compatible = "rk,otp_eeprom";
310*4882a593Smuzhiyun		status = "okay";
311*4882a593Smuzhiyun		reg = <0x50>;
312*4882a593Smuzhiyun	};
313*4882a593Smuzhiyun
314*4882a593Smuzhiyun	ov50c40: ov50c40@36 {
315*4882a593Smuzhiyun		compatible = "ovti,ov50c40";
316*4882a593Smuzhiyun		reg = <0x36>;
317*4882a593Smuzhiyun		clocks = <&cru CLK_CIF_OUT>;
318*4882a593Smuzhiyun		clock-names = "xvclk";
319*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
320*4882a593Smuzhiyun		pinctrl-names = "default";
321*4882a593Smuzhiyun		pinctrl-0 = <&cif_clk>;
322*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;// must be high at last
323*4882a593Smuzhiyun		reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;// must be high at last
324*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
325*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
326*4882a593Smuzhiyun		rockchip,camera-module-name = "HZGA06";
327*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "ZE0082C1-RK3568";
328*4882a593Smuzhiyun		eeprom-ctrl = <&otp_eeprom>;
329*4882a593Smuzhiyun		lens-focus = <&aw8601>;
330*4882a593Smuzhiyun		port {
331*4882a593Smuzhiyun			ov50c40_out: endpoint {
332*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam1>;
333*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
334*4882a593Smuzhiyun			};
335*4882a593Smuzhiyun		};
336*4882a593Smuzhiyun	};
337*4882a593Smuzhiyun};
338*4882a593Smuzhiyun
339*4882a593Smuzhiyun&leds {
340*4882a593Smuzhiyun	status = "okay";
341*4882a593Smuzhiyun	compatible = "gpio-leds";
342*4882a593Smuzhiyun	work_led: work {
343*4882a593Smuzhiyun		gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
344*4882a593Smuzhiyun		linux,default-trigger = "heartbeat";
345*4882a593Smuzhiyun	};
346*4882a593Smuzhiyun};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun&mdio1 {
349*4882a593Smuzhiyun	rgmii_phy1: phy@0 {
350*4882a593Smuzhiyun		compatible = "ethernet-phy-ieee802.3-c22";
351*4882a593Smuzhiyun		reg = <0x0>;
352*4882a593Smuzhiyun		clocks = <&cru CLK_MAC1_OUT>;
353*4882a593Smuzhiyun	};
354*4882a593Smuzhiyun};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun&pcie2x1 {
357*4882a593Smuzhiyun	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
358*4882a593Smuzhiyun	pinctrl-names = "default";
359*4882a593Smuzhiyun	pinctrl-0 = <&rtl8111_isolate>;
360*4882a593Smuzhiyun	status = "okay";
361*4882a593Smuzhiyun};
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun&pcie30phy {
364*4882a593Smuzhiyun	status = "okay";
365*4882a593Smuzhiyun};
366*4882a593Smuzhiyun
367*4882a593Smuzhiyun&pcie3x2 {
368*4882a593Smuzhiyun	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
369*4882a593Smuzhiyun	vpcie3v3-supply = <&pcie30_3v3>;
370*4882a593Smuzhiyun	status = "okay";
371*4882a593Smuzhiyun};
372*4882a593Smuzhiyun
373*4882a593Smuzhiyun&reserved_memory {
374*4882a593Smuzhiyun	linux,cma {
375*4882a593Smuzhiyun		compatible = "shared-dma-pool";
376*4882a593Smuzhiyun		inactive;
377*4882a593Smuzhiyun		reusable;
378*4882a593Smuzhiyun		reg = <0x0 0x10000000 0x0 0x08000000>;
379*4882a593Smuzhiyun		linux,cma-default;
380*4882a593Smuzhiyun	};
381*4882a593Smuzhiyun};
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun&rkisp {
384*4882a593Smuzhiyun	status = "okay";
385*4882a593Smuzhiyun};
386*4882a593Smuzhiyun
387*4882a593Smuzhiyun&rkisp_mmu {
388*4882a593Smuzhiyun	status = "okay";
389*4882a593Smuzhiyun};
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun&rkisp_vir0 {
392*4882a593Smuzhiyun	status = "okay";
393*4882a593Smuzhiyun
394*4882a593Smuzhiyun	port {
395*4882a593Smuzhiyun		#address-cells = <1>;
396*4882a593Smuzhiyun		#size-cells = <0>;
397*4882a593Smuzhiyun
398*4882a593Smuzhiyun		isp0_in: endpoint@0 {
399*4882a593Smuzhiyun			reg = <0>;
400*4882a593Smuzhiyun			remote-endpoint = <&csidphy_out>;
401*4882a593Smuzhiyun		};
402*4882a593Smuzhiyun	};
403*4882a593Smuzhiyun};
404*4882a593Smuzhiyun
405*4882a593Smuzhiyun&rockchip_suspend {
406*4882a593Smuzhiyun	status = "disabled";
407*4882a593Smuzhiyun};
408*4882a593Smuzhiyun
409*4882a593Smuzhiyun&rknpu {
410*4882a593Smuzhiyun	status = "okay";
411*4882a593Smuzhiyun};
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun&rknpu_mmu {
414*4882a593Smuzhiyun	status = "okay";
415*4882a593Smuzhiyun};
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun&sdio_pwrseq {
418*4882a593Smuzhiyun	compatible = "mmc-pwrseq-simple";
419*4882a593Smuzhiyun	clocks = <&rk809 1>;
420*4882a593Smuzhiyun	clock-names = "ext_clock";
421*4882a593Smuzhiyun	pinctrl-names = "default";
422*4882a593Smuzhiyun	pinctrl-0 = <&wifi_enable_h>;
423*4882a593Smuzhiyun
424*4882a593Smuzhiyun	/*
425*4882a593Smuzhiyun	 * On the module itself this is one of these (depending
426*4882a593Smuzhiyun	 * on the actual card populated):
427*4882a593Smuzhiyun	 * - SDIO_RESET_L_WL_REG_ON
428*4882a593Smuzhiyun	 * - PDN (power down when low)
429*4882a593Smuzhiyun	 */
430*4882a593Smuzhiyun	reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
431*4882a593Smuzhiyun	post-power-on-delay-ms = <200>;
432*4882a593Smuzhiyun	status = "okay";
433*4882a593Smuzhiyun};
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun&sdmmc1 {
436*4882a593Smuzhiyun	status = "disabled";
437*4882a593Smuzhiyun};
438*4882a593Smuzhiyun
439*4882a593Smuzhiyun&sdmmc2 {
440*4882a593Smuzhiyun	max-frequency = <150000000>;
441*4882a593Smuzhiyun	supports-sdio;
442*4882a593Smuzhiyun	bus-width = <4>;
443*4882a593Smuzhiyun	disable-wp;
444*4882a593Smuzhiyun	cap-sd-highspeed;
445*4882a593Smuzhiyun	cap-sdio-irq;
446*4882a593Smuzhiyun	keep-power-in-suspend;
447*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
448*4882a593Smuzhiyun	non-removable;
449*4882a593Smuzhiyun	pinctrl-names = "default";
450*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
451*4882a593Smuzhiyun	sd-uhs-sdr104;
452*4882a593Smuzhiyun	status = "okay";
453*4882a593Smuzhiyun};
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun&uart1 {
456*4882a593Smuzhiyun	status = "okay";
457*4882a593Smuzhiyun	pinctrl-names = "default";
458*4882a593Smuzhiyun	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
459*4882a593Smuzhiyun};
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun&video_phy0 {
462*4882a593Smuzhiyun	status = "okay";
463*4882a593Smuzhiyun};
464*4882a593Smuzhiyun
465*4882a593Smuzhiyun&video_phy1 {
466*4882a593Smuzhiyun	status = "disabled";
467*4882a593Smuzhiyun};
468*4882a593Smuzhiyun
469*4882a593Smuzhiyun&wireless_wlan {
470*4882a593Smuzhiyun	pinctrl-names = "default";
471*4882a593Smuzhiyun	pinctrl-0 = <&wifi_host_wake_irq>;
472*4882a593Smuzhiyun	WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
473*4882a593Smuzhiyun};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun&wireless_bluetooth {
476*4882a593Smuzhiyun	compatible = "bluetooth-platdata";
477*4882a593Smuzhiyun	clocks = <&rk809 1>;
478*4882a593Smuzhiyun	clock-names = "ext_clock";
479*4882a593Smuzhiyun	//wifi-bt-power-toggle;
480*4882a593Smuzhiyun	uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
481*4882a593Smuzhiyun	pinctrl-names = "default", "rts_gpio";
482*4882a593Smuzhiyun	pinctrl-0 = <&uart1m0_rtsn>;
483*4882a593Smuzhiyun	pinctrl-1 = <&uart1_pin>;
484*4882a593Smuzhiyun	BT,reset_gpio    = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
485*4882a593Smuzhiyun	BT,wake_gpio     = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
486*4882a593Smuzhiyun	BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
487*4882a593Smuzhiyun	status = "okay";
488*4882a593Smuzhiyun};
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun&pinctrl {
491*4882a593Smuzhiyun	cam {
492*4882a593Smuzhiyun		camera_pwr: camera-pwr {
493*4882a593Smuzhiyun			rockchip,pins =
494*4882a593Smuzhiyun				/* camera power en */
495*4882a593Smuzhiyun				<0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
496*4882a593Smuzhiyun		};
497*4882a593Smuzhiyun	};
498*4882a593Smuzhiyun
499*4882a593Smuzhiyun	headphone {
500*4882a593Smuzhiyun		hp_det: hp-det {
501*4882a593Smuzhiyun			rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
502*4882a593Smuzhiyun		};
503*4882a593Smuzhiyun	};
504*4882a593Smuzhiyun
505*4882a593Smuzhiyun	i2s1 {
506*4882a593Smuzhiyun		/omit-if-no-ref/
507*4882a593Smuzhiyun		i2s1m0_lrckrx: i2s1m0-lrckrx {
508*4882a593Smuzhiyun			rockchip,pins =
509*4882a593Smuzhiyun				/* i2s1m0_lrckrx */
510*4882a593Smuzhiyun				<1 RK_PA6 1 &pcfg_pull_up_drv_level_4>;
511*4882a593Smuzhiyun		};
512*4882a593Smuzhiyun		/omit-if-no-ref/
513*4882a593Smuzhiyun		i2s1m0_lrcktx: i2s1m0-lrcktx {
514*4882a593Smuzhiyun			rockchip,pins =
515*4882a593Smuzhiyun				/* i2s1m0_lrcktx */
516*4882a593Smuzhiyun				<1 RK_PA5 1 &pcfg_pull_up_drv_level_4>;
517*4882a593Smuzhiyun		};
518*4882a593Smuzhiyun		/omit-if-no-ref/
519*4882a593Smuzhiyun		i2s1m0_mclk: i2s1m0-mclk {
520*4882a593Smuzhiyun			rockchip,pins =
521*4882a593Smuzhiyun				/* i2s1m0_mclk */
522*4882a593Smuzhiyun				<1 RK_PA2 1 &pcfg_pull_up_drv_level_4>;
523*4882a593Smuzhiyun		};
524*4882a593Smuzhiyun		/omit-if-no-ref/
525*4882a593Smuzhiyun		i2s1m0_sclkrx: i2s1m0-sclkrx {
526*4882a593Smuzhiyun			rockchip,pins =
527*4882a593Smuzhiyun				/* i2s1m0_sclkrx */
528*4882a593Smuzhiyun				<1 RK_PA4 1 &pcfg_pull_up_drv_level_4>;
529*4882a593Smuzhiyun		};
530*4882a593Smuzhiyun		/omit-if-no-ref/
531*4882a593Smuzhiyun		i2s1m0_sclktx: i2s1m0-sclktx {
532*4882a593Smuzhiyun			rockchip,pins =
533*4882a593Smuzhiyun				/* i2s1m0_sclktx */
534*4882a593Smuzhiyun				<1 RK_PA3 1 &pcfg_pull_up_drv_level_4>;
535*4882a593Smuzhiyun		};
536*4882a593Smuzhiyun		/omit-if-no-ref/
537*4882a593Smuzhiyun		i2s1m0_sdi0: i2s1m0-sdi0 {
538*4882a593Smuzhiyun			rockchip,pins =
539*4882a593Smuzhiyun				/* i2s1m0_sdi0 */
540*4882a593Smuzhiyun				<1 RK_PB3 1 &pcfg_pull_up_drv_level_4>;
541*4882a593Smuzhiyun		};
542*4882a593Smuzhiyun		/omit-if-no-ref/
543*4882a593Smuzhiyun		i2s1m0_sdi1: i2s1m0-sdi1 {
544*4882a593Smuzhiyun			rockchip,pins =
545*4882a593Smuzhiyun				/* i2s1m0_sdi1 */
546*4882a593Smuzhiyun				<1 RK_PB2 2 &pcfg_pull_up_drv_level_4>;
547*4882a593Smuzhiyun		};
548*4882a593Smuzhiyun		/omit-if-no-ref/
549*4882a593Smuzhiyun		i2s1m0_sdi2: i2s1m0-sdi2 {
550*4882a593Smuzhiyun			rockchip,pins =
551*4882a593Smuzhiyun				/* i2s1m0_sdi2 */
552*4882a593Smuzhiyun				<1 RK_PB1 2 &pcfg_pull_up_drv_level_4>;
553*4882a593Smuzhiyun		};
554*4882a593Smuzhiyun		/omit-if-no-ref/
555*4882a593Smuzhiyun		i2s1m0_sdi3: i2s1m0-sdi3 {
556*4882a593Smuzhiyun			rockchip,pins =
557*4882a593Smuzhiyun				/* i2s1m0_sdi3 */
558*4882a593Smuzhiyun				<1 RK_PB0 2 &pcfg_pull_up_drv_level_4>;
559*4882a593Smuzhiyun		};
560*4882a593Smuzhiyun		/omit-if-no-ref/
561*4882a593Smuzhiyun		i2s1m0_sdo0: i2s1m0-sdo0 {
562*4882a593Smuzhiyun			rockchip,pins =
563*4882a593Smuzhiyun				/* i2s1m0_sdo0 */
564*4882a593Smuzhiyun				<1 RK_PA7 1 &pcfg_pull_up_drv_level_4>;
565*4882a593Smuzhiyun		};
566*4882a593Smuzhiyun	};
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun	rtc {
569*4882a593Smuzhiyun		rtc_int: rtc-int {
570*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
571*4882a593Smuzhiyun		};
572*4882a593Smuzhiyun	};
573*4882a593Smuzhiyun
574*4882a593Smuzhiyun	rtl8111 {
575*4882a593Smuzhiyun		rtl8111_isolate: rtl8111-isolate {
576*4882a593Smuzhiyun			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
577*4882a593Smuzhiyun		};
578*4882a593Smuzhiyun	};
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun	sdio-pwrseq {
581*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
582*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
583*4882a593Smuzhiyun		};
584*4882a593Smuzhiyun	};
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun	usb {
587*4882a593Smuzhiyun		vcc5v0_host_en: vcc5v0-host-en {
588*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
589*4882a593Smuzhiyun		};
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun		vcc5v0_otg_en: vcc5v0-otg-en {
592*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
593*4882a593Smuzhiyun		};
594*4882a593Smuzhiyun	};
595*4882a593Smuzhiyun
596*4882a593Smuzhiyun	wireless-wlan {
597*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
598*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>;
599*4882a593Smuzhiyun		};
600*4882a593Smuzhiyun	};
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun	wireless-bluetooth {
603*4882a593Smuzhiyun		uart1_pin: uart1-pin {
604*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
605*4882a593Smuzhiyun		};
606*4882a593Smuzhiyun	};
607*4882a593Smuzhiyun};
608