1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2023 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include "rk3568.dtsi" 10#include "rk3568-toybrick.dtsi" 11 12/delete-node/ &adc_keys; 13 14/ { 15 compatible = "rockchip,rk3568-toybrick-sd0", "rockchip,rk3568"; 16 17 bt-sound { 18 status = "okay"; 19 compatible = "simple-audio-card"; 20 simple-audio-card,format = "dsp_a"; 21 simple-audio-card,bitclock-inversion = <1>; 22 simple-audio-card,mclk-fs = <512>; 23 simple-audio-card,name = "rockchip,bt"; 24 #simple-audio-card,bitclock-master = <&sound2_master>; 25 #simple-audio-card,frame-master = <&sound2_master>; 26 simple-audio-card,cpu { 27 sound-dai = <&i2s2_2ch>; 28 }; 29 sound2_master:simple-audio-card,codec { 30 #sound-dai-cells = <0>; 31 sound-dai = <&bt_sco>; 32 }; 33 }; 34 pcie30_avdd0v9: pcie30-avdd0v9 { 35 compatible = "regulator-fixed"; 36 regulator-name = "pcie30_avdd0v9"; 37 regulator-always-on; 38 regulator-boot-on; 39 regulator-min-microvolt = <900000>; 40 regulator-max-microvolt = <900000>; 41 vin-supply = <&vcc3v3_sys>; 42 }; 43 44 pcie30_avdd1v8: pcie30-avdd1v8 { 45 compatible = "regulator-fixed"; 46 regulator-name = "pcie30_avdd1v8"; 47 regulator-always-on; 48 regulator-boot-on; 49 regulator-min-microvolt = <1800000>; 50 regulator-max-microvolt = <1800000>; 51 vin-supply = <&vcc3v3_sys>; 52 }; 53 54 pcie30_3v3: gpio-regulator { 55 compatible = "regulator-gpio"; 56 regulator-name = "pcie30_3v3"; 57 regulator-min-microvolt = <100000>; 58 regulator-max-microvolt = <3300000>; 59 gpios = <&gpio2 RK_PD7 GPIO_ACTIVE_HIGH>; 60 gpios-states = <0x1>; 61 states = <100000 0x0 62 3300000 0x1>; 63 }; 64 65 rk_headset: rk-headset { 66 compatible = "rockchip_headset"; 67 headset_gpio = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; 68 pinctrl-names = "default"; 69 pinctrl-0 = <&hp_det>; 70 io-channels = <&saradc 2>; 71 }; 72 73 vcc2v5_sys: vcc2v5-ddr { 74 compatible = "regulator-fixed"; 75 regulator-name = "vcc2v5-sys"; 76 regulator-always-on; 77 regulator-boot-on; 78 regulator-min-microvolt = <2500000>; 79 regulator-max-microvolt = <2500000>; 80 vin-supply = <&vcc3v3_sys>; 81 }; 82 83 vcc3v3_pcie: gpio-regulator { 84 compatible = "regulator-fixed"; 85 regulator-name = "vcc3v3_pcie"; 86 regulator-min-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>; 88 enable-active-high; 89 startup-delay-us = <5000>; 90 vin-supply = <&vcc5v0_sys>; 91 }; 92 93 vcc3v3_bu: vcc3v3-bu { 94 compatible = "regulator-fixed"; 95 regulator-name = "vcc3v3_bu"; 96 regulator-always-on; 97 regulator-boot-on; 98 regulator-min-microvolt = <3300000>; 99 regulator-max-microvolt = <3300000>; 100 vin-supply = <&vcc5v0_sys>; 101 }; 102 103 vcc_camera: vcc-camera-regulator { 104 compatible = "regulator-fixed"; 105 gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&camera_pwr>; 108 regulator-name = "vcc_camera"; 109 enable-active-high; 110 regulator-always-on; 111 regulator-boot-on; 112 }; 113 114 vcc5v0_host: vcc5v0-host-regulator { 115 compatible = "regulator-fixed"; 116 enable-active-high; 117 gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; 118 pinctrl-names = "default"; 119 pinctrl-0 = <&vcc5v0_host_en>; 120 regulator-name = "vcc5v0_host"; 121 regulator-always-on; 122 }; 123 124 vcc5v0_otg: vcc5v0-otg-regulator { 125 compatible = "regulator-fixed"; 126 enable-active-high; 127 gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>; 128 pinctrl-names = "default"; 129 pinctrl-0 = <&vcc5v0_otg_en>; 130 regulator-name = "vcc5v0_otg"; 131 }; 132}; 133 134&bus_npu { 135 status = "okay"; 136}; 137 138&combphy0_us { 139 status = "okay"; 140}; 141 142&combphy1_usq { 143 status = "okay"; 144}; 145 146&combphy2_psq { 147 status = "okay"; 148}; 149 150&csi2_dphy_hw { 151 status = "okay"; 152}; 153 154&csi2_dphy0 { 155 status = "okay"; 156 157 ports { 158 #address-cells = <1>; 159 #size-cells = <0>; 160 port@0 { 161 reg = <0>; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 165 mipi_in_ucam0: endpoint@1 { 166 reg = <1>; 167 remote-endpoint = <&imx415_out>; 168 data-lanes = <1 2 3 4>; 169 }; 170 mipi_in_ucam1: endpoint@2 { 171 reg = <2>; 172 remote-endpoint = <&ov50c40_out>; 173 data-lanes = <1 2 3 4>; 174 }; 175 }; 176 port@1 { 177 reg = <1>; 178 #address-cells = <1>; 179 #size-cells = <0>; 180 181 csidphy_out: endpoint@0 { 182 reg = <0>; 183 remote-endpoint = <&isp0_in>; 184 }; 185 }; 186 }; 187}; 188 189&gmac1 { 190 phy-mode = "rgmii"; 191 clock_in_out = "output"; 192 193 snps,reset-gpio = <&gpio2 RK_PD1 GPIO_ACTIVE_LOW>; 194 snps,reset-active-low; 195 /* Reset time is 20ms, 100ms for rtl8211f */ 196 snps,reset-delays-us = <0 20000 100000>; 197 198 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>, <&cru CLK_MAC1_OUT>; 199 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>; 200 assigned-clock-rates = <0>, <125000000>, <25000000>; 201 202 pinctrl-names = "default"; 203 pinctrl-0 = <&gmac1m1_miim 204 &gmac1m1_tx_bus2 205 &gmac1m1_rx_bus2 206 &gmac1m1_rgmii_clk 207 &gmac1m1_rgmii_bus 208 ð1m1_pins>; 209 210 tx_delay = <0x47>; 211 rx_delay = <0x28>; 212 213 phy-handle = <&rgmii_phy1>; 214 status = "okay"; 215}; 216 217&i2s2_2ch { 218 status = "okay"; 219 #sound-dai-cells = <0>; 220}; 221 222&i2c0 { 223 status = "okay"; 224 rk809: pmic@20 { 225 compatible = "rockchip,rk809"; 226 reg = <0x20>; 227 regulators { 228 vccio_acodec: LDO_REG4 { 229 regulator-always-on; 230 regulator-boot-on; 231 regulator-min-microvolt = <3300000>; 232 regulator-max-microvolt = <3300000>; 233 regulator-name = "vccio_acodec"; 234 regulator-state-mem { 235 regulator-off-in-suspend; 236 }; 237 }; 238 }; 239 }; 240}; 241 242&i2s1_8ch { 243 status = "okay"; 244 #sound-dai-cells = <0>; 245 rockchip,clk-trcm = <1>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&i2s1m0_sclktx 248 &i2s1m0_lrcktx 249 &i2s1m0_sdo0 250 &i2s1m0_sdi0>; 251}; 252 253&i2c5 { 254 status = "okay"; 255 hym8563: hym8563@51 { 256 compatible = "haoyu,hym8563"; 257 reg = <0x51>; 258 #clock-cells = <0>; 259 clock-frequency = <32768>; 260 clock-output-names = "hym8563"; 261 pinctrl-names = "default"; 262 pinctrl-0 = <&rtc_int>; 263 interrupt-parent = <&gpio0>; 264 interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>; 265 }; 266}; 267 268&i2c2 { 269 status = "okay"; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&i2c2m1_xfer>; 272 imx415: imx415@1a { 273 compatible = "sony,imx415"; 274 reg = <0x1a>; 275 clocks = <&cru CLK_CIF_OUT>; 276 clock-names = "xvclk"; 277 power-domains = <&power RK3568_PD_VI>; 278 pinctrl-names = "default"; 279 pinctrl-0 = <&cif_clk>; 280 // must be high at last 281 power-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 282 // must be high at last do at vcc_camera 283 //reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>; 284 rockchip,camera-module-index = <0>; 285 rockchip,camera-module-facing = "back"; 286 rockchip,camera-module-name = "CMK-OT2022-PX1"; 287 rockchip,camera-module-lens-name = "IR0147-50IRC-8M-F20-RK3568"; 288 //lens-focus = <&cam_ircut0>; 289 port { 290 imx415_out: endpoint { 291 remote-endpoint = <&mipi_in_ucam0>; 292 data-lanes = <1 2 3 4>; 293 }; 294 }; 295 }; 296 297 aw8601: aw8601@c { 298 compatible = "awinic,aw8601"; 299 status = "okay"; 300 reg = <0x0c>; 301 rockchip,vcm-start-current = <56>; 302 rockchip,vcm-rated-current = <96>; 303 rockchip,vcm-step-mode = <4>; 304 rockchip,camera-module-index = <0>; 305 rockchip,camera-module-facing = "back"; 306 }; 307 308 otp_eeprom: otp_eeprom@50 { 309 compatible = "rk,otp_eeprom"; 310 status = "okay"; 311 reg = <0x50>; 312 }; 313 314 ov50c40: ov50c40@36 { 315 compatible = "ovti,ov50c40"; 316 reg = <0x36>; 317 clocks = <&cru CLK_CIF_OUT>; 318 clock-names = "xvclk"; 319 power-domains = <&power RK3568_PD_VI>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&cif_clk>; 322 pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>;// must be high at last 323 reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_LOW>;// must be high at last 324 rockchip,camera-module-index = <0>; 325 rockchip,camera-module-facing = "back"; 326 rockchip,camera-module-name = "HZGA06"; 327 rockchip,camera-module-lens-name = "ZE0082C1-RK3568"; 328 eeprom-ctrl = <&otp_eeprom>; 329 lens-focus = <&aw8601>; 330 port { 331 ov50c40_out: endpoint { 332 remote-endpoint = <&mipi_in_ucam1>; 333 data-lanes = <1 2 3 4>; 334 }; 335 }; 336 }; 337}; 338 339&leds { 340 status = "okay"; 341 compatible = "gpio-leds"; 342 work_led: work { 343 gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 344 linux,default-trigger = "heartbeat"; 345 }; 346}; 347 348&mdio1 { 349 rgmii_phy1: phy@0 { 350 compatible = "ethernet-phy-ieee802.3-c22"; 351 reg = <0x0>; 352 clocks = <&cru CLK_MAC1_OUT>; 353 }; 354}; 355 356&pcie2x1 { 357 reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 358 pinctrl-names = "default"; 359 pinctrl-0 = <&rtl8111_isolate>; 360 status = "okay"; 361}; 362 363&pcie30phy { 364 status = "okay"; 365}; 366 367&pcie3x2 { 368 reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>; 369 vpcie3v3-supply = <&pcie30_3v3>; 370 status = "okay"; 371}; 372 373&reserved_memory { 374 linux,cma { 375 compatible = "shared-dma-pool"; 376 inactive; 377 reusable; 378 reg = <0x0 0x10000000 0x0 0x08000000>; 379 linux,cma-default; 380 }; 381}; 382 383&rkisp { 384 status = "okay"; 385}; 386 387&rkisp_mmu { 388 status = "okay"; 389}; 390 391&rkisp_vir0 { 392 status = "okay"; 393 394 port { 395 #address-cells = <1>; 396 #size-cells = <0>; 397 398 isp0_in: endpoint@0 { 399 reg = <0>; 400 remote-endpoint = <&csidphy_out>; 401 }; 402 }; 403}; 404 405&rockchip_suspend { 406 status = "disabled"; 407}; 408 409&rknpu { 410 status = "okay"; 411}; 412 413&rknpu_mmu { 414 status = "okay"; 415}; 416 417&sdio_pwrseq { 418 compatible = "mmc-pwrseq-simple"; 419 clocks = <&rk809 1>; 420 clock-names = "ext_clock"; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&wifi_enable_h>; 423 424 /* 425 * On the module itself this is one of these (depending 426 * on the actual card populated): 427 * - SDIO_RESET_L_WL_REG_ON 428 * - PDN (power down when low) 429 */ 430 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 431 post-power-on-delay-ms = <200>; 432 status = "okay"; 433}; 434 435&sdmmc1 { 436 status = "disabled"; 437}; 438 439&sdmmc2 { 440 max-frequency = <150000000>; 441 supports-sdio; 442 bus-width = <4>; 443 disable-wp; 444 cap-sd-highspeed; 445 cap-sdio-irq; 446 keep-power-in-suspend; 447 mmc-pwrseq = <&sdio_pwrseq>; 448 non-removable; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; 451 sd-uhs-sdr104; 452 status = "okay"; 453}; 454 455&uart1 { 456 status = "okay"; 457 pinctrl-names = "default"; 458 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; 459}; 460 461&video_phy0 { 462 status = "okay"; 463}; 464 465&video_phy1 { 466 status = "disabled"; 467}; 468 469&wireless_wlan { 470 pinctrl-names = "default"; 471 pinctrl-0 = <&wifi_host_wake_irq>; 472 WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; 473}; 474 475&wireless_bluetooth { 476 compatible = "bluetooth-platdata"; 477 clocks = <&rk809 1>; 478 clock-names = "ext_clock"; 479 //wifi-bt-power-toggle; 480 uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 481 pinctrl-names = "default", "rts_gpio"; 482 pinctrl-0 = <&uart1m0_rtsn>; 483 pinctrl-1 = <&uart1_pin>; 484 BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 485 BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 486 BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; 487 status = "okay"; 488}; 489 490&pinctrl { 491 cam { 492 camera_pwr: camera-pwr { 493 rockchip,pins = 494 /* camera power en */ 495 <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; 496 }; 497 }; 498 499 headphone { 500 hp_det: hp-det { 501 rockchip,pins = <4 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>; 502 }; 503 }; 504 505 i2s1 { 506 /omit-if-no-ref/ 507 i2s1m0_lrckrx: i2s1m0-lrckrx { 508 rockchip,pins = 509 /* i2s1m0_lrckrx */ 510 <1 RK_PA6 1 &pcfg_pull_up_drv_level_4>; 511 }; 512 /omit-if-no-ref/ 513 i2s1m0_lrcktx: i2s1m0-lrcktx { 514 rockchip,pins = 515 /* i2s1m0_lrcktx */ 516 <1 RK_PA5 1 &pcfg_pull_up_drv_level_4>; 517 }; 518 /omit-if-no-ref/ 519 i2s1m0_mclk: i2s1m0-mclk { 520 rockchip,pins = 521 /* i2s1m0_mclk */ 522 <1 RK_PA2 1 &pcfg_pull_up_drv_level_4>; 523 }; 524 /omit-if-no-ref/ 525 i2s1m0_sclkrx: i2s1m0-sclkrx { 526 rockchip,pins = 527 /* i2s1m0_sclkrx */ 528 <1 RK_PA4 1 &pcfg_pull_up_drv_level_4>; 529 }; 530 /omit-if-no-ref/ 531 i2s1m0_sclktx: i2s1m0-sclktx { 532 rockchip,pins = 533 /* i2s1m0_sclktx */ 534 <1 RK_PA3 1 &pcfg_pull_up_drv_level_4>; 535 }; 536 /omit-if-no-ref/ 537 i2s1m0_sdi0: i2s1m0-sdi0 { 538 rockchip,pins = 539 /* i2s1m0_sdi0 */ 540 <1 RK_PB3 1 &pcfg_pull_up_drv_level_4>; 541 }; 542 /omit-if-no-ref/ 543 i2s1m0_sdi1: i2s1m0-sdi1 { 544 rockchip,pins = 545 /* i2s1m0_sdi1 */ 546 <1 RK_PB2 2 &pcfg_pull_up_drv_level_4>; 547 }; 548 /omit-if-no-ref/ 549 i2s1m0_sdi2: i2s1m0-sdi2 { 550 rockchip,pins = 551 /* i2s1m0_sdi2 */ 552 <1 RK_PB1 2 &pcfg_pull_up_drv_level_4>; 553 }; 554 /omit-if-no-ref/ 555 i2s1m0_sdi3: i2s1m0-sdi3 { 556 rockchip,pins = 557 /* i2s1m0_sdi3 */ 558 <1 RK_PB0 2 &pcfg_pull_up_drv_level_4>; 559 }; 560 /omit-if-no-ref/ 561 i2s1m0_sdo0: i2s1m0-sdo0 { 562 rockchip,pins = 563 /* i2s1m0_sdo0 */ 564 <1 RK_PA7 1 &pcfg_pull_up_drv_level_4>; 565 }; 566 }; 567 568 rtc { 569 rtc_int: rtc-int { 570 rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>; 571 }; 572 }; 573 574 rtl8111 { 575 rtl8111_isolate: rtl8111-isolate { 576 rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>; 577 }; 578 }; 579 580 sdio-pwrseq { 581 wifi_enable_h: wifi-enable-h { 582 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 583 }; 584 }; 585 586 usb { 587 vcc5v0_host_en: vcc5v0-host-en { 588 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>; 589 }; 590 591 vcc5v0_otg_en: vcc5v0-otg-en { 592 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; 593 }; 594 }; 595 596 wireless-wlan { 597 wifi_host_wake_irq: wifi-host-wake-irq { 598 rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 599 }; 600 }; 601 602 wireless-bluetooth { 603 uart1_pin: uart1-pin { 604 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 605 }; 606 }; 607}; 608