xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3566-rk817-eink-w6.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h>
10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h>
11*4882a593Smuzhiyun#include <dt-bindings/input/rk-input.h>
12*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
13*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h>
14*4882a593Smuzhiyun#include "rk3566.dtsi"
15*4882a593Smuzhiyun#include "rk3568-android.dtsi"
16*4882a593Smuzhiyun#include "rk3566-eink.dtsi"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun/ {
19*4882a593Smuzhiyun	model = "Rockchip RK3566 RK817 EINK W6 LP4X Board";
20*4882a593Smuzhiyun	compatible = "rockchip,rk3566-rk817-eink-W6", "rockchip,rk3566";
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun	charge-animation {
23*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
24*4882a593Smuzhiyun		rockchip,uboot-charge-on = <1>;
25*4882a593Smuzhiyun		rockchip,android-charge-on = <0>;
26*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <3350>;
27*4882a593Smuzhiyun		rockchip,screen-on-voltage = <3400>;
28*4882a593Smuzhiyun		rockchip,auto-wakeup-interval = <60>;
29*4882a593Smuzhiyun		status = "okay";
30*4882a593Smuzhiyun	};
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun	adc_keys: adc-keys {
33*4882a593Smuzhiyun		status = "disabled";
34*4882a593Smuzhiyun		compatible = "adc-keys";
35*4882a593Smuzhiyun		io-channels = <&saradc 0>;
36*4882a593Smuzhiyun		io-channel-names = "buttons";
37*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
38*4882a593Smuzhiyun		poll-interval = <100>;
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun		vol-up-key {
41*4882a593Smuzhiyun			label = "volume up";
42*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
43*4882a593Smuzhiyun			press-threshold-microvolt = <1750>;
44*4882a593Smuzhiyun		};
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	hdmi_sound: hdmi-sound {
48*4882a593Smuzhiyun		compatible = "simple-audio-card";
49*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
50*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <128>;
51*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,hdmi";
52*4882a593Smuzhiyun		status = "disabled";
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun		simple-audio-card,cpu {
55*4882a593Smuzhiyun			sound-dai = <&i2s0_8ch>;
56*4882a593Smuzhiyun		};
57*4882a593Smuzhiyun		simple-audio-card,codec {
58*4882a593Smuzhiyun			sound-dai = <&hdmi>;
59*4882a593Smuzhiyun		};
60*4882a593Smuzhiyun	};
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun	leds: gpio-leds {
63*4882a593Smuzhiyun		compatible = "gpio-leds";
64*4882a593Smuzhiyun		pinctrl-names = "default";
65*4882a593Smuzhiyun		pinctrl-0 =<&leds_gpio>;
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun		led@1 {
68*4882a593Smuzhiyun			gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
69*4882a593Smuzhiyun			linux,default-trigger = "battery-full";
70*4882a593Smuzhiyun			label = "battery_full";
71*4882a593Smuzhiyun			retain-state-suspended;
72*4882a593Smuzhiyun		};
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun		led@2 {
75*4882a593Smuzhiyun			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
76*4882a593Smuzhiyun			linux,default-trigger = "battery-charging";
77*4882a593Smuzhiyun			label = "battery_charging";
78*4882a593Smuzhiyun			retain-state-suspended;
79*4882a593Smuzhiyun		};
80*4882a593Smuzhiyun	};
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun	vccsys: vccsys {
83*4882a593Smuzhiyun		compatible = "regulator-fixed";
84*4882a593Smuzhiyun		regulator-name = "vcc3v8_sys";
85*4882a593Smuzhiyun		regulator-always-on;
86*4882a593Smuzhiyun		regulator-boot-on;
87*4882a593Smuzhiyun		regulator-min-microvolt = <3800000>;
88*4882a593Smuzhiyun		regulator-max-microvolt = <3800000>;
89*4882a593Smuzhiyun	};
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun	vcc_camera: vcc-camera-regulator {
92*4882a593Smuzhiyun		compatible = "regulator-fixed";
93*4882a593Smuzhiyun		gpio = <&gpio4 RK_PC3 GPIO_ACTIVE_HIGH>;
94*4882a593Smuzhiyun		pinctrl-names = "default";
95*4882a593Smuzhiyun		pinctrl-0 = <&camera_rst>;
96*4882a593Smuzhiyun		regulator-name = "vcc_camera";
97*4882a593Smuzhiyun		enable-active-high;
98*4882a593Smuzhiyun		regulator-always-on;
99*4882a593Smuzhiyun		regulator-boot-on;
100*4882a593Smuzhiyun	};
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun	vcc_tp: vcc-tp-regulator {
103*4882a593Smuzhiyun		compatible = "regulator-fixed";
104*4882a593Smuzhiyun		enable-active-high;
105*4882a593Smuzhiyun		gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
106*4882a593Smuzhiyun		pinctrl-names = "default";
107*4882a593Smuzhiyun		pinctrl-0 = <&vcc_tp_en>;
108*4882a593Smuzhiyun		regulator-name = "vcc_tp";
109*4882a593Smuzhiyun	};
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun	dummy_codec: dummy-codec {
112*4882a593Smuzhiyun		compatible = "rockchip,dummy-codec";
113*4882a593Smuzhiyun		#sound-dai-cells = <0>;
114*4882a593Smuzhiyun	};
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun	mic_sound: mic-sound {
117*4882a593Smuzhiyun		compatible = "simple-audio-card";
118*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,rk-mic-sound";
119*4882a593Smuzhiyun		simple-audio-card,cpu {
120*4882a593Smuzhiyun			sound-dai = <&i2s1_8ch>;
121*4882a593Smuzhiyun		};
122*4882a593Smuzhiyun		simple-audio-card,codec {
123*4882a593Smuzhiyun			sound-dai = <&dummy_codec>;
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun	};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
128*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
129*4882a593Smuzhiyun		clocks = <&rk817 1>;
130*4882a593Smuzhiyun		clock-names = "ext_clock";
131*4882a593Smuzhiyun		pinctrl-names = "default";
132*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun		/*
135*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
136*4882a593Smuzhiyun		 * on the actual card populated):
137*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
138*4882a593Smuzhiyun		 * - PDN (power down when low)
139*4882a593Smuzhiyun		 */
140*4882a593Smuzhiyun		post-power-on-delay-ms = <200>;
141*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_LOW>;
142*4882a593Smuzhiyun	};
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun	wireless-wlan {
145*4882a593Smuzhiyun		compatible = "wlan-platdata";
146*4882a593Smuzhiyun		rockchip,grf = <&grf>;
147*4882a593Smuzhiyun		wifi_chip_type = "ap6255";
148*4882a593Smuzhiyun		pinctrl-names = "default";
149*4882a593Smuzhiyun		pinctrl-0 = <&wifi_vbat &wifi_host_wake_irq>;
150*4882a593Smuzhiyun		WIFI,vbat_gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
151*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
152*4882a593Smuzhiyun		status = "okay";
153*4882a593Smuzhiyun	};
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun	wireless-bluetooth {
156*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
157*4882a593Smuzhiyun		clocks = <&rk817 1>;
158*4882a593Smuzhiyun		clock-names = "ext_clock";
159*4882a593Smuzhiyun		wifi-bt-power-toggle;
160*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>;
161*4882a593Smuzhiyun		pinctrl-names = "default", "rts_gpio";
162*4882a593Smuzhiyun		pinctrl-0 = <&uart1m0_rtsn>;
163*4882a593Smuzhiyun		pinctrl-1 = <&uart1_gpios>;
164*4882a593Smuzhiyun		BT,reset_gpio    = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
165*4882a593Smuzhiyun		BT,wake_gpio     = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
166*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
167*4882a593Smuzhiyun		status = "okay";
168*4882a593Smuzhiyun	};
169*4882a593Smuzhiyun};
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun&ebc {
172*4882a593Smuzhiyun	/* clock rate 1000M/n, (n=1~32) */
173*4882a593Smuzhiyun	assigned-clocks = <&cru CPLL_333M>, <&cru DCLK_EBC>;
174*4882a593Smuzhiyun	assigned-clock-rates = <85000000>, <85000000>;
175*4882a593Smuzhiyun	status = "okay";
176*4882a593Smuzhiyun};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun&ebc_dev {
179*4882a593Smuzhiyun	pmic = <&tps65185>;
180*4882a593Smuzhiyun	status = "okay";
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun	/* ED060XCD */
183*4882a593Smuzhiyun	panel,width = <1024>;
184*4882a593Smuzhiyun	panel,height = <758>;
185*4882a593Smuzhiyun	panel,vir_width = <1024>;
186*4882a593Smuzhiyun	panel,vir_height = <758>;
187*4882a593Smuzhiyun	panel,sdck = <20000000>;
188*4882a593Smuzhiyun	panel,lsl = <6>;
189*4882a593Smuzhiyun	panel,lbl = <6>;
190*4882a593Smuzhiyun	panel,ldl = <256>;
191*4882a593Smuzhiyun	panel,lel = <38>;
192*4882a593Smuzhiyun	panel,gdck-sta = <4>;
193*4882a593Smuzhiyun	panel,lgonl = <262>;
194*4882a593Smuzhiyun	panel,fsl = <2>;
195*4882a593Smuzhiyun	panel,fbl = <4>;
196*4882a593Smuzhiyun	panel,fdl = <758>;
197*4882a593Smuzhiyun	panel,fel = <5>;
198*4882a593Smuzhiyun	panel,mirror = <0>;
199*4882a593Smuzhiyun	panel,panel_16bit = <0>;
200*4882a593Smuzhiyun	panel,panel_color = <0>;
201*4882a593Smuzhiyun	panel,width-mm = <90>;
202*4882a593Smuzhiyun	panel,height-mm = <122>;
203*4882a593Smuzhiyun};
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun&cpu0 {
206*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
207*4882a593Smuzhiyun};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun&csi2_dphy_hw {
210*4882a593Smuzhiyun	status = "okay";
211*4882a593Smuzhiyun};
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun&csi2_dphy0 {
214*4882a593Smuzhiyun	status = "okay";
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun	ports {
217*4882a593Smuzhiyun		#address-cells = <1>;
218*4882a593Smuzhiyun		#size-cells = <0>;
219*4882a593Smuzhiyun		port@0 {
220*4882a593Smuzhiyun			reg = <0>;
221*4882a593Smuzhiyun			#address-cells = <1>;
222*4882a593Smuzhiyun			#size-cells = <0>;
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@0 {
225*4882a593Smuzhiyun				reg = <0>;
226*4882a593Smuzhiyun				remote-endpoint = <&ov5648_out>;
227*4882a593Smuzhiyun				data-lanes = <1 2>;
228*4882a593Smuzhiyun			};
229*4882a593Smuzhiyun		};
230*4882a593Smuzhiyun		port@1 {
231*4882a593Smuzhiyun			reg = <1>;
232*4882a593Smuzhiyun			#address-cells = <1>;
233*4882a593Smuzhiyun			#size-cells = <0>;
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun			csidphy0_out: endpoint@0 {
236*4882a593Smuzhiyun				reg = <0>;
237*4882a593Smuzhiyun				remote-endpoint = <&isp0_in>;
238*4882a593Smuzhiyun			};
239*4882a593Smuzhiyun		};
240*4882a593Smuzhiyun	};
241*4882a593Smuzhiyun};
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun&gpu {
244*4882a593Smuzhiyun	mali-supply = <&vdd_gpu>;
245*4882a593Smuzhiyun	status = "okay";
246*4882a593Smuzhiyun};
247*4882a593Smuzhiyun
248*4882a593Smuzhiyun&hdmi {
249*4882a593Smuzhiyun	status = "disabled";
250*4882a593Smuzhiyun};
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun&hdmi_in_vp0 {
253*4882a593Smuzhiyun	status = "disabled";
254*4882a593Smuzhiyun};
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun&hdmi_in_vp1 {
257*4882a593Smuzhiyun	status = "disabled";
258*4882a593Smuzhiyun};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun&hdmi_sound {
261*4882a593Smuzhiyun	status = "disabled";
262*4882a593Smuzhiyun};
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun&i2c0 {
265*4882a593Smuzhiyun	status = "okay";
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun	vdd_cpu: tcs4525@1c {
268*4882a593Smuzhiyun		compatible = "tcs,tcs4525";
269*4882a593Smuzhiyun		reg = <0x1c>;
270*4882a593Smuzhiyun		vin-supply = <&vccsys>;
271*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
272*4882a593Smuzhiyun		regulator-name = "vdd_cpu";
273*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
274*4882a593Smuzhiyun		regulator-max-microvolt = <1390000>;
275*4882a593Smuzhiyun		regulator-init-microvolt = <900000>;
276*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
277*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <0>;
278*4882a593Smuzhiyun		regulator-boot-on;
279*4882a593Smuzhiyun		regulator-always-on;
280*4882a593Smuzhiyun		regulator-initial-mode = <0x2>;
281*4882a593Smuzhiyun		regulator-state-mem {
282*4882a593Smuzhiyun			regulator-on-in-suspend;
283*4882a593Smuzhiyun			regulator-suspend-microvolt = <1100000>;
284*4882a593Smuzhiyun			regulator-changeable-in-suspend;
285*4882a593Smuzhiyun		};
286*4882a593Smuzhiyun	};
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun	rk817: pmic@20 {
289*4882a593Smuzhiyun		compatible = "rockchip,rk817";
290*4882a593Smuzhiyun		reg = <0x20>;
291*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
292*4882a593Smuzhiyun		interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
293*4882a593Smuzhiyun		pinctrl-names = "default";
294*4882a593Smuzhiyun//		pinctrl-names = "default", "pmic-sleep",
295*4882a593Smuzhiyun//				"pmic-power-off", "pmic-reset";
296*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
297*4882a593Smuzhiyun//		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
298*4882a593Smuzhiyun//		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
299*4882a593Smuzhiyun//		pinctrl-3 = <&soc_slppin_gpio>, <&rk817_slppin_rst>;
300*4882a593Smuzhiyun		rockchip,system-power-controller;
301*4882a593Smuzhiyun		wakeup-source;
302*4882a593Smuzhiyun		#clock-cells = <1>;
303*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
304*4882a593Smuzhiyun		//fb-inner-reg-idxs = <2>;
305*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
306*4882a593Smuzhiyun		pmic-reset-func = <0>;
307*4882a593Smuzhiyun		/* not save the PMIC_POWER_EN register in uboot */
308*4882a593Smuzhiyun		not-save-power-en = <1>;
309*4882a593Smuzhiyun		vcc1-supply = <&vccsys>;
310*4882a593Smuzhiyun		vcc2-supply = <&vccsys>;
311*4882a593Smuzhiyun		vcc3-supply = <&vccsys>;
312*4882a593Smuzhiyun		vcc4-supply = <&vccsys>;
313*4882a593Smuzhiyun		vcc5-supply = <&vccsys>;
314*4882a593Smuzhiyun		vcc6-supply = <&vccsys>;
315*4882a593Smuzhiyun		vcc7-supply = <&vccsys>;
316*4882a593Smuzhiyun		vcc8-supply = <&vccsys>;
317*4882a593Smuzhiyun		vcc9-supply = <&dcdc_boost>;
318*4882a593Smuzhiyun
319*4882a593Smuzhiyun		pwrkey {
320*4882a593Smuzhiyun			status = "okay";
321*4882a593Smuzhiyun		};
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
324*4882a593Smuzhiyun			gpio-controller;
325*4882a593Smuzhiyun			#gpio-cells = <2>;
326*4882a593Smuzhiyun
327*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
328*4882a593Smuzhiyun				pins = "gpio_slp";
329*4882a593Smuzhiyun				function = "pin_fun0";
330*4882a593Smuzhiyun			};
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
333*4882a593Smuzhiyun				pins = "gpio_slp";
334*4882a593Smuzhiyun				function = "pin_fun1";
335*4882a593Smuzhiyun			};
336*4882a593Smuzhiyun
337*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
338*4882a593Smuzhiyun				pins = "gpio_slp";
339*4882a593Smuzhiyun				function = "pin_fun2";
340*4882a593Smuzhiyun			};
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
343*4882a593Smuzhiyun				pins = "gpio_slp";
344*4882a593Smuzhiyun				function = "pin_fun3";
345*4882a593Smuzhiyun			};
346*4882a593Smuzhiyun		};
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun		regulators {
349*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
350*4882a593Smuzhiyun				regulator-always-on;
351*4882a593Smuzhiyun				regulator-boot-on;
352*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
353*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
354*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
355*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
356*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
357*4882a593Smuzhiyun				regulator-name = "vdd_logic";
358*4882a593Smuzhiyun				regulator-state-mem {
359*4882a593Smuzhiyun					regulator-off-in-suspend;
360*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
361*4882a593Smuzhiyun					regulator-changeable-in-suspend;
362*4882a593Smuzhiyun				};
363*4882a593Smuzhiyun			};
364*4882a593Smuzhiyun
365*4882a593Smuzhiyun			vdd_gpu: DCDC_REG2 {
366*4882a593Smuzhiyun				regulator-always-on;
367*4882a593Smuzhiyun				regulator-boot-on;
368*4882a593Smuzhiyun				regulator-min-microvolt = <500000>;
369*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
370*4882a593Smuzhiyun				regulator-init-microvolt = <900000>;
371*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
372*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
373*4882a593Smuzhiyun				regulator-name = "vdd_gpu";
374*4882a593Smuzhiyun					regulator-state-mem {
375*4882a593Smuzhiyun					regulator-off-in-suspend;
376*4882a593Smuzhiyun					regulator-changeable-in-suspend;
377*4882a593Smuzhiyun				};
378*4882a593Smuzhiyun			};
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
381*4882a593Smuzhiyun				regulator-always-on;
382*4882a593Smuzhiyun				regulator-boot-on;
383*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
384*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
385*4882a593Smuzhiyun				regulator-state-mem {
386*4882a593Smuzhiyun					regulator-on-in-suspend;
387*4882a593Smuzhiyun				};
388*4882a593Smuzhiyun			};
389*4882a593Smuzhiyun
390*4882a593Smuzhiyun			vcc_3v3: DCDC_REG4 {
391*4882a593Smuzhiyun				regulator-always-on;
392*4882a593Smuzhiyun				regulator-boot-on;
393*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
394*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
395*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
396*4882a593Smuzhiyun				regulator-name = "vcc_3v3";
397*4882a593Smuzhiyun				regulator-state-mem {
398*4882a593Smuzhiyun					regulator-off-in-suspend;
399*4882a593Smuzhiyun					regulator-changeable-in-suspend;
400*4882a593Smuzhiyun				};
401*4882a593Smuzhiyun			};
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun			vcca1v8_pmu: LDO_REG1 {
404*4882a593Smuzhiyun				regulator-always-on;
405*4882a593Smuzhiyun				regulator-boot-on;
406*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
407*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
408*4882a593Smuzhiyun				regulator-name = "vcca1v8_pmu";
409*4882a593Smuzhiyun				regulator-state-mem {
410*4882a593Smuzhiyun					regulator-on-in-suspend;
411*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
412*4882a593Smuzhiyun					regulator-changeable-in-suspend;
413*4882a593Smuzhiyun				};
414*4882a593Smuzhiyun			};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun			vdda_0v9: LDO_REG2 {
417*4882a593Smuzhiyun				regulator-always-on;
418*4882a593Smuzhiyun				regulator-boot-on;
419*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
420*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
421*4882a593Smuzhiyun				regulator-name = "vdda_0v9";
422*4882a593Smuzhiyun				regulator-state-mem {
423*4882a593Smuzhiyun					regulator-off-in-suspend;
424*4882a593Smuzhiyun					regulator-changeable-in-suspend;
425*4882a593Smuzhiyun				};
426*4882a593Smuzhiyun			};
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun			vdda0v9_pmu: LDO_REG3 {
429*4882a593Smuzhiyun				regulator-always-on;
430*4882a593Smuzhiyun				regulator-boot-on;
431*4882a593Smuzhiyun				regulator-min-microvolt = <900000>;
432*4882a593Smuzhiyun				regulator-max-microvolt = <900000>;
433*4882a593Smuzhiyun				regulator-name = "vdda0v9_pmu";
434*4882a593Smuzhiyun				regulator-state-mem {
435*4882a593Smuzhiyun					regulator-on-in-suspend;
436*4882a593Smuzhiyun					regulator-suspend-microvolt = <900000>;
437*4882a593Smuzhiyun					regulator-changeable-in-suspend;
438*4882a593Smuzhiyun				};
439*4882a593Smuzhiyun			};
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun			vccio_acodec: LDO_REG4 {
442*4882a593Smuzhiyun				regulator-always-on;
443*4882a593Smuzhiyun				regulator-boot-on;
444*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
445*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
446*4882a593Smuzhiyun				regulator-name = "vccio_acodec";
447*4882a593Smuzhiyun				regulator-state-mem {
448*4882a593Smuzhiyun					regulator-off-in-suspend;
449*4882a593Smuzhiyun					regulator-changeable-in-suspend;
450*4882a593Smuzhiyun				};
451*4882a593Smuzhiyun			};
452*4882a593Smuzhiyun
453*4882a593Smuzhiyun			vccio_sd: LDO_REG5 {
454*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
455*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
456*4882a593Smuzhiyun				regulator-name = "vccio_sd";
457*4882a593Smuzhiyun				regulator-state-mem {
458*4882a593Smuzhiyun					regulator-off-in-suspend;
459*4882a593Smuzhiyun					regulator-changeable-in-suspend;
460*4882a593Smuzhiyun				};
461*4882a593Smuzhiyun			};
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun			vcc3v3_pmu: LDO_REG6 {
464*4882a593Smuzhiyun				regulator-always-on;
465*4882a593Smuzhiyun				regulator-boot-on;
466*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
467*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
468*4882a593Smuzhiyun				regulator-name = "vcc3v3_pmu";
469*4882a593Smuzhiyun				regulator-state-mem {
470*4882a593Smuzhiyun					regulator-on-in-suspend;
471*4882a593Smuzhiyun					regulator-suspend-microvolt = <3000000>;
472*4882a593Smuzhiyun					regulator-changeable-in-suspend;
473*4882a593Smuzhiyun				};
474*4882a593Smuzhiyun			};
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun			vcc_1v8: LDO_REG7 {
477*4882a593Smuzhiyun				regulator-always-on;
478*4882a593Smuzhiyun				regulator-boot-on;
479*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
480*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
481*4882a593Smuzhiyun				regulator-name = "vcc_1v8";
482*4882a593Smuzhiyun				regulator-state-mem {
483*4882a593Smuzhiyun					regulator-off-in-suspend;
484*4882a593Smuzhiyun					regulator-changeable-in-suspend;
485*4882a593Smuzhiyun				};
486*4882a593Smuzhiyun			};
487*4882a593Smuzhiyun
488*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG8 {
489*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
490*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
491*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
492*4882a593Smuzhiyun				regulator-state-mem {
493*4882a593Smuzhiyun					regulator-off-in-suspend;
494*4882a593Smuzhiyun					regulator-changeable-in-suspend;
495*4882a593Smuzhiyun				};
496*4882a593Smuzhiyun			};
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun			sleep_sta_ctl: LDO_REG9 {
499*4882a593Smuzhiyun				regulator-name = "sleep_sta_ctl";
500*4882a593Smuzhiyun				regulator-state-mem {
501*4882a593Smuzhiyun					regulator-on-in-suspend;
502*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
503*4882a593Smuzhiyun					regulator-changeable-in-suspend;
504*4882a593Smuzhiyun				};
505*4882a593Smuzhiyun			};
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun			dcdc_boost: BOOST {
508*4882a593Smuzhiyun				regulator-always-on;
509*4882a593Smuzhiyun				regulator-boot-on;
510*4882a593Smuzhiyun				regulator-min-microvolt = <4700000>;
511*4882a593Smuzhiyun				regulator-max-microvolt = <5400000>;
512*4882a593Smuzhiyun				regulator-name = "boost";
513*4882a593Smuzhiyun				regulator-state-mem {
514*4882a593Smuzhiyun					regulator-off-in-suspend;
515*4882a593Smuzhiyun					regulator-changeable-in-suspend;
516*4882a593Smuzhiyun				};
517*4882a593Smuzhiyun			};
518*4882a593Smuzhiyun
519*4882a593Smuzhiyun			otg_switch: OTG_SWITCH {
520*4882a593Smuzhiyun				regulator-name = "otg_switch";
521*4882a593Smuzhiyun				regulator-state-mem {
522*4882a593Smuzhiyun					regulator-off-in-suspend;
523*4882a593Smuzhiyun					regulator-changeable-in-suspend;
524*4882a593Smuzhiyun				};
525*4882a593Smuzhiyun			};
526*4882a593Smuzhiyun		};
527*4882a593Smuzhiyun
528*4882a593Smuzhiyun		battery {
529*4882a593Smuzhiyun			compatible = "rk817,battery";
530*4882a593Smuzhiyun			ocv_table = <3400 3513 3578 3687 3734 3752 3763
531*4882a593Smuzhiyun				     3766 3771 3784 3804 3836 3885 3925
532*4882a593Smuzhiyun				     3962 4005 4063 4114 4169 4227 4303>;
533*4882a593Smuzhiyun			design_capacity = <2250>;
534*4882a593Smuzhiyun			design_qmax = <2750>;
535*4882a593Smuzhiyun			bat_res = <100>;
536*4882a593Smuzhiyun			sleep_enter_current = <150>;
537*4882a593Smuzhiyun			sleep_exit_current = <180>;
538*4882a593Smuzhiyun			sleep_filter_current = <100>;
539*4882a593Smuzhiyun			power_off_thresd = <3450>;
540*4882a593Smuzhiyun			zero_algorithm_vol = <3850>;
541*4882a593Smuzhiyun			max_soc_offset = <60>;
542*4882a593Smuzhiyun			monitor_sec = <5>;
543*4882a593Smuzhiyun			sample_res = <10>;
544*4882a593Smuzhiyun			virtual_power = <0>;
545*4882a593Smuzhiyun			low_power_sleep = <1>;
546*4882a593Smuzhiyun		};
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun		charger {
549*4882a593Smuzhiyun			compatible = "rk817,charger";
550*4882a593Smuzhiyun			min_input_voltage = <4500>;
551*4882a593Smuzhiyun			max_input_current = <1500>;
552*4882a593Smuzhiyun			max_chrg_current = <2000>;
553*4882a593Smuzhiyun			max_chrg_voltage = <4300>;
554*4882a593Smuzhiyun			chrg_term_mode = <0>;
555*4882a593Smuzhiyun			chrg_finish_cur = <300>;
556*4882a593Smuzhiyun			virtual_power = <0>;
557*4882a593Smuzhiyun			dc_det_adc = <0>;
558*4882a593Smuzhiyun			extcon = <&usb2phy0>;
559*4882a593Smuzhiyun			gate_function_disable = <1>;
560*4882a593Smuzhiyun		};
561*4882a593Smuzhiyun	};
562*4882a593Smuzhiyun};
563*4882a593Smuzhiyun
564*4882a593Smuzhiyun&i2c1 {
565*4882a593Smuzhiyun	status = "okay";
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun	ov5648: ov5648@36 {
568*4882a593Smuzhiyun		status = "okay";
569*4882a593Smuzhiyun		compatible = "ovti,ov5648";
570*4882a593Smuzhiyun		reg = <0x36>;
571*4882a593Smuzhiyun		clocks = <&cru CLK_CAM0_OUT>;
572*4882a593Smuzhiyun		clock-names = "xvclk";
573*4882a593Smuzhiyun		/* avdd-supply = <&vcc2v8_dvp>; */
574*4882a593Smuzhiyun		dovdd-supply = <&vcc1v8_dvp>;
575*4882a593Smuzhiyun		/* dvdd-supply = <&vcc1v8_dvp>; */
576*4882a593Smuzhiyun
577*4882a593Smuzhiyun		power-domains = <&power RK3568_PD_VI>;
578*4882a593Smuzhiyun		pinctrl-names = "default";
579*4882a593Smuzhiyun		pinctrl-0 = <&cam_clkout0>;
580*4882a593Smuzhiyun		//reset pin control by hardware,used this pin switch to mipi input
581*4882a593Smuzhiyun		//1->2LANE(LANE 0&1) FRONT camera, 0->4LANE REAR camera
582*4882a593Smuzhiyun		//reset-gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
583*4882a593Smuzhiyun		pwdn-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
584*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
585*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
586*4882a593Smuzhiyun		rockchip,camera-module-name = "HS5885-BNSM1018-V01";
587*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "default";
588*4882a593Smuzhiyun		port {
589*4882a593Smuzhiyun			ov5648_out: endpoint {
590*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
591*4882a593Smuzhiyun				data-lanes = <1 2>;
592*4882a593Smuzhiyun			};
593*4882a593Smuzhiyun		};
594*4882a593Smuzhiyun	};
595*4882a593Smuzhiyun};
596*4882a593Smuzhiyun
597*4882a593Smuzhiyun&i2c3 {
598*4882a593Smuzhiyun	status = "okay";
599*4882a593Smuzhiyun	pinctrl-names = "default";
600*4882a593Smuzhiyun	pinctrl-0 = <&i2c3m1_xfer>;
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun	tps65185: tps65185@68 {
603*4882a593Smuzhiyun		compatible = "ti,tps65185";
604*4882a593Smuzhiyun		reg = <0x68>;
605*4882a593Smuzhiyun		pinctrl-names = "default";
606*4882a593Smuzhiyun		pinctrl-0 = <&tps65185_gpio>;
607*4882a593Smuzhiyun		int-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
608*4882a593Smuzhiyun		wakeup-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
609*4882a593Smuzhiyun		vcomctl-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
610*4882a593Smuzhiyun		powerup-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
611*4882a593Smuzhiyun		poweren-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
612*4882a593Smuzhiyun	};
613*4882a593Smuzhiyun
614*4882a593Smuzhiyun};
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun&i2c5 {
617*4882a593Smuzhiyun	status = "okay";
618*4882a593Smuzhiyun
619*4882a593Smuzhiyun	sensor@4c {
620*4882a593Smuzhiyun		status = "okay";
621*4882a593Smuzhiyun		compatible = "gs_mma7660";
622*4882a593Smuzhiyun		reg = <0x4c>;
623*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
624*4882a593Smuzhiyun		irq_enable = <0>;
625*4882a593Smuzhiyun		poll_delay_ms = <30>;
626*4882a593Smuzhiyun		layout = <6>;
627*4882a593Smuzhiyun		reprobe_en = <1>;
628*4882a593Smuzhiyun	};
629*4882a593Smuzhiyun
630*4882a593Smuzhiyun	gt9xx: gt9xx@14 {
631*4882a593Smuzhiyun		compatible = "goodix,gt9xx";
632*4882a593Smuzhiyun		reg = <0x14>;
633*4882a593Smuzhiyun		pinctrl-names = "default";
634*4882a593Smuzhiyun		pinctrl-0 = <&tp_gpio>;
635*4882a593Smuzhiyun		touch-gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
636*4882a593Smuzhiyun		reset-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
637*4882a593Smuzhiyun		touchscreen-size-x = <1024>;
638*4882a593Smuzhiyun		touchscreen-size-y = <758>;
639*4882a593Smuzhiyun		max-x = <1024>;
640*4882a593Smuzhiyun		max-y = <758>;
641*4882a593Smuzhiyun		tp-size = <9111>;
642*4882a593Smuzhiyun		tp-supply = <&vcc_tp>;
643*4882a593Smuzhiyun		wakeup-source;
644*4882a593Smuzhiyun		touchscreen-key-map = <158>; //KEY_HOMEPAGE=172,KEY_BACK=158,KEY_MENU=139
645*4882a593Smuzhiyun		goodix,driver-send-cfg = <0>;
646*4882a593Smuzhiyun		goodix,cfg-group0 =[
647*4882a593Smuzhiyun			42 00 03 00 04 0A 45 03 22 1F 28 0F 64 3C 03 0F 00 00 00 00 11 00
648*4882a593Smuzhiyun			08 00 00 00 00 8B 29 0E 71 6F B2 04 00 00 00 39 02 10 00 21 00 00
649*4882a593Smuzhiyun			00 03 64 32 00 00 00 3C 78 94 D5 02 07 00 00 04 C8 40 00 B1 4A 00
650*4882a593Smuzhiyun			9E 55 00 8E 61 00 7F 70 00 7F 70 00 00 00 F0 90 3C FF FF 07 00 00
651*4882a593Smuzhiyun			00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
652*4882a593Smuzhiyun			00 00 1C 1A 18 16 14 12 10 0E 0C 0A 08 06 04 02 FF FF FF FF FF FF
653*4882a593Smuzhiyun			FF FF FF FF FF FF FF FF FF FF 00 02 04 06 08 0A 0C 0F 10 12 13 16
654*4882a593Smuzhiyun			18 1C 1D 1E 1F 20 21 22 FF FF FF FF FF FF FF FF FF FF FF FF FF FF
655*4882a593Smuzhiyun			FF FF FF FF FF FF FF FF F6 01
656*4882a593Smuzhiyun		];
657*4882a593Smuzhiyun	};
658*4882a593Smuzhiyun
659*4882a593Smuzhiyun	ft5436: focaltech@38 {
660*4882a593Smuzhiyun		status = "okay";
661*4882a593Smuzhiyun		compatible = "focaltech,ft5436";
662*4882a593Smuzhiyun		reg = <0x38>;
663*4882a593Smuzhiyun		pinctrl-names = "default";
664*4882a593Smuzhiyun		pinctrl-0 = <&tp_gpio>;
665*4882a593Smuzhiyun		vdd-supply = <&vcc_tp>;
666*4882a593Smuzhiyun		focaltech,reset-gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
667*4882a593Smuzhiyun		focaltech,irq-gpio = <&gpio0 RK_PA6 IRQ_TYPE_EDGE_FALLING>;
668*4882a593Smuzhiyun		focaltech,max-touch-number = <5>;
669*4882a593Smuzhiyun		focaltech,display-coords =  <0 0 1024 758>;
670*4882a593Smuzhiyun		focaltech,have-key = <1>;
671*4882a593Smuzhiyun		focaltech,key-number = <1>;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun		focaltech,key-x-coords = <300>;
674*4882a593Smuzhiyun		focaltech,key-y-coords = <1200>;
675*4882a593Smuzhiyun		wakeup-source;
676*4882a593Smuzhiyun	};
677*4882a593Smuzhiyun};
678*4882a593Smuzhiyun
679*4882a593Smuzhiyun&i2s0_8ch {
680*4882a593Smuzhiyun	status = "disabled";
681*4882a593Smuzhiyun};
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun&i2s1_8ch {
684*4882a593Smuzhiyun	status = "okay";
685*4882a593Smuzhiyun	rockchip,clk-trcm = <1>;
686*4882a593Smuzhiyun	pinctrl-names = "default";
687*4882a593Smuzhiyun	pinctrl-0 = <&i2s1m0_sclktx
688*4882a593Smuzhiyun		     &i2s1m0_lrcktx
689*4882a593Smuzhiyun		     &i2s1m0_sdi0
690*4882a593Smuzhiyun		     &i2s1m0_sdo0>;
691*4882a593Smuzhiyun};
692*4882a593Smuzhiyun
693*4882a593Smuzhiyun&jpegd {
694*4882a593Smuzhiyun	status = "okay";
695*4882a593Smuzhiyun};
696*4882a593Smuzhiyun
697*4882a593Smuzhiyun&jpegd_mmu {
698*4882a593Smuzhiyun	status = "okay";
699*4882a593Smuzhiyun};
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun&video_phy0 {
702*4882a593Smuzhiyun	status = "disabled";
703*4882a593Smuzhiyun};
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun&mpp_srv {
706*4882a593Smuzhiyun	status = "okay";
707*4882a593Smuzhiyun};
708*4882a593Smuzhiyun
709*4882a593Smuzhiyun&nandc0 {
710*4882a593Smuzhiyun	status = "disabled";
711*4882a593Smuzhiyun};
712*4882a593Smuzhiyun
713*4882a593Smuzhiyun&pinctrl {
714*4882a593Smuzhiyun	cam {
715*4882a593Smuzhiyun		cam_clkout0: cam-clkout0 {
716*4882a593Smuzhiyun			rockchip,pins =
717*4882a593Smuzhiyun				/* cam_clkout0 */
718*4882a593Smuzhiyun				<4 RK_PA7 1 &pcfg_pull_none>;
719*4882a593Smuzhiyun		};
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun		camera_rst: camera-rst {
722*4882a593Smuzhiyun			rockchip,pins =
723*4882a593Smuzhiyun				<4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
724*4882a593Smuzhiyun		};
725*4882a593Smuzhiyun	};
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun	leds {
728*4882a593Smuzhiyun		leds_gpio: leds-gpio {
729*4882a593Smuzhiyun			rockchip,pins =
730*4882a593Smuzhiyun				<3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>,
731*4882a593Smuzhiyun				<3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
732*4882a593Smuzhiyun		};
733*4882a593Smuzhiyun	};
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun	tps_pmic {
736*4882a593Smuzhiyun		tps65185_gpio: tps65185-gpio {
737*4882a593Smuzhiyun			rockchip,pins =
738*4882a593Smuzhiyun				<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
739*4882a593Smuzhiyun				<3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
740*4882a593Smuzhiyun				<3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
741*4882a593Smuzhiyun				<3 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>,
742*4882a593Smuzhiyun				<0 RK_PC1 RK_FUNC_GPIO &pcfg_output_high>;
743*4882a593Smuzhiyun		};
744*4882a593Smuzhiyun	};
745*4882a593Smuzhiyun
746*4882a593Smuzhiyun	tp {
747*4882a593Smuzhiyun		tp_gpio: tp-gpio {
748*4882a593Smuzhiyun			rockchip,pins =
749*4882a593Smuzhiyun				<0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
750*4882a593Smuzhiyun				<0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
751*4882a593Smuzhiyun		};
752*4882a593Smuzhiyun	};
753*4882a593Smuzhiyun
754*4882a593Smuzhiyun	pmic {
755*4882a593Smuzhiyun		pmic_int: pmic_int {
756*4882a593Smuzhiyun			rockchip,pins =
757*4882a593Smuzhiyun				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
758*4882a593Smuzhiyun		};
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun		soc_slppin_gpio: soc_slppin_gpio {
761*4882a593Smuzhiyun			rockchip,pins =
762*4882a593Smuzhiyun				<0 RK_PA2 RK_FUNC_GPIO &pcfg_output_low>;
763*4882a593Smuzhiyun		};
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun		soc_slppin_slp: soc_slppin_slp {
766*4882a593Smuzhiyun			rockchip,pins =
767*4882a593Smuzhiyun				<0 RK_PA2 1 &pcfg_pull_none>;
768*4882a593Smuzhiyun		};
769*4882a593Smuzhiyun
770*4882a593Smuzhiyun		soc_slppin_rst: soc_slppin_rst {
771*4882a593Smuzhiyun			rockchip,pins =
772*4882a593Smuzhiyun				<0 RK_PA2 2 &pcfg_pull_none>;
773*4882a593Smuzhiyun		};
774*4882a593Smuzhiyun	};
775*4882a593Smuzhiyun
776*4882a593Smuzhiyun	sdio-pwrseq {
777*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
778*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
779*4882a593Smuzhiyun		};
780*4882a593Smuzhiyun	};
781*4882a593Smuzhiyun
782*4882a593Smuzhiyun	vcc-tp {
783*4882a593Smuzhiyun		vcc_tp_en: vcc-tp-en {
784*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
785*4882a593Smuzhiyun		};
786*4882a593Smuzhiyun	};
787*4882a593Smuzhiyun
788*4882a593Smuzhiyun	wireless-wlan {
789*4882a593Smuzhiyun		wifi_vbat: wifi-vbat {
790*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
791*4882a593Smuzhiyun		};
792*4882a593Smuzhiyun
793*4882a593Smuzhiyun		wifi_host_wake_irq: wifi-host-wake-irq {
794*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
795*4882a593Smuzhiyun		};
796*4882a593Smuzhiyun	};
797*4882a593Smuzhiyun
798*4882a593Smuzhiyun	wireless-bluetooth {
799*4882a593Smuzhiyun		uart1_gpios: uart1-gpios {
800*4882a593Smuzhiyun			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
801*4882a593Smuzhiyun		};
802*4882a593Smuzhiyun	};
803*4882a593Smuzhiyun};
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun&pmu_io_domains {
806*4882a593Smuzhiyun	status = "okay";
807*4882a593Smuzhiyun	pmuio1-supply = <&vcc3v3_pmu>;
808*4882a593Smuzhiyun	pmuio2-supply = <&vcca1v8_pmu>;
809*4882a593Smuzhiyun	vccio1-supply = <&vccio_acodec>;
810*4882a593Smuzhiyun	vccio3-supply = <&vcc_3v3>;
811*4882a593Smuzhiyun	vccio4-supply = <&vcca1v8_pmu>;
812*4882a593Smuzhiyun	vccio5-supply = <&vcc_3v3>;
813*4882a593Smuzhiyun	vccio6-supply = <&vcc_3v3>;
814*4882a593Smuzhiyun	vccio7-supply = <&vcc1v8_dvp>;
815*4882a593Smuzhiyun};
816*4882a593Smuzhiyun
817*4882a593Smuzhiyun&pwm4 {
818*4882a593Smuzhiyun	status = "disabled";
819*4882a593Smuzhiyun};
820*4882a593Smuzhiyun
821*4882a593Smuzhiyun&rk_rga {
822*4882a593Smuzhiyun	status = "okay";
823*4882a593Smuzhiyun};
824*4882a593Smuzhiyun
825*4882a593Smuzhiyun&rkisp {
826*4882a593Smuzhiyun	status = "okay";
827*4882a593Smuzhiyun};
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun&rkisp_mmu {
830*4882a593Smuzhiyun	status = "okay";
831*4882a593Smuzhiyun};
832*4882a593Smuzhiyun
833*4882a593Smuzhiyun&rkisp_vir0 {
834*4882a593Smuzhiyun	status = "okay";
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun	port {
837*4882a593Smuzhiyun		#address-cells = <1>;
838*4882a593Smuzhiyun		#size-cells = <0>;
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun		isp0_in: endpoint@0 {
841*4882a593Smuzhiyun			reg = <0>;
842*4882a593Smuzhiyun			remote-endpoint = <&csidphy0_out>;
843*4882a593Smuzhiyun		};
844*4882a593Smuzhiyun	};
845*4882a593Smuzhiyun};
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun&rkvdec {
848*4882a593Smuzhiyun	status = "okay";
849*4882a593Smuzhiyun};
850*4882a593Smuzhiyun
851*4882a593Smuzhiyun&rkvdec_mmu {
852*4882a593Smuzhiyun	status = "okay";
853*4882a593Smuzhiyun};
854*4882a593Smuzhiyun
855*4882a593Smuzhiyun&rkvenc {
856*4882a593Smuzhiyun	status = "okay";
857*4882a593Smuzhiyun};
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun&rkvenc_mmu {
860*4882a593Smuzhiyun	status = "okay";
861*4882a593Smuzhiyun};
862*4882a593Smuzhiyun
863*4882a593Smuzhiyun&rockchip_suspend {
864*4882a593Smuzhiyun	status = "okay";
865*4882a593Smuzhiyun
866*4882a593Smuzhiyun	rockchip,regulator-off-in-mem-lite =
867*4882a593Smuzhiyun		<&vdd_cpu>, <&vdd_logic>, <&vdd_gpu>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>,
868*4882a593Smuzhiyun		<&vccio_acodec>, <&vccio_sd>, <&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>,
869*4882a593Smuzhiyun		<&sleep_sta_ctl>;
870*4882a593Smuzhiyun	rockchip,regulator-on-in-mem-lite =
871*4882a593Smuzhiyun		<&vcc_ddr>, <&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>;
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun	rockchip,regulator-off-in-mem =
874*4882a593Smuzhiyun		<&vdd_cpu>, <&vdd_logic>, <&vdd_gpu>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>,
875*4882a593Smuzhiyun		<&vccio_acodec>, <&vccio_sd>, <&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>,
876*4882a593Smuzhiyun		<&sleep_sta_ctl>;
877*4882a593Smuzhiyun	rockchip,regulator-on-in-mem =
878*4882a593Smuzhiyun		<&vcc_ddr>, <&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>;
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun	rockchip,regulator-off-in-mem-ultra =
881*4882a593Smuzhiyun		<&vdd_logic>, <&vdd_gpu>, <&vcc_ddr>, <&vcc_3v3>, <&vdda_0v9>, <&vcc_1v8>,
882*4882a593Smuzhiyun		<&vdda0v9_pmu>, <&vcca1v8_pmu>, <&vcc3v3_pmu>, <&vccio_acodec>, <&vccio_sd>,
883*4882a593Smuzhiyun		<&vcc1v8_dvp>, <&dcdc_boost>, <&otg_switch>;
884*4882a593Smuzhiyun	rockchip,regulator-on-in-mem-ultra = <&vdd_cpu>, <&sleep_sta_ctl>;
885*4882a593Smuzhiyun};
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun&saradc {
888*4882a593Smuzhiyun	status = "disabled";
889*4882a593Smuzhiyun	vref-supply = <&vcc_1v8>;
890*4882a593Smuzhiyun};
891*4882a593Smuzhiyun
892*4882a593Smuzhiyun&sdhci {
893*4882a593Smuzhiyun	bus-width = <8>;
894*4882a593Smuzhiyun	no-sdio;
895*4882a593Smuzhiyun	no-sd;
896*4882a593Smuzhiyun	non-removable;
897*4882a593Smuzhiyun	keep-power-in-suspend;
898*4882a593Smuzhiyun	max-frequency = <200000000>;
899*4882a593Smuzhiyun	status = "okay";
900*4882a593Smuzhiyun};
901*4882a593Smuzhiyun
902*4882a593Smuzhiyun&sdmmc1 {
903*4882a593Smuzhiyun	max-frequency = <150000000>;
904*4882a593Smuzhiyun	no-sd;
905*4882a593Smuzhiyun	no-mmc;
906*4882a593Smuzhiyun	bus-width = <4>;
907*4882a593Smuzhiyun	disable-wp;
908*4882a593Smuzhiyun	cap-sd-highspeed;
909*4882a593Smuzhiyun	cap-sdio-irq;
910*4882a593Smuzhiyun	keep-power-in-suspend;
911*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
912*4882a593Smuzhiyun	non-removable;
913*4882a593Smuzhiyun	pinctrl-names = "default";
914*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
915*4882a593Smuzhiyun	sd-uhs-sdr104;
916*4882a593Smuzhiyun	rockchip,default-sample-phase = <90>;
917*4882a593Smuzhiyun	status = "okay";
918*4882a593Smuzhiyun};
919*4882a593Smuzhiyun
920*4882a593Smuzhiyun&tsadc {
921*4882a593Smuzhiyun	status = "okay";
922*4882a593Smuzhiyun};
923*4882a593Smuzhiyun
924*4882a593Smuzhiyun&uart1 {
925*4882a593Smuzhiyun	status = "okay";
926*4882a593Smuzhiyun	pinctrl-names = "default";
927*4882a593Smuzhiyun	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
928*4882a593Smuzhiyun};
929*4882a593Smuzhiyun
930*4882a593Smuzhiyun&u2phy0_otg {
931*4882a593Smuzhiyun	status = "okay";
932*4882a593Smuzhiyun};
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun&usb2phy0 {
935*4882a593Smuzhiyun	status = "okay";
936*4882a593Smuzhiyun};
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun&usbdrd_dwc3 {
939*4882a593Smuzhiyun	status = "okay";
940*4882a593Smuzhiyun};
941*4882a593Smuzhiyun
942*4882a593Smuzhiyun&usbdrd30 {
943*4882a593Smuzhiyun	status = "okay";
944*4882a593Smuzhiyun};
945*4882a593Smuzhiyun
946*4882a593Smuzhiyun&vdpu {
947*4882a593Smuzhiyun	status = "okay";
948*4882a593Smuzhiyun};
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun&vdpu_mmu {
951*4882a593Smuzhiyun	status = "okay";
952*4882a593Smuzhiyun};
953*4882a593Smuzhiyun
954*4882a593Smuzhiyun&vepu {
955*4882a593Smuzhiyun	status = "okay";
956*4882a593Smuzhiyun};
957*4882a593Smuzhiyun
958*4882a593Smuzhiyun&vepu_mmu {
959*4882a593Smuzhiyun	status = "okay";
960*4882a593Smuzhiyun};
961*4882a593Smuzhiyun
962*4882a593Smuzhiyun&vop {
963*4882a593Smuzhiyun	status = "okay";
964*4882a593Smuzhiyun};
965*4882a593Smuzhiyun
966*4882a593Smuzhiyun&vop_mmu {
967*4882a593Smuzhiyun	status = "okay";
968*4882a593Smuzhiyun};
969