1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/display/media-bus-format.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include "rk3566.dtsi" 13#include "rk3566-evb.dtsi" 14 15/ { 16 model = "Rockchip RK3566 EVB2 LP4X V10 Board"; 17 compatible = "rockchip,rk3566-evb2-lp4x-v10", "rockchip,rk3566"; 18 19 vcc_camera: vcc-camera-regulator { 20 compatible = "regulator-fixed"; 21 gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 22 pinctrl-names = "default"; 23 pinctrl-0 = <&camera_pwr>; 24 regulator-name = "vcc_camera"; 25 enable-active-high; 26 regulator-always-on; 27 regulator-boot-on; 28 }; 29 30 vcc3v3_pcie: gpio-regulator { 31 compatible = "regulator-fixed"; 32 regulator-name = "vcc3v3_pcie"; 33 regulator-min-microvolt = <3300000>; 34 regulator-max-microvolt = <3300000>; 35 enable-active-high; 36 gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; 37 startup-delay-us = <5000>; 38 vin-supply = <&dc_12v>; 39 }; 40}; 41 42&bt_sound { 43 status = "disabled"; 44 simple-audio-card,cpu { 45 sound-dai = <&i2s2_2ch>; 46 }; 47}; 48 49&combphy1_usq { 50 status = "okay"; 51}; 52 53&combphy2_psq { 54 status = "okay"; 55}; 56 57&csi2_dphy_hw { 58 status = "okay"; 59}; 60 61&csi2_dphy0 { 62 status = "okay"; 63 /* 64 * dphy0 only used for full mode, 65 * full mode and split mode are mutually exclusive 66 */ 67 ports { 68 #address-cells = <1>; 69 #size-cells = <0>; 70 71 port@0 { 72 reg = <0>; 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 dphy0_in: endpoint@1 { 77 reg = <1>; 78 remote-endpoint = <&gc8034_out>; 79 data-lanes = <1 2 3 4>; 80 }; 81 82 mipi_in_ucam1: endpoint@2 { 83 reg = <2>; 84 remote-endpoint = <&ov5695_out>; 85 data-lanes = <1 2>; 86 }; 87 88 mipi_in_ucam2: endpoint@3 { 89 reg = <3>; 90 remote-endpoint = <&gc5025_out>; 91 data-lanes = <1 2>; 92 }; 93 }; 94 95 port@1 { 96 reg = <1>; 97 #address-cells = <1>; 98 #size-cells = <0>; 99 100 dphy0_out: endpoint@1 { 101 reg = <1>; 102 remote-endpoint = <&isp0_in_dphy0>; 103 }; 104 }; 105 }; 106}; 107 108&csi2_dphy1 { 109 status = "disabled"; 110 111 /* 112 * dphy1 only used for split mode, 113 * can be used concurrently with dphy2 114 * full mode and split mode are mutually exclusive 115 */ 116 ports { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 port@0 { 121 reg = <0>; 122 #address-cells = <1>; 123 #size-cells = <0>; 124 125 dphy1_in: endpoint@1 { 126 reg = <1>; 127 //remote-endpoint = <&ov5695_out>; 128 data-lanes = <1 2>; 129 }; 130 }; 131 132 port@1 { 133 reg = <1>; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 137 dphy1_out: endpoint@1 { 138 reg = <1>; 139 remote-endpoint = <&isp0_in>; 140 }; 141 }; 142 }; 143}; 144 145&csi2_dphy2 { 146 status = "disabled"; 147 148 /* 149 * dphy2 only used for split mode, 150 * can be used concurrently with dphy1 151 * full mode and split mode are mutually exclusive 152 */ 153 ports { 154 #address-cells = <1>; 155 #size-cells = <0>; 156 157 port@0 { 158 reg = <0>; 159 #address-cells = <1>; 160 #size-cells = <0>; 161 162 dphy2_in: endpoint@1 { 163 reg = <1>; 164 //remote-endpoint = <&gc5025_out>; 165 data-lanes = <1 2>; 166 }; 167 }; 168 169 port@1 { 170 reg = <1>; 171 #address-cells = <1>; 172 #size-cells = <0>; 173 174 dphy2_out: endpoint@1 { 175 reg = <1>; 176 remote-endpoint = <&mipi_csi2_input>; 177 }; 178 }; 179 }; 180}; 181 182/* 183 * video_phy0 needs to be enabled 184 * when dsi0 is enabled 185 */ 186&dsi0 { 187 status = "okay"; 188}; 189 190&dsi0_in_vp0 { 191 status = "disabled"; 192}; 193 194&dsi0_in_vp1 { 195 status = "okay"; 196}; 197 198&dsi0_panel { 199 power-supply = <&vcc3v3_lcd0_n>; 200 reset-gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_LOW>; 201 pinctrl-names = "default"; 202 pinctrl-0 = <&lcd0_rst_gpio>; 203}; 204 205/* 206 * video_phy1 needs to be enabled 207 * when dsi1 is enabled 208 */ 209&dsi1 { 210 status = "disabled"; 211}; 212 213&dsi1_in_vp0 { 214 status = "disabled"; 215}; 216 217&dsi1_in_vp1 { 218 status = "disabled"; 219}; 220 221&dsi1_panel { 222 power-supply = <&vcc3v3_lcd1_n>; 223 reset-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_LOW>; 224 pinctrl-names = "default"; 225 pinctrl-0 = <&lcd1_rst_gpio>; 226}; 227 228&gmac1 { 229 phy-mode = "rgmii"; 230 clock_in_out = "output"; 231 232 snps,reset-gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>; 233 snps,reset-active-low; 234 /* Reset time is 20ms, 100ms for rtl8211f */ 235 snps,reset-delays-us = <0 20000 100000>; 236 237 assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>; 238 assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>; 239 assigned-clock-rates = <0>, <125000000>; 240 241 pinctrl-names = "default"; 242 pinctrl-0 = <&gmac1m1_miim 243 &gmac1m1_tx_bus2 244 &gmac1m1_rx_bus2 245 &gmac1m1_rgmii_clk 246 &gmac1m1_rgmii_bus>; 247 248 tx_delay = <0x4f>; 249 rx_delay = <0x25>; 250 251 phy-handle = <&rgmii_phy0>; 252 status = "okay"; 253}; 254 255&i2c2 { 256 status = "okay"; 257 pinctrl-0 = <&i2c2m1_xfer>; 258 259 /* split mode: lane0/1 */ 260 ov5695: ov5695@36 { 261 status = "okay"; 262 compatible = "ovti,ov5695"; 263 reg = <0x36>; 264 clocks = <&cru CLK_CIF_OUT>; 265 clock-names = "xvclk"; 266 power-domains = <&power RK3568_PD_VI>; 267 pinctrl-names = "default"; 268 pinctrl-0 = <&cif_clk>; 269 reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>; 270 pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>; 271 /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ 272 rockchip,camera-module-index = <0>; 273 rockchip,camera-module-facing = "back"; 274 rockchip,camera-module-name = "TongJu"; 275 rockchip,camera-module-lens-name = "CHT842-MD"; 276 port { 277 ov5695_out: endpoint { 278 remote-endpoint = <&mipi_in_ucam1>; 279 data-lanes = <1 2>; 280 }; 281 }; 282 }; 283 284 /* split mode: lane:2/3 */ 285 gc5025: gc5025@37 { 286 status = "okay"; 287 compatible = "galaxycore,gc5025"; 288 reg = <0x37>; 289 clocks = <&pmucru CLK_WIFI>; 290 clock-names = "xvclk"; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&refclk_pins>; 293 reset-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>; 294 pwdn-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>; 295 power-domains = <&power RK3568_PD_VI>; 296 /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ 297 rockchip,camera-module-index = <1>; 298 rockchip,camera-module-facing = "front"; 299 rockchip,camera-module-name = "TongJu"; 300 rockchip,camera-module-lens-name = "CHT842-MD"; 301 port { 302 gc5025_out: endpoint { 303 remote-endpoint = <&mipi_in_ucam2>; 304 data-lanes = <1 2>; 305 }; 306 }; 307 }; 308 309 /* full mode: lane0-3 */ 310 gc8034: gc8034@37 { 311 compatible = "galaxycore,gc8034"; 312 status = "okay"; 313 reg = <0x37>; 314 clocks = <&cru CLK_CIF_OUT>; 315 clock-names = "xvclk"; 316 power-domains = <&power RK3568_PD_VI>; 317 pinctrl-names = "default"; 318 pinctrl-0 = <&cif_clk>; 319 reset-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>; 320 pwdn-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_LOW>; 321 rockchip,camera-module-index = <0>; 322 rockchip,camera-module-facing = "back"; 323 rockchip,camera-module-name = "RK-CMK-8M-2-v1"; 324 rockchip,camera-module-lens-name = "CK8401"; 325 port { 326 gc8034_out: endpoint { 327 remote-endpoint = <&dphy0_in>; 328 data-lanes = <1 2 3 4>; 329 }; 330 }; 331 }; 332}; 333 334&i2c4 { 335 /* i2c4 sda conflict with camera pwdn */ 336 status = "disabled"; 337 338 /* 339 * gc2145 needs to be disabled, 340 * when gmac1 is enabled; 341 * pinctrl conflicts; 342 */ 343 gc2145: gc2145@3c { 344 status = "disabled"; 345 compatible = "galaxycore,gc2145"; 346 reg = <0x3c>; 347 clocks = <&cru CLK_CIF_OUT>; 348 clock-names = "xvclk"; 349 power-domains = <&power RK3568_PD_VI>; 350 pinctrl-names = "default"; 351 /* conflict with gmac1m1_rgmii_pins & cif_clk*/ 352 pinctrl-0 = <&cif_clk &cif_dvp_clk &cif_dvp_bus16>; 353 354 /*avdd-supply = <&vcc2v8_dvp>;*/ 355 /*dovdd-supply = <&vcc1v8_dvp>;*/ 356 /*dvdd-supply = <&vcc1v8_dvp>;*/ 357 358 /*reset-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_LOW>;*/ 359 pwdn-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 360 rockchip,camera-module-index = <0>; 361 rockchip,camera-module-facing = "back"; 362 rockchip,camera-module-name = "CameraKing"; 363 rockchip,camera-module-lens-name = "Largan"; 364 port { 365 gc2145_out: endpoint { 366 remote-endpoint = <&dvp_in_bcam>; 367 }; 368 }; 369 }; 370}; 371 372&i2s2_2ch { 373 pinctrl-0 = <&i2s2m0_sclktx &i2s2m0_lrcktx &i2s2m0_sdi &i2s2m0_sdo>; 374 rockchip,bclk-fs = <32>; 375 status = "disabled"; 376}; 377 378&mdio1 { 379 rgmii_phy0: phy@0 { 380 compatible = "ethernet-phy-ieee802.3-c22"; 381 reg = <0x0>; 382 }; 383}; 384 385 386 387/* 388 * power-supply should switche to vcc3v3_lcd1_n 389 * when mipi panel is connected to dsi1. 390 */ 391>1x { 392 power-supply = <&vcc3v3_lcd0_n>; 393}; 394 395&mipi_csi2 { 396 status = "okay"; 397 398 ports { 399 #address-cells = <1>; 400 #size-cells = <0>; 401 402 port@0 { 403 reg = <0>; 404 #address-cells = <1>; 405 #size-cells = <0>; 406 407 mipi_csi2_input: endpoint@1 { 408 reg = <1>; 409 remote-endpoint = <&dphy2_out>; 410 data-lanes = <1 2>; 411 }; 412 }; 413 414 port@1 { 415 reg = <1>; 416 #address-cells = <1>; 417 #size-cells = <0>; 418 419 mipi_csi2_output: endpoint@0 { 420 reg = <0>; 421 remote-endpoint = <&cif_mipi_in>; 422 data-lanes = <1 2>; 423 }; 424 }; 425 }; 426}; 427 428&video_phy0 { 429 status = "okay"; 430}; 431 432&video_phy1 { 433 status = "disabled"; 434}; 435 436&pcie2x1 { 437 reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 438 vpcie3v3-supply = <&vcc3v3_pcie>; 439 status = "okay"; 440}; 441 442&pinctrl { 443 cam { 444 camera_pwr: camera-pwr { 445 rockchip,pins = 446 /* camera power en */ 447 <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 448 }; 449 }; 450 451 sdio-pwrseq { 452 wifi_enable_h: wifi-enable-h { 453 rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; 454 }; 455 }; 456 457 wireless-wlan { 458 wifi_host_wake_irq: wifi-host-wake-irq { 459 rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_down>; 460 }; 461 }; 462 463 wireless-bluetooth { 464 uart1_gpios: uart1-gpios { 465 rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>; 466 }; 467 }; 468 469 lcd0 { 470 lcd0_rst_gpio: lcd0-rst-gpio { 471 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 472 }; 473 }; 474 475 lcd1 { 476 lcd1_rst_gpio: lcd1-rst-gpio { 477 rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 478 }; 479 }; 480}; 481 482&rkcif { 483 status = "okay"; 484}; 485 486&rkcif_dvp { 487 status = "disabled"; 488 489 port { 490 /* Parallel bus endpoint */ 491 dvp_in_bcam: endpoint { 492 remote-endpoint = <&gc2145_out>; 493 bus-width = <8>; 494 vsync-active = <0>; 495 hsync-active = <1>; 496 }; 497 }; 498}; 499 500&rkcif_mipi_lvds { 501 status = "okay"; 502 503 port { 504 cif_mipi_in: endpoint { 505 remote-endpoint = <&mipi_csi2_output>; 506 data-lanes = <1 2>; 507 }; 508 }; 509}; 510 511&rkcif_mmu { 512 status = "okay"; 513}; 514 515&rkisp { 516 status = "okay"; 517}; 518 519&rkisp_mmu { 520 status = "okay"; 521}; 522 523&rkisp_vir0 { 524 status = "okay"; 525 526 port { 527 #address-cells = <1>; 528 #size-cells = <0>; 529 530 isp0_in: endpoint@0 { 531 reg = <0>; 532 remote-endpoint = <&dphy1_out>; 533 }; 534 isp0_in_dphy0: endpoint@1 { 535 reg = <1>; 536 remote-endpoint = <&dphy0_out>; 537 }; 538 }; 539}; 540 541&route_dsi0 { 542 status = "okay"; 543 connect = <&vp1_out_dsi0>; 544}; 545 546&sdmmc2 { 547 status = "disabled"; 548}; 549 550&sdmmc1 { 551 max-frequency = <150000000>; 552 no-sd; 553 no-mmc; 554 bus-width = <4>; 555 disable-wp; 556 cap-sd-highspeed; 557 cap-sdio-irq; 558 keep-power-in-suspend; 559 mmc-pwrseq = <&sdio_pwrseq>; 560 non-removable; 561 pinctrl-names = "default"; 562 pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>; 563 sd-uhs-sdr104; 564 status = "okay"; 565}; 566 567&sdio_pwrseq { 568 reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>; 569}; 570 571&spdif_8ch { 572 status = "okay"; 573 pinctrl-names = "default"; 574 pinctrl-0 = <&spdifm1_tx>; 575}; 576 577&uart1 { 578 status = "okay"; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>; 581}; 582 583&vcc3v3_lcd0_n { 584 gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 585 enable-active-high; 586}; 587 588&vcc3v3_lcd1_n { 589 gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>; 590 enable-active-high; 591}; 592&wireless_wlan { 593 pinctrl-names = "default"; 594 pinctrl-0 = <&wifi_host_wake_irq>; 595 WIFI,host_wake_irq = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>; 596 WIFI,poweren_gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; 597}; 598 599&work_led { 600 gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 601}; 602 603&wireless_bluetooth { 604 compatible = "bluetooth-platdata"; 605 clocks = <&rk809 1>; 606 clock-names = "ext_clock"; 607 //wifi-bt-power-toggle; 608 uart_rts_gpios = <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; 609 pinctrl-names = "default", "rts_gpio"; 610 pinctrl-0 = <&uart1m0_rtsn>; 611 pinctrl-1 = <&uart1_gpios>; 612 BT,reset_gpio = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>; 613 BT,wake_gpio = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>; 614 BT,wake_host_irq = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>; 615 status = "okay"; 616}; 617