1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/pinctrl/rockchip.h> 10#include "rk3566.dtsi" 11#include "rk3566-evb.dtsi" 12 13/ { 14 model = "Rockchip RK3566 EVB MIPITEST V10 Board"; 15 compatible = "rockchip,rk3566-evb-mipitest-v10", "rockchip,rk3566"; 16 17 vcc3v3_pcie: gpio-regulator { 18 compatible = "regulator-fixed"; 19 regulator-name = "vcc3v3_pcie"; 20 regulator-min-microvolt = <3300000>; 21 regulator-max-microvolt = <3300000>; 22 enable-active-high; 23 gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>; 24 startup-delay-us = <5000>; 25 vin-supply = <&dc_12v>; 26 }; 27 28 rk_headset: rk-headset { 29 compatible = "rockchip_headset"; 30 headset_gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>; 31 pinctrl-names = "default"; 32 pinctrl-0 = <&hp_det>; 33 }; 34 35 vcc3v3_vga: vcc3v3-vga { 36 compatible = "regulator-fixed"; 37 regulator-name = "vcc3v3_vga"; 38 regulator-always-on; 39 regulator-boot-on; 40 gpio = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>; 41 enable-active-high; 42 vin-supply = <&vcc3v3_sys>; 43 }; 44 45 vcc_camera: vcc-camera-regulator { 46 compatible = "regulator-fixed"; 47 gpio = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 48 pinctrl-names = "default"; 49 pinctrl-0 = <&camera_pwr>; 50 regulator-name = "vcc_camera"; 51 enable-active-high; 52 regulator-always-on; 53 regulator-boot-on; 54 }; 55}; 56 57&audiopwmout_diff { 58 status = "disabled"; 59}; 60 61&combphy1_usq { 62 status = "okay"; 63}; 64 65&combphy2_psq { 66 status = "okay"; 67}; 68 69&csi2_dphy_hw { 70 status = "okay"; 71}; 72 73&csi2_dphy1 { 74 status = "okay"; 75 76 /* 77 * dphy1 only used for split mode, 78 * can be used concurrently with dphy2 79 * full mode and split mode are mutually exclusive 80 */ 81 ports { 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 port@0 { 86 reg = <0>; 87 #address-cells = <1>; 88 #size-cells = <0>; 89 90 dphy1_in: endpoint@1 { 91 reg = <1>; 92 remote-endpoint = <&ov5695_out>; 93 data-lanes = <1 2>; 94 }; 95 }; 96 97 port@1 { 98 reg = <1>; 99 #address-cells = <1>; 100 #size-cells = <0>; 101 102 dphy1_out: endpoint@1 { 103 reg = <1>; 104 remote-endpoint = <&isp0_in>; 105 }; 106 }; 107 }; 108}; 109 110&csi2_dphy2 { 111 status = "okay"; 112 113 /* 114 * dphy2 only used for split mode, 115 * can be used concurrently with dphy1 116 * full mode and split mode are mutually exclusive 117 */ 118 ports { 119 #address-cells = <1>; 120 #size-cells = <0>; 121 122 port@0 { 123 reg = <0>; 124 #address-cells = <1>; 125 #size-cells = <0>; 126 127 dphy2_in: endpoint@1 { 128 reg = <1>; 129 remote-endpoint = <&ov02k10_out>; 130 data-lanes = <1 2>; 131 }; 132 }; 133 134 port@1 { 135 reg = <1>; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 dphy2_out: endpoint@1 { 140 reg = <1>; 141 remote-endpoint = <&mipi_csi2_input>; 142 }; 143 }; 144 }; 145}; 146 147&dig_acodec { 148 status = "disabled"; 149 rockchip,pwm-output-mode; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&audiopwm_loutp 152 &audiopwm_loutn 153 &audiopwm_routp 154 &audiopwm_routn 155 >; 156}; 157 158/* 159 * video_phy0 needs to be enabled 160 * when dsi0 is enabled 161 */ 162&dsi0 { 163 status = "okay"; 164}; 165 166&dsi0_in_vp0 { 167 status = "disabled"; 168}; 169 170&dsi0_in_vp1 { 171 status = "okay"; 172}; 173 174&dsi0_panel { 175 power-supply = <&vcc3v3_lcd0_n>; 176 reset-gpios = <&gpio4 RK_PC5 GPIO_ACTIVE_LOW>; 177 pinctrl-names = "default"; 178 pinctrl-0 = <&lcd0_rst_gpio>; 179}; 180 181/* 182 * video_phy1 needs to be enabled 183 * when dsi1 is enabled 184 */ 185&dsi1 { 186 status = "disabled"; 187}; 188 189&dsi1_in_vp0 { 190 status = "disabled"; 191}; 192 193&dsi1_in_vp1 { 194 status = "disabled"; 195}; 196 197&dsi1_panel { 198 power-supply = <&vcc3v3_lcd1_n>; 199 reset-gpios = <&gpio4 RK_PC6 GPIO_ACTIVE_LOW>; 200 pinctrl-names = "default"; 201 pinctrl-0 = <&lcd1_rst_gpio>; 202}; 203 204&edp { 205 hpd-gpios = <&gpio4 RK_PC4 GPIO_ACTIVE_HIGH>; 206 status = "okay"; 207}; 208 209&edp_phy { 210 status = "okay"; 211}; 212 213&edp_in_vp0 { 214 status = "okay"; 215}; 216 217&edp_in_vp1 { 218 status = "disabled"; 219}; 220 221/* 222 * power-supply should switche to vcc3v3_lcd1_n 223 * when mipi panel is connected to dsi1. 224 */ 225>1x { 226 status = "disabled"; 227 power-supply = <&vcc3v3_lcd0_n>; 228}; 229 230&hdmi { 231 status = "disabled"; 232}; 233 234&i2c2 { 235 status = "okay"; 236 pinctrl-names = "default"; 237 pinctrl-0 = <&i2c2m1_xfer>; 238 239 /* split mode: lane0/1 */ 240 ov5695: ov5695@36 { 241 status = "okay"; 242 compatible = "ovti,ov5695"; 243 reg = <0x36>; 244 clocks = <&cru CLK_CAM0_OUT>; 245 clock-names = "xvclk"; 246 power-domains = <&power RK3568_PD_VI>; 247 pinctrl-names = "default"; 248 pinctrl-0 = <&cam_clkout0>; 249 reset-gpios = <&gpio4 RK_PC0 GPIO_ACTIVE_HIGH>; 250 pwdn-gpios = <&gpio2 RK_PC5 GPIO_ACTIVE_HIGH>; 251 /*power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;*/ 252 rockchip,camera-module-index = <0>; 253 rockchip,camera-module-facing = "back"; 254 rockchip,camera-module-name = "TongJu"; 255 rockchip,camera-module-lens-name = "CHT842-MD"; 256 port { 257 ov5695_out: endpoint { 258 remote-endpoint = <&dphy1_in>; 259 data-lanes = <1 2>; 260 }; 261 }; 262 }; 263 264 ov02k10: ov02k10@36 { 265 status = "okay"; 266 compatible = "ovti,ov02k10"; 267 reg = <0x36>; 268 clocks = <&cru CLK_CAM1_OUT>; 269 clock-names = "xvclk"; 270 pinctrl-names = "default"; 271 pinctrl-0 = <&cam_clkout1>; 272 reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>; 273 pwdn-gpios = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>; 274 power-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>; 275 rockchip,camera-module-index = <0>; 276 rockchip,camera-module-facing = "back"; 277 rockchip,camera-module-name = "TongJu"; 278 rockchip,camera-module-lens-name = "CHT842-MD"; 279 port { 280 ov02k10_out: endpoint { 281 remote-endpoint = <&dphy2_in>; 282 data-lanes = <1 2>; 283 }; 284 }; 285 }; 286}; 287 288&i2s3_2ch { 289 status = "disabled"; 290}; 291 292&mipi_csi2 { 293 status = "okay"; 294 295 ports { 296 #address-cells = <1>; 297 #size-cells = <0>; 298 299 port@0 { 300 reg = <0>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 304 mipi_csi2_input: endpoint@1 { 305 reg = <1>; 306 remote-endpoint = <&dphy2_out>; 307 data-lanes = <1 2>; 308 }; 309 }; 310 311 port@1 { 312 reg = <1>; 313 #address-cells = <1>; 314 #size-cells = <0>; 315 316 mipi_csi2_output: endpoint@0 { 317 reg = <0>; 318 remote-endpoint = <&cif_mipi_in>; 319 data-lanes = <1 2>; 320 }; 321 }; 322 }; 323}; 324 325&video_phy0 { 326 status = "okay"; 327}; 328 329&video_phy1 { 330 status = "disabled"; 331}; 332 333&pcie2x1 { 334 reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>; 335 vpcie3v3-supply = <&vcc3v3_pcie>; 336 status = "disabled"; 337}; 338 339&pdm { 340 status = "disabled"; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pdmm1_clk1 343 &pdmm1_sdi1 344 &pdmm1_sdi2 345 &pdmm1_sdi3>; 346}; 347 348&pdmics { 349 status = "disabled"; 350}; 351 352&pdm_mic_array { 353 status = "disabled"; 354}; 355 356&rkcif { 357 status = "okay"; 358}; 359 360&rkcif_mipi_lvds { 361 status = "okay"; 362 363 port { 364 cif_mipi_in: endpoint { 365 remote-endpoint = <&mipi_csi2_output>; 366 data-lanes = <1 2>; 367 }; 368 }; 369}; 370 371&rkcif_mmu { 372 status = "okay"; 373}; 374 375&rkisp { 376 status = "okay"; 377}; 378 379&rkisp_mmu { 380 status = "okay"; 381}; 382 383&rkisp_vir0 { 384 status = "okay"; 385 386 port { 387 #address-cells = <1>; 388 #size-cells = <0>; 389 390 isp0_in: endpoint@0 { 391 reg = <0>; 392 remote-endpoint = <&dphy1_out>; 393 }; 394 }; 395}; 396 397&route_dsi0 { 398 status = "okay"; 399 connect = <&vp1_out_dsi0>; 400}; 401 402&sdmmc2 { 403 max-frequency = <150000000>; 404 no-sd; 405 no-mmc; 406 bus-width = <4>; 407 disable-wp; 408 cap-sd-highspeed; 409 cap-sdio-irq; 410 keep-power-in-suspend; 411 mmc-pwrseq = <&sdio_pwrseq>; 412 non-removable; 413 pinctrl-names = "default"; 414 pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>; 415 sd-uhs-sdr104; 416 status = "okay"; 417}; 418 419&uart1 { 420 status = "okay"; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&uart1m1_xfer &uart1m1_ctsn>; 423}; 424 425&u2phy1_host { 426 status = "disabled"; 427}; 428 429&u2phy1_otg { 430 status = "disabled"; 431}; 432 433&usb2phy1 { 434 status = "disabled"; 435}; 436 437&usb_host1_ohci { 438 status = "disabled"; 439}; 440 441&vcc3v3_lcd0_n { 442 gpio = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>; 443 enable-active-high; 444}; 445 446&vcc3v3_lcd1_n { 447 gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>; 448 enable-active-high; 449}; 450 451&wireless_bluetooth { 452 uart_rts_gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_LOW>; 453 pinctrl-names = "default", "rts_gpio"; 454 pinctrl-0 = <&uart1m1_rtsn>; 455 pinctrl-1 = <&uart1_gpios>; 456 BT,reset_gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>; 457 BT,wake_gpio = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; 458 BT,wake_host_irq = <&gpio4 RK_PB1 GPIO_ACTIVE_HIGH>; 459 status = "disabled"; 460}; 461 462&wireless_wlan { 463 status = "disabled"; 464 pinctrl-names = "default"; 465 pinctrl-0 = <&wifi_host_wake_irq>; 466 WIFI,host_wake_irq = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; 467}; 468 469&pinctrl { 470 cam { 471 camera_pwr: camera-pwr { 472 rockchip,pins = 473 /* camera power en */ 474 <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 475 }; 476 }; 477 478 headphone { 479 hp_det: hp-det { 480 rockchip,pins = <3 RK_PA1 RK_FUNC_GPIO &pcfg_pull_down>; 481 }; 482 }; 483 484 lcd0 { 485 lcd0_rst_gpio: lcd0-rst-gpio { 486 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 487 }; 488 }; 489 490 lcd1 { 491 lcd1_rst_gpio: lcd1-rst-gpio { 492 rockchip,pins = <4 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>; 493 }; 494 }; 495 496 wireless-wlan { 497 wifi_host_wake_irq: wifi-host-wake-irq { 498 rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>; 499 }; 500 }; 501 502 wireless-bluetooth { 503 uart1_gpios: uart1-gpios { 504 rockchip,pins = <4 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 505 }; 506 }; 507}; 508