1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rk3528-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/phy/phy.h> 11#include <dt-bindings/pinctrl/rockchip.h> 12#include <dt-bindings/power/rk3528-power.h> 13#include <dt-bindings/soc/rockchip,boot-mode.h> 14#include <dt-bindings/soc/rockchip-system-status.h> 15#include <dt-bindings/suspend/rockchip-rk3528.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/display/rockchip-tve.h> 18 19/ { 20 compatible = "rockchip,rk3528"; 21 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 ethernet0 = &gmac0; 28 ethernet1 = &gmac1; 29 gpio0 = &gpio0; 30 gpio1 = &gpio1; 31 gpio2 = &gpio2; 32 gpio3 = &gpio3; 33 gpio4 = &gpio4; 34 i2c0 = &i2c0; 35 i2c1 = &i2c1; 36 i2c2 = &i2c2; 37 i2c3 = &i2c3; 38 i2c4 = &i2c4; 39 i2c5 = &i2c5; 40 i2c6 = &i2c6; 41 i2c7 = &i2c7; 42 serial0 = &uart0; 43 serial1 = &uart1; 44 serial2 = &uart2; 45 serial3 = &uart3; 46 serial4 = &uart4; 47 serial5 = &uart5; 48 serial6 = &uart6; 49 serial7 = &uart7; 50 spi0 = &spi0; 51 spi1 = &spi1; 52 spi2 = &sfc; 53 }; 54 55 clocks { 56 compatible = "simple-bus"; 57 #address-cells = <2>; 58 #size-cells = <2>; 59 ranges; 60 61 xin24m: xin24m { 62 compatible = "fixed-clock"; 63 #clock-cells = <0>; 64 clock-frequency = <24000000>; 65 clock-output-names = "xin24m"; 66 }; 67 68 mclkin_sai0: mclkin-sai0 { 69 compatible = "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <0>; 72 clock-output-names = "i2s0_mclkin"; 73 }; 74 75 mclkin_sai1: mclkin-sai1 { 76 compatible = "fixed-clock"; 77 #clock-cells = <0>; 78 clock-frequency = <0>; 79 clock-output-names = "i2s1_mclkin"; 80 }; 81 82 mclkout_sai0: mclkout-sai0@ff340014 { 83 compatible = "rockchip,clk-out"; 84 reg = <0 0xff340014 0 0x4>; 85 clocks = <&cru MCLK_SAI_I2S0>; 86 #clock-cells = <0>; 87 clock-output-names = "mclk_sai0_to_io"; 88 rockchip,bit-shift = <1>; 89 rockchip,bit-set-to-disable; 90 }; 91 92 mclkout_sai1: mclkout-sai1@ff320004 { 93 compatible = "rockchip,clk-out"; 94 reg = <0 0xff320004 0 0x4>; 95 clocks = <&cru MCLK_SAI_I2S1>; 96 #clock-cells = <0>; 97 clock-output-names = "mclk_sai1_to_io"; 98 rockchip,bit-shift = <14>; 99 rockchip,bit-set-to-disable; 100 }; 101 }; 102 103 cpus { 104 #address-cells = <2>; 105 #size-cells = <0>; 106 107 cpu-map { 108 cluster0 { 109 core0 { 110 cpu = <&cpu0>; 111 }; 112 core1 { 113 cpu = <&cpu1>; 114 }; 115 core2 { 116 cpu = <&cpu2>; 117 }; 118 core3 { 119 cpu = <&cpu3>; 120 }; 121 }; 122 }; 123 124 cpu0: cpu@0 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a53"; 127 reg = <0x0 0x0>; 128 enable-method = "psci"; 129 clocks = <&scmi_clk SCMI_CLK_CPU>; 130 #cooling-cells = <2>; /* min followed by max */ 131 dynamic-power-coefficient = <147>; 132 operating-points-v2 = <&cpu0_opp_table>; 133 cpu-idle-states = <&CPU_SLEEP0>; 134 }; 135 136 cpu1: cpu@1 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a53"; 139 reg = <0x0 0x1>; 140 enable-method = "psci"; 141 clocks = <&scmi_clk SCMI_CLK_CPU>; 142 operating-points-v2 = <&cpu0_opp_table>; 143 cpu-idle-states = <&CPU_SLEEP0>; 144 }; 145 146 cpu2: cpu@2 { 147 device_type = "cpu"; 148 compatible = "arm,cortex-a53"; 149 reg = <0x0 0x2>; 150 enable-method = "psci"; 151 clocks = <&scmi_clk SCMI_CLK_CPU>; 152 operating-points-v2 = <&cpu0_opp_table>; 153 cpu-idle-states = <&CPU_SLEEP1>; 154 }; 155 156 cpu3: cpu@3 { 157 device_type = "cpu"; 158 compatible = "arm,cortex-a53"; 159 reg = <0x0 0x3>; 160 enable-method = "psci"; 161 clocks = <&scmi_clk SCMI_CLK_CPU>; 162 operating-points-v2 = <&cpu0_opp_table>; 163 cpu-idle-states = <&CPU_SLEEP1>; 164 }; 165 166 idle-states { 167 entry-method = "psci"; 168 169 CPU_SLEEP0: cpu-sleep0 { 170 compatible = "arm,idle-state"; 171 local-timer-stop; 172 arm,psci-suspend-param = <0x0010000>; 173 entry-latency-us = <120>; 174 exit-latency-us = <250>; 175 min-residency-us = <900>; 176 status = "disabled"; 177 }; 178 179 CPU_SLEEP1: cpu-sleep { 180 compatible = "arm,idle-state"; 181 local-timer-stop; 182 arm,psci-suspend-param = <0x0010000>; 183 entry-latency-us = <120>; 184 exit-latency-us = <250>; 185 min-residency-us = <900>; 186 status = "okay"; 187 }; 188 }; 189 }; 190 191 cpu0_opp_table: cpu0-opp-table { 192 compatible = "operating-points-v2"; 193 opp-shared; 194 195 mbist-vmin = <825000 925000 975000>; 196 nvmem-cells = <&cpu_leakage>, <&cpu_opp_info>, <&cpu_mbist_vmin>; 197 nvmem-cell-names = "leakage", "opp-info", "mbist-vmin"; 198 199 rockchip,video-4k-freq = <1200000>; 200 rockchip,pvtm-voltage-sel = < 201 0 1320 0 202 1321 1350 1 203 1351 1375 2 204 1376 1405 3 205 1406 1435 4 206 1436 1470 5 207 1471 1505 6 208 1506 1540 7 209 1541 1575 8 210 1576 1610 9 211 1611 1640 10 212 1641 9999 11 213 >; 214 rockchip,pvtm-pvtpll; 215 rockchip,pvtm-offset = <0x18>; 216 rockchip,pvtm-sample-time = <1100>; 217 rockchip,pvtm-freq = <1608000>; 218 rockchip,pvtm-volt = <900000>; 219 rockchip,pvtm-ref-temp = <40>; 220 rockchip,pvtm-temp-prop = <0 0>; 221 rockchip,pvtm-thermal-zone = "soc-thermal"; 222 rockchip,grf = <&grf>; 223 224 opp-408000000 { 225 opp-hz = /bits/ 64 <408000000>; 226 opp-microvolt = <825000 825000 1100000>; 227 opp-microvolt-L0 = <875000 875000 1100000>; 228 opp-microvolt-L1 = <875000 875000 1100000>; 229 opp-microvolt-L2 = <875000 875000 1100000>; 230 opp-microvolt-L3 = <875000 875000 1100000>; 231 opp-microvolt-L4 = <875000 875000 1100000>; 232 opp-microvolt-L5 = <850000 850000 1100000>; 233 clock-latency-ns = <40000>; 234 opp-suspend; 235 }; 236 opp-600000000 { 237 opp-hz = /bits/ 64 <600000000>; 238 opp-microvolt = <825000 825000 1100000>; 239 opp-microvolt-L0 = <875000 875000 1100000>; 240 opp-microvolt-L1 = <875000 875000 1100000>; 241 opp-microvolt-L2 = <875000 875000 1100000>; 242 opp-microvolt-L3 = <875000 875000 1100000>; 243 opp-microvolt-L4 = <875000 875000 1100000>; 244 opp-microvolt-L5 = <850000 850000 1100000>; 245 clock-latency-ns = <40000>; 246 }; 247 opp-816000000 { 248 opp-hz = /bits/ 64 <816000000>; 249 opp-microvolt = <825000 825000 1100000>; 250 opp-microvolt-L0 = <875000 875000 1100000>; 251 opp-microvolt-L1 = <875000 875000 1100000>; 252 opp-microvolt-L2 = <875000 875000 1100000>; 253 opp-microvolt-L3 = <875000 875000 1100000>; 254 opp-microvolt-L4 = <875000 875000 1100000>; 255 opp-microvolt-L5 = <850000 850000 1100000>; 256 clock-latency-ns = <40000>; 257 }; 258 opp-1008000000 { 259 opp-hz = /bits/ 64 <1008000000>; 260 opp-microvolt = <825000 825000 1100000>; 261 opp-microvolt-L0 = <875000 875000 1100000>; 262 opp-microvolt-L1 = <875000 875000 1100000>; 263 opp-microvolt-L2 = <875000 875000 1100000>; 264 opp-microvolt-L3 = <875000 875000 1100000>; 265 opp-microvolt-L4 = <875000 875000 1100000>; 266 opp-microvolt-L5 = <850000 850000 1100000>; 267 clock-latency-ns = <40000>; 268 }; 269 opp-1200000000 { 270 opp-hz = /bits/ 64 <1200000000>; 271 opp-microvolt = <825000 825000 1100000>; 272 opp-microvolt-L0 = <900000 900000 1100000>; 273 opp-microvolt-L1 = <887500 887500 1100000>; 274 opp-microvolt-L2 = <875000 875000 1100000>; 275 opp-microvolt-L3 = <875000 875000 1100000>; 276 opp-microvolt-L4 = <875000 875000 1100000>; 277 opp-microvolt-L5 = <862500 862500 1100000>; 278 opp-microvolt-L6 = <850000 850000 1100000>; 279 clock-latency-ns = <40000>; 280 }; 281 opp-1416000000 { 282 opp-hz = /bits/ 64 <1416000000>; 283 opp-microvolt = <962500 962500 1100000>; 284 opp-microvolt-L1 = <950000 950000 1100000>; 285 opp-microvolt-L2 = <950000 950000 1100000>; 286 opp-microvolt-L3 = <937500 937500 1100000>; 287 opp-microvolt-L4 = <925000 925000 1100000>; 288 opp-microvolt-L5 = <912500 912500 1100000>; 289 opp-microvolt-L6 = <900000 900000 1100000>; 290 opp-microvolt-L7 = <887500 887000 1100000>; 291 opp-microvolt-L8 = <875000 875000 1100000>; 292 opp-microvolt-L9 = <862500 862500 1100000>; 293 opp-microvolt-L10 = <850000 850000 1100000>; 294 opp-microvolt-L11 = <850000 850000 1100000>; 295 clock-latency-ns = <40000>; 296 }; 297 opp-1608000000 { 298 opp-hz = /bits/ 64 <1608000000>; 299 opp-microvolt = <1012500 1012500 1100000>; 300 opp-microvolt-L2 = <1000000 1000000 1100000>; 301 opp-microvolt-L3 = <987500 987500 1100000>; 302 opp-microvolt-L4 = <975000 975000 1100000>; 303 opp-microvolt-L5 = <962500 962500 1100000>; 304 opp-microvolt-L6 = <950000 950000 1100000>; 305 opp-microvolt-L7 = <937500 937500 1100000>; 306 opp-microvolt-L8 = <925000 925000 1100000>; 307 opp-microvolt-L9 = <912500 912500 1100000>; 308 opp-microvolt-L10 = <900000 900000 1100000>; 309 opp-microvolt-L11 = <887500 887500 1100000>; 310 clock-latency-ns = <40000>; 311 }; 312 opp-1800000000 { 313 opp-hz = /bits/ 64 <1800000000>; 314 opp-microvolt = <1062500 1062500 1100000>; 315 opp-microvolt-L1 = <1050000 1050000 1100000>; 316 opp-microvolt-L2 = <1037500 1037500 1100000>; 317 opp-microvolt-L3 = <1025000 1025000 1100000>; 318 opp-microvolt-L4 = <1012500 1012500 1100000>; 319 opp-microvolt-L5 = <1000000 1000000 1100000>; 320 opp-microvolt-L6 = <987500 987500 1100000>; 321 opp-microvolt-L7 = <975000 975000 1100000>; 322 opp-microvolt-L8 = <962500 962500 1100000>; 323 opp-microvolt-L9 = <950000 950000 1100000>; 324 opp-microvolt-L10 = <937500 937500 1100000>; 325 opp-microvolt-L11 = <925000 925000 1100000>; 326 clock-latency-ns = <40000>; 327 }; 328 opp-2016000000 { 329 opp-hz = /bits/ 64 <2016000000>; 330 opp-microvolt = <1100000 1100000 1100000>; 331 opp-microvolt-L1 = <1087500 1087500 1100000>; 332 opp-microvolt-L2 = <1075000 1075000 1100000>; 333 opp-microvolt-L3 = <1062500 1062500 1100000>; 334 opp-microvolt-L4 = <1050000 1050000 1100000>; 335 opp-microvolt-L5 = <1037500 1037500 1100000>; 336 opp-microvolt-L6 = <1025000 1025000 1100000>; 337 opp-microvolt-L7 = <1012500 1012500 1100000>; 338 opp-microvolt-L8 = <1000000 1000000 1100000>; 339 opp-microvolt-L9 = <987500 987500 1100000>; 340 opp-microvolt-L10 = <975000 975000 1100000>; 341 opp-microvolt-L11 = <962500 962500 1100000>; 342 clock-latency-ns = <40000>; 343 }; 344 }; 345 346 arm-pmu { 347 compatible = "arm,cortex-a53-pmu"; 348 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 349 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 352 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 353 }; 354 355 cpuinfo { 356 compatible = "rockchip,cpuinfo"; 357 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 358 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 359 }; 360 361 display_subsystem: display-subsystem { 362 compatible = "rockchip,display-subsystem"; 363 ports = <&vop_out>; 364 status = "disabled"; 365 }; 366 367 dmc: dmc { 368 compatible = "rockchip,rk3528-dmc"; 369 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 370 interrupt-names = "complete"; 371 devfreq-events = <&dfi>; 372 clocks = <&scmi_clk SCMI_CLK_DDR>; 373 clock-names = "dmc_clk"; 374 operating-points-v2 = <&dmc_opp_table>; 375 upthreshold = <40>; 376 downdifferential = <20>; 377 system-status-level = < 378 /* system status freq level */ 379 SYS_STATUS_NORMAL DMC_FREQ_LEVEL_HIGH 380 >; 381 auto-min-freq = <324000>; 382 auto-freq-en = <0>; 383 status = "disabled"; 384 }; 385 386 dmc_opp_table: dmc-opp-table { 387 compatible = "operating-points-v2"; 388 389 mbist-vmin = <850000 900000>; 390 nvmem-cells = <&log_leakage>, <&dmc_opp_info>, <&logic_mbist_vmin>; 391 nvmem-cell-names = "leakage", "opp-info", "mbist-vmin"; 392 393 rockchip,temp-hysteresis = <5000>; 394 rockchip,low-temp = <10000>; 395 rockchip,low-temp-min-volt = <900000>; 396 397 rockchip,leakage-voltage-sel = < 398 1 10 0 399 11 14 1 400 15 22 2 401 23 28 3 402 29 254 4 403 >; 404 405 opp-920000000 { 406 opp-hz = /bits/ 64 <920000000>; 407 opp-microvolt = <850000 850000 1000000>; 408 }; 409 opp-1056000000 { 410 opp-hz = /bits/ 64 <1056000000>; 411 opp-microvolt = <850000 850000 1000000>; 412 opp-microvolt-L0 = <875000 875000 1000000>; 413 opp-microvolt-L1 = <850000 850000 1000000>; 414 opp-microvolt-L2 = <850000 850000 1000000>; 415 opp-microvolt-L3 = <850000 850000 1000000>; 416 opp-microvolt-L4 = <850000 850000 1000000>; 417 }; 418 opp-1184000000 { 419 opp-hz = /bits/ 64 <1184000000>; 420 opp-microvolt = <900000 900000 1000000>; 421 opp-microvolt-L0 = <950000 950000 1000000>; 422 opp-microvolt-L1 = <925000 925000 1000000>; 423 opp-microvolt-L2 = <900000 900000 1000000>; 424 opp-microvolt-L3 = <875000 875000 1000000>; 425 opp-microvolt-L4 = <862500 862500 1000000>; 426 status = "disabled"; 427 }; 428 }; 429 430 firmware { 431 scmi: scmi { 432 compatible = "arm,scmi-smc"; 433 shmem = <&scmi_shmem>; 434 arm,smc-id = <0x82000010>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 438 scmi_clk: protocol@14 { 439 reg = <0x14>; 440 #clock-cells = <1>; 441 442 assigned-clocks = <&scmi_clk SCMI_CLK_CPU>; 443 assigned-clock-rates = <1200000000>; 444 }; 445 }; 446 }; 447 448 mpp_srv: mpp-srv { 449 compatible = "rockchip,mpp-service"; 450 rockchip,taskqueue-count = <5>; 451 rockchip,resetgroup-count = <5>; 452 status = "disabled"; 453 }; 454 455 psci { 456 compatible = "arm,psci-1.0"; 457 method = "smc"; 458 }; 459 460 rkvtunnel: rkvtunnel { 461 compatible = "rockchip,video-tunnel"; 462 status = "disabled"; 463 }; 464 465 rockchip_suspend: rockchip-suspend { 466 compatible = "rockchip,pm-rk3528"; 467 status = "disabled"; 468 rockchip,sleep-debug-en = <0>; 469 rockchip,sleep-mode-config = < 470 (0 471 | RKPM_SLP_ARMPD 472 ) 473 >; 474 rockchip,wakeup-config = < 475 (0 476 | RKPM_CPU0_WKUP_EN 477 | RKPM_GPIO_WKUP_EN 478 ) 479 >; 480 }; 481 482 rockchip_system_monitor: rockchip-system-monitor { 483 compatible = "rockchip,system-monitor"; 484 485 rockchip,thermal-zone = "soc-thermal"; 486 rockchip,polling-delay = <200>; /* milliseconds */ 487 rockchip,temp-hysteresis = <5000>; /* millicelsius */ 488 rockchip,offline-cpu-temp = <105000>; /* millicelsius */ 489 rockchip,temp-offline-cpus = "2-3"; 490 }; 491 492 secure_otp: secure-otp { 493 compatible = "rockchip,secure-otp"; 494 rockchip,otp-size = <32>; 495 status = "disabled"; 496 }; 497 498 thermal_zones: thermal-zones { 499 soc_thermal: soc-thermal { 500 polling-delay-passive = <20>; /* milliseconds */ 501 polling-delay = <1000>; /* milliseconds */ 502 sustainable-power = <638>; /* milliwatts */ 503 504 thermal-sensors = <&tsadc 0>; 505 506 trips { 507 threshold: trip-point-0 { 508 temperature = <95000>; 509 hysteresis = <2000>; 510 type = "passive"; 511 }; 512 target: trip-point-1 { 513 temperature = <110000>; 514 hysteresis = <2000>; 515 type = "passive"; 516 }; 517 soc_crit: soc-crit { 518 temperature = <120000>; /* millicelsius */ 519 hysteresis = <2000>; /* millicelsius */ 520 type = "critical"; 521 }; 522 }; 523 524 cooling-maps { 525 map0 { 526 trip = <&target>; 527 cooling-device = 528 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 529 contribution = <1024>; 530 }; 531 map1 { 532 trip = <&target>; 533 cooling-device = 534 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 535 contribution = <1024>; 536 }; 537 }; 538 539 }; 540 }; 541 542 timer { 543 compatible = "arm,armv8-timer"; 544 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 545 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 546 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 547 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 548 }; 549 550 scmi_shmem: scmi-shmem@10f000 { 551 compatible = "arm,scmi-shmem"; 552 reg = <0x0 0x0010f000 0x0 0x100>; 553 }; 554 555 sram: sram@fe480000 { 556 compatible = "mmio-sram"; 557 reg = <0x0 0xfe480000 0x0 0xc000>; 558 559 #address-cells = <1>; 560 #size-cells = <1>; 561 ranges = <0x0 0x0 0xfe480000 0xc000>; 562 563 /* start address and size should be 4k algin */ 564 rkvdec_sram: rkvdec-sram@0 { 565 reg = <0x0 0xc000>; 566 }; 567 }; 568 569 pcie2x1: pcie@fe4f0000 { 570 compatible = "rockchip,rk3528-pcie", "snps,dw-pcie"; 571 #address-cells = <3>; 572 #size-cells = <2>; 573 bus-range = <0x0 0xff>; 574 clocks = <&cru ACLK_PCIE>, <&cru HCLK_PCIE_SLV>, 575 <&cru HCLK_PCIE_DBI>, <&cru PCLK_CRU_PCIE>, 576 <&cru CLK_PCIE_AUX>, <&cru PCLK_PCIE>, 577 <&cru PCLK_PCIE_PHY>; 578 clock-names = "aclk", "hclk_slv", 579 "hclk_dbi", "pclk_cru", 580 "aux", "pclk", 581 "pipe"; 582 device_type = "pci"; 583 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 584 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 589 interrupt-names = "msi", "pmc", "sys", "legacy", "msg", "err"; 590 #interrupt-cells = <1>; 591 interrupt-map-mask = <0 0 0 7>; 592 interrupt-map = <0 0 0 1 &pcie2x1_intc 0>, 593 <0 0 0 2 &pcie2x1_intc 1>, 594 <0 0 0 3 &pcie2x1_intc 2>, 595 <0 0 0 4 &pcie2x1_intc 3>; 596 linux,pci-domain = <0>; 597 num-ib-windows = <8>; 598 num-ob-windows = <8>; 599 num-viewport = <4>; 600 max-link-speed = <2>; 601 num-lanes = <1>; 602 phys = <&combphy_pu PHY_TYPE_PCIE>; 603 phy-names = "pcie-phy"; 604 ranges = <0x00000800 0x0 0xfc000000 0x0 0xfc000000 0x0 0x100000 605 0x81000000 0x0 0xfc100000 0x0 0xfc100000 0x0 0x100000 606 0x82000000 0x0 0xfc200000 0x0 0xfc200000 0x0 0x1e00000 607 0xc3000000 0x1 0x00000000 0x1 0x00000000 0x0 0x40000000>; 608 reg = <0x0 0xfe4f0000 0x0 0x10000>, 609 <0x1 0x40000000 0x0 0x400000>; 610 reg-names = "pcie-apb", "pcie-dbi"; 611 resets = <&cru SRST_RESETN_PCIE_POWER_UP>, <&cru SRST_PRESETN_PCIE>, 612 <&cru SRST_PRESETN_CRU_PCIE>; 613 reset-names = "pcie", "periph", "preset_cru"; 614 status = "disabled"; 615 616 pcie2x1_intc: legacy-interrupt-controller { 617 interrupt-controller; 618 #address-cells = <0>; 619 #interrupt-cells = <1>; 620 interrupt-parent = <&gic>; 621 interrupts = <GIC_SPI 155 IRQ_TYPE_EDGE_RISING>; 622 }; 623 }; 624 625 usbdrd30: usbdrd { 626 compatible = "rockchip,rk3528-dwc3", "rockchip,rk3399-dwc3"; 627 clocks = <&cru CLK_REF_USB3OTG>, <&cru CLK_SUSPEND_USB3OTG>, 628 <&cru ACLK_USB3OTG>; 629 clock-names = "ref_clk", "suspend_clk", 630 "bus_clk"; 631 #address-cells = <2>; 632 #size-cells = <2>; 633 ranges; 634 status = "disabled"; 635 636 usbdrd_dwc3: dwc3@fe500000 { 637 compatible = "snps,dwc3"; 638 reg = <0x0 0xfe500000 0x0 0x400000>; 639 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 640 dr_mode = "otg"; 641 phys = <&u2phy_otg>, <&combphy_pu PHY_TYPE_USB3>; 642 phy-names = "usb2-phy", "usb3-phy"; 643 phy_type = "utmi_wide"; 644 resets = <&cru SRST_ARESETN_USB3OTG>; 645 reset-names = "usb3-otg"; 646 snps,dis_enblslpm_quirk; 647 snps,dis-u1u2-quirk; 648 snps,dis-u2-freeclk-exists-quirk; 649 snps,dis-del-phy-power-chg-quirk; 650 snps,dis-tx-ipgap-linecheck-quirk; 651 snps,xhci-trb-ent-quirk; 652 snps,dis_rxdet_inp3_quirk; 653 quirk-skip-phy-init; 654 status = "disabled"; 655 }; 656 }; 657 658 gic: interrupt-controller@fed01000 { 659 compatible = "arm,gic-400"; 660 #interrupt-cells = <3>; 661 #address-cells = <0>; 662 interrupt-controller; 663 reg = <0x0 0xfed01000 0 0x1000>, 664 <0x0 0xfed02000 0 0x2000>, 665 <0x0 0xfed04000 0 0x2000>, 666 <0x0 0xfed06000 0 0x2000>; 667 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 668 }; 669 670 usb_host0_ehci: usb@ff100000 { 671 compatible = "generic-ehci"; 672 reg = <0x0 0xff100000 0x0 0x40000>; 673 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&cru HCLK_USBHOST>, 675 <&cru HCLK_USBHOST_ARB>, 676 <&usb2phy>; 677 clock-names = "usbhost", "arbiter", "utmi"; 678 phys = <&u2phy_host>; 679 phy-names = "usb2-phy"; 680 status = "disabled"; 681 }; 682 683 usb_host0_ohci: usb@ff140000 { 684 compatible = "generic-ohci"; 685 reg = <0x0 0xff140000 0x0 0x40000>; 686 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 687 clocks = <&cru HCLK_USBHOST>, 688 <&cru HCLK_USBHOST_ARB>, 689 <&usb2phy>; 690 clock-names = "usbhost", "arbiter", "utmi"; 691 phys = <&u2phy_host>; 692 phy-names = "usb2-phy"; 693 status = "disabled"; 694 }; 695 696 debug: debug@ff190000 { 697 compatible = "rockchip,debug"; 698 reg = <0x0 0xff190000 0x0 0x1000>, 699 <0x0 0xff192000 0x0 0x1000>, 700 <0x0 0xff194000 0x0 0x1000>, 701 <0x0 0xff196000 0x0 0x1000>; 702 }; 703 704 qos_crypto_a: qos@ff200000 { 705 compatible = "syscon"; 706 reg = <0x0 0xff200000 0x0 0x20>; 707 }; 708 709 qos_crypto_p: qos@ff200080 { 710 compatible = "syscon"; 711 reg = <0x0 0xff200080 0x0 0x20>; 712 }; 713 714 qos_dcf: qos@ff200100 { 715 compatible = "syscon"; 716 reg = <0x0 0xff200100 0x0 0x20>; 717 }; 718 719 qos_dft2apb: qos@ff200200 { 720 compatible = "syscon"; 721 reg = <0x0 0xff200200 0x0 0x20>; 722 }; 723 724 qos_dma2ddr: qos@ff200280 { 725 compatible = "syscon"; 726 reg = <0x0 0xff200280 0x0 0x20>; 727 }; 728 729 qos_dmac: qos@ff200300 { 730 compatible = "syscon"; 731 reg = <0x0 0xff200300 0x0 0x20>; 732 }; 733 734 qos_keyreader: qos@ff200380 { 735 compatible = "syscon"; 736 reg = <0x0 0xff200380 0x0 0x20>; 737 }; 738 739 qos_cpu: qos@ff210000 { 740 compatible = "syscon"; 741 reg = <0x0 0xff210000 0x0 0x20>; 742 }; 743 744 qos_debug: qos@ff210080 { 745 compatible = "syscon"; 746 reg = <0x0 0xff210080 0x0 0x20>; 747 }; 748 749 qos_gpu_m0: qos@ff220000 { 750 compatible = "syscon"; 751 reg = <0x0 0xff220000 0x0 0x20>; 752 }; 753 754 qos_gpu_m1: qos@ff220080 { 755 compatible = "syscon"; 756 reg = <0x0 0xff220080 0x0 0x20>; 757 }; 758 759 qos_pmu_mcu: qos@ff240000 { 760 compatible = "syscon"; 761 reg = <0x0 0xff240000 0x0 0x20>; 762 }; 763 764 qos_rkvdec: qos@ff250000 { 765 compatible = "syscon"; 766 reg = <0x0 0xff250000 0x0 0x20>; 767 }; 768 769 qos_rkvenc: qos@ff260000 { 770 compatible = "syscon"; 771 reg = <0x0 0xff260000 0x0 0x20>; 772 }; 773 774 qos_gmac0: qos@ff270000 { 775 compatible = "syscon"; 776 reg = <0x0 0xff270000 0x0 0x20>; 777 }; 778 779 qos_hdcp: qos@ff270080 { 780 compatible = "syscon"; 781 reg = <0x0 0xff270080 0x0 0x20>; 782 }; 783 784 qos_jpegdec: qos@ff270100 { 785 compatible = "syscon"; 786 reg = <0x0 0xff270100 0x0 0x20>; 787 }; 788 789 qos_rga2_m0ro: qos@ff270200 { 790 compatible = "syscon"; 791 reg = <0x0 0xff270200 0x0 0x20>; 792 }; 793 794 qos_rga2_m0wo: qos@ff270280 { 795 compatible = "syscon"; 796 reg = <0x0 0xff270280 0x0 0x20>; 797 }; 798 799 qos_sdmmc0: qos@ff270300 { 800 compatible = "syscon"; 801 reg = <0x0 0xff270300 0x0 0x20>; 802 }; 803 804 qos_usb2host: qos@ff270380 { 805 compatible = "syscon"; 806 reg = <0x0 0xff270380 0x0 0x20>; 807 }; 808 809 qos_vdpp: qos@ff270480 { 810 compatible = "syscon"; 811 reg = <0x0 0xff270480 0x0 0x20>; 812 }; 813 814 qos_vop: qos@ff270500 { 815 compatible = "syscon"; 816 reg = <0x0 0xff270500 0x0 0x20>; 817 }; 818 819 qos_emmc: qos@ff280000 { 820 compatible = "syscon"; 821 reg = <0x0 0xff280000 0x0 0x20>; 822 }; 823 824 qos_fspi: qos@ff280080 { 825 compatible = "syscon"; 826 reg = <0x0 0xff280080 0x0 0x20>; 827 }; 828 829 qos_gmac1: qos@ff280100 { 830 compatible = "syscon"; 831 reg = <0x0 0xff280100 0x0 0x20>; 832 }; 833 834 qos_pcie: qos@ff280180 { 835 compatible = "syscon"; 836 reg = <0x0 0xff280180 0x0 0x20>; 837 }; 838 839 qos_sdio0: qos@ff280200 { 840 compatible = "syscon"; 841 reg = <0x0 0xff280200 0x0 0x20>; 842 }; 843 844 qos_sdio1: qos@ff280280 { 845 compatible = "syscon"; 846 reg = <0x0 0xff280280 0x0 0x20>; 847 }; 848 849 qos_tsp: qos@ff280300 { 850 compatible = "syscon"; 851 reg = <0x0 0xff280300 0x0 0x20>; 852 }; 853 854 qos_usb3otg: qos@ff280380 { 855 compatible = "syscon"; 856 reg = <0x0 0xff280380 0x0 0x20>; 857 }; 858 859 qos_vpu: qos@ff280400 { 860 compatible = "syscon"; 861 reg = <0x0 0xff280400 0x0 0x20>; 862 }; 863 864 /* 865 * Merge all GRF, each independent GRF offset is shown as bellow: 866 * CORE_GRF: 0xff300000 867 * GPU_GRF: 0xff310000 868 * RKVENC_GRF: 0xff320000 869 * DDR_GRF: 0xff330000 870 * VPU_GRF: 0xff340000 871 * COMBO_PIPE_PHY_GRF: 0xff348000 872 * RKVDEC_GRF: 0xff350000 873 * VO_GRF: 0xff360000 874 * PMU_GRF: 0xff370000 875 * SYS_GRF: 0xff380000 876 */ 877 grf: syscon@ff300000 { 878 compatible = "rockchip,rk3528-grf", "syscon", "simple-mfd"; 879 reg = <0x0 0xff300000 0x0 0x90000>; 880 881 grf_cru: grf-clock-controller { 882 compatible = "rockchip,rk3528-grf-cru"; 883 #clock-cells = <1>; 884 }; 885 886 reboot_mode: reboot-mode { 887 compatible = "syscon-reboot-mode"; 888 offset = <0x70200>; 889 mode-bootloader = <BOOT_BL_DOWNLOAD>; 890 mode-charge = <BOOT_CHARGING>; 891 mode-fastboot = <BOOT_FASTBOOT>; 892 mode-loader = <BOOT_BL_DOWNLOAD>; 893 mode-normal = <BOOT_NORMAL>; 894 mode-recovery = <BOOT_RECOVERY>; 895 mode-ums = <BOOT_UMS>; 896 mode-panic = <BOOT_PANIC>; 897 mode-watchdog = <BOOT_WATCHDOG>; 898 }; 899 }; 900 901 cru: clock-controller@ff4a0000 { 902 compatible = "rockchip,rk3528-cru"; 903 reg = <0x0 0xff4a0000 0x0 0x30000>; 904 rockchip,grf = <&grf>; 905 #clock-cells = <1>; 906 #reset-cells = <1>; 907 908 assigned-clocks = 909 <&cru XIN_OSC0_DIV>, 910 <&cru PLL_GPLL>, 911 <&cru PLL_PPLL>, 912 <&cru PLL_CPLL>, 913 <&cru CLK_MATRIX_250M_SRC>, 914 <&cru CLK_MATRIX_500M_SRC>, 915 <&cru CLK_MATRIX_50M_SRC>, 916 <&cru CLK_MATRIX_100M_SRC>, 917 <&cru CLK_MATRIX_150M_SRC>, 918 <&cru CLK_MATRIX_200M_SRC>, 919 <&cru CLK_MATRIX_300M_SRC>, 920 <&cru CLK_MATRIX_339M_SRC>, 921 <&cru CLK_MATRIX_400M_SRC>, 922 <&cru CLK_MATRIX_600M_SRC>, 923 <&cru CLK_PPLL_50M_MATRIX>, 924 <&cru CLK_PPLL_100M_MATRIX>, 925 <&cru CLK_PPLL_125M_MATRIX>, 926 <&cru ACLK_BUS_VOPGL_ROOT>, 927 <&cru ACLK_VO_ROOT>, 928 <&cru ACLK_VPU_ROOT>, 929 <&cru ACLK_VPU_L_ROOT>; 930 931 assigned-clock-rates = 932 <32768>, 933 <1188000000>, 934 <1000000000>, 935 <996000000>, 936 <250000000>, 937 <500000000>, 938 <50000000>, 939 <100000000>, 940 <150000000>, 941 <200000000>, 942 <300000000>, 943 <340000000>, 944 <400000000>, 945 <600000000>, 946 <50000000>, 947 <100000000>, 948 <125000000>, 949 <500000000>, 950 <340000000>, 951 <300000000>, 952 <200000000>; 953 }; 954 955 ioc_grf: syscon@ff540000 { 956 compatible = "rockchip,rk3528-ioc-grf", "syscon"; 957 reg = <0x0 0xff540000 0x0 0x40000>; 958 }; 959 960 pmu: power-management@ff600000 { 961 compatible = "rockchip,rk3528-pmu", "syscon", "simple-mfd"; 962 reg = <0x0 0xff600000 0x0 0x2000>; 963 964 power: power-controller { 965 compatible = "rockchip,rk3528-power-controller"; 966 #power-domain-cells = <1>; 967 #address-cells = <1>; 968 #size-cells = <0>; 969 status = "okay"; 970 971 /* These power domains are grouped by VD_GPU */ 972 pd_gpu@RK3528_PD_GPU { 973 reg = <RK3528_PD_GPU>; 974 clocks = <&cru ACLK_GPU_MALI>, 975 <&cru PCLK_GPU_ROOT>; 976 pm_qos = <&qos_gpu_m0>, 977 <&qos_gpu_m1>; 978 }; 979 /* These power domains are grouped by VD_LOGIC */ 980 pd_rkvdec@RK3528_PD_RKVDEC { 981 reg = <RK3528_PD_RKVDEC>; 982 }; 983 pd_rkvenc@RK3528_PD_RKVENC { 984 reg = <RK3528_PD_RKVENC>; 985 }; 986 pd_vo@RK3528_PD_VO { 987 reg = <RK3528_PD_VO>; 988 }; 989 pd_vpu@RK3528_PD_VPU { 990 reg = <RK3528_PD_VPU>; 991 }; 992 }; 993 }; 994 995 mailbox: mailbox@ff630000 { 996 compatible = "rockchip,rk3528-mailbox", 997 "rockchip,rk3368-mailbox"; 998 reg = <0x0 0xff630000 0x0 0x200>; 999 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&cru PCLK_PMU_MAILBOX>; 1001 clock-names = "pclk_mailbox"; 1002 #mbox-cells = <1>; 1003 status = "disabled"; 1004 }; 1005 1006 gpu: gpu@ff700000 { 1007 compatible = "arm,mali-450"; 1008 reg = <0x0 0xff700000 0x0 0x40000>; 1009 1010 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1011 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1012 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 1013 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1017 interrupt-names = "Mali_GP_IRQ", 1018 "Mali_GP_MMU_IRQ", 1019 "IRQPP", 1020 "Mali_PP0_IRQ", 1021 "Mali_PP0_MMU_IRQ", 1022 "Mali_PP1_IRQ", 1023 "Mali_PP1_MMU_IRQ"; 1024 clocks = <&scmi_clk SCMI_CLK_GPU>, <&cru ACLK_GPU_MALI>, 1025 <&cru PCLK_GPU_ROOT>; 1026 clock-names = "clk_mali", "aclk_gpu_mali", "pclk_gpu"; 1027 assigned-clocks = <&scmi_clk SCMI_CLK_GPU>; 1028 assigned-clock-rates = <300000000>; 1029 power-domains = <&power RK3528_PD_GPU>; 1030 operating-points-v2 = <&gpu_opp_table>; 1031 #cooling-cells = <2>; 1032 rockchip,grf = <&grf>; 1033 status = "disabled"; 1034 1035 gpu_power_model: power-model { 1036 compatible = "simple-power-model"; 1037 leakage-range= <1 3>; 1038 ls = <(-15658) 67354 0>; 1039 static-coefficient = <10000>; 1040 dynamic-coefficient = <724>; 1041 ts = <3156546 120154 (-2506) 39>; 1042 thermal-zone = "soc-thermal"; 1043 }; 1044 }; 1045 1046 gpu_opp_table: gpu-opp-table { 1047 compatible = "operating-points-v2"; 1048 1049 mbist-vmin = <825000 925000>; 1050 nvmem-cells = <&gpu_leakage>, <&gpu_opp_info>, <&gpu_mbist_vmin>; 1051 nvmem-cell-names = "leakage", "opp-info", "mbist-vmin"; 1052 1053 rockchip,pvtm-voltage-sel = < 1054 0 750 0 1055 751 770 1 1056 771 790 2 1057 791 810 3 1058 811 830 4 1059 831 850 5 1060 851 870 6 1061 871 890 7 1062 891 9999 8 1063 >; 1064 rockchip,pvtm-pvtpll; 1065 rockchip,pvtm-offset = <0x10018>; 1066 rockchip,pvtm-sample-time = <1100>; 1067 rockchip,pvtm-freq = <800000>; 1068 rockchip,pvtm-volt = <900000>; 1069 rockchip,pvtm-ref-temp = <40>; 1070 rockchip,pvtm-temp-prop = <0 0>; 1071 rockchip,pvtm-thermal-zone = "soc-thermal"; 1072 rockchip,grf = <&grf>; 1073 1074 opp-300000000 { 1075 opp-hz = /bits/ 64 <300000000>; 1076 opp-microvolt = <875000 875000 1000000>; 1077 opp-microvolt-L5 = <850000 850000 1000000>; 1078 opp-microvolt-L6 = <837500 837500 1000000>; 1079 opp-microvolt-L7 = <825000 825000 1000000>; 1080 opp-microvolt-L8 = <825000 825000 1000000>; 1081 }; 1082 opp-500000000 { 1083 opp-hz = /bits/ 64 <500000000>; 1084 opp-microvolt = <875000 875000 1000000>; 1085 opp-microvolt-L5 = <850000 850000 1000000>; 1086 opp-microvolt-L6 = <837500 837500 1000000>; 1087 opp-microvolt-L7 = <825000 825000 1000000>; 1088 opp-microvolt-L8 = <825000 825000 1000000>; 1089 }; 1090 opp-600000000 { 1091 opp-hz = /bits/ 64 <600000000>; 1092 opp-microvolt = <875000 875000 1000000>; 1093 opp-microvolt-L5 = <850000 850000 1000000>; 1094 opp-microvolt-L6 = <837500 837500 1000000>; 1095 opp-microvolt-L7 = <825000 825000 1000000>; 1096 opp-microvolt-L8 = <825000 825000 1000000>; 1097 }; 1098 opp-700000000 { 1099 opp-hz = /bits/ 64 <700000000>; 1100 opp-microvolt = <900000 900000 1000000>; 1101 opp-microvolt-L1 = <887500 887500 1000000>; 1102 opp-microvolt-L2 = <875000 875000 1000000>; 1103 opp-microvolt-L3 = <875000 875000 1000000>; 1104 opp-microvolt-L4 = <875000 875000 1000000>; 1105 opp-microvolt-L5 = <850000 850000 1000000>; 1106 opp-microvolt-L6 = <837500 837500 1000000>; 1107 opp-microvolt-L7 = <825000 825000 1000000>; 1108 opp-microvolt-L8 = <825000 825000 1000000>; 1109 clock-latency-ns = <40000>; 1110 }; 1111 opp-800000000 { 1112 opp-hz = /bits/ 64 <800000000>; 1113 opp-microvolt = <950000 950000 1000000>; 1114 opp-microvolt-L1 = <937500 937500 1000000>; 1115 opp-microvolt-L2 = <925000 925000 1000000>; 1116 opp-microvolt-L3 = <912500 912500 1000000>; 1117 opp-microvolt-L4 = <900000 900000 1000000>; 1118 opp-microvolt-L5 = <887500 887500 1000000>; 1119 opp-microvolt-L6 = <875000 875000 1000000>; 1120 opp-microvolt-L7 = <862500 862500 1000000>; 1121 opp-microvolt-L8 = <850000 850000 1000000>; 1122 clock-latency-ns = <40000>; 1123 }; 1124 }; 1125 1126 gpu_bus: gpu-bus { 1127 compatible = "rockchip,rk3528-bus"; 1128 rockchip,busfreq-policy = "clkfreq"; 1129 clocks = <&scmi_clk SCMI_CLK_GPU>; 1130 clock-names = "bus"; 1131 operating-points-v2 = <&gpu_bus_opp_table>; 1132 status = "disabled"; 1133 }; 1134 1135 gpu_bus_opp_table: gpu-bus-opp-table { 1136 compatible = "operating-points-v2"; 1137 1138 nvmem-cells = <&log_leakage>; 1139 nvmem-cell-names = "leakage"; 1140 1141 rockchip,leakage-voltage-sel = < 1142 1 22 0 1143 23 254 1 1144 >; 1145 1146 opp-700000000 { 1147 opp-hz = /bits/ 64 <700000000>; 1148 opp-microvolt = <850000 850000 1000000>; 1149 }; 1150 opp-800000000 { 1151 opp-hz = /bits/ 64 <800000000>; 1152 opp-microvolt = <875000 875000 1000000>; 1153 opp-microvolt-L1 = <850000 850000 1000000>; 1154 }; 1155 }; 1156 1157 rkvdec: rkvdec@ff740100 { 1158 compatible = "rockchip,rkv-decoder-rk3528", "rockchip,rkv-decoder-v2"; 1159 reg = <0x0 0xff740100 0x0 0x400>, <0x0 0xff740000 0x0 0x100>; 1160 reg-names = "regs", "link"; 1161 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 1162 interrupt-names = "irq_dec"; 1163 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 1164 clock-names = "aclk_vcodec", "hclk_vcodec","clk_hevc_cabac"; 1165 rockchip,normal-rates = <340000000>, <0>, <600000000>; 1166 assigned-clocks = <&cru ACLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 1167 assigned-clock-rates = <340000000>, <600000000>; 1168 resets = <&cru SRST_ARESETN_RKVDEC>, <&cru SRST_HRESETN_RKVDEC>, 1169 <&cru SRST_RESETN_HEVC_CA_RKVDEC>; 1170 reset-names = "video_a", "video_h", "video_hevc_cabac"; 1171 iommus = <&rkvdec_mmu>; 1172 rockchip,srv = <&mpp_srv>; 1173 rockchip,taskqueue-node = <0>; 1174 rockchip,resetgroup-node = <0>; 1175 rockchip,task-capacity = <16>; 1176 rockchip,sram = <&rkvdec_sram>; 1177 /* rcb_iova: start and size */ 1178 rockchip,rcb-iova = <0x10000000 65536>; 1179 rockchip,rcb-min-width = <512>; 1180 status = "disabled"; 1181 }; 1182 1183 rkvdec_mmu: iommu@ff740800 { 1184 compatible = "rockchip,iommu-v2"; 1185 reg = <0x0 0xff740800 0x0 0x40>, <0x0 0xff740900 0x0 0x40>; 1186 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1187 interrupt-names = "rkvdec_mmu"; 1188 clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>, <&cru CLK_HEVC_CA_RKVDEC>; 1189 clock-names = "aclk", "iface", "clk_hevc_cabac"; 1190 #iommu-cells = <0>; 1191 rockchip,shootdown-entire; 1192 status = "disabled"; 1193 }; 1194 1195 rkvenc: rkvenc@ff780000 { 1196 compatible = "rockchip,rkv-encoder-rk3528", "rockchip,rkv-encoder-v2"; 1197 reg = <0x0 0xff780000 0x0 0x6000>; 1198 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1199 interrupt-names = "irq_rkvenc"; 1200 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>, <&cru CLK_CORE_RKVENC>; 1201 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1202 rockchip,normal-rates = <300000000>, <0>, <300000000>; 1203 resets = <&cru SRST_ARESETN_RKVENC>, <&cru SRST_HRESETN_RKVENC>, 1204 <&cru SRST_RESETN_CORE_RKVENC>; 1205 reset-names = "video_a", "video_h", "video_core"; 1206 assigned-clocks = <&cru ACLK_RKVENC>, <&cru CLK_CORE_RKVENC>; 1207 assigned-clock-rates = <300000000>, <300000000>; 1208 iommus = <&rkvenc_mmu>; 1209 rockchip,srv = <&mpp_srv>; 1210 rockchip,grf = <&grf>; 1211 rockchip,grf-mem-offset = <0x20010>; 1212 rockchip,grf-mem-values = <0x00000021>, <0xffff0021>; 1213 rockchip,taskqueue-node = <1>; 1214 rockchip,resetgroup-node = <1>; 1215 status = "disabled"; 1216 }; 1217 1218 rkvenc_mmu: iommu@ff78f000 { 1219 compatible = "rockchip,iommu-v2"; 1220 reg = <0x0 0xff78f000 0x0 0x40>; 1221 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1222 interrupt-names = "rkvenc_mmu"; 1223 clocks = <&cru ACLK_RKVENC>, <&cru HCLK_RKVENC>; 1224 clock-names = "aclk", "iface"; 1225 #iommu-cells = <0>; 1226 rockchip,shootdown-entire; 1227 status = "disabled"; 1228 }; 1229 1230 vdpu: vdpu@ff7c0400 { 1231 compatible = "rockchip,vpu-decoder-v2"; 1232 reg = <0x0 0xff7c0400 0x0 0x400>; 1233 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1234 interrupt-names = "irq_dec"; 1235 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1236 clock-names = "aclk_vcodec", "hclk_vcodec"; 1237 rockchip,normal-rates = <300000000>, <0>; 1238 assigned-clocks = <&cru ACLK_VPU>; 1239 assigned-clock-rates = <300000000>; 1240 resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>; 1241 reset-names = "shared_video_a", "shared_video_h"; 1242 iommus = <&vdpu_mmu>; 1243 rockchip,srv = <&mpp_srv>; 1244 rockchip,grf = <&grf>; 1245 rockchip,grf-mem-offset = <0x40034>; 1246 rockchip,grf-mem-values = <0x0f040000>, <0x0f040f04>; 1247 rockchip,taskqueue-node = <2>; 1248 rockchip,resetgroup-node = <2>; 1249 rockchip,disable-auto-freq; 1250 status = "disabled"; 1251 }; 1252 1253 vdpu_mmu: iommu@ff7c0800 { 1254 compatible = "rockchip,iommu-v2"; 1255 reg = <0x0 0xff7c0800 0x0 0x40>; 1256 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1257 interrupt-names = "vdpu_mmu"; 1258 clock-names = "aclk", "iface"; 1259 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1260 #iommu-cells = <0>; 1261 rockchip,shootdown-entire; 1262 status = "disabled"; 1263 }; 1264 1265 avsd: avsd_plus@ff7c1000 { 1266 compatible = "rockchip,avs-plus-decoder"; 1267 reg = <0x0 0xff7c1000 0x0 0x200>; 1268 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1269 interrupt-names = "irq_dec"; 1270 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>; 1271 clock-names = "aclk_vcodec", "hclk_vcodec"; 1272 rockchip,normal-rates = <300000000>, <0>; 1273 assigned-clocks = <&cru ACLK_VPU>; 1274 assigned-clock-rates = <300000000>; 1275 resets = <&cru SRST_ARESETN_VPU>, <&cru SRST_HRESETN_VPU>; 1276 reset-names = "shared_video_a", "shared_video_h"; 1277 iommus = <&vdpu_mmu>; 1278 rockchip,srv = <&mpp_srv>; 1279 rockchip,taskqueue-node = <2>; 1280 rockchip,resetgroup-node = <2>; 1281 rockchip,disable-auto-freq; 1282 status = "disabled"; 1283 }; 1284 1285 vop: vop@ff840000 { 1286 compatible = "rockchip,rk3528-vop"; 1287 reg = <0x0 0xff840000 0x0 0x3000>, 1288 <0x0 0xff845000 0x0 0x1000>, 1289 <0x0 0xff846400 0x0 0x800>; 1290 reg-names = "regs", 1291 "gamma_lut", 1292 "acm_regs"; 1293 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&cru ACLK_VOP>, 1295 <&cru HCLK_VOP>, 1296 <&cru DCLK_VOP0>, 1297 <&cru DCLK_VOP1>; 1298 clock-names = "aclk_vop", 1299 "hclk_vop", 1300 "dclk_vp0", 1301 "dclk_vp1"; 1302 assigned-clocks = <&cru DCLK_VOP0>; 1303 assigned-clock-parents = <&inno_hdmiphy_clk>; 1304 iommus = <&vop_mmu>; 1305 rockchip,grf = <&grf>; 1306 status = "disabled"; 1307 1308 vop_out: ports { 1309 #address-cells = <1>; 1310 #size-cells = <0>; 1311 1312 port@0 { 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 reg = <0>; 1316 1317 vp0_out_hdmi: endpoint@0 { 1318 reg = <0>; 1319 remote-endpoint = <&hdmi_in_vp0>; 1320 }; 1321 }; 1322 1323 port@1 { 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 reg = <1>; 1327 1328 vp1_out_tve: endpoint@0 { 1329 reg = <0>; 1330 remote-endpoint = <&tve_in_vp1>; 1331 }; 1332 }; 1333 }; 1334 }; 1335 1336 vop_mmu: iommu@ff847e00 { 1337 compatible = "rockchip,iommu-v2"; 1338 reg = <0x0 0xff847e00 0x0 0x100>; 1339 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 1340 interrupt-names = "vop_mmu"; 1341 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 1342 clock-names = "aclk", "iface"; 1343 #iommu-cells = <0>; 1344 rockchip,disable-device-link-resume; 1345 rockchip,shootdown-entire; 1346 status = "disabled"; 1347 }; 1348 1349 rga2: rga@ff850000 { 1350 compatible = "rockchip,rga2_core0"; 1351 reg = <0x0 0xff850000 0x0 0x1000>; 1352 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1353 interrupt-names = "rga2_irq"; 1354 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>, <&cru CLK_CORE_RGA2E>; 1355 clock-names = "aclk_rga2", "hclk_rga2", "clk_rga2"; 1356 iommus = <&rga2_mmu>; 1357 rockchip,grf = <&grf>; 1358 rockchip,grf-offset = <0x600e0>; 1359 rockchip,grf-values = <0x0ff10000>, <0x0ff10ff1>; 1360 status = "disabled"; 1361 }; 1362 1363 rga2_mmu: iommu@ff850f00 { 1364 compatible = "rockchip,iommu-v2"; 1365 reg = <0x0 0xff850f00 0x0 0x100>; 1366 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1367 interrupt-names = "rga2_mmu"; 1368 clocks = <&cru ACLK_RGA2E>, <&cru HCLK_RGA2E>; 1369 clock-names = "aclk", "iface"; 1370 #iommu-cells = <0>; 1371 status = "disabled"; 1372 }; 1373 1374 iep: iep@ff860000 { 1375 compatible = "rockchip,iep-v2"; 1376 reg = <0x0 0xff860000 0x0 0x500>; 1377 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1378 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; 1379 clock-names = "aclk", "hclk", "sclk"; 1380 rockchip,normal-rates = <340000000>, <0>, <340000000>; 1381 assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>; 1382 assigned-clock-rates = <340000000>, <340000000>; 1383 resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>, 1384 <&cru SRST_RESETN_CORE_VDPP>; 1385 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; 1386 rockchip,srv = <&mpp_srv>; 1387 rockchip,taskqueue-node = <3>; 1388 rockchip,resetgroup-node = <3>; 1389 iommus = <&iep_mmu>; 1390 status = "disabled"; 1391 }; 1392 1393 iep_mmu: iommu@ff860800 { 1394 compatible = "rockchip,iommu-v2"; 1395 reg = <0x0 0xff860800 0x0 0x100>; 1396 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1397 interrupt-names = "iep_mmu"; 1398 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>; 1399 clock-names = "aclk", "iface"; 1400 #iommu-cells = <0>; 1401 rockchip,shootdown-entire; 1402 status = "disabled"; 1403 }; 1404 1405 vdpp: vdpp@ff861000 { 1406 compatible = "rockchip,vdpp-v1"; 1407 reg = <0x0 0xff861000 0x0 0x100>, <0x0 0xff862000 0x0 0x900>; 1408 reg-names = "vdpp_regs", "zme_regs"; 1409 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1410 clocks = <&cru ACLK_VDPP>, <&cru HCLK_VDPP>, <&cru CLK_CORE_VDPP>; 1411 clock-names = "aclk", "hclk", "sclk"; 1412 rockchip,normal-rates = <340000000>, <0>, <340000000>; 1413 assigned-clocks = <&cru ACLK_VDPP>, <&cru CLK_CORE_VDPP>; 1414 assigned-clock-rates = <340000000>, <340000000>; 1415 resets = <&cru SRST_ARESETN_VDPP>, <&cru SRST_HRESETN_VDPP>, 1416 <&cru SRST_RESETN_CORE_VDPP>; 1417 reset-names = "shared_rst_a", "shared_rst_h", "shared_rst_s"; 1418 rockchip,srv = <&mpp_srv>; 1419 rockchip,grf = <&grf>; 1420 rockchip,grf-mem-offset = <0x600e0>; 1421 rockchip,grf-mem-values = <0xf0040000>, <0xf004f004>; 1422 rockchip,taskqueue-node = <3>; 1423 rockchip,resetgroup-node = <3>; 1424 rockchip,disable-auto-freq; 1425 iommus = <&iep_mmu>; 1426 status = "disabled"; 1427 }; 1428 1429 jpegd: jpegd@ff870000 { 1430 compatible = "rockchip,rkv-jpeg-decoder-v1"; 1431 reg = <0x0 0xff870000 0x0 0x400>; 1432 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1433 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 1434 clock-names = "aclk_vcodec", "hclk_vcodec"; 1435 rockchip,normal-rates = <340000000>, <0>; 1436 assigned-clocks = <&cru ACLK_JPEG_DECODER>; 1437 assigned-clock-rates = <340000000>; 1438 rockchip,disable-auto-freq; 1439 resets = <&cru SRST_ARESETN_JPEG_DECODER>, <&cru SRST_HRESETN_JPEG_DECODER>; 1440 reset-names = "video_a", "video_h"; 1441 iommus = <&jpegd_mmu>; 1442 rockchip,srv = <&mpp_srv>; 1443 rockchip,taskqueue-node = <4>; 1444 rockchip,resetgroup-node = <4>; 1445 status = "disabled"; 1446 }; 1447 1448 jpegd_mmu: iommu@ff870480 { 1449 compatible = "rockchip,iommu-v2"; 1450 reg = <0x0 0xff870480 0x0 0x40>; 1451 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1452 interrupt-names = "jpegd_mmu"; 1453 clock-names = "aclk", "iface"; 1454 clocks = <&cru ACLK_JPEG_DECODER>, <&cru HCLK_JPEG_DECODER>; 1455 #iommu-cells = <0>; 1456 rockchip,shootdown-entire; 1457 status = "disabled"; 1458 }; 1459 1460 tve: tve@ff880000 { 1461 compatible = "rockchip,rk3528-tve"; 1462 reg = <0x0 0xff880000 0x0 0x4000>, 1463 <0x0 0xffde0000 0x0 0x300>; 1464 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1465 clocks = <&cru HCLK_CVBS>, 1466 <&cru PCLK_VCDCPHY>, 1467 <&cru DCLK_CVBS>, 1468 <&cru DCLK_4X_CVBS>; 1469 clock-names = "hclk", 1470 "pclk_vdac", 1471 "dclk", 1472 "dclk_4x"; 1473 rockchip,lumafilter0 = <0x0ff80006>; 1474 rockchip,lumafilter1 = <0x00090010>; 1475 rockchip,lumafilter2 = <0x0ffb0fd8>; 1476 rockchip,lumafilter3 = <0x00080057>; 1477 rockchip,lumafilter4 = <0x0fef0f64>; 1478 rockchip,lumafilter5 = <0x0016010a>; 1479 rockchip,lumafilter6 = <0x0f830df7>; 1480 rockchip,lumafilter7 = <0x08de055f>; 1481 rockchip,tve-upsample = <DCLK_UPSAMPLEx4>; 1482 rockchip,grf = <&grf>; 1483 nvmem-cells = <&vdac_out_current>, <&test_version>; 1484 nvmem-cell-names = "out-current", "version"; 1485 status = "disabled"; 1486 1487 ports { 1488 #address-cells = <1>; 1489 #size-cells = <0>; 1490 1491 port@0 { 1492 reg = <0>; 1493 #address-cells = <1>; 1494 #size-cells = <0>; 1495 1496 tve_in_vp1: endpoint@0 { 1497 reg = <0>; 1498 remote-endpoint = <&vp1_out_tve>; 1499 status = "disabled"; 1500 }; 1501 }; 1502 }; 1503 }; 1504 1505 hdcp2: hdcp2@ff8c0000 { 1506 compatible = "rockchip,rk3528-hdmi-hdcp2"; 1507 reg = <0x0 0xff8c0000 0x0 0x2000>; 1508 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 1509 clocks = <&cru ACLK_HDCP>, <&cru PCLK_HDCP>, 1510 <&cru HCLK_HDCP>; 1511 clock-names ="aclk_hdcp2", "pclk_hdcp2", "hdcp2_clk_hdmi"; 1512 status = "disabled"; 1513 }; 1514 1515 hdmi: hdmi@ff8d0000 { 1516 compatible = "rockchip,rk3528-dw-hdmi"; 1517 reg = <0x0 0xff8d0000 0x0 0x20000>, 1518 <0x0 0xff610000 0x0 0x200>; 1519 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1521 interrupt-names = "hdmi", "hdmi_wakeup"; 1522 clocks = <&cru PCLK_HDMI>, 1523 <&cru CLK_SFR_HDMI>, 1524 <&cru CLK_CEC_HDMI>, 1525 <&inno_hdmiphy_clk>; 1526 clock-names = "iahb", "isfr", "cec", "dclk_vp0"; 1527 ddc-i2c-scl-high-time-ns = <9625>; 1528 ddc-i2c-scl-low-time-ns = <10000>; 1529 reg-io-width = <4>; 1530 rockchip,grf = <&grf>; 1531 pinctrl-names = "default", "idle"; 1532 pinctrl-0 = <&hdmi_pins>; 1533 pinctrl-1 = <&hdmi_pins_idle>; 1534 phys = <&hdmiphy>; 1535 phy-names = "hdmi"; 1536 #sound-dai-cells = <0>; 1537 hpd-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; 1538 status = "disabled"; 1539 1540 ports { 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 1544 port@0 { 1545 reg = <0>; 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 1549 hdmi_in_vp0: endpoint@0 { 1550 reg = <0>; 1551 remote-endpoint = <&vp0_out_hdmi>; 1552 status = "disabled"; 1553 }; 1554 }; 1555 }; 1556 }; 1557 1558 dfi: dfi@ff930000 { 1559 reg = <0x0 0xff930000 0x0 0x400>; 1560 compatible = "rockchip,rk3528-dfi"; 1561 rockchip,grf = <&grf>; 1562 status = "disabled"; 1563 }; 1564 1565 spi0: spi@ff9c0000 { 1566 compatible = "rockchip,rk3066-spi"; 1567 reg = <0x0 0xff9c0000 0x0 0x1000>; 1568 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 1569 #address-cells = <1>; 1570 #size-cells = <0>; 1571 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>, <&cru SCLK_IN_SPI0>; 1572 clock-names = "spiclk", "apb_pclk", "sclk_in"; 1573 dmas = <&dmac 25>, <&dmac 24>; 1574 dma-names = "tx", "rx"; 1575 pinctrl-names = "default"; 1576 pinctrl-0 = <&spi0_csn0 &spi0_csn1 &spi0_pins>; 1577 status = "disabled"; 1578 }; 1579 1580 spi1: spi@ff9d0000 { 1581 compatible = "rockchip,rk3066-spi"; 1582 reg = <0x0 0xff9d0000 0x0 0x1000>; 1583 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>, <&cru SCLK_IN_SPI1>; 1587 clock-names = "spiclk", "apb_pclk", "sclk_in"; 1588 dmas = <&dmac 31>, <&dmac 30>; 1589 dma-names = "tx", "rx"; 1590 pinctrl-names = "default"; 1591 pinctrl-0 = <&spi1_csn0 &spi1_csn1 &spi1_pins>; 1592 status = "disabled"; 1593 }; 1594 1595 uart0: serial@ff9f0000 { 1596 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1597 reg = <0x0 0xff9f0000 0x0 0x100>; 1598 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1599 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 1600 clock-names = "baudclk", "apb_pclk"; 1601 reg-shift = <2>; 1602 reg-io-width = <4>; 1603 dmas = <&dmac 9>, <&dmac 8>; 1604 status = "disabled"; 1605 }; 1606 1607 uart1: serial@ff9f8000 { 1608 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1609 reg = <0x0 0xff9f8000 0x0 0x100>; 1610 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1611 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 1612 clock-names = "baudclk", "apb_pclk"; 1613 reg-shift = <2>; 1614 reg-io-width = <4>; 1615 dmas = <&dmac 11>, <&dmac 10>; 1616 status = "disabled"; 1617 }; 1618 1619 uart2: serial@ffa00000 { 1620 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1621 reg = <0x0 0xffa00000 0x0 0x100>; 1622 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 1624 clock-names = "baudclk", "apb_pclk"; 1625 reg-shift = <2>; 1626 reg-io-width = <4>; 1627 dmas = <&dmac 13>, <&dmac 12>; 1628 status = "disabled"; 1629 }; 1630 1631 uart3: serial@ffa08000 { 1632 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1633 reg = <0x0 0xffa08000 0x0 0x100>; 1634 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1635 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 1636 clock-names = "baudclk", "apb_pclk"; 1637 reg-shift = <2>; 1638 reg-io-width = <4>; 1639 dmas = <&dmac 15>, <&dmac 14>; 1640 status = "disabled"; 1641 }; 1642 1643 uart4: serial@ffa10000 { 1644 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1645 reg = <0x0 0xffa10000 0x0 0x100>; 1646 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1647 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 1648 clock-names = "baudclk", "apb_pclk"; 1649 reg-shift = <2>; 1650 reg-io-width = <4>; 1651 dmas = <&dmac 17>, <&dmac 16>; 1652 status = "disabled"; 1653 }; 1654 1655 uart5: serial@ffa18000 { 1656 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1657 reg = <0x0 0xffa18000 0x0 0x100>; 1658 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1659 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 1660 clock-names = "baudclk", "apb_pclk"; 1661 reg-shift = <2>; 1662 reg-io-width = <4>; 1663 dmas = <&dmac 19>, <&dmac 18>; 1664 status = "disabled"; 1665 }; 1666 1667 uart6: serial@ffa20000 { 1668 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1669 reg = <0x0 0xffa20000 0x0 0x100>; 1670 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 1671 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>; 1672 clock-names = "baudclk", "apb_pclk"; 1673 reg-shift = <2>; 1674 reg-io-width = <4>; 1675 dmas = <&dmac 21>, <&dmac 20>; 1676 status = "disabled"; 1677 }; 1678 1679 uart7: serial@ffa28000 { 1680 compatible = "rockchip,rk3528-uart", "snps,dw-apb-uart"; 1681 reg = <0x0 0xffa28000 0x0 0x100>; 1682 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1683 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>; 1684 clock-names = "baudclk", "apb_pclk"; 1685 reg-shift = <2>; 1686 reg-io-width = <4>; 1687 dmas = <&dmac 23>, <&dmac 22>; 1688 status = "disabled"; 1689 }; 1690 1691 i2c0: i2c@ffa50000 { 1692 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1693 reg = <0x0 0xffa50000 0x0 0x1000>; 1694 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 1695 clock-names = "i2c", "pclk"; 1696 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1697 pinctrl-names = "default"; 1698 pinctrl-0 = <&i2c0m0_xfer>; 1699 #address-cells = <1>; 1700 #size-cells = <0>; 1701 status = "disabled"; 1702 }; 1703 1704 i2c1: i2c@ffa58000 { 1705 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1706 reg = <0x0 0xffa58000 0x0 0x1000>; 1707 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 1708 clock-names = "i2c", "pclk"; 1709 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1710 pinctrl-names = "default"; 1711 pinctrl-0 = <&i2c1m0_xfer>; 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 status = "disabled"; 1715 }; 1716 1717 i2c2: i2c@ffa60000 { 1718 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1719 reg = <0x0 0xffa60000 0x0 0x1000>; 1720 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 1721 clock-names = "i2c", "pclk"; 1722 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 1723 pinctrl-names = "default"; 1724 pinctrl-0 = <&i2c2m0_xfer>; 1725 #address-cells = <1>; 1726 #size-cells = <0>; 1727 status = "disabled"; 1728 }; 1729 1730 i2c3: i2c@ffa68000 { 1731 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1732 reg = <0x0 0xffa68000 0x0 0x1000>; 1733 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 1734 clock-names = "i2c", "pclk"; 1735 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 1736 pinctrl-names = "default"; 1737 pinctrl-0 = <&i2c3m0_xfer>; 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 status = "disabled"; 1741 }; 1742 1743 i2c4: i2c@ffa70000 { 1744 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1745 reg = <0x0 0xffa70000 0x0 0x1000>; 1746 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 1747 clock-names = "i2c", "pclk"; 1748 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 1749 pinctrl-names = "default"; 1750 pinctrl-0 = <&i2c4_xfer>; 1751 #address-cells = <1>; 1752 #size-cells = <0>; 1753 status = "disabled"; 1754 }; 1755 1756 i2c5: i2c@ffa78000 { 1757 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1758 reg = <0x0 0xffa78000 0x0 0x1000>; 1759 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>; 1760 clock-names = "i2c", "pclk"; 1761 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 1762 pinctrl-names = "default"; 1763 pinctrl-0 = <&i2c5m0_xfer>; 1764 #address-cells = <1>; 1765 #size-cells = <0>; 1766 status = "disabled"; 1767 }; 1768 1769 i2c6: i2c@ffa80000 { 1770 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1771 reg = <0x0 0xffa80000 0x0 0x1000>; 1772 clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>; 1773 clock-names = "i2c", "pclk"; 1774 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 1775 pinctrl-names = "default"; 1776 pinctrl-0 = <&i2c6m0_xfer>; 1777 #address-cells = <1>; 1778 #size-cells = <0>; 1779 status = "disabled"; 1780 }; 1781 1782 i2c7: i2c@ffa88000 { 1783 compatible = "rockchip,rk3528-i2c", "rockchip,rk3399-i2c"; 1784 reg = <0x0 0xffa88000 0x0 0x1000>; 1785 clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>; 1786 clock-names = "i2c", "pclk"; 1787 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1788 pinctrl-names = "default"; 1789 pinctrl-0 = <&i2c7_xfer>; 1790 #address-cells = <1>; 1791 #size-cells = <0>; 1792 status = "disabled"; 1793 }; 1794 1795 pwm0: pwm@ffa90000 { 1796 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1797 reg = <0x0 0xffa90000 0x0 0x10>; 1798 #pwm-cells = <3>; 1799 pinctrl-names = "active"; 1800 pinctrl-0 = <&pwm0m0_pins>; 1801 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1802 clock-names = "pwm", "pclk"; 1803 status = "disabled"; 1804 }; 1805 1806 pwm1: pwm@ffa90010 { 1807 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1808 reg = <0x0 0xffa90010 0x0 0x10>; 1809 #pwm-cells = <3>; 1810 pinctrl-names = "active"; 1811 pinctrl-0 = <&pwm1m0_pins>; 1812 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1813 clock-names = "pwm", "pclk"; 1814 status = "disabled"; 1815 }; 1816 1817 pwm2: pwm@ffa90020 { 1818 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1819 reg = <0x0 0xffa90020 0x0 0x10>; 1820 #pwm-cells = <3>; 1821 pinctrl-names = "active"; 1822 pinctrl-0 = <&pwm2m0_pins>; 1823 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1824 clock-names = "pwm", "pclk"; 1825 status = "disabled"; 1826 }; 1827 1828 pwm3: pwm@ffa90030 { 1829 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1830 reg = <0x0 0xffa90030 0x0 0x10>; 1831 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1832 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1833 #pwm-cells = <3>; 1834 pinctrl-names = "active"; 1835 pinctrl-0 = <&pwm3m0_pins>; 1836 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 1837 clock-names = "pwm", "pclk"; 1838 status = "disabled"; 1839 }; 1840 1841 pwm4: pwm@ffa98000 { 1842 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1843 reg = <0x0 0xffa98000 0x0 0x10>; 1844 #pwm-cells = <3>; 1845 pinctrl-names = "active"; 1846 pinctrl-0 = <&pwm4m0_pins>; 1847 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1848 clock-names = "pwm", "pclk"; 1849 status = "disabled"; 1850 }; 1851 1852 pwm5: pwm@ffa98010 { 1853 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1854 reg = <0x0 0xffa98010 0x0 0x10>; 1855 #pwm-cells = <3>; 1856 pinctrl-names = "active"; 1857 pinctrl-0 = <&pwm5m0_pins>; 1858 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1859 clock-names = "pwm", "pclk"; 1860 status = "disabled"; 1861 }; 1862 1863 pwm6: pwm@ffa98020 { 1864 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1865 reg = <0x0 0xffa98020 0x0 0x10>; 1866 #pwm-cells = <3>; 1867 pinctrl-names = "active"; 1868 pinctrl-0 = <&pwm6m0_pins>; 1869 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1870 clock-names = "pwm", "pclk"; 1871 status = "disabled"; 1872 }; 1873 1874 pwm7: pwm@ffa98030 { 1875 compatible = "rockchip,rk3528-pwm", "rockchip,rk3328-pwm"; 1876 reg = <0x0 0xffa98030 0x0 0x10>; 1877 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1878 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1879 #pwm-cells = <3>; 1880 pinctrl-names = "active"; 1881 pinctrl-0 = <&pwm7m0_pins>; 1882 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 1883 clock-names = "pwm", "pclk"; 1884 status = "disabled"; 1885 }; 1886 1887 rktimer: timer@ffab0000 { 1888 compatible = "rockchip,rk3528-timer", "rockchip,rk3288-timer"; 1889 reg = <0x0 0xffab0000 0x0 0x20>; 1890 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1891 clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; 1892 clock-names = "pclk", "timer"; 1893 }; 1894 1895 wdt: watchdog@ffac0000 { 1896 compatible = "snps,dw-wdt"; 1897 reg = <0x0 0xffac0000 0x0 0x100>; 1898 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 1899 clock-names = "tclk", "pclk"; 1900 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1901 status = "disabled"; 1902 }; 1903 1904 tsadc: tsadc@ffad0000 { 1905 compatible = "rockchip,rk3528-tsadc"; 1906 reg = <0x0 0xffad0000 0x0 0x400>; 1907 rockchip,grf = <&grf>; 1908 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1909 clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>, <&cru PCLK_TSADC>; 1910 clock-names = "tsadc", "tsadc_tsen", "apb_pclk"; 1911 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; 1912 assigned-clock-rates = <1200000>, <12000000>; 1913 resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>; 1914 reset-names = "tsadc", "tsadc-apb"; 1915 #thermal-sensor-cells = <1>; 1916 rockchip,hw-tshut-temp = <120000>; 1917 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 1918 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 1919 status = "disabled"; 1920 }; 1921 1922 saradc: saradc@ffae0000 { 1923 compatible = "rockchip,rk3528-saradc"; 1924 reg = <0x0 0xffae0000 0x0 0x10000>; 1925 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1926 #io-channel-cells = <1>; 1927 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 1928 clock-names = "saradc", "apb_pclk"; 1929 resets = <&cru SRST_PRESETN_SARADC>; 1930 reset-names = "saradc-apb"; 1931 status = "disabled"; 1932 }; 1933 1934 sai3: sai@ffb70000 { 1935 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1936 reg = <0x0 0xffb70000 0x0 0x1000>; 1937 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1938 clocks = <&cru MCLK_SAI_I2S3>, <&cru HCLK_SAI_I2S3>; 1939 clock-names = "mclk", "hclk"; 1940 dmas = <&dmac 5>; 1941 dma-names = "tx"; 1942 resets = <&cru SRST_MRESETN_SAI_I2S3>, <&cru SRST_HRESETN_SAI_I2S3>; 1943 reset-names = "m", "h"; 1944 #sound-dai-cells = <0>; 1945 status = "disabled"; 1946 }; 1947 1948 sai0: sai@ffb80000 { 1949 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1950 reg = <0x0 0xffb80000 0x0 0x1000>; 1951 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 1952 clocks = <&cru MCLK_SAI_I2S0>, <&cru HCLK_SAI_I2S0>; 1953 clock-names = "mclk", "hclk"; 1954 dmas = <&dmac 1>, <&dmac 0>; 1955 dma-names = "tx", "rx"; 1956 resets = <&cru SRST_MRESETN_SAI_I2S0>, <&cru SRST_HRESETN_SAI_I2S0>; 1957 reset-names = "m", "h"; 1958 pinctrl-names = "default"; 1959 pinctrl-0 = <&i2s0m0_lrck 1960 &i2s0m0_sclk 1961 &i2s0m0_sdi 1962 &i2s0m0_sdo>; 1963 #sound-dai-cells = <0>; 1964 status = "disabled"; 1965 }; 1966 1967 sai2: sai@ffb90000 { 1968 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1969 reg = <0x0 0xffb90000 0x0 0x1000>; 1970 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1971 clocks = <&cru MCLK_SAI_I2S2>, <&cru HCLK_SAI_I2S2>; 1972 clock-names = "mclk", "hclk"; 1973 dmas = <&dmac 4>; 1974 dma-names = "tx"; 1975 resets = <&cru SRST_MRESETN_SAI_I2S2>, <&cru SRST_HRESETN_SAI_I2S2>; 1976 reset-names = "m", "h"; 1977 #sound-dai-cells = <0>; 1978 status = "disabled"; 1979 }; 1980 1981 sai1: sai@ffba0000 { 1982 compatible = "rockchip,rk3528-sai", "rockchip,sai-v1"; 1983 reg = <0x0 0xffba0000 0x0 0x1000>; 1984 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1985 clocks = <&cru MCLK_SAI_I2S1>, <&cru HCLK_SAI_I2S1>; 1986 clock-names = "mclk", "hclk"; 1987 dmas = <&dmac 3>, <&dmac 2>; 1988 dma-names = "tx", "rx"; 1989 resets = <&cru SRST_MRESETN_SAI_I2S1>, <&cru SRST_HRESETN_SAI_I2S1>; 1990 reset-names = "m", "h"; 1991 pinctrl-names = "default"; 1992 pinctrl-0 = <&i2s1_sclk 1993 &i2s1_lrck 1994 &i2s1_sdi0 1995 &i2s1_sdi1 1996 &i2s1_sdi2 1997 &i2s1_sdi3 1998 &i2s1_sdo0 1999 &i2s1_sdo1 2000 &i2s1_sdo2 2001 &i2s1_sdo3>; 2002 #sound-dai-cells = <0>; 2003 status = "disabled"; 2004 }; 2005 2006 pdm: pdm@ffbb0000 { 2007 compatible = "rockchip,rk3528-pdm", "rockchip,rk3568-pdm"; 2008 reg = <0x0 0xffbb0000 0x0 0x1000>; 2009 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>; 2010 clock-names = "pdm_clk", "pdm_hclk"; 2011 dmas = <&dmac 6>; 2012 dma-names = "rx"; 2013 pinctrl-names = "default"; 2014 pinctrl-0 = <&pdm_clk0 2015 &pdm_clk1 2016 &pdm_sdi0 2017 &pdm_sdi1 2018 &pdm_sdi2 2019 &pdm_sdi3>; 2020 #sound-dai-cells = <0>; 2021 status = "disabled"; 2022 }; 2023 2024 spdif_8ch: spdif@ffbc0000 { 2025 compatible = "rockchip,rk3528-spdif", "rockchip,rk3568-spdif"; 2026 reg = <0x0 0xffbc0000 0x0 0x1000>; 2027 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 2028 dmas = <&dmac 7>; 2029 dma-names = "tx"; 2030 clock-names = "mclk", "hclk"; 2031 clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>; 2032 #sound-dai-cells = <0>; 2033 pinctrl-names = "default"; 2034 pinctrl-0 = <&spdifm0_pins>; 2035 status = "disabled"; 2036 }; 2037 2038 gmac0: ethernet@ffbd0000 { 2039 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 2040 reg = <0x0 0xffbd0000 0x0 0x10000>; 2041 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2042 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 2043 interrupt-names = "macirq", "eth_wake_irq"; 2044 rockchip,grf = <&grf>; 2045 clocks = <&cru CLK_GMAC0_SRC>, <&cru CLK_GMAC0_RMII_50M>, 2046 <&cru CLK_GMAC0_RX>, <&cru CLK_GMAC0_TX>, 2047 <&cru PCLK_MAC_VO>, <&cru ACLK_MAC_VO>; 2048 clock-names = "stmmaceth", "clk_mac_ref", 2049 "mac_clk_rx", "mac_clk_tx", 2050 "pclk_mac", "aclk_mac"; 2051 resets = <&cru SRST_ARESETN_MAC_VO>; 2052 reset-names = "stmmaceth"; 2053 2054 snps,mixed-burst; 2055 snps,tso; 2056 2057 snps,axi-config = <&gmac0_stmmac_axi_setup>; 2058 snps,mtl-rx-config = <&gmac0_mtl_rx_setup>; 2059 snps,mtl-tx-config = <&gmac0_mtl_tx_setup>; 2060 2061 phy-mode = "rmii"; 2062 clock_in_out = "input"; 2063 phy-handle = <&rmii0_phy>; 2064 2065 nvmem-cells = <&macphy_bgs>; 2066 nvmem-cell-names = "bgs"; 2067 status = "disabled"; 2068 2069 mdio0: mdio { 2070 compatible = "snps,dwmac-mdio"; 2071 #address-cells = <0x1>; 2072 #size-cells = <0x0>; 2073 rmii0_phy: ethernet-phy@2 { 2074 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22"; 2075 reg = <2>; 2076 clocks = <&cru CLK_MACPHY>; 2077 resets = <&cru SRST_RESETN_MACPHY>; 2078 phy-is-integrated; 2079 pinctrl-names = "default"; 2080 pinctrl-0 = <&fephym0_led_link &fephym0_led_spd>; 2081 nvmem-cells = <&macphy_txlevel>; 2082 nvmem-cell-names = "txlevel"; 2083 }; 2084 }; 2085 2086 gmac0_stmmac_axi_setup: stmmac-axi-config { 2087 snps,wr_osr_lmt = <4>; 2088 snps,rd_osr_lmt = <8>; 2089 snps,blen = <0 0 0 0 16 8 4>; 2090 }; 2091 2092 gmac0_mtl_rx_setup: rx-queues-config { 2093 snps,rx-queues-to-use = <1>; 2094 queue0 {}; 2095 }; 2096 2097 gmac0_mtl_tx_setup: tx-queues-config { 2098 snps,tx-queues-to-use = <1>; 2099 queue0 {}; 2100 }; 2101 }; 2102 2103 gmac1: ethernet@ffbe0000 { 2104 compatible = "rockchip,rk3528-gmac", "snps,dwmac-4.20a"; 2105 reg = <0x0 0xffbe0000 0x0 0x10000>; 2106 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 2108 interrupt-names = "macirq", "eth_wake_irq"; 2109 rockchip,grf = <&grf>; 2110 clocks = <&cru CLK_GMAC1_SRC_VPU>, <&cru CLK_GMAC1_RMII_VPU>, 2111 <&cru PCLK_MAC_VPU>, <&cru ACLK_MAC_VPU>; 2112 clock-names = "stmmaceth", "clk_mac_ref", 2113 "pclk_mac", "aclk_mac"; 2114 resets = <&cru SRST_ARESETN_MAC>; 2115 reset-names = "stmmaceth"; 2116 2117 snps,mixed-burst; 2118 snps,tso; 2119 2120 snps,axi-config = <&gmac1_stmmac_axi_setup>; 2121 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>; 2122 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>; 2123 2124 status = "disabled"; 2125 2126 mdio1: mdio { 2127 compatible = "snps,dwmac-mdio"; 2128 #address-cells = <0x1>; 2129 #size-cells = <0x0>; 2130 }; 2131 2132 gmac1_stmmac_axi_setup: stmmac-axi-config { 2133 snps,wr_osr_lmt = <4>; 2134 snps,rd_osr_lmt = <8>; 2135 snps,blen = <0 0 0 0 16 8 4>; 2136 }; 2137 2138 gmac1_mtl_rx_setup: rx-queues-config { 2139 snps,rx-queues-to-use = <1>; 2140 queue0 {}; 2141 }; 2142 2143 gmac1_mtl_tx_setup: tx-queues-config { 2144 snps,tx-queues-to-use = <1>; 2145 queue0 {}; 2146 }; 2147 }; 2148 2149 sdhci: mmc@ffbf0000 { 2150 compatible = "rockchip,rk3528-dwcmshc"; 2151 reg = <0x0 0xffbf0000 0x0 0x10000>; 2152 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 2153 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_SRC_EMMC>; 2154 assigned-clock-rates = <200000000>, <24000000>, <200000000>; 2155 clocks = <&cru CCLK_SRC_EMMC>, <&cru HCLK_EMMC>, 2156 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>, 2157 <&cru TCLK_EMMC>; 2158 clock-names = "core", "bus", "axi", "block", "timer"; 2159 resets = <&cru SRST_CRESETN_EMMC>, <&cru SRST_HRESETN_EMMC>, 2160 <&cru SRST_ARESETN_EMMC>, <&cru SRST_BRESETN_EMMC>, 2161 <&cru SRST_TRESETN_EMMC>; 2162 reset-names = "core", "bus", "axi", "block", "timer"; 2163 max-frequency = <200000000>; 2164 status = "disabled"; 2165 }; 2166 2167 sfc: spi@ffc00000 { 2168 compatible = "rockchip,sfc"; 2169 reg = <0x0 0xffc00000 0x0 0x4000>; 2170 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 2171 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>; 2172 clock-names = "clk_sfc", "hclk_sfc"; 2173 assigned-clocks = <&cru SCLK_SFC>; 2174 assigned-clock-rates = <100000000>; 2175 #address-cells = <1>; 2176 #size-cells = <0>; 2177 status = "disabled"; 2178 }; 2179 2180 sdio0: mmc@ffc10000 { 2181 compatible = "rockchip,rk3528-dw-mshc", 2182 "rockchip,rk3288-dw-mshc"; 2183 reg = <0x0 0xffc10000 0x0 0x4000>; 2184 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 2185 max-frequency = <150000000>; 2186 clocks = <&cru HCLK_SDIO0>, <&cru CCLK_SRC_SDIO0>, 2187 <&grf_cru SCLK_SDIO0_DRV>, <&grf_cru SCLK_SDIO0_SAMPLE>; 2188 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2189 fifo-depth = <0x100>; 2190 resets = <&cru SRST_HRESETN_SDIO0>; 2191 reset-names = "reset"; 2192 rockchip,use-v2-tuning; 2193 status = "disabled"; 2194 }; 2195 2196 sdio1: mmc@ffc20000 { 2197 compatible = "rockchip,rk3528-dw-mshc", 2198 "rockchip,rk3288-dw-mshc"; 2199 reg = <0x0 0xffc20000 0x0 0x4000>; 2200 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 2201 max-frequency = <150000000>; 2202 clocks = <&cru HCLK_SDIO1>, <&cru CCLK_SRC_SDIO1>, 2203 <&grf_cru SCLK_SDIO1_DRV>, <&grf_cru SCLK_SDIO1_SAMPLE>; 2204 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2205 fifo-depth = <0x100>; 2206 resets = <&cru SRST_HRESETN_SDIO1>; 2207 reset-names = "reset"; 2208 rockchip,use-v2-tuning; 2209 status = "disabled"; 2210 }; 2211 2212 sdmmc: mmc@ffc30000 { 2213 compatible = "rockchip,rk3528-dw-mshc", 2214 "rockchip,rk3288-dw-mshc"; 2215 reg = <0x0 0xffc30000 0x0 0x4000>; 2216 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 2217 max-frequency = <150000000>; 2218 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SRC_SDMMC0>, 2219 <&grf_cru SCLK_SDMMC_DRV>, <&grf_cru SCLK_SDMMC_SAMPLE>; 2220 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 2221 fifo-depth = <0x100>; 2222 resets = <&cru SRST_HRESETN_SDMMC0>; 2223 reset-names = "reset"; 2224 rockchip,use-v2-tuning; 2225 status = "disabled"; 2226 }; 2227 2228 crypto: crypto@ffc40000 { 2229 compatible = "rockchip,crypto-v4"; 2230 reg = <0x0 0xffc40000 0x0 0x2000>; 2231 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 2232 clocks = <&scmi_clk SCMI_ACLK_CRYPTO>, <&scmi_clk SCMI_HCLK_CRYPTO>, 2233 <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>; 2234 clock-names = "aclk", "hclk", "sclk", "pka"; 2235 assigned-clocks = <&scmi_clk SCMI_CORE_CRYPTO>, <&scmi_clk SCMI_PKA_CRYPTO>; 2236 assigned-clock-rates = <300000000>, <300000000>; 2237 resets = <&cru SRST_RESETN_CORE_CRYPTO>; 2238 reset-names = "crypto-rst"; 2239 status = "disabled"; 2240 }; 2241 2242 rng: rng@ffc50000 { 2243 compatible = "rockchip,rkrng"; 2244 reg = <0x0 0xffc50000 0x0 0x200>; 2245 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 2246 clocks = <&scmi_clk SCMI_HCLK_TRNG>; 2247 clock-names = "hclk_trng"; 2248 resets = <&cru SRST_HRESETN_TRNG_NS>; 2249 reset-names = "reset"; 2250 status = "disabled"; 2251 }; 2252 2253 otp: otp@ffce0000 { 2254 compatible = "rockchip,rk3528-otp"; 2255 reg = <0x0 0xffce0000 0x0 0x4000>; 2256 #address-cells = <1>; 2257 #size-cells = <1>; 2258 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 2259 <&cru PCLK_OTPC_NS>; 2260 clock-names = "usr", "sbpi", "apb"; 2261 resets = <&cru SRST_RESETN_USER_OTPC_NS>, 2262 <&cru SRST_RESETN_SBPI_OTPC_NS>, 2263 <&cru SRST_PRESETN_OTPC_NS>; 2264 reset-names = "usr", "sbpi", "apb"; 2265 2266 /* Data cells */ 2267 cpu_code: cpu-code@2 { 2268 reg = <0x02 0x2>; 2269 }; 2270 otp_cpu_version: cpu-version@8 { 2271 reg = <0x08 0x1>; 2272 bits = <3 3>; 2273 }; 2274 cpu_mbist_vmin: cpu-mbist-vmin@9 { 2275 reg = <0x09 0x1>; 2276 bits = <0 3>; 2277 }; 2278 gpu_mbist_vmin: gpu-mbist-vmin@9 { 2279 reg = <0x09 0x1>; 2280 bits = <3 2>; 2281 }; 2282 logic_mbist_vmin: logic-mbist-vmin@9 { 2283 reg = <0x09 0x1>; 2284 bits = <5 2>; 2285 }; 2286 otp_id: id@a { 2287 reg = <0x0a 0x10>; 2288 }; 2289 cpu_leakage: cpu-leakage@1a { 2290 reg = <0x1a 0x1>; 2291 }; 2292 log_leakage: log-leakage@1b { 2293 reg = <0x1b 0x1>; 2294 }; 2295 gpu_leakage: gpu-leakage@1c { 2296 reg = <0x1c 0x1>; 2297 }; 2298 test_version: test-version@29 { 2299 reg = <0x29 0x1>; 2300 }; 2301 macphy_bgs: macphy-bgs@2d { 2302 reg = <0x2d 0x1>; 2303 }; 2304 macphy_txlevel: macphy-txlevel@2e { 2305 reg = <0x2e 0x2>; 2306 }; 2307 vdac_out_current: vdac-out-current@30 { 2308 reg = <0x30 0x1>; 2309 }; 2310 cpu_opp_info: cpu-opp-info@32 { 2311 reg = <0x32 0x6>; 2312 }; 2313 gpu_opp_info: gpu-opp-info@38 { 2314 reg = <0x38 0x6>; 2315 }; 2316 dmc_opp_info: dmc-opp-info@3e { 2317 reg = <0x3e 0x6>; 2318 }; 2319 }; 2320 2321 dmac: dma-controller@ffd60000 { 2322 compatible = "arm,pl330", "arm,primecell"; 2323 reg = <0x0 0xffd60000 0x0 0x4000>; 2324 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 2325 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 2326 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 2327 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2328 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2329 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 2330 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 2331 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 2332 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2333 clocks = <&cru ACLK_DMAC>; 2334 clock-names = "apb_pclk"; 2335 #dma-cells = <1>; 2336 arm,pl330-periph-burst; 2337 }; 2338 2339 hwlock: hwspinlock@ffd70000 { 2340 compatible = "rockchip,hwspinlock"; 2341 reg = <0x0 0xffd70000 0x0 0x100>; 2342 #hwlock-cells = <1>; 2343 status = "disabled"; 2344 }; 2345 2346 combphy_pu: phy@ffdc0000 { 2347 compatible = "rockchip,rk3528-naneng-combphy"; 2348 reg = <0x0 0xffdc0000 0x0 0x10000>; 2349 #phy-cells = <1>; 2350 clocks = <&cru CLK_REF_PCIE_INNER_PHY>, <&cru PCLK_PCIE_PHY>, <&cru PCLK_PIPE_GRF>; 2351 clock-names = "refclk", "apbclk", "pipe_clk"; 2352 assigned-clocks = <&cru CLK_REF_PCIE_INNER_PHY>; 2353 assigned-clock-rates = <100000000>; 2354 resets = <&cru SRST_PRESETN_PCIE_PHY>, <&cru SRST_RESETN_PCIE_PIPE_PHY>; 2355 reset-names = "combphy-apb", "combphy"; 2356 rockchip,pipe-grf = <&grf>; 2357 rockchip,pipe-phy-grf = <&grf>; 2358 status = "disabled"; 2359 }; 2360 2361 usb2phy: usb2-phy@ffdf0000 { 2362 compatible = "rockchip,rk3528-usb2phy"; 2363 reg = <0x0 0xffdf0000 0x0 0x10000>; 2364 clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; 2365 clock-names = "phyclk", "apb_pclk"; 2366 #clock-cells = <0>; 2367 rockchip,usbgrf = <&grf>; 2368 status = "disabled"; 2369 2370 u2phy_otg: otg-port { 2371 #phy-cells = <0>; 2372 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2373 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2374 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2375 interrupt-names = "otg-bvalid", 2376 "otg-id", 2377 "linestate"; 2378 status = "disabled"; 2379 }; 2380 2381 u2phy_host: host-port { 2382 #phy-cells = <0>; 2383 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2384 interrupt-names = "linestate"; 2385 status = "disabled"; 2386 }; 2387 }; 2388 2389 hdmiphy: hdmiphy@ffe00000 { 2390 compatible = "rockchip,rk3528-hdmi-phy"; 2391 reg = <0x0 0xffe00000 0x0 0x10000>; 2392 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2393 #phy-cells = <0>; 2394 clocks = <&cru PCLK_HDMIPHY>, <&xin24m>; 2395 clock-names = "sysclk", "refclk"; 2396 status = "disabled"; 2397 2398 inno_hdmiphy_clk: clk-port { 2399 #clock-cells = <0>; 2400 clock-output-names = "clk_hdmiphy_pixel_io"; 2401 status = "okay"; 2402 }; 2403 }; 2404 2405 acodec: acodec@ffe10000 { 2406 compatible = "rockchip,rk3528-codec"; 2407 reg = <0x0 0xffe10000 0x0 0x1000>; 2408 #sound-dai-cells = <0>; 2409 clocks = <&cru PCLK_ACODEC>, <&cru MCLK_ACODEC_TX>; 2410 clock-names = "pclk", "mclk"; 2411 resets = <&cru SRST_PRESETN_ACODEC>; 2412 reset-names = "acodec"; 2413 status = "disabled"; 2414 }; 2415 2416 pinctrl: pinctrl { 2417 compatible = "rockchip,rk3528-pinctrl"; 2418 rockchip,grf = <&ioc_grf>; 2419 #address-cells = <2>; 2420 #size-cells = <2>; 2421 ranges; 2422 2423 gpio0: gpio@ff610000 { 2424 compatible = "rockchip,gpio-bank"; 2425 reg = <0x0 0xff610000 0x0 0x200>; 2426 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 2427 clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>; 2428 gpio-controller; 2429 #gpio-cells = <2>; 2430 gpio-ranges = <&pinctrl 0 0 32>; 2431 interrupt-controller; 2432 #interrupt-cells = <2>; 2433 }; 2434 2435 gpio1: gpio@ffaf0000 { 2436 compatible = "rockchip,gpio-bank"; 2437 reg = <0x0 0xffaf0000 0x0 0x200>; 2438 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 2439 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 2440 gpio-controller; 2441 #gpio-cells = <2>; 2442 gpio-ranges = <&pinctrl 0 32 32>; 2443 interrupt-controller; 2444 #interrupt-cells = <2>; 2445 }; 2446 2447 gpio2: gpio@ffb00000 { 2448 compatible = "rockchip,gpio-bank"; 2449 reg = <0x0 0xffb00000 0x0 0x200>; 2450 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 2451 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 2452 gpio-controller; 2453 #gpio-cells = <2>; 2454 gpio-ranges = <&pinctrl 0 64 32>; 2455 interrupt-controller; 2456 #interrupt-cells = <2>; 2457 }; 2458 2459 gpio3: gpio@ffb10000 { 2460 compatible = "rockchip,gpio-bank"; 2461 reg = <0x0 0xffb10000 0x0 0x200>; 2462 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 2463 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; 2464 gpio-controller; 2465 #gpio-cells = <2>; 2466 gpio-ranges = <&pinctrl 0 96 32>; 2467 interrupt-controller; 2468 #interrupt-cells = <2>; 2469 }; 2470 2471 gpio4: gpio@ffb20000 { 2472 compatible = "rockchip,gpio-bank"; 2473 reg = <0x0 0xffb20000 0x0 0x200>; 2474 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 2475 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; 2476 gpio-controller; 2477 #gpio-cells = <2>; 2478 gpio-ranges = <&pinctrl 0 128 32>; 2479 interrupt-controller; 2480 #interrupt-cells = <2>; 2481 }; 2482 }; 2483}; 2484 2485#include "rk3528-pinctrl.dtsi" 2486