1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/pinctrl/rockchip.h> 7#include "rockchip-pinconf.dtsi" 8 9/* 10 * This file is auto generated by pin2dts tool, please keep these code 11 * by adding changes at end of this file. 12 */ 13&pinctrl { 14 arm { 15 /omit-if-no-ref/ 16 arm_pins: arm-pins { 17 rockchip,pins = 18 /* arm_avs */ 19 <4 RK_PC4 3 &pcfg_pull_none>; 20 }; 21 }; 22 23 clk { 24 /omit-if-no-ref/ 25 clkm0_32k_out: clkm0-32k-out { 26 rockchip,pins = 27 /* clkm0_32k_out */ 28 <3 RK_PC3 3 &pcfg_pull_none>; 29 }; 30 31 /omit-if-no-ref/ 32 clkm1_32k_out: clkm1-32k-out { 33 rockchip,pins = 34 /* clkm1_32k_out */ 35 <1 RK_PC3 1 &pcfg_pull_none>; 36 }; 37 }; 38 39 emmc { 40 /omit-if-no-ref/ 41 emmc_rstnout: emmc-rstnout { 42 rockchip,pins = 43 /* emmc_rstn */ 44 <1 RK_PD6 1 &pcfg_pull_none>; 45 }; 46 47 /omit-if-no-ref/ 48 emmc_bus8: emmc-bus8 { 49 rockchip,pins = 50 /* emmc_d0 */ 51 <1 RK_PC4 1 &pcfg_pull_up_drv_level_2>, 52 /* emmc_d1 */ 53 <1 RK_PC5 1 &pcfg_pull_up_drv_level_2>, 54 /* emmc_d2 */ 55 <1 RK_PC6 1 &pcfg_pull_up_drv_level_2>, 56 /* emmc_d3 */ 57 <1 RK_PC7 1 &pcfg_pull_up_drv_level_2>, 58 /* emmc_d4 */ 59 <1 RK_PD0 1 &pcfg_pull_up_drv_level_2>, 60 /* emmc_d5 */ 61 <1 RK_PD1 1 &pcfg_pull_up_drv_level_2>, 62 /* emmc_d6 */ 63 <1 RK_PD2 1 &pcfg_pull_up_drv_level_2>, 64 /* emmc_d7 */ 65 <1 RK_PD3 1 &pcfg_pull_up_drv_level_2>; 66 }; 67 68 /omit-if-no-ref/ 69 emmc_clk: emmc-clk { 70 rockchip,pins = 71 /* emmc_clk */ 72 <1 RK_PD5 1 &pcfg_pull_up_drv_level_2>; 73 }; 74 75 /omit-if-no-ref/ 76 emmc_cmd: emmc-cmd { 77 rockchip,pins = 78 /* emmc_cmd */ 79 <1 RK_PD4 1 &pcfg_pull_up_drv_level_2>; 80 }; 81 82 /omit-if-no-ref/ 83 emmc_strb: emmc-strb { 84 rockchip,pins = 85 /* emmc_strb */ 86 <1 RK_PD7 1 &pcfg_pull_none>; 87 }; 88 }; 89 90 eth { 91 /omit-if-no-ref/ 92 eth_pins: eth-pins { 93 rockchip,pins = 94 /* eth_clk_25m_out */ 95 <3 RK_PB5 2 &pcfg_pull_none_drv_level_2>; 96 }; 97 }; 98 99 fephy { 100 /omit-if-no-ref/ 101 fephym0_led_dpx: fephym0-led_dpx { 102 rockchip,pins = 103 /* fephy_led_dpx_m0 */ 104 <4 RK_PB5 2 &pcfg_pull_none>; 105 }; 106 107 /omit-if-no-ref/ 108 fephym0_led_link: fephym0-led_link { 109 rockchip,pins = 110 /* fephy_led_link_m0 */ 111 <4 RK_PC0 2 &pcfg_pull_none>; 112 }; 113 114 /omit-if-no-ref/ 115 fephym0_led_spd: fephym0-led_spd { 116 rockchip,pins = 117 /* fephy_led_spd_m0 */ 118 <4 RK_PB7 2 &pcfg_pull_none>; 119 }; 120 121 /omit-if-no-ref/ 122 fephym1_led_dpx: fephym1-led_dpx { 123 rockchip,pins = 124 /* fephy_led_dpx_m1 */ 125 <2 RK_PA4 5 &pcfg_pull_none>; 126 }; 127 128 /omit-if-no-ref/ 129 fephym1_led_link: fephym1-led_link { 130 rockchip,pins = 131 /* fephy_led_link_m1 */ 132 <2 RK_PA6 5 &pcfg_pull_none>; 133 }; 134 135 /omit-if-no-ref/ 136 fephym1_led_spd: fephym1-led_spd { 137 rockchip,pins = 138 /* fephy_led_spd_m1 */ 139 <2 RK_PA5 5 &pcfg_pull_none>; 140 }; 141 }; 142 143 fspi { 144 /omit-if-no-ref/ 145 fspi_pins: fspi-pins { 146 rockchip,pins = 147 /* fspi_clk */ 148 <1 RK_PD5 2 &pcfg_pull_none>, 149 /* fspi_d0 */ 150 <1 RK_PC4 2 &pcfg_pull_none>, 151 /* fspi_d1 */ 152 <1 RK_PC5 2 &pcfg_pull_none>, 153 /* fspi_d2 */ 154 <1 RK_PC6 2 &pcfg_pull_none>, 155 /* fspi_d3 */ 156 <1 RK_PC7 2 &pcfg_pull_none>; 157 }; 158 159 /omit-if-no-ref/ 160 fspi_csn0: fspi-csn0 { 161 rockchip,pins = 162 /* fspi_csn0 */ 163 <1 RK_PD0 2 &pcfg_pull_none>; 164 }; 165 /omit-if-no-ref/ 166 fspi_csn1: fspi-csn1 { 167 rockchip,pins = 168 /* fspi_csn1 */ 169 <1 RK_PD1 2 &pcfg_pull_none>; 170 }; 171 }; 172 173 gpu { 174 /omit-if-no-ref/ 175 gpu_pins: gpu-pins { 176 rockchip,pins = 177 /* gpu_avs */ 178 <4 RK_PC3 3 &pcfg_pull_none>; 179 }; 180 }; 181 182 hdmi { 183 /omit-if-no-ref/ 184 hdmi_pins: hdmi-pins { 185 rockchip,pins = 186 /* hdmi_tx_cec */ 187 <0 RK_PA3 1 &pcfg_pull_none>, 188 /* hdmi_tx_scl */ 189 <0 RK_PA4 1 &pcfg_pull_none>, 190 /* hdmi_tx_sda */ 191 <0 RK_PA5 1 &pcfg_pull_none>; 192 }; 193 194 /omit-if-no-ref/ 195 hdmi_pins_idle: hdmi-pins-idle { 196 rockchip,pins = 197 /* hdmi_tx_cec */ 198 <0 RK_PA3 1 &pcfg_pull_none>, 199 /* hdmi_tx_scl */ 200 <0 RK_PA4 0 &pcfg_output_low_pull_down>, 201 /* hdmi_tx_sda */ 202 <0 RK_PA5 0 &pcfg_output_low_pull_down>; 203 }; 204 }; 205 206 hsm { 207 /omit-if-no-ref/ 208 hsmm0_pins: hsmm0-pins { 209 rockchip,pins = 210 /* hsm_clk_out_m0 */ 211 <2 RK_PA2 4 &pcfg_pull_none>; 212 }; 213 214 /omit-if-no-ref/ 215 hsmm1_pins: hsmm1-pins { 216 rockchip,pins = 217 /* hsm_clk_out_m1 */ 218 <1 RK_PA4 3 &pcfg_pull_none>; 219 }; 220 }; 221 222 i2c0 { 223 /omit-if-no-ref/ 224 i2c0m0_xfer: i2c0m0-xfer { 225 rockchip,pins = 226 /* i2c0_scl_m0 */ 227 <4 RK_PC4 2 &pcfg_pull_none_smt>, 228 /* i2c0_sda_m0 */ 229 <4 RK_PC3 2 &pcfg_pull_none_smt>; 230 }; 231 232 /omit-if-no-ref/ 233 i2c0m1_xfer: i2c0m1-xfer { 234 rockchip,pins = 235 /* i2c0_scl_m1 */ 236 <4 RK_PA1 2 &pcfg_pull_none_smt>, 237 /* i2c0_sda_m1 */ 238 <4 RK_PA0 2 &pcfg_pull_none_smt>; 239 }; 240 }; 241 242 i2c1 { 243 /omit-if-no-ref/ 244 i2c1m0_xfer: i2c1m0-xfer { 245 rockchip,pins = 246 /* i2c1_scl_m0 */ 247 <4 RK_PA3 2 &pcfg_pull_none_smt>, 248 /* i2c1_sda_m0 */ 249 <4 RK_PA2 2 &pcfg_pull_none_smt>; 250 }; 251 252 /omit-if-no-ref/ 253 i2c1m1_xfer: i2c1m1-xfer { 254 rockchip,pins = 255 /* i2c1_scl_m1 */ 256 <4 RK_PC5 4 &pcfg_pull_none_smt>, 257 /* i2c1_sda_m1 */ 258 <4 RK_PC6 4 &pcfg_pull_none_smt>; 259 }; 260 }; 261 262 i2c2 { 263 /omit-if-no-ref/ 264 i2c2m0_xfer: i2c2m0-xfer { 265 rockchip,pins = 266 /* i2c2_scl_m0 */ 267 <0 RK_PA4 2 &pcfg_pull_none_smt>, 268 /* i2c2_sda_m0 */ 269 <0 RK_PA5 2 &pcfg_pull_none_smt>; 270 }; 271 272 /omit-if-no-ref/ 273 i2c2m1_xfer: i2c2m1-xfer { 274 rockchip,pins = 275 /* i2c2_scl_m1 */ 276 <1 RK_PA5 3 &pcfg_pull_none_smt>, 277 /* i2c2_sda_m1 */ 278 <1 RK_PA6 3 &pcfg_pull_none_smt>; 279 }; 280 }; 281 282 i2c3 { 283 /omit-if-no-ref/ 284 i2c3m0_xfer: i2c3m0-xfer { 285 rockchip,pins = 286 /* i2c3_scl_m0 */ 287 <1 RK_PA0 2 &pcfg_pull_none_smt>, 288 /* i2c3_sda_m0 */ 289 <1 RK_PA1 2 &pcfg_pull_none_smt>; 290 }; 291 292 /omit-if-no-ref/ 293 i2c3m1_xfer: i2c3m1-xfer { 294 rockchip,pins = 295 /* i2c3_scl_m1 */ 296 <3 RK_PC1 5 &pcfg_pull_none_smt>, 297 /* i2c3_sda_m1 */ 298 <3 RK_PC3 5 &pcfg_pull_none_smt>; 299 }; 300 }; 301 302 i2c4 { 303 /omit-if-no-ref/ 304 i2c4_xfer: i2c4-xfer { 305 rockchip,pins = 306 /* i2c4_scl */ 307 <2 RK_PA0 4 &pcfg_pull_none_smt>, 308 /* i2c4_sda */ 309 <2 RK_PA1 4 &pcfg_pull_none_smt>; 310 }; 311 }; 312 313 i2c5 { 314 /omit-if-no-ref/ 315 i2c5m0_xfer: i2c5m0-xfer { 316 rockchip,pins = 317 /* i2c5_scl_m0 */ 318 <1 RK_PB2 3 &pcfg_pull_none_smt>, 319 /* i2c5_sda_m0 */ 320 <1 RK_PB3 3 &pcfg_pull_none_smt>; 321 }; 322 323 /omit-if-no-ref/ 324 i2c5m1_xfer: i2c5m1-xfer { 325 rockchip,pins = 326 /* i2c5_scl_m1 */ 327 <1 RK_PD2 3 &pcfg_pull_none_smt>, 328 /* i2c5_sda_m1 */ 329 <1 RK_PD3 3 &pcfg_pull_none_smt>; 330 }; 331 }; 332 333 i2c6 { 334 /omit-if-no-ref/ 335 i2c6m0_xfer: i2c6m0-xfer { 336 rockchip,pins = 337 /* i2c6_scl_m0 */ 338 <3 RK_PB2 5 &pcfg_pull_none_smt>, 339 /* i2c6_sda_m0 */ 340 <3 RK_PB3 5 &pcfg_pull_none_smt>; 341 }; 342 343 /omit-if-no-ref/ 344 i2c6m1_xfer: i2c6m1-xfer { 345 rockchip,pins = 346 /* i2c6_scl_m1 */ 347 <1 RK_PD4 3 &pcfg_pull_none_smt>, 348 /* i2c6_sda_m1 */ 349 <1 RK_PD7 3 &pcfg_pull_none_smt>; 350 }; 351 }; 352 353 i2c7 { 354 /omit-if-no-ref/ 355 i2c7_xfer: i2c7-xfer { 356 rockchip,pins = 357 /* i2c7_scl */ 358 <2 RK_PA5 4 &pcfg_pull_none_smt>, 359 /* i2c7_sda */ 360 <2 RK_PA6 4 &pcfg_pull_none_smt>; 361 }; 362 }; 363 364 i2s0 { 365 /omit-if-no-ref/ 366 i2s0m0_lrck: i2s0m0-lrck { 367 rockchip,pins = 368 /* i2s0_lrck_m0 */ 369 <3 RK_PB6 1 &pcfg_pull_none_smt>; 370 }; 371 372 /omit-if-no-ref/ 373 i2s0m0_mclk: i2s0m0-mclk { 374 rockchip,pins = 375 /* i2s0_mclk_m0 */ 376 <3 RK_PB4 1 &pcfg_pull_none_smt>; 377 }; 378 379 /omit-if-no-ref/ 380 i2s0m0_sclk: i2s0m0-sclk { 381 rockchip,pins = 382 /* i2s0_sclk_m0 */ 383 <3 RK_PB5 1 &pcfg_pull_none_smt>; 384 }; 385 386 /omit-if-no-ref/ 387 i2s0m0_sdi: i2s0m0-sdi { 388 rockchip,pins = 389 /* i2s0m0_sdi */ 390 <3 RK_PB7 1 &pcfg_pull_none>; 391 }; 392 /omit-if-no-ref/ 393 i2s0m0_sdo: i2s0m0-sdo { 394 rockchip,pins = 395 /* i2s0m0_sdo */ 396 <3 RK_PC0 1 &pcfg_pull_none>; 397 }; 398 399 /omit-if-no-ref/ 400 i2s0m1_lrck: i2s0m1-lrck { 401 rockchip,pins = 402 /* i2s0_lrck_m1 */ 403 <1 RK_PB6 1 &pcfg_pull_none_smt>; 404 }; 405 406 /omit-if-no-ref/ 407 i2s0m1_mclk: i2s0m1-mclk { 408 rockchip,pins = 409 /* i2s0_mclk_m1 */ 410 <1 RK_PB4 1 &pcfg_pull_none_smt>; 411 }; 412 413 /omit-if-no-ref/ 414 i2s0m1_sclk: i2s0m1-sclk { 415 rockchip,pins = 416 /* i2s0_sclk_m1 */ 417 <1 RK_PB5 1 &pcfg_pull_none_smt>; 418 }; 419 420 /omit-if-no-ref/ 421 i2s0m1_sdi: i2s0m1-sdi { 422 rockchip,pins = 423 /* i2s0m1_sdi */ 424 <1 RK_PB7 1 &pcfg_pull_none>; 425 }; 426 /omit-if-no-ref/ 427 i2s0m1_sdo: i2s0m1-sdo { 428 rockchip,pins = 429 /* i2s0m1_sdo */ 430 <1 RK_PC0 1 &pcfg_pull_none>; 431 }; 432 }; 433 434 i2s1 { 435 /omit-if-no-ref/ 436 i2s1_lrck: i2s1-lrck { 437 rockchip,pins = 438 /* i2s1_lrck */ 439 <4 RK_PA6 1 &pcfg_pull_none_smt>; 440 }; 441 442 /omit-if-no-ref/ 443 i2s1_mclk: i2s1-mclk { 444 rockchip,pins = 445 /* i2s1_mclk */ 446 <4 RK_PA4 1 &pcfg_pull_none_smt>; 447 }; 448 449 /omit-if-no-ref/ 450 i2s1_sclk: i2s1-sclk { 451 rockchip,pins = 452 /* i2s1_sclk */ 453 <4 RK_PA5 1 &pcfg_pull_none_smt>; 454 }; 455 456 /omit-if-no-ref/ 457 i2s1_sdi0: i2s1-sdi0 { 458 rockchip,pins = 459 /* i2s1_sdi0 */ 460 <4 RK_PB4 1 &pcfg_pull_none>; 461 }; 462 463 /omit-if-no-ref/ 464 i2s1_sdi1: i2s1-sdi1 { 465 rockchip,pins = 466 /* i2s1_sdi1 */ 467 <4 RK_PB3 1 &pcfg_pull_none>; 468 }; 469 470 /omit-if-no-ref/ 471 i2s1_sdi2: i2s1-sdi2 { 472 rockchip,pins = 473 /* i2s1_sdi2 */ 474 <4 RK_PA3 1 &pcfg_pull_none>; 475 }; 476 477 /omit-if-no-ref/ 478 i2s1_sdi3: i2s1-sdi3 { 479 rockchip,pins = 480 /* i2s1_sdi3 */ 481 <4 RK_PA2 1 &pcfg_pull_none>; 482 }; 483 484 /omit-if-no-ref/ 485 i2s1_sdo0: i2s1-sdo0 { 486 rockchip,pins = 487 /* i2s1_sdo0 */ 488 <4 RK_PA7 1 &pcfg_pull_none>; 489 }; 490 491 /omit-if-no-ref/ 492 i2s1_sdo1: i2s1-sdo1 { 493 rockchip,pins = 494 /* i2s1_sdo1 */ 495 <4 RK_PB0 1 &pcfg_pull_none>; 496 }; 497 498 /omit-if-no-ref/ 499 i2s1_sdo2: i2s1-sdo2 { 500 rockchip,pins = 501 /* i2s1_sdo2 */ 502 <4 RK_PB1 1 &pcfg_pull_none>; 503 }; 504 505 /omit-if-no-ref/ 506 i2s1_sdo3: i2s1-sdo3 { 507 rockchip,pins = 508 /* i2s1_sdo3 */ 509 <4 RK_PB2 1 &pcfg_pull_none>; 510 }; 511 }; 512 513 jtag { 514 /omit-if-no-ref/ 515 jtagm0_pins: jtagm0-pins { 516 rockchip,pins = 517 /* jtag_cpu_tck_m0 */ 518 <2 RK_PA2 2 &pcfg_pull_none>, 519 /* jtag_cpu_tms_m0 */ 520 <2 RK_PA3 2 &pcfg_pull_none>, 521 /* jtag_mcu_tck_m0 */ 522 <2 RK_PA4 2 &pcfg_pull_none>, 523 /* jtag_mcu_tms_m0 */ 524 <2 RK_PA5 2 &pcfg_pull_none>; 525 }; 526 527 /omit-if-no-ref/ 528 jtagm1_pins: jtagm1-pins { 529 rockchip,pins = 530 /* jtag_cpu_tck_m1 */ 531 <4 RK_PD0 2 &pcfg_pull_none>, 532 /* jtag_cpu_tms_m1 */ 533 <4 RK_PC7 2 &pcfg_pull_none>, 534 /* jtag_mcu_tck_m1 */ 535 <4 RK_PD0 3 &pcfg_pull_none>, 536 /* jtag_mcu_tms_m1 */ 537 <4 RK_PC7 3 &pcfg_pull_none>; 538 }; 539 }; 540 541 pcie { 542 /omit-if-no-ref/ 543 pciem0_pins: pciem0-pins { 544 rockchip,pins = 545 /* pcie_clkreqn_m0 */ 546 <3 RK_PA6 5 &pcfg_pull_none>, 547 /* pcie_perstn_m0 */ 548 <3 RK_PB0 5 &pcfg_pull_none>, 549 /* pcie_waken_m0 */ 550 <3 RK_PA7 5 &pcfg_pull_none>; 551 }; 552 553 /omit-if-no-ref/ 554 pciem1_pins: pciem1-pins { 555 rockchip,pins = 556 /* pcie_clkreqn_m1 */ 557 <1 RK_PA0 4 &pcfg_pull_none>, 558 /* pcie_perstn_m1 */ 559 <1 RK_PA2 4 &pcfg_pull_none>, 560 /* pcie_waken_m1 */ 561 <1 RK_PA1 4 &pcfg_pull_none>; 562 }; 563 }; 564 565 pdm { 566 /omit-if-no-ref/ 567 pdm_clk0: pdm-clk0 { 568 rockchip,pins = 569 /* pdm_clk0 */ 570 <4 RK_PB5 3 &pcfg_pull_none>; 571 }; 572 573 /omit-if-no-ref/ 574 pdm_clk1: pdm-clk1 { 575 rockchip,pins = 576 /* pdm_clk1 */ 577 <4 RK_PA4 3 &pcfg_pull_none>; 578 }; 579 580 /omit-if-no-ref/ 581 pdm_sdi0: pdm-sdi0 { 582 rockchip,pins = 583 /* pdm_sdi0 */ 584 <4 RK_PB2 3 &pcfg_pull_none>; 585 }; 586 587 /omit-if-no-ref/ 588 pdm_sdi1: pdm-sdi1 { 589 rockchip,pins = 590 /* pdm_sdi1 */ 591 <4 RK_PB1 3 &pcfg_pull_none>; 592 }; 593 594 /omit-if-no-ref/ 595 pdm_sdi2: pdm-sdi2 { 596 rockchip,pins = 597 /* pdm_sdi2 */ 598 <4 RK_PB3 3 &pcfg_pull_none>; 599 }; 600 601 /omit-if-no-ref/ 602 pdm_sdi3: pdm-sdi3 { 603 rockchip,pins = 604 /* pdm_sdi3 */ 605 <4 RK_PC1 3 &pcfg_pull_none>; 606 }; 607 }; 608 609 pmu { 610 /omit-if-no-ref/ 611 pmu_pins: pmu-pins { 612 rockchip,pins = 613 /* pmu_debug */ 614 <4 RK_PA0 4 &pcfg_pull_none>; 615 }; 616 }; 617 618 pwm0 { 619 /omit-if-no-ref/ 620 pwm0m0_pins: pwm0m0-pins { 621 rockchip,pins = 622 /* pwm0_m0 */ 623 <4 RK_PC3 1 &pcfg_pull_none_drv_level_0>; 624 }; 625 626 /omit-if-no-ref/ 627 pwm0m1_pins: pwm0m1-pins { 628 rockchip,pins = 629 /* pwm0_m1 */ 630 <1 RK_PA2 5 &pcfg_pull_none_drv_level_0>; 631 }; 632 }; 633 634 pwm1 { 635 /omit-if-no-ref/ 636 pwm1m0_pins: pwm1m0-pins { 637 rockchip,pins = 638 /* pwm1_m0 */ 639 <4 RK_PC4 1 &pcfg_pull_none_drv_level_0>; 640 }; 641 642 /omit-if-no-ref/ 643 pwm1m1_pins: pwm1m1-pins { 644 rockchip,pins = 645 /* pwm1_m1 */ 646 <1 RK_PA3 4 &pcfg_pull_none_drv_level_0>; 647 }; 648 }; 649 650 pwm2 { 651 /omit-if-no-ref/ 652 pwm2m0_pins: pwm2m0-pins { 653 rockchip,pins = 654 /* pwm2_m0 */ 655 <4 RK_PC5 1 &pcfg_pull_none_drv_level_0>; 656 }; 657 658 /omit-if-no-ref/ 659 pwm2m1_pins: pwm2m1-pins { 660 rockchip,pins = 661 /* pwm2_m1 */ 662 <1 RK_PA7 2 &pcfg_pull_none_drv_level_0>; 663 }; 664 }; 665 666 pwm3 { 667 /omit-if-no-ref/ 668 pwm3m0_pins: pwm3m0-pins { 669 rockchip,pins = 670 /* pwm3_m0 */ 671 <4 RK_PC6 1 &pcfg_pull_none_drv_level_0>; 672 }; 673 674 /omit-if-no-ref/ 675 pwm3m1_pins: pwm3m1-pins { 676 rockchip,pins = 677 /* pwm3_m1 */ 678 <2 RK_PA4 3 &pcfg_pull_none_drv_level_0>; 679 }; 680 }; 681 682 pwm4 { 683 /omit-if-no-ref/ 684 pwm4m0_pins: pwm4m0-pins { 685 rockchip,pins = 686 /* pwm4_m0 */ 687 <4 RK_PB7 1 &pcfg_pull_none_drv_level_0>; 688 }; 689 690 /omit-if-no-ref/ 691 pwm4m1_pins: pwm4m1-pins { 692 rockchip,pins = 693 /* pwm4_m1 */ 694 <1 RK_PA4 2 &pcfg_pull_none_drv_level_0>; 695 }; 696 }; 697 698 pwm5 { 699 /omit-if-no-ref/ 700 pwm5m0_pins: pwm5m0-pins { 701 rockchip,pins = 702 /* pwm5_m0 */ 703 <4 RK_PC0 1 &pcfg_pull_none_drv_level_0>; 704 }; 705 706 /omit-if-no-ref/ 707 pwm5m1_pins: pwm5m1-pins { 708 rockchip,pins = 709 /* pwm5_m1 */ 710 <3 RK_PC3 1 &pcfg_pull_none_drv_level_0>; 711 }; 712 }; 713 714 pwm6 { 715 /omit-if-no-ref/ 716 pwm6m0_pins: pwm6m0-pins { 717 rockchip,pins = 718 /* pwm6_m0 */ 719 <4 RK_PC1 1 &pcfg_pull_none_drv_level_0>; 720 }; 721 722 /omit-if-no-ref/ 723 pwm6m1_pins: pwm6m1-pins { 724 rockchip,pins = 725 /* pwm6_m1 */ 726 <1 RK_PC3 3 &pcfg_pull_none_drv_level_0>; 727 }; 728 729 /omit-if-no-ref/ 730 pwm6m2_pins: pwm6m2-pins { 731 rockchip,pins = 732 /* pwm6_m2 */ 733 <3 RK_PC1 1 &pcfg_pull_none_drv_level_0>; 734 }; 735 }; 736 737 pwm7 { 738 /omit-if-no-ref/ 739 pwm7m0_pins: pwm7m0-pins { 740 rockchip,pins = 741 /* pwm7_m0 */ 742 <4 RK_PC2 1 &pcfg_pull_none_drv_level_0>; 743 }; 744 745 /omit-if-no-ref/ 746 pwm7m1_pins: pwm7m1-pins { 747 rockchip,pins = 748 /* pwm7_m1 */ 749 <1 RK_PC2 2 &pcfg_pull_none_drv_level_0>; 750 }; 751 }; 752 753 pwr { 754 /omit-if-no-ref/ 755 pwr_pins: pwr-pins { 756 rockchip,pins = 757 /* pwr_ctrl0 */ 758 <4 RK_PC2 2 &pcfg_pull_none>, 759 /* pwr_ctrl1 */ 760 <4 RK_PB6 1 &pcfg_pull_none>; 761 }; 762 }; 763 764 ref { 765 /omit-if-no-ref/ 766 refm0_pins: refm0-pins { 767 rockchip,pins = 768 /* ref_clk_out_m0 */ 769 <0 RK_PA1 1 &pcfg_pull_none>; 770 }; 771 772 /omit-if-no-ref/ 773 refm1_pins: refm1-pins { 774 rockchip,pins = 775 /* ref_clk_out_m1 */ 776 <3 RK_PC3 6 &pcfg_pull_none>; 777 }; 778 }; 779 780 rgmii { 781 /omit-if-no-ref/ 782 rgmii_miim: rgmii-miim { 783 rockchip,pins = 784 /* rgmii_mdc */ 785 <3 RK_PB6 2 &pcfg_pull_none_drv_level_2>, 786 /* rgmii_mdio */ 787 <3 RK_PB7 2 &pcfg_pull_none_drv_level_2>; 788 }; 789 790 /omit-if-no-ref/ 791 rgmii_rx_bus2: rgmii-rx_bus2 { 792 rockchip,pins = 793 /* rgmii_rxd0 */ 794 <3 RK_PA3 2 &pcfg_pull_none>, 795 /* rgmii_rxd1 */ 796 <3 RK_PA2 2 &pcfg_pull_none>, 797 /* rgmii_rxdv_crs */ 798 <3 RK_PC2 2 &pcfg_pull_none>; 799 }; 800 801 /omit-if-no-ref/ 802 rgmii_tx_bus2: rgmii-tx_bus2 { 803 rockchip,pins = 804 /* rgmii_txd0 */ 805 <3 RK_PA1 2 &pcfg_pull_none_drv_level_2>, 806 /* rgmii_txd1 */ 807 <3 RK_PA0 2 &pcfg_pull_none_drv_level_2>, 808 /* rgmii_txen */ 809 <3 RK_PC0 2 &pcfg_pull_none>; 810 }; 811 812 /omit-if-no-ref/ 813 rgmii_rgmii_clk: rgmii-rgmii_clk { 814 rockchip,pins = 815 /* rgmii_rxclk */ 816 <3 RK_PA5 2 &pcfg_pull_none>, 817 /* rgmii_txclk */ 818 <3 RK_PA4 2 &pcfg_pull_none_drv_level_2>; 819 }; 820 821 /omit-if-no-ref/ 822 rgmii_rgmii_bus: rgmii-rgmii_bus { 823 rockchip,pins = 824 /* rgmii_rxd2 */ 825 <3 RK_PA7 2 &pcfg_pull_none>, 826 /* rgmii_rxd3 */ 827 <3 RK_PA6 2 &pcfg_pull_none>, 828 /* rgmii_txd2 */ 829 <3 RK_PB1 2 &pcfg_pull_none_drv_level_2>, 830 /* rgmii_txd3 */ 831 <3 RK_PB0 2 &pcfg_pull_none_drv_level_2>; 832 }; 833 834 /omit-if-no-ref/ 835 rgmii_clk: rgmii-clk { 836 rockchip,pins = 837 /* rgmii_clk */ 838 <3 RK_PB4 2 &pcfg_pull_none>; 839 }; 840 /omit-if-no-ref/ 841 rgmii_txer: rgmii-txer { 842 rockchip,pins = 843 /* rgmii_txer */ 844 <3 RK_PC1 2 &pcfg_pull_none>; 845 }; 846 }; 847 848 scr { 849 /omit-if-no-ref/ 850 scrm0_pins: scrm0-pins { 851 rockchip,pins = 852 /* scr_clk_m0 */ 853 <1 RK_PA2 3 &pcfg_pull_none>, 854 /* scr_data_m0 */ 855 <1 RK_PA1 3 &pcfg_pull_none>, 856 /* scr_detn_m0 */ 857 <1 RK_PA0 3 &pcfg_pull_none>, 858 /* scr_rstn_m0 */ 859 <1 RK_PA3 3 &pcfg_pull_none>; 860 }; 861 862 /omit-if-no-ref/ 863 scrm1_pins: scrm1-pins { 864 rockchip,pins = 865 /* scr_clk_m1 */ 866 <2 RK_PA5 3 &pcfg_pull_none>, 867 /* scr_data_m1 */ 868 <2 RK_PA3 4 &pcfg_pull_none>, 869 /* scr_detn_m1 */ 870 <2 RK_PA6 3 &pcfg_pull_none>, 871 /* scr_rstn_m1 */ 872 <2 RK_PA4 4 &pcfg_pull_none>; 873 }; 874 }; 875 876 sdio0 { 877 /omit-if-no-ref/ 878 sdio0_bus4: sdio0-bus4 { 879 rockchip,pins = 880 /* sdio0_d0 */ 881 <1 RK_PA0 1 &pcfg_pull_up_drv_level_2>, 882 /* sdio0_d1 */ 883 <1 RK_PA1 1 &pcfg_pull_up_drv_level_2>, 884 /* sdio0_d2 */ 885 <1 RK_PA2 1 &pcfg_pull_up_drv_level_2>, 886 /* sdio0_d3 */ 887 <1 RK_PA3 1 &pcfg_pull_up_drv_level_2>; 888 }; 889 890 /omit-if-no-ref/ 891 sdio0_clk: sdio0-clk { 892 rockchip,pins = 893 /* sdio0_clk */ 894 <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>; 895 }; 896 897 /omit-if-no-ref/ 898 sdio0_cmd: sdio0-cmd { 899 rockchip,pins = 900 /* sdio0_cmd */ 901 <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>; 902 }; 903 904 /omit-if-no-ref/ 905 sdio0_det: sdio0-det { 906 rockchip,pins = 907 /* sdio0_det */ 908 <1 RK_PA6 1 &pcfg_pull_up>; 909 }; 910 911 /omit-if-no-ref/ 912 sdio0_pwren: sdio0-pwren { 913 rockchip,pins = 914 /* sdio0_pwren */ 915 <1 RK_PA7 1 &pcfg_pull_none>; 916 }; 917 }; 918 919 sdio1 { 920 /omit-if-no-ref/ 921 sdio1_bus4: sdio1-bus4 { 922 rockchip,pins = 923 /* sdio1_d0 */ 924 <3 RK_PA6 1 &pcfg_pull_up_drv_level_2>, 925 /* sdio1_d1 */ 926 <3 RK_PA7 1 &pcfg_pull_up_drv_level_2>, 927 /* sdio1_d2 */ 928 <3 RK_PB0 1 &pcfg_pull_up_drv_level_2>, 929 /* sdio1_d3 */ 930 <3 RK_PB1 1 &pcfg_pull_up_drv_level_2>; 931 }; 932 933 /omit-if-no-ref/ 934 sdio1_clk: sdio1-clk { 935 rockchip,pins = 936 /* sdio1_clk */ 937 <3 RK_PA4 1 &pcfg_pull_up_drv_level_2>; 938 }; 939 940 /omit-if-no-ref/ 941 sdio1_cmd: sdio1-cmd { 942 rockchip,pins = 943 /* sdio1_cmd */ 944 <3 RK_PA5 1 &pcfg_pull_up_drv_level_2>; 945 }; 946 947 /omit-if-no-ref/ 948 sdio1_det: sdio1-det { 949 rockchip,pins = 950 /* sdio1_det */ 951 <3 RK_PB3 1 &pcfg_pull_up>; 952 }; 953 954 /omit-if-no-ref/ 955 sdio1_pwren: sdio1-pwren { 956 rockchip,pins = 957 /* sdio1_pwren */ 958 <3 RK_PB2 1 &pcfg_pull_none>; 959 }; 960 }; 961 962 sdmmc { 963 /omit-if-no-ref/ 964 sdmmc_bus4: sdmmc-bus4 { 965 rockchip,pins = 966 /* sdmmc_d0 */ 967 <2 RK_PA0 1 &pcfg_pull_up_drv_level_2>, 968 /* sdmmc_d1 */ 969 <2 RK_PA1 1 &pcfg_pull_up_drv_level_2>, 970 /* sdmmc_d2 */ 971 <2 RK_PA2 1 &pcfg_pull_up_drv_level_2>, 972 /* sdmmc_d3 */ 973 <2 RK_PA3 1 &pcfg_pull_up_drv_level_2>; 974 }; 975 976 /omit-if-no-ref/ 977 sdmmc_clk: sdmmc-clk { 978 rockchip,pins = 979 /* sdmmc_clk */ 980 <2 RK_PA5 1 &pcfg_pull_up_drv_level_2>; 981 }; 982 983 /omit-if-no-ref/ 984 sdmmc_cmd: sdmmc-cmd { 985 rockchip,pins = 986 /* sdmmc_cmd */ 987 <2 RK_PA4 1 &pcfg_pull_up_drv_level_2>; 988 }; 989 990 /omit-if-no-ref/ 991 sdmmc_det: sdmmc-det { 992 rockchip,pins = 993 /* sdmmc_detn */ 994 <2 RK_PA6 1 &pcfg_pull_up>; 995 }; 996 997 /omit-if-no-ref/ 998 sdmmc_pwren: sdmmc-pwren { 999 rockchip,pins = 1000 /* sdmmc_pwren */ 1001 <4 RK_PA1 1 &pcfg_pull_none>; 1002 }; 1003 }; 1004 1005 spdif { 1006 /omit-if-no-ref/ 1007 spdifm0_pins: spdifm0-pins { 1008 rockchip,pins = 1009 /* spdif_tx_m0 */ 1010 <4 RK_PA0 1 &pcfg_pull_none>; 1011 }; 1012 1013 /omit-if-no-ref/ 1014 spdifm1_pins: spdifm1-pins { 1015 rockchip,pins = 1016 /* spdif_tx_m1 */ 1017 <1 RK_PC3 2 &pcfg_pull_none>; 1018 }; 1019 1020 /omit-if-no-ref/ 1021 spdifm2_pins: spdifm2-pins { 1022 rockchip,pins = 1023 /* spdif_tx_m2 */ 1024 <3 RK_PC3 2 &pcfg_pull_none>; 1025 }; 1026 }; 1027 1028 spi0 { 1029 /omit-if-no-ref/ 1030 spi0_pins: spi0-pins { 1031 rockchip,pins = 1032 /* spi0_clk */ 1033 <4 RK_PB4 2 &pcfg_pull_none>, 1034 /* spi0_miso */ 1035 <4 RK_PB3 2 &pcfg_pull_none>, 1036 /* spi0_mosi */ 1037 <4 RK_PB2 2 &pcfg_pull_none>; 1038 }; 1039 1040 /omit-if-no-ref/ 1041 spi0_csn0: spi0-csn0 { 1042 rockchip,pins = 1043 /* spi0_csn0 */ 1044 <4 RK_PB6 2 &pcfg_pull_none>; 1045 }; 1046 /omit-if-no-ref/ 1047 spi0_csn1: spi0-csn1 { 1048 rockchip,pins = 1049 /* spi0_csn1 */ 1050 <4 RK_PC1 2 &pcfg_pull_none>; 1051 }; 1052 }; 1053 1054 spi1 { 1055 /omit-if-no-ref/ 1056 spi1_pins: spi1-pins { 1057 rockchip,pins = 1058 /* spi1_clk */ 1059 <1 RK_PB6 2 &pcfg_pull_none>, 1060 /* spi1_miso */ 1061 <1 RK_PC0 2 &pcfg_pull_none>, 1062 /* spi1_mosi */ 1063 <1 RK_PB7 2 &pcfg_pull_none>; 1064 }; 1065 1066 /omit-if-no-ref/ 1067 spi1_csn0: spi1-csn0 { 1068 rockchip,pins = 1069 /* spi1_csn0 */ 1070 <1 RK_PC1 1 &pcfg_pull_none>; 1071 }; 1072 /omit-if-no-ref/ 1073 spi1_csn1: spi1-csn1 { 1074 rockchip,pins = 1075 /* spi1_csn1 */ 1076 <1 RK_PC2 1 &pcfg_pull_none>; 1077 }; 1078 }; 1079 1080 tsi0 { 1081 /omit-if-no-ref/ 1082 tsi0_pins: tsi0-pins { 1083 rockchip,pins = 1084 /* tsi0_clkin */ 1085 <3 RK_PB2 3 &pcfg_pull_none>, 1086 /* tsi0_d0 */ 1087 <3 RK_PB1 3 &pcfg_pull_none>, 1088 /* tsi0_d1 */ 1089 <3 RK_PB5 3 &pcfg_pull_none>, 1090 /* tsi0_d2 */ 1091 <3 RK_PB6 3 &pcfg_pull_none>, 1092 /* tsi0_d3 */ 1093 <3 RK_PB7 3 &pcfg_pull_none>, 1094 /* tsi0_d4 */ 1095 <3 RK_PA3 3 &pcfg_pull_none>, 1096 /* tsi0_d5 */ 1097 <3 RK_PA2 3 &pcfg_pull_none>, 1098 /* tsi0_d6 */ 1099 <3 RK_PA1 3 &pcfg_pull_none>, 1100 /* tsi0_d7 */ 1101 <3 RK_PA0 3 &pcfg_pull_none>, 1102 /* tsi0_fail */ 1103 <3 RK_PC0 3 &pcfg_pull_none>, 1104 /* tsi0_sync */ 1105 <3 RK_PB4 3 &pcfg_pull_none>, 1106 /* tsi0_valid */ 1107 <3 RK_PB3 3 &pcfg_pull_none>; 1108 }; 1109 }; 1110 1111 tsi1 { 1112 /omit-if-no-ref/ 1113 tsi1_pins: tsi1-pins { 1114 rockchip,pins = 1115 /* tsi1_clkin */ 1116 <3 RK_PA5 3 &pcfg_pull_none>, 1117 /* tsi1_d0 */ 1118 <3 RK_PA4 3 &pcfg_pull_none>, 1119 /* tsi1_sync */ 1120 <3 RK_PA7 3 &pcfg_pull_none>, 1121 /* tsi1_valid */ 1122 <3 RK_PA6 3 &pcfg_pull_none>; 1123 }; 1124 }; 1125 1126 uart0 { 1127 /omit-if-no-ref/ 1128 uart0m0_xfer: uart0m0-xfer { 1129 rockchip,pins = 1130 /* uart0_rx_m0 */ 1131 <4 RK_PC7 1 &pcfg_pull_up>, 1132 /* uart0_tx_m0 */ 1133 <4 RK_PD0 1 &pcfg_pull_up>; 1134 }; 1135 1136 /omit-if-no-ref/ 1137 uart0m1_xfer: uart0m1-xfer { 1138 rockchip,pins = 1139 /* uart0_rx_m1 */ 1140 <2 RK_PA0 2 &pcfg_pull_up>, 1141 /* uart0_tx_m1 */ 1142 <2 RK_PA1 2 &pcfg_pull_up>; 1143 }; 1144 }; 1145 1146 uart1 { 1147 /omit-if-no-ref/ 1148 uart1m0_xfer: uart1m0-xfer { 1149 rockchip,pins = 1150 /* uart1_rx_m0 */ 1151 <4 RK_PA7 2 &pcfg_pull_up>, 1152 /* uart1_tx_m0 */ 1153 <4 RK_PA6 2 &pcfg_pull_up>; 1154 }; 1155 1156 /omit-if-no-ref/ 1157 uart1m1_xfer: uart1m1-xfer { 1158 rockchip,pins = 1159 /* uart1_rx_m1 */ 1160 <4 RK_PC6 2 &pcfg_pull_up>, 1161 /* uart1_tx_m1 */ 1162 <4 RK_PC5 2 &pcfg_pull_up>; 1163 }; 1164 1165 /omit-if-no-ref/ 1166 uart1_ctsn: uart1-ctsn { 1167 rockchip,pins = 1168 /* uart1_ctsn */ 1169 <4 RK_PA4 2 &pcfg_pull_none>; 1170 }; 1171 /omit-if-no-ref/ 1172 uart1_rtsn: uart1-rtsn { 1173 rockchip,pins = 1174 /* uart1_rtsn */ 1175 <4 RK_PA5 2 &pcfg_pull_none>; 1176 }; 1177 }; 1178 1179 uart2 { 1180 /omit-if-no-ref/ 1181 uart2m0_xfer: uart2m0-xfer { 1182 rockchip,pins = 1183 /* uart2_rx_m0 */ 1184 <3 RK_PA0 1 &pcfg_pull_up>, 1185 /* uart2_tx_m0 */ 1186 <3 RK_PA1 1 &pcfg_pull_up>; 1187 }; 1188 1189 /omit-if-no-ref/ 1190 uart2m0_ctsn: uart2m0-ctsn { 1191 rockchip,pins = 1192 /* uart2m0_ctsn */ 1193 <3 RK_PA3 1 &pcfg_pull_none>; 1194 }; 1195 /omit-if-no-ref/ 1196 uart2m0_rtsn: uart2m0-rtsn { 1197 rockchip,pins = 1198 /* uart2m0_rtsn */ 1199 <3 RK_PA2 1 &pcfg_pull_none>; 1200 }; 1201 1202 /omit-if-no-ref/ 1203 uart2m1_xfer: uart2m1-xfer { 1204 rockchip,pins = 1205 /* uart2_rx_m1 */ 1206 <1 RK_PB0 1 &pcfg_pull_up>, 1207 /* uart2_tx_m1 */ 1208 <1 RK_PB1 1 &pcfg_pull_up>; 1209 }; 1210 1211 /omit-if-no-ref/ 1212 uart2m1_ctsn: uart2m1-ctsn { 1213 rockchip,pins = 1214 /* uart2m1_ctsn */ 1215 <1 RK_PB3 1 &pcfg_pull_none>; 1216 }; 1217 /omit-if-no-ref/ 1218 uart2m1_rtsn: uart2m1-rtsn { 1219 rockchip,pins = 1220 /* uart2m1_rtsn */ 1221 <1 RK_PB2 1 &pcfg_pull_none>; 1222 }; 1223 }; 1224 1225 uart3 { 1226 /omit-if-no-ref/ 1227 uart3m0_xfer: uart3m0-xfer { 1228 rockchip,pins = 1229 /* uart3_rx_m0 */ 1230 <4 RK_PB0 2 &pcfg_pull_up>, 1231 /* uart3_tx_m0 */ 1232 <4 RK_PB1 2 &pcfg_pull_up>; 1233 }; 1234 1235 /omit-if-no-ref/ 1236 uart3m1_xfer: uart3m1-xfer { 1237 rockchip,pins = 1238 /* uart3_rx_m1 */ 1239 <4 RK_PB7 3 &pcfg_pull_up>, 1240 /* uart3_tx_m1 */ 1241 <4 RK_PC0 3 &pcfg_pull_up>; 1242 }; 1243 1244 /omit-if-no-ref/ 1245 uart3_ctsn: uart3-ctsn { 1246 rockchip,pins = 1247 /* uart3_ctsn */ 1248 <4 RK_PA3 3 &pcfg_pull_none>; 1249 }; 1250 /omit-if-no-ref/ 1251 uart3_rtsn: uart3-rtsn { 1252 rockchip,pins = 1253 /* uart3_rtsn */ 1254 <4 RK_PA2 3 &pcfg_pull_none>; 1255 }; 1256 }; 1257 1258 uart4 { 1259 /omit-if-no-ref/ 1260 uart4_xfer: uart4-xfer { 1261 rockchip,pins = 1262 /* uart4_rx */ 1263 <2 RK_PA2 3 &pcfg_pull_up>, 1264 /* uart4_tx */ 1265 <2 RK_PA3 3 &pcfg_pull_up>; 1266 }; 1267 1268 /omit-if-no-ref/ 1269 uart4_ctsn: uart4-ctsn { 1270 rockchip,pins = 1271 /* uart4_ctsn */ 1272 <2 RK_PA1 3 &pcfg_pull_none>; 1273 }; 1274 /omit-if-no-ref/ 1275 uart4_rtsn: uart4-rtsn { 1276 rockchip,pins = 1277 /* uart4_rtsn */ 1278 <2 RK_PA0 3 &pcfg_pull_none>; 1279 }; 1280 }; 1281 1282 uart5 { 1283 /omit-if-no-ref/ 1284 uart5m0_xfer: uart5m0-xfer { 1285 rockchip,pins = 1286 /* uart5_rx_m0 */ 1287 <1 RK_PA2 2 &pcfg_pull_up>, 1288 /* uart5_tx_m0 */ 1289 <1 RK_PA3 2 &pcfg_pull_up>; 1290 }; 1291 1292 /omit-if-no-ref/ 1293 uart5m0_ctsn: uart5m0-ctsn { 1294 rockchip,pins = 1295 /* uart5m0_ctsn */ 1296 <1 RK_PA6 2 &pcfg_pull_none>; 1297 }; 1298 /omit-if-no-ref/ 1299 uart5m0_rtsn: uart5m0-rtsn { 1300 rockchip,pins = 1301 /* uart5m0_rtsn */ 1302 <1 RK_PA5 2 &pcfg_pull_none>; 1303 }; 1304 1305 /omit-if-no-ref/ 1306 uart5m1_xfer: uart5m1-xfer { 1307 rockchip,pins = 1308 /* uart5_rx_m1 */ 1309 <1 RK_PD4 2 &pcfg_pull_up>, 1310 /* uart5_tx_m1 */ 1311 <1 RK_PD7 2 &pcfg_pull_up>; 1312 }; 1313 1314 /omit-if-no-ref/ 1315 uart5m1_ctsn: uart5m1-ctsn { 1316 rockchip,pins = 1317 /* uart5m1_ctsn */ 1318 <1 RK_PD3 2 &pcfg_pull_none>; 1319 }; 1320 /omit-if-no-ref/ 1321 uart5m1_rtsn: uart5m1-rtsn { 1322 rockchip,pins = 1323 /* uart5m1_rtsn */ 1324 <1 RK_PD2 2 &pcfg_pull_none>; 1325 }; 1326 }; 1327 1328 uart6 { 1329 /omit-if-no-ref/ 1330 uart6m0_xfer: uart6m0-xfer { 1331 rockchip,pins = 1332 /* uart6_rx_m0 */ 1333 <3 RK_PA7 4 &pcfg_pull_up>, 1334 /* uart6_tx_m0 */ 1335 <3 RK_PA6 4 &pcfg_pull_up>; 1336 }; 1337 1338 /omit-if-no-ref/ 1339 uart6m1_xfer: uart6m1-xfer { 1340 rockchip,pins = 1341 /* uart6_rx_m1 */ 1342 <3 RK_PC3 4 &pcfg_pull_up>, 1343 /* uart6_tx_m1 */ 1344 <3 RK_PC1 4 &pcfg_pull_up>; 1345 }; 1346 1347 /omit-if-no-ref/ 1348 uart6_ctsn: uart6-ctsn { 1349 rockchip,pins = 1350 /* uart6_ctsn */ 1351 <3 RK_PA4 4 &pcfg_pull_none>; 1352 }; 1353 /omit-if-no-ref/ 1354 uart6_rtsn: uart6-rtsn { 1355 rockchip,pins = 1356 /* uart6_rtsn */ 1357 <3 RK_PA5 4 &pcfg_pull_none>; 1358 }; 1359 }; 1360 1361 uart7 { 1362 /omit-if-no-ref/ 1363 uart7m0_xfer: uart7m0-xfer { 1364 rockchip,pins = 1365 /* uart7_rx_m0 */ 1366 <3 RK_PB3 4 &pcfg_pull_up>, 1367 /* uart7_tx_m0 */ 1368 <3 RK_PB2 4 &pcfg_pull_up>; 1369 }; 1370 1371 /omit-if-no-ref/ 1372 uart7m0_ctsn: uart7m0-ctsn { 1373 rockchip,pins = 1374 /* uart7m0_ctsn */ 1375 <3 RK_PB0 4 &pcfg_pull_none>; 1376 }; 1377 /omit-if-no-ref/ 1378 uart7m0_rtsn: uart7m0-rtsn { 1379 rockchip,pins = 1380 /* uart7m0_rtsn */ 1381 <3 RK_PB1 4 &pcfg_pull_none>; 1382 }; 1383 1384 /omit-if-no-ref/ 1385 uart7m1_xfer: uart7m1-xfer { 1386 rockchip,pins = 1387 /* uart7_rx_m1 */ 1388 <1 RK_PB3 4 &pcfg_pull_up>, 1389 /* uart7_tx_m1 */ 1390 <1 RK_PB2 4 &pcfg_pull_up>; 1391 }; 1392 1393 /omit-if-no-ref/ 1394 uart7m1_ctsn: uart7m1-ctsn { 1395 rockchip,pins = 1396 /* uart7m1_ctsn */ 1397 <1 RK_PB0 4 &pcfg_pull_none>; 1398 }; 1399 /omit-if-no-ref/ 1400 uart7m1_rtsn: uart7m1-rtsn { 1401 rockchip,pins = 1402 /* uart7m1_rtsn */ 1403 <1 RK_PB1 4 &pcfg_pull_none>; 1404 }; 1405 }; 1406}; 1407