1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2023 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun */
6*4882a593Smuzhiyun
7*4882a593Smuzhiyun/dts-v1/;
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun#include "rk3399-excavator-sapphire.dtsi"
10*4882a593Smuzhiyun#include "rk3399-linux.dtsi"
11*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun/ {
14*4882a593Smuzhiyun	model = "Rockchip RK3399 Excavator Board (Linux Opensource)";
15*4882a593Smuzhiyun	compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399";
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun	backlight: backlight {
18*4882a593Smuzhiyun		compatible = "pwm-backlight";
19*4882a593Smuzhiyun		brightness-levels = <
20*4882a593Smuzhiyun			  0   1   2   3   4   5   6   7
21*4882a593Smuzhiyun			  8   9  10  11  12  13  14  15
22*4882a593Smuzhiyun			 16  17  18  19  20  21  22  23
23*4882a593Smuzhiyun			 24  25  26  27  28  29  30  31
24*4882a593Smuzhiyun			 32  33  34  35  36  37  38  39
25*4882a593Smuzhiyun			 40  41  42  43  44  45  46  47
26*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
27*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
28*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
29*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
30*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
31*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
32*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
33*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
34*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
35*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
36*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
37*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
38*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
39*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
40*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
41*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
42*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
43*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
44*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
45*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
46*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
47*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
48*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
49*4882a593Smuzhiyun			232 233 234 235 236 237 238 239
50*4882a593Smuzhiyun			240 241 242 243 244 245 246 247
51*4882a593Smuzhiyun			248 249 250 251 252 253 254 255>;
52*4882a593Smuzhiyun		default-brightness-level = <200>;
53*4882a593Smuzhiyun		pwms = <&pwm0 0 25000 0>;
54*4882a593Smuzhiyun		enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
55*4882a593Smuzhiyun	};
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun	vcc_lcd: vcc-lcd {
58*4882a593Smuzhiyun		compatible = "regulator-fixed";
59*4882a593Smuzhiyun		regulator-name = "vcc_lcd";
60*4882a593Smuzhiyun		gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
61*4882a593Smuzhiyun		startup-delay-us = <20000>;
62*4882a593Smuzhiyun		enable-active-high;
63*4882a593Smuzhiyun		regulator-min-microvolt = <3300000>;
64*4882a593Smuzhiyun		regulator-max-microvolt = <3300000>;
65*4882a593Smuzhiyun		regulator-boot-on;
66*4882a593Smuzhiyun		vin-supply = <&vcc_sys>;
67*4882a593Smuzhiyun	};
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun	panel: panel {
70*4882a593Smuzhiyun		compatible = "simple-panel";
71*4882a593Smuzhiyun		backlight = <&backlight>;
72*4882a593Smuzhiyun		power-supply = <&vcc_lcd>;
73*4882a593Smuzhiyun		enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
74*4882a593Smuzhiyun		prepare-delay-ms = <20>;
75*4882a593Smuzhiyun		enable-delay-ms = <20>;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun		display-timings {
78*4882a593Smuzhiyun			native-mode = <&timing0>;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun			timing0: timing0 {
81*4882a593Smuzhiyun				clock-frequency = <200000000>;
82*4882a593Smuzhiyun				hactive = <1536>;
83*4882a593Smuzhiyun				vactive = <2048>;
84*4882a593Smuzhiyun				hfront-porch = <12>;
85*4882a593Smuzhiyun				hsync-len = <16>;
86*4882a593Smuzhiyun				hback-porch = <48>;
87*4882a593Smuzhiyun				vfront-porch = <8>;
88*4882a593Smuzhiyun				vsync-len = <4>;
89*4882a593Smuzhiyun				vback-porch = <8>;
90*4882a593Smuzhiyun				hsync-active = <0>;
91*4882a593Smuzhiyun				vsync-active = <0>;
92*4882a593Smuzhiyun				de-active = <0>;
93*4882a593Smuzhiyun				pixelclk-active = <0>;
94*4882a593Smuzhiyun			};
95*4882a593Smuzhiyun		};
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun		ports {
98*4882a593Smuzhiyun			panel_in: endpoint {
99*4882a593Smuzhiyun				remote-endpoint = <&edp_out>;
100*4882a593Smuzhiyun			};
101*4882a593Smuzhiyun		};
102*4882a593Smuzhiyun	};
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun	hdmi_sound: hdmi-sound {
105*4882a593Smuzhiyun		status = "okay";
106*4882a593Smuzhiyun	};
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun	gpio-keys {
109*4882a593Smuzhiyun		compatible = "gpio-keys";
110*4882a593Smuzhiyun		#address-cells = <1>;
111*4882a593Smuzhiyun		#size-cells = <0>;
112*4882a593Smuzhiyun		autorepeat;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun		pinctrl-names = "default";
115*4882a593Smuzhiyun		pinctrl-0 = <&pwrbtn>;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun		button@0 {
118*4882a593Smuzhiyun			gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
119*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
120*4882a593Smuzhiyun			label = "GPIO Key Power";
121*4882a593Smuzhiyun			linux,input-type = <1>;
122*4882a593Smuzhiyun			gpio-key,wakeup = <1>;
123*4882a593Smuzhiyun			debounce-interval = <100>;
124*4882a593Smuzhiyun		};
125*4882a593Smuzhiyun	};
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun	vccadc_ref: vccadc-ref {
128*4882a593Smuzhiyun		compatible = "regulator-fixed";
129*4882a593Smuzhiyun		regulator-name = "vcc1v8_sys";
130*4882a593Smuzhiyun		regulator-always-on;
131*4882a593Smuzhiyun		regulator-boot-on;
132*4882a593Smuzhiyun		regulator-min-microvolt = <1800000>;
133*4882a593Smuzhiyun		regulator-max-microvolt = <1800000>;
134*4882a593Smuzhiyun	};
135*4882a593Smuzhiyun
136*4882a593Smuzhiyun	ext_cam_clk: external-camera-clock {
137*4882a593Smuzhiyun		compatible = "fixed-clock";
138*4882a593Smuzhiyun		clock-frequency = <27000000>;
139*4882a593Smuzhiyun		clock-output-names = "CLK_CAMERA_27MHZ";
140*4882a593Smuzhiyun		#clock-cells = <0>;
141*4882a593Smuzhiyun	};
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun	adc-keys {
144*4882a593Smuzhiyun		compatible = "adc-keys";
145*4882a593Smuzhiyun		io-channels = <&saradc 1>;
146*4882a593Smuzhiyun		io-channel-names = "buttons";
147*4882a593Smuzhiyun		poll-interval = <100>;
148*4882a593Smuzhiyun		keyup-threshold-microvolt = <1800000>;
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun		button-up {
151*4882a593Smuzhiyun			label = "Volume Up";
152*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
153*4882a593Smuzhiyun			press-threshold-microvolt = <100000>;
154*4882a593Smuzhiyun		};
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun		button-down {
157*4882a593Smuzhiyun			label = "Volume Down";
158*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
159*4882a593Smuzhiyun			press-threshold-microvolt = <300000>;
160*4882a593Smuzhiyun		};
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun		back {
163*4882a593Smuzhiyun			label = "Back";
164*4882a593Smuzhiyun			linux,code = <KEY_BACK>;
165*4882a593Smuzhiyun			press-threshold-microvolt = <985000>;
166*4882a593Smuzhiyun		};
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun		menu {
169*4882a593Smuzhiyun			label = "Menu";
170*4882a593Smuzhiyun			linux,code = <KEY_MENU>;
171*4882a593Smuzhiyun			press-threshold-microvolt = <1314000>;
172*4882a593Smuzhiyun		};
173*4882a593Smuzhiyun	};
174*4882a593Smuzhiyun};
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun&rkisp1_0 {
177*4882a593Smuzhiyun	status = "okay";
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun	port {
180*4882a593Smuzhiyun		#address-cells = <1>;
181*4882a593Smuzhiyun		#size-cells = <0>;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun		isp0_mipi_in: endpoint@0 {
184*4882a593Smuzhiyun			reg = <0>;
185*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx0_out>;
186*4882a593Smuzhiyun		};
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun};
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun&mipi_dphy_rx0 {
191*4882a593Smuzhiyun	status = "okay";
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun	ports {
194*4882a593Smuzhiyun		#address-cells = <1>;
195*4882a593Smuzhiyun		#size-cells = <0>;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun		port@0 {
198*4882a593Smuzhiyun			reg = <0>;
199*4882a593Smuzhiyun			#address-cells = <1>;
200*4882a593Smuzhiyun			#size-cells = <0>;
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun			mipi_in_ucam0: endpoint@1 {
203*4882a593Smuzhiyun				reg = <1>;
204*4882a593Smuzhiyun				remote-endpoint = <&ucam_out0>;
205*4882a593Smuzhiyun				data-lanes = <1 2>;
206*4882a593Smuzhiyun			};
207*4882a593Smuzhiyun		};
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun		port@1 {
210*4882a593Smuzhiyun			reg = <1>;
211*4882a593Smuzhiyun			#address-cells = <1>;
212*4882a593Smuzhiyun			#size-cells = <0>;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun			dphy_rx0_out: endpoint@0 {
215*4882a593Smuzhiyun				reg = <0>;
216*4882a593Smuzhiyun				remote-endpoint = <&isp0_mipi_in>;
217*4882a593Smuzhiyun			};
218*4882a593Smuzhiyun		};
219*4882a593Smuzhiyun	};
220*4882a593Smuzhiyun};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun&isp0_mmu {
223*4882a593Smuzhiyun	status = "okay";
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&rkisp1_1 {
227*4882a593Smuzhiyun	status = "okay";
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun	port {
230*4882a593Smuzhiyun		#address-cells = <1>;
231*4882a593Smuzhiyun		#size-cells = <0>;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun		isp1_mipi_in: endpoint@0 {
234*4882a593Smuzhiyun			reg = <0>;
235*4882a593Smuzhiyun			remote-endpoint = <&dphy_tx1rx1_out>;
236*4882a593Smuzhiyun		};
237*4882a593Smuzhiyun	};
238*4882a593Smuzhiyun};
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun&mipi_dphy_tx1rx1 {
241*4882a593Smuzhiyun	status = "okay";
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun	ports {
244*4882a593Smuzhiyun		#address-cells = <1>;
245*4882a593Smuzhiyun		#size-cells = <0>;
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun		port@0 {
248*4882a593Smuzhiyun			reg = <0>;
249*4882a593Smuzhiyun			#address-cells = <1>;
250*4882a593Smuzhiyun			#size-cells = <0>;
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun			mipi_in_ucam1: endpoint@1 {
253*4882a593Smuzhiyun				reg = <1>;
254*4882a593Smuzhiyun				/* Unlinked camera */
255*4882a593Smuzhiyun				//remote-endpoint = <&ucam_out1>;
256*4882a593Smuzhiyun				data-lanes = <1 2>;
257*4882a593Smuzhiyun			};
258*4882a593Smuzhiyun		};
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun		port@1 {
261*4882a593Smuzhiyun			reg = <1>;
262*4882a593Smuzhiyun			#address-cells = <1>;
263*4882a593Smuzhiyun			#size-cells = <0>;
264*4882a593Smuzhiyun
265*4882a593Smuzhiyun			dphy_tx1rx1_out: endpoint@0 {
266*4882a593Smuzhiyun				reg = <0>;
267*4882a593Smuzhiyun				remote-endpoint = <&isp1_mipi_in>;
268*4882a593Smuzhiyun			};
269*4882a593Smuzhiyun		};
270*4882a593Smuzhiyun	};
271*4882a593Smuzhiyun};
272*4882a593Smuzhiyun
273*4882a593Smuzhiyun&isp1_mmu {
274*4882a593Smuzhiyun	status = "okay";
275*4882a593Smuzhiyun};
276*4882a593Smuzhiyun
277*4882a593Smuzhiyun&saradc {
278*4882a593Smuzhiyun	vref-supply = <&vccadc_ref>;
279*4882a593Smuzhiyun};
280*4882a593Smuzhiyun
281*4882a593Smuzhiyun&display_subsystem {
282*4882a593Smuzhiyun	status = "okay";
283*4882a593Smuzhiyun};
284*4882a593Smuzhiyun
285*4882a593Smuzhiyun&route_edp {
286*4882a593Smuzhiyun	status = "okay";
287*4882a593Smuzhiyun};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun&edp {
290*4882a593Smuzhiyun	status = "okay";
291*4882a593Smuzhiyun	force-hpd;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun	ports {
294*4882a593Smuzhiyun		port@1 {
295*4882a593Smuzhiyun			reg = <1>;
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun			edp_out: endpoint {
298*4882a593Smuzhiyun				remote-endpoint = <&panel_in>;
299*4882a593Smuzhiyun			};
300*4882a593Smuzhiyun		};
301*4882a593Smuzhiyun	};
302*4882a593Smuzhiyun};
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun&edp_in_vopb {
305*4882a593Smuzhiyun	status = "disabled";
306*4882a593Smuzhiyun};
307*4882a593Smuzhiyun
308*4882a593Smuzhiyun&hdmi {
309*4882a593Smuzhiyun	pinctrl-names = "default";
310*4882a593Smuzhiyun	pinctrl-0 = <&hdmi_i2c_xfer>, <&hdmi_cec>;
311*4882a593Smuzhiyun	#address-cells = <1>;
312*4882a593Smuzhiyun	#size-cells = <0>;
313*4882a593Smuzhiyun	#sound-dai-cells = <0>;
314*4882a593Smuzhiyun	status = "okay";
315*4882a593Smuzhiyun};
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun&hdmi_in_vopl {
318*4882a593Smuzhiyun	status = "disabled";
319*4882a593Smuzhiyun};
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun&i2c1 {
322*4882a593Smuzhiyun	status = "okay";
323*4882a593Smuzhiyun
324*4882a593Smuzhiyun	gsl3673: gsl3673@40 {
325*4882a593Smuzhiyun		compatible = "GSL,GSL3673";
326*4882a593Smuzhiyun		reg = <0x40>;
327*4882a593Smuzhiyun		screen_max_x = <1536>;
328*4882a593Smuzhiyun		screen_max_y = <2048>;
329*4882a593Smuzhiyun		irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
330*4882a593Smuzhiyun		rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>;
331*4882a593Smuzhiyun	};
332*4882a593Smuzhiyun
333*4882a593Smuzhiyun	tc358749x: tc358749x@f {
334*4882a593Smuzhiyun		compatible = "toshiba,tc358749";
335*4882a593Smuzhiyun		reg = <0xf>;
336*4882a593Smuzhiyun		clocks = <&ext_cam_clk>;
337*4882a593Smuzhiyun		clock-names = "refclk";
338*4882a593Smuzhiyun		reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
339*4882a593Smuzhiyun		interrupt-parent = <&gpio2>;
340*4882a593Smuzhiyun		interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
341*4882a593Smuzhiyun		pinctrl-names = "default";
342*4882a593Smuzhiyun		pinctrl-0 = <&hdmiin_gpios>;
343*4882a593Smuzhiyun		status = "disabled";
344*4882a593Smuzhiyun		port {
345*4882a593Smuzhiyun			hdmiin_out0: endpoint {
346*4882a593Smuzhiyun				/* Unlinked mipi dphy rx0 */
347*4882a593Smuzhiyun				//remote-endpoint = <&mipi_in_ucam0>;
348*4882a593Smuzhiyun				data-lanes = <1 2 3 4>;
349*4882a593Smuzhiyun				clock-noncontinuous;
350*4882a593Smuzhiyun				link-frequencies =
351*4882a593Smuzhiyun					/bits/ 64 <297000000>;
352*4882a593Smuzhiyun			};
353*4882a593Smuzhiyun		};
354*4882a593Smuzhiyun	};
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun	vm149c: vm149c@0c {
357*4882a593Smuzhiyun		compatible = "silicon touch,vm149c";
358*4882a593Smuzhiyun		status = "okay";
359*4882a593Smuzhiyun		reg = <0x0c>;
360*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
361*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
362*4882a593Smuzhiyun	};
363*4882a593Smuzhiyun
364*4882a593Smuzhiyun	ov13850: ov13850@10 {
365*4882a593Smuzhiyun		compatible = "ovti,ov13850";
366*4882a593Smuzhiyun		status = "okay";
367*4882a593Smuzhiyun		reg = <0x10>;
368*4882a593Smuzhiyun		clocks = <&cru SCLK_CIF_OUT>;
369*4882a593Smuzhiyun		clock-names = "xvclk";
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun		/* conflict with csi-ctl-gpios */
372*4882a593Smuzhiyun		reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
373*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
374*4882a593Smuzhiyun		pinctrl-names = "rockchip,camera_default";
375*4882a593Smuzhiyun		pinctrl-0 = <&cif_clkout>;
376*4882a593Smuzhiyun
377*4882a593Smuzhiyun		lens-focus = <&vm149c>;
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun		port {
380*4882a593Smuzhiyun			ucam_out0: endpoint {
381*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_ucam0>;
382*4882a593Smuzhiyun				data-lanes = <1 2>;
383*4882a593Smuzhiyun			};
384*4882a593Smuzhiyun		};
385*4882a593Smuzhiyun	};
386*4882a593Smuzhiyun};
387*4882a593Smuzhiyun
388*4882a593Smuzhiyun&i2c4 {
389*4882a593Smuzhiyun	status = "okay";
390*4882a593Smuzhiyun};
391*4882a593Smuzhiyun
392*4882a593Smuzhiyun&pcie_phy {
393*4882a593Smuzhiyun	status = "okay";
394*4882a593Smuzhiyun};
395*4882a593Smuzhiyun
396*4882a593Smuzhiyun&pcie0 {
397*4882a593Smuzhiyun	status = "okay";
398*4882a593Smuzhiyun};
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun&vopb {
401*4882a593Smuzhiyun	status = "okay";
402*4882a593Smuzhiyun	assigned-clocks = <&cru DCLK_VOP0_DIV>;
403*4882a593Smuzhiyun	assigned-clock-parents = <&cru PLL_CPLL>;
404*4882a593Smuzhiyun};
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun&vopb_mmu {
407*4882a593Smuzhiyun	status = "okay";
408*4882a593Smuzhiyun};
409*4882a593Smuzhiyun
410*4882a593Smuzhiyun&vopl {
411*4882a593Smuzhiyun	status = "okay";
412*4882a593Smuzhiyun	assigned-clocks = <&cru DCLK_VOP1_DIV>;
413*4882a593Smuzhiyun	assigned-clock-parents = <&cru PLL_VPLL>;
414*4882a593Smuzhiyun};
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun&vopl_mmu {
417*4882a593Smuzhiyun	status = "okay";
418*4882a593Smuzhiyun};
419*4882a593Smuzhiyun
420*4882a593Smuzhiyun&pinctrl {
421*4882a593Smuzhiyun	buttons {
422*4882a593Smuzhiyun		pwrbtn: pwrbtn {
423*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>;
424*4882a593Smuzhiyun		};
425*4882a593Smuzhiyun	};
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun	lcd-panel {
428*4882a593Smuzhiyun		lcd_panel_reset: lcd-panel-reset {
429*4882a593Smuzhiyun			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
430*4882a593Smuzhiyun		};
431*4882a593Smuzhiyun	};
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun	hdmiin {
434*4882a593Smuzhiyun		hdmiin_gpios: hdmiin-gpios {
435*4882a593Smuzhiyun			rockchip,pins =
436*4882a593Smuzhiyun				<2 RK_PA5 RK_FUNC_GPIO &pcfg_output_high>,
437*4882a593Smuzhiyun				<2 RK_PA6 RK_FUNC_GPIO &pcfg_output_high>,
438*4882a593Smuzhiyun				<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>,
439*4882a593Smuzhiyun				<2 RK_PB0 RK_FUNC_GPIO &pcfg_output_high>,
440*4882a593Smuzhiyun				<2 RK_PB1 RK_FUNC_GPIO &pcfg_output_high>,
441*4882a593Smuzhiyun				<2 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>,
442*4882a593Smuzhiyun				<2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
443*4882a593Smuzhiyun		};
444*4882a593Smuzhiyun	};
445*4882a593Smuzhiyun};
446