1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun/dts-v1/; 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun#include "rk3399-excavator-sapphire.dtsi" 10*4882a593Smuzhiyun#include "rk3399-android.dtsi" 11*4882a593Smuzhiyun#include "rk3399-vop-clk-set.dtsi" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun/ { 14*4882a593Smuzhiyun backlight: backlight { 15*4882a593Smuzhiyun compatible = "pwm-backlight"; 16*4882a593Smuzhiyun brightness-levels = < 17*4882a593Smuzhiyun 0 1 2 3 4 5 6 7 18*4882a593Smuzhiyun 8 9 10 11 12 13 14 15 19*4882a593Smuzhiyun 16 17 18 19 20 21 22 23 20*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 21*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 22*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 23*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 24*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 25*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 26*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 27*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 28*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 29*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 30*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 31*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 32*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 33*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 34*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 35*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 36*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 37*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 38*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 39*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 40*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 41*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 42*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 43*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 44*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 45*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 46*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 47*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 48*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 49*4882a593Smuzhiyun default-brightness-level = <200>; 50*4882a593Smuzhiyun pwms = <&pwm0 0 25000 0>; 51*4882a593Smuzhiyun enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun vcc_lcd: vcc-lcd { 55*4882a593Smuzhiyun compatible = "regulator-fixed"; 56*4882a593Smuzhiyun regulator-name = "vcc_lcd"; 57*4882a593Smuzhiyun gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>; 58*4882a593Smuzhiyun startup-delay-us = <20000>; 59*4882a593Smuzhiyun enable-active-high; 60*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 61*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 62*4882a593Smuzhiyun regulator-boot-on; 63*4882a593Smuzhiyun vin-supply = <&vcc_sys>; 64*4882a593Smuzhiyun }; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun panel: panel { 67*4882a593Smuzhiyun compatible = "simple-panel"; 68*4882a593Smuzhiyun backlight = <&backlight>; 69*4882a593Smuzhiyun power-supply = <&vcc_lcd>; 70*4882a593Smuzhiyun enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; 71*4882a593Smuzhiyun prepare-delay-ms = <20>; 72*4882a593Smuzhiyun enable-delay-ms = <20>; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun display-timings { 75*4882a593Smuzhiyun native-mode = <&timing0>; 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun timing0: timing0 { 78*4882a593Smuzhiyun clock-frequency = <200000000>; 79*4882a593Smuzhiyun hactive = <1536>; 80*4882a593Smuzhiyun vactive = <2048>; 81*4882a593Smuzhiyun hfront-porch = <12>; 82*4882a593Smuzhiyun hsync-len = <16>; 83*4882a593Smuzhiyun hback-porch = <48>; 84*4882a593Smuzhiyun vfront-porch = <8>; 85*4882a593Smuzhiyun vsync-len = <4>; 86*4882a593Smuzhiyun vback-porch = <8>; 87*4882a593Smuzhiyun hsync-active = <0>; 88*4882a593Smuzhiyun vsync-active = <0>; 89*4882a593Smuzhiyun de-active = <0>; 90*4882a593Smuzhiyun pixelclk-active = <0>; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun ports { 95*4882a593Smuzhiyun panel_in: endpoint { 96*4882a593Smuzhiyun remote-endpoint = <&edp_out>; 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun }; 99*4882a593Smuzhiyun }; 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun test-power { 102*4882a593Smuzhiyun status = "okay"; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun hdmiin_sound: hdmiin-sound { 106*4882a593Smuzhiyun compatible = "rockchip,rockchip-rt5651-sound"; 107*4882a593Smuzhiyun rockchip,cpu = <&i2s0>; 108*4882a593Smuzhiyun rockchip,codec = <&rt5651 &rt5651>; 109*4882a593Smuzhiyun status = "okay"; 110*4882a593Smuzhiyun }; 111*4882a593Smuzhiyun}; 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun&edp { 115*4882a593Smuzhiyun status = "okay"; 116*4882a593Smuzhiyun force-hpd; 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun ports { 119*4882a593Smuzhiyun port@1 { 120*4882a593Smuzhiyun reg = <1>; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun edp_out: endpoint { 123*4882a593Smuzhiyun remote-endpoint = <&panel_in>; 124*4882a593Smuzhiyun }; 125*4882a593Smuzhiyun }; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun}; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun&edp_in_vopl { 130*4882a593Smuzhiyun status = "disabled"; 131*4882a593Smuzhiyun}; 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun&hdmi_in_vopb { 134*4882a593Smuzhiyun status = "disabled"; 135*4882a593Smuzhiyun}; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun&rt5651 { 138*4882a593Smuzhiyun status = "okay"; 139*4882a593Smuzhiyun}; 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun&hdmi_dp_sound { 143*4882a593Smuzhiyun status = "okay"; 144*4882a593Smuzhiyun}; 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun&hdmiin_sound { 147*4882a593Smuzhiyun status = "disabled"; 148*4882a593Smuzhiyun}; 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun&dp_in_vopb { 151*4882a593Smuzhiyun status = "disabled"; 152*4882a593Smuzhiyun}; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun&i2s2 { 155*4882a593Smuzhiyun status = "okay"; 156*4882a593Smuzhiyun}; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun&i2c1 { 159*4882a593Smuzhiyun status = "okay"; 160*4882a593Smuzhiyun 161*4882a593Smuzhiyun gsl3673: gsl3673@40 { 162*4882a593Smuzhiyun compatible = "GSL,GSL3673"; 163*4882a593Smuzhiyun reg = <0x40>; 164*4882a593Smuzhiyun screen_max_x = <1536>; 165*4882a593Smuzhiyun screen_max_y = <2048>; 166*4882a593Smuzhiyun irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; 167*4882a593Smuzhiyun rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>; 168*4882a593Smuzhiyun }; 169*4882a593Smuzhiyun 170*4882a593Smuzhiyun sgm3784: sgm3784@30 { 171*4882a593Smuzhiyun #address-cells = <1>; 172*4882a593Smuzhiyun #size-cells = <0>; 173*4882a593Smuzhiyun compatible = "sgmicro,gsm3784"; 174*4882a593Smuzhiyun reg = <0x30>; 175*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 176*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 177*4882a593Smuzhiyun enable-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>; 178*4882a593Smuzhiyun strobe-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; 179*4882a593Smuzhiyun status = "okay"; 180*4882a593Smuzhiyun sgm3784_led0: led@0 { 181*4882a593Smuzhiyun reg = <0x0>; 182*4882a593Smuzhiyun led-max-microamp = <299200>; 183*4882a593Smuzhiyun flash-max-microamp = <1122000>; 184*4882a593Smuzhiyun flash-max-timeout-us = <1600000>; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun sgm3784_led1: led@1 { 188*4882a593Smuzhiyun reg = <0x1>; 189*4882a593Smuzhiyun led-max-microamp = <299200>; 190*4882a593Smuzhiyun flash-max-microamp = <1122000>; 191*4882a593Smuzhiyun flash-max-timeout-us = <1600000>; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun }; 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun tc358749x: tc358749x@0f { 196*4882a593Smuzhiyun compatible = "toshiba,tc358749x"; 197*4882a593Smuzhiyun reg = <0x0f>; 198*4882a593Smuzhiyun power-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>; 199*4882a593Smuzhiyun power18-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>; 200*4882a593Smuzhiyun power33-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; 201*4882a593Smuzhiyun csi-ctl-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; 202*4882a593Smuzhiyun stanby-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>; 203*4882a593Smuzhiyun reset-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>; 204*4882a593Smuzhiyun int-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>; 205*4882a593Smuzhiyun pinctrl-names = "default"; 206*4882a593Smuzhiyun pinctrl-0 = <&hdmiin_gpios>; 207*4882a593Smuzhiyun status = "disabled"; 208*4882a593Smuzhiyun }; 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun vm149c: vm149c@0c { 211*4882a593Smuzhiyun compatible = "silicon touch,vm149c"; 212*4882a593Smuzhiyun status = "okay"; 213*4882a593Smuzhiyun reg = <0x0c>; 214*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 215*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 216*4882a593Smuzhiyun }; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun gc2145: gc2145@3c{ 219*4882a593Smuzhiyun status = "okay"; 220*4882a593Smuzhiyun compatible = "galaxycore,gc2145"; 221*4882a593Smuzhiyun reg = <0x3c>; 222*4882a593Smuzhiyun pinctrl-names = "default"; 223*4882a593Smuzhiyun pinctrl-0 = <&cif_clkout>; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 226*4882a593Smuzhiyun clock-names = "xvclk"; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* avdd-supply = <>; */ 229*4882a593Smuzhiyun /* dvdd-supply = <>; */ 230*4882a593Smuzhiyun /* dovdd-supply = <>; */ 231*4882a593Smuzhiyun pwdn-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; //ok 232*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 233*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 234*4882a593Smuzhiyun rockchip,camera-module-name = "CameraKing"; 235*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan"; 236*4882a593Smuzhiyun port { 237*4882a593Smuzhiyun gc2145_out: endpoint { 238*4882a593Smuzhiyun remote-endpoint = <&dvp_in_fcam>; 239*4882a593Smuzhiyun }; 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun vm149c: vm149c@0c { 244*4882a593Smuzhiyun compatible = "silicon touch,vm149c"; 245*4882a593Smuzhiyun status = "okay"; 246*4882a593Smuzhiyun reg = <0x0c>; 247*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 248*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 249*4882a593Smuzhiyun }; 250*4882a593Smuzhiyun 251*4882a593Smuzhiyun ov13850: ov13850@10 { 252*4882a593Smuzhiyun compatible = "ovti,ov13850"; 253*4882a593Smuzhiyun status = "okay"; 254*4882a593Smuzhiyun reg = <0x10>; 255*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 256*4882a593Smuzhiyun clock-names = "xvclk"; 257*4882a593Smuzhiyun /* avdd-supply = <>; */ 258*4882a593Smuzhiyun /* dvdd-supply = <>; */ 259*4882a593Smuzhiyun /* dovdd-supply = <>; */ 260*4882a593Smuzhiyun /* reset-gpios = <>; */ 261*4882a593Smuzhiyun reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; // conflict with csi-ctl-gpios 262*4882a593Smuzhiyun pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; 263*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 264*4882a593Smuzhiyun pinctrl-0 = <&cif_clkout>; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 267*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 268*4882a593Smuzhiyun rockchip,camera-module-name = "CMK-CT0116"; 269*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan-50013A1"; 270*4882a593Smuzhiyun lens-focus = <&vm149c>; 271*4882a593Smuzhiyun flash-leds = <&sgm3784_led0 &sgm3784_led1>; 272*4882a593Smuzhiyun 273*4882a593Smuzhiyun port { 274*4882a593Smuzhiyun ucam_out0: endpoint { 275*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam0>; 276*4882a593Smuzhiyun //remote-endpoint = <&mipi_in_ucam1>; 277*4882a593Smuzhiyun data-lanes = <1 2>; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun }; 280*4882a593Smuzhiyun }; 281*4882a593Smuzhiyun 282*4882a593Smuzhiyun ov4689: ov4689@36 { 283*4882a593Smuzhiyun compatible = "ovti,ov4689"; 284*4882a593Smuzhiyun status = "disabled"; 285*4882a593Smuzhiyun reg = <0x36>; 286*4882a593Smuzhiyun clocks = <&cru SCLK_CIF_OUT>; 287*4882a593Smuzhiyun clock-names = "xvclk"; 288*4882a593Smuzhiyun /* avdd-supply = <>; */ 289*4882a593Smuzhiyun /* dvdd-supply = <>; */ 290*4882a593Smuzhiyun /* dovdd-supply = <>; */ 291*4882a593Smuzhiyun /* reset-gpios = <>; */ 292*4882a593Smuzhiyun pwdn-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; // conflict with backlight 293*4882a593Smuzhiyun pinctrl-names = "rockchip,camera_default"; 294*4882a593Smuzhiyun pinctrl-0 = <&cif_clkout>; 295*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 296*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 297*4882a593Smuzhiyun rockchip,camera-module-name = "JSD3425-C1"; 298*4882a593Smuzhiyun rockchip,camera-module-lens-name = "JSD3425-C1"; 299*4882a593Smuzhiyun port { 300*4882a593Smuzhiyun ucam_out1: endpoint { 301*4882a593Smuzhiyun //remote-endpoint = <&mipi_in_ucam0>; 302*4882a593Smuzhiyun remote-endpoint = <&mipi_in_ucam1>; 303*4882a593Smuzhiyun data-lanes = <1 2>; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun }; 306*4882a593Smuzhiyun }; 307*4882a593Smuzhiyun}; 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun&i2c6 { 310*4882a593Smuzhiyun cw2015@62 { 311*4882a593Smuzhiyun status = "disabled"; 312*4882a593Smuzhiyun compatible = "cw201x"; 313*4882a593Smuzhiyun reg = <0x62>; 314*4882a593Smuzhiyun bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4D 0x48 315*4882a593Smuzhiyun 0x48 0x44 0x44 0x46 0x49 0x48 0x32 0x24 316*4882a593Smuzhiyun 0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45 317*4882a593Smuzhiyun 0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E 318*4882a593Smuzhiyun 0x4D 0x52 0x52 0x57 0x3D 0x1B 0x6A 0x2D 319*4882a593Smuzhiyun 0x25 0x43 0x52 0x87 0x8F 0x91 0x94 0x52 320*4882a593Smuzhiyun 0x82 0x8C 0x92 0x96 0xFF 0x7B 0xBB 0xCB 321*4882a593Smuzhiyun 0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x46 0xAE>; 322*4882a593Smuzhiyun monitor_sec = <5>; 323*4882a593Smuzhiyun virtual_power = <0>; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun}; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun&isp0_mmu { 328*4882a593Smuzhiyun status = "okay"; 329*4882a593Smuzhiyun}; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun&isp1_mmu { 332*4882a593Smuzhiyun status = "okay"; 333*4882a593Smuzhiyun}; 334*4882a593Smuzhiyun 335*4882a593Smuzhiyun&mipi_dphy_rx0 { 336*4882a593Smuzhiyun status = "disabled"; 337*4882a593Smuzhiyun 338*4882a593Smuzhiyun ports { 339*4882a593Smuzhiyun #address-cells = <1>; 340*4882a593Smuzhiyun #size-cells = <0>; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun port@0 { 343*4882a593Smuzhiyun reg = <0>; 344*4882a593Smuzhiyun #address-cells = <1>; 345*4882a593Smuzhiyun #size-cells = <0>; 346*4882a593Smuzhiyun 347*4882a593Smuzhiyun mipi_in_ucam0: endpoint@1 { 348*4882a593Smuzhiyun reg = <1>; 349*4882a593Smuzhiyun remote-endpoint = <&ucam_out0>; 350*4882a593Smuzhiyun data-lanes = <1 2>; 351*4882a593Smuzhiyun }; 352*4882a593Smuzhiyun }; 353*4882a593Smuzhiyun 354*4882a593Smuzhiyun port@1 { 355*4882a593Smuzhiyun reg = <1>; 356*4882a593Smuzhiyun #address-cells = <1>; 357*4882a593Smuzhiyun #size-cells = <0>; 358*4882a593Smuzhiyun 359*4882a593Smuzhiyun dphy_rx0_out: endpoint@0 { 360*4882a593Smuzhiyun reg = <0>; 361*4882a593Smuzhiyun remote-endpoint = <&isp0_mipi_in>; 362*4882a593Smuzhiyun }; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun}; 366*4882a593Smuzhiyun 367*4882a593Smuzhiyun&mipi_dphy_tx1rx1 { 368*4882a593Smuzhiyun status = "disabled"; 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun ports { 371*4882a593Smuzhiyun #address-cells = <1>; 372*4882a593Smuzhiyun #size-cells = <0>; 373*4882a593Smuzhiyun 374*4882a593Smuzhiyun port@0 { 375*4882a593Smuzhiyun reg = <0>; 376*4882a593Smuzhiyun #address-cells = <1>; 377*4882a593Smuzhiyun #size-cells = <0>; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun mipi_in_ucam1: endpoint@1 { 380*4882a593Smuzhiyun reg = <1>; 381*4882a593Smuzhiyun remote-endpoint = <&ucam_out1>; 382*4882a593Smuzhiyun data-lanes = <1 2>; 383*4882a593Smuzhiyun }; 384*4882a593Smuzhiyun }; 385*4882a593Smuzhiyun 386*4882a593Smuzhiyun port@1 { 387*4882a593Smuzhiyun reg = <1>; 388*4882a593Smuzhiyun #address-cells = <1>; 389*4882a593Smuzhiyun #size-cells = <0>; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun dphy_tx1rx1_out: endpoint@0 { 392*4882a593Smuzhiyun reg = <0>; 393*4882a593Smuzhiyun remote-endpoint = <&isp1_mipi_in>; 394*4882a593Smuzhiyun }; 395*4882a593Smuzhiyun }; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun}; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun&vopb { 400*4882a593Smuzhiyun status = "okay"; 401*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP0_DIV>; 402*4882a593Smuzhiyun assigned-clock-parents = <&cru PLL_CPLL>; 403*4882a593Smuzhiyun}; 404*4882a593Smuzhiyun 405*4882a593Smuzhiyun&vopl { 406*4882a593Smuzhiyun status = "okay"; 407*4882a593Smuzhiyun assigned-clocks = <&cru DCLK_VOP1_DIV>; 408*4882a593Smuzhiyun assigned-clock-parents = <&cru PLL_VPLL>; 409*4882a593Smuzhiyun}; 410*4882a593Smuzhiyun 411*4882a593Smuzhiyun&pcie_phy { 412*4882a593Smuzhiyun status = "okay"; 413*4882a593Smuzhiyun}; 414*4882a593Smuzhiyun 415*4882a593Smuzhiyun&pcie0 { 416*4882a593Smuzhiyun status = "okay"; 417*4882a593Smuzhiyun}; 418*4882a593Smuzhiyun 419*4882a593Smuzhiyun&rkisp1_0 { 420*4882a593Smuzhiyun status = "disabled"; 421*4882a593Smuzhiyun 422*4882a593Smuzhiyun port { 423*4882a593Smuzhiyun #address-cells = <1>; 424*4882a593Smuzhiyun #size-cells = <0>; 425*4882a593Smuzhiyun 426*4882a593Smuzhiyun isp0_mipi_in: endpoint@0 { 427*4882a593Smuzhiyun reg = <0>; 428*4882a593Smuzhiyun remote-endpoint = <&dphy_rx0_out>; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun }; 431*4882a593Smuzhiyun}; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun&rkisp1_1 { 434*4882a593Smuzhiyun status = "disabled"; 435*4882a593Smuzhiyun 436*4882a593Smuzhiyun port { 437*4882a593Smuzhiyun #address-cells = <1>; 438*4882a593Smuzhiyun #size-cells = <0>; 439*4882a593Smuzhiyun 440*4882a593Smuzhiyun isp1_mipi_in: endpoint@0 { 441*4882a593Smuzhiyun reg = <0>; 442*4882a593Smuzhiyun remote-endpoint = <&dphy_tx1rx1_out>; 443*4882a593Smuzhiyun }; 444*4882a593Smuzhiyun dvp_in_fcam: endpoint@1 { 445*4882a593Smuzhiyun reg = <1>; 446*4882a593Smuzhiyun remote-endpoint = <&gc2145_out>; 447*4882a593Smuzhiyun }; 448*4882a593Smuzhiyun }; 449*4882a593Smuzhiyun}; 450*4882a593Smuzhiyun 451*4882a593Smuzhiyun&route_edp { 452*4882a593Smuzhiyun status = "okay"; 453*4882a593Smuzhiyun}; 454*4882a593Smuzhiyun 455*4882a593Smuzhiyun&route_hdmi { 456*4882a593Smuzhiyun status = "okay"; 457*4882a593Smuzhiyun connect = <&vopl_out_hdmi>; 458*4882a593Smuzhiyun}; 459*4882a593Smuzhiyun 460*4882a593Smuzhiyun&rt5651_sound { 461*4882a593Smuzhiyun status = "okay"; 462*4882a593Smuzhiyun}; 463*4882a593Smuzhiyun 464*4882a593Smuzhiyun&pinctrl { 465*4882a593Smuzhiyun lcd-panel { 466*4882a593Smuzhiyun lcd_panel_reset: lcd-panel-reset { 467*4882a593Smuzhiyun rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>; 468*4882a593Smuzhiyun }; 469*4882a593Smuzhiyun }; 470*4882a593Smuzhiyun 471*4882a593Smuzhiyun hdmiin { 472*4882a593Smuzhiyun hdmiin_gpios: hdmiin_gpios { 473*4882a593Smuzhiyun rockchip,pins = 474*4882a593Smuzhiyun <2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>, 475*4882a593Smuzhiyun <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, 476*4882a593Smuzhiyun <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>, 477*4882a593Smuzhiyun <2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>, 478*4882a593Smuzhiyun <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>, 479*4882a593Smuzhiyun <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>; 480*4882a593Smuzhiyun }; 481*4882a593Smuzhiyun }; 482*4882a593Smuzhiyun}; 483*4882a593Smuzhiyun 484