1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
4 *
5 */
6
7/dts-v1/;
8
9#include "rk3399-excavator-sapphire.dtsi"
10#include "rk3399-android.dtsi"
11#include "rk3399-vop-clk-set.dtsi"
12
13/ {
14	backlight: backlight {
15		compatible = "pwm-backlight";
16		brightness-levels = <
17			  0   1   2   3   4   5   6   7
18			  8   9  10  11  12  13  14  15
19			 16  17  18  19  20  21  22  23
20			 24  25  26  27  28  29  30  31
21			 32  33  34  35  36  37  38  39
22			 40  41  42  43  44  45  46  47
23			 48  49  50  51  52  53  54  55
24			 56  57  58  59  60  61  62  63
25			 64  65  66  67  68  69  70  71
26			 72  73  74  75  76  77  78  79
27			 80  81  82  83  84  85  86  87
28			 88  89  90  91  92  93  94  95
29			 96  97  98  99 100 101 102 103
30			104 105 106 107 108 109 110 111
31			112 113 114 115 116 117 118 119
32			120 121 122 123 124 125 126 127
33			128 129 130 131 132 133 134 135
34			136 137 138 139 140 141 142 143
35			144 145 146 147 148 149 150 151
36			152 153 154 155 156 157 158 159
37			160 161 162 163 164 165 166 167
38			168 169 170 171 172 173 174 175
39			176 177 178 179 180 181 182 183
40			184 185 186 187 188 189 190 191
41			192 193 194 195 196 197 198 199
42			200 201 202 203 204 205 206 207
43			208 209 210 211 212 213 214 215
44			216 217 218 219 220 221 222 223
45			224 225 226 227 228 229 230 231
46			232 233 234 235 236 237 238 239
47			240 241 242 243 244 245 246 247
48			248 249 250 251 252 253 254 255>;
49		default-brightness-level = <200>;
50		pwms = <&pwm0 0 25000 0>;
51		enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
52	};
53
54	vcc_lcd: vcc-lcd {
55		compatible = "regulator-fixed";
56		regulator-name = "vcc_lcd";
57		gpio = <&gpio4 30 GPIO_ACTIVE_HIGH>;
58		startup-delay-us = <20000>;
59		enable-active-high;
60		regulator-min-microvolt = <3300000>;
61		regulator-max-microvolt = <3300000>;
62		regulator-boot-on;
63		vin-supply = <&vcc_sys>;
64	};
65
66	panel: panel {
67		compatible = "simple-panel";
68		backlight = <&backlight>;
69		power-supply = <&vcc_lcd>;
70		enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
71		prepare-delay-ms = <20>;
72		enable-delay-ms = <20>;
73
74		display-timings {
75			native-mode = <&timing0>;
76
77			timing0: timing0 {
78				clock-frequency = <200000000>;
79				hactive = <1536>;
80				vactive = <2048>;
81				hfront-porch = <12>;
82				hsync-len = <16>;
83				hback-porch = <48>;
84				vfront-porch = <8>;
85				vsync-len = <4>;
86				vback-porch = <8>;
87				hsync-active = <0>;
88				vsync-active = <0>;
89				de-active = <0>;
90				pixelclk-active = <0>;
91			};
92		};
93
94		ports {
95			panel_in: endpoint {
96				remote-endpoint = <&edp_out>;
97			};
98		};
99	};
100
101	test-power {
102		status = "okay";
103	};
104
105	hdmiin_sound: hdmiin-sound {
106		compatible = "rockchip,rockchip-rt5651-sound";
107		rockchip,cpu = <&i2s0>;
108		rockchip,codec = <&rt5651 &rt5651>;
109		status = "okay";
110	};
111};
112
113
114&edp {
115	status = "okay";
116	force-hpd;
117
118	ports {
119		port@1 {
120			reg = <1>;
121
122			edp_out: endpoint {
123				remote-endpoint = <&panel_in>;
124			};
125		};
126	};
127};
128
129&edp_in_vopl {
130	status = "disabled";
131};
132
133&hdmi_in_vopb {
134	status = "disabled";
135};
136
137&rt5651 {
138	status = "okay";
139};
140
141
142&hdmi_dp_sound {
143	status = "okay";
144};
145
146&hdmiin_sound {
147	status = "disabled";
148};
149
150&dp_in_vopb {
151	status = "disabled";
152};
153
154&i2s2 {
155	status = "okay";
156};
157
158&i2c1 {
159	status = "okay";
160
161	gsl3673: gsl3673@40 {
162		compatible = "GSL,GSL3673";
163		reg = <0x40>;
164		screen_max_x = <1536>;
165		screen_max_y = <2048>;
166		irq_gpio_number = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>;
167		rst_gpio_number = <&gpio4 22 GPIO_ACTIVE_HIGH>;
168	};
169
170	sgm3784: sgm3784@30 {
171		#address-cells = <1>;
172		#size-cells = <0>;
173		compatible = "sgmicro,gsm3784";
174		reg = <0x30>;
175		rockchip,camera-module-index = <0>;
176		rockchip,camera-module-facing = "back";
177		enable-gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
178		strobe-gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>;
179		status = "okay";
180		sgm3784_led0: led@0 {
181			reg = <0x0>;
182			led-max-microamp = <299200>;
183			flash-max-microamp = <1122000>;
184			flash-max-timeout-us = <1600000>;
185		};
186
187		sgm3784_led1: led@1 {
188			reg = <0x1>;
189			led-max-microamp = <299200>;
190			flash-max-microamp = <1122000>;
191			flash-max-timeout-us = <1600000>;
192		};
193	};
194
195	tc358749x: tc358749x@0f {
196		compatible = "toshiba,tc358749x";
197		reg = <0x0f>;
198		power-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
199		power18-gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
200		power33-gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
201		csi-ctl-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
202		stanby-gpios = <&gpio2 8 GPIO_ACTIVE_HIGH>;
203		reset-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
204		int-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
205		pinctrl-names = "default";
206		pinctrl-0 = <&hdmiin_gpios>;
207		status = "disabled";
208	};
209
210	vm149c: vm149c@0c {
211		compatible = "silicon touch,vm149c";
212		status = "okay";
213		reg = <0x0c>;
214		rockchip,camera-module-index = <0>;
215		rockchip,camera-module-facing = "back";
216	};
217
218	gc2145: gc2145@3c{
219		status = "okay";
220		compatible = "galaxycore,gc2145";
221		reg = <0x3c>;
222		pinctrl-names = "default";
223		pinctrl-0 = <&cif_clkout>;
224
225		clocks = <&cru SCLK_CIF_OUT>;
226		clock-names = "xvclk";
227
228		/* avdd-supply = <>; */
229		/* dvdd-supply = <>; */
230		/* dovdd-supply = <>; */
231		pwdn-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;	//ok
232		rockchip,camera-module-index = <1>;
233		rockchip,camera-module-facing = "front";
234		rockchip,camera-module-name = "CameraKing";
235		rockchip,camera-module-lens-name = "Largan";
236		port {
237			gc2145_out: endpoint {
238				remote-endpoint = <&dvp_in_fcam>;
239			};
240		};
241	};
242
243	vm149c: vm149c@0c {
244		compatible = "silicon touch,vm149c";
245		status = "okay";
246		reg = <0x0c>;
247		rockchip,camera-module-index = <0>;
248		rockchip,camera-module-facing = "back";
249	};
250
251	ov13850: ov13850@10 {
252		compatible = "ovti,ov13850";
253		status = "okay";
254		reg = <0x10>;
255		clocks = <&cru SCLK_CIF_OUT>;
256		clock-names = "xvclk";
257		/* avdd-supply = <>; */
258		/* dvdd-supply = <>; */
259		/* dovdd-supply = <>; */
260		/* reset-gpios = <>; */
261		reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; // conflict with csi-ctl-gpios
262		pwdn-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
263		pinctrl-names = "rockchip,camera_default";
264		pinctrl-0 = <&cif_clkout>;
265
266		rockchip,camera-module-index = <0>;
267		rockchip,camera-module-facing = "back";
268		rockchip,camera-module-name = "CMK-CT0116";
269		rockchip,camera-module-lens-name = "Largan-50013A1";
270		lens-focus = <&vm149c>;
271		flash-leds = <&sgm3784_led0 &sgm3784_led1>;
272
273		port {
274			ucam_out0: endpoint {
275				remote-endpoint = <&mipi_in_ucam0>;
276				//remote-endpoint = <&mipi_in_ucam1>;
277				data-lanes = <1 2>;
278			};
279		};
280	};
281
282	ov4689: ov4689@36 {
283		compatible = "ovti,ov4689";
284		status = "disabled";
285		reg = <0x36>;
286		clocks = <&cru SCLK_CIF_OUT>;
287		clock-names = "xvclk";
288		/* avdd-supply = <>; */
289		/* dvdd-supply = <>; */
290		/* dovdd-supply = <>; */
291		/* reset-gpios = <>; */
292		pwdn-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; // conflict with backlight
293		pinctrl-names = "rockchip,camera_default";
294		pinctrl-0 = <&cif_clkout>;
295		rockchip,camera-module-index = <1>;
296		rockchip,camera-module-facing = "front";
297		rockchip,camera-module-name = "JSD3425-C1";
298		rockchip,camera-module-lens-name = "JSD3425-C1";
299		port {
300			ucam_out1: endpoint {
301				//remote-endpoint = <&mipi_in_ucam0>;
302				remote-endpoint = <&mipi_in_ucam1>;
303				data-lanes = <1 2>;
304			};
305		};
306	};
307};
308
309&i2c6 {
310	cw2015@62 {
311		status = "disabled";
312		compatible = "cw201x";
313		reg = <0x62>;
314		bat_config_info = <0x15 0x42 0x60 0x59 0x52 0x58 0x4D 0x48
315				   0x48 0x44 0x44 0x46 0x49 0x48 0x32 0x24
316				   0x20 0x17 0x13 0x0F 0x19 0x3E 0x51 0x45
317				   0x08 0x76 0x0B 0x85 0x0E 0x1C 0x2E 0x3E
318				   0x4D 0x52 0x52 0x57 0x3D 0x1B 0x6A 0x2D
319				   0x25 0x43 0x52 0x87 0x8F 0x91 0x94 0x52
320				   0x82 0x8C 0x92 0x96 0xFF 0x7B 0xBB 0xCB
321				   0x2F 0x7D 0x72 0xA5 0xB5 0xC1 0x46 0xAE>;
322		monitor_sec = <5>;
323		virtual_power = <0>;
324	};
325};
326
327&isp0_mmu {
328	status = "okay";
329};
330
331&isp1_mmu {
332	status = "okay";
333};
334
335&mipi_dphy_rx0 {
336	status = "disabled";
337
338	ports {
339		#address-cells = <1>;
340		#size-cells = <0>;
341
342		port@0 {
343			reg = <0>;
344			#address-cells = <1>;
345			#size-cells = <0>;
346
347			mipi_in_ucam0: endpoint@1 {
348				reg = <1>;
349				remote-endpoint = <&ucam_out0>;
350				data-lanes = <1 2>;
351			};
352		};
353
354		port@1 {
355			reg = <1>;
356			#address-cells = <1>;
357			#size-cells = <0>;
358
359			dphy_rx0_out: endpoint@0 {
360				reg = <0>;
361				remote-endpoint = <&isp0_mipi_in>;
362			};
363		};
364	};
365};
366
367&mipi_dphy_tx1rx1 {
368	status = "disabled";
369
370	ports {
371		#address-cells = <1>;
372		#size-cells = <0>;
373
374		port@0 {
375			reg = <0>;
376			#address-cells = <1>;
377			#size-cells = <0>;
378
379			mipi_in_ucam1: endpoint@1 {
380				reg = <1>;
381				remote-endpoint = <&ucam_out1>;
382				data-lanes = <1 2>;
383			};
384		};
385
386		port@1 {
387			reg = <1>;
388			#address-cells = <1>;
389			#size-cells = <0>;
390
391			dphy_tx1rx1_out: endpoint@0 {
392				reg = <0>;
393				remote-endpoint = <&isp1_mipi_in>;
394			};
395		};
396	};
397};
398
399&vopb {
400	status = "okay";
401	assigned-clocks = <&cru DCLK_VOP0_DIV>;
402	assigned-clock-parents = <&cru PLL_CPLL>;
403};
404
405&vopl {
406	status = "okay";
407	assigned-clocks = <&cru DCLK_VOP1_DIV>;
408	assigned-clock-parents = <&cru PLL_VPLL>;
409};
410
411&pcie_phy {
412	status = "okay";
413};
414
415&pcie0 {
416	status = "okay";
417};
418
419&rkisp1_0 {
420	status = "disabled";
421
422	port {
423		#address-cells = <1>;
424		#size-cells = <0>;
425
426		isp0_mipi_in: endpoint@0 {
427			reg = <0>;
428			remote-endpoint = <&dphy_rx0_out>;
429		};
430	};
431};
432
433&rkisp1_1 {
434	status = "disabled";
435
436	port {
437		#address-cells = <1>;
438		#size-cells = <0>;
439
440		isp1_mipi_in: endpoint@0 {
441			reg = <0>;
442			remote-endpoint = <&dphy_tx1rx1_out>;
443		};
444		dvp_in_fcam: endpoint@1 {
445			reg = <1>;
446			remote-endpoint = <&gc2145_out>;
447		};
448	};
449};
450
451&route_edp {
452	status = "okay";
453};
454
455&route_hdmi {
456	status = "okay";
457	connect = <&vopl_out_hdmi>;
458};
459
460&rt5651_sound {
461	status = "okay";
462};
463
464&pinctrl {
465	lcd-panel {
466		lcd_panel_reset: lcd-panel-reset {
467			rockchip,pins = <4 RK_PD6 RK_FUNC_GPIO &pcfg_pull_up>;
468		};
469	};
470
471	hdmiin {
472		hdmiin_gpios: hdmiin_gpios {
473		rockchip,pins =
474				<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
475				<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>,
476				<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>,
477				<2 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>,
478				<2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>,
479				<2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
480		};
481	};
482};
483
484