1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 * 5 */ 6 7/dts-v1/; 8 9#include "dt-bindings/pwm/pwm.h" 10#include "rk3399.dtsi" 11#include "rk3399-opp.dtsi" 12#include "rk3399-linux.dtsi" 13#include <dt-bindings/input/input.h> 14 15/ { 16 model = "Rockchip RK3399 Firefly Board (Linux Opensource)"; 17 compatible = "rockchip,rk3399-firefly-linux", "rockchip,rk3399"; 18 19 backlight: backlight { 20 status = "disabled"; 21 compatible = "pwm-backlight"; 22 pwms = <&pwm0 0 25000 0>; 23 brightness-levels = < 24 0 1 2 3 4 5 6 7 25 8 9 10 11 12 13 14 15 26 16 17 18 19 20 21 22 23 27 24 25 26 27 28 29 30 31 28 32 33 34 35 36 37 38 39 29 40 41 42 43 44 45 46 47 30 48 49 50 51 52 53 54 55 31 56 57 58 59 60 61 62 63 32 64 65 66 67 68 69 70 71 33 72 73 74 75 76 77 78 79 34 80 81 82 83 84 85 86 87 35 88 89 90 91 92 93 94 95 36 96 97 98 99 100 101 102 103 37 104 105 106 107 108 109 110 111 38 112 113 114 115 116 117 118 119 39 120 121 122 123 124 125 126 127 40 128 129 130 131 132 133 134 135 41 136 137 138 139 140 141 142 143 42 144 145 146 147 148 149 150 151 43 152 153 154 155 156 157 158 159 44 160 161 162 163 164 165 166 167 45 168 169 170 171 172 173 174 175 46 176 177 178 179 180 181 182 183 47 184 185 186 187 188 189 190 191 48 192 193 194 195 196 197 198 199 49 200 201 202 203 204 205 206 207 50 208 209 210 211 212 213 214 215 51 216 217 218 219 220 221 222 223 52 224 225 226 227 228 229 230 231 53 232 233 234 235 236 237 238 239 54 240 241 242 243 244 245 246 247 55 248 249 250 251 252 253 254 255>; 56 default-brightness-level = <200>; 57 }; 58 59 clkin_gmac: external-gmac-clock { 60 compatible = "fixed-clock"; 61 clock-frequency = <125000000>; 62 clock-output-names = "clkin_gmac"; 63 #clock-cells = <0>; 64 }; 65 66 dw_hdmi_audio: dw-hdmi-audio { 67 status = "disabled"; 68 compatible = "rockchip,dw-hdmi-audio"; 69 #sound-dai-cells = <0>; 70 }; 71 72 edp_panel: edp-panel { 73 status = "disabled"; 74 compatible = "sharp,lcd-f402", "panel-simple"; 75 backlight = <&backlight>; 76 power-supply = <&vcc_lcd>; 77 enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 78 pinctrl-names = "default"; 79 pinctrl-0 = <&lcd_panel_reset>; 80 81 ports { 82 panel_in_edp: endpoint { 83 remote-endpoint = <&edp_out_panel>; 84 }; 85 }; 86 }; 87 88 gpio-keys { 89 compatible = "gpio-keys"; 90 #address-cells = <1>; 91 #size-cells = <0>; 92 autorepeat; 93 94 pinctrl-names = "default"; 95 pinctrl-0 = <&pwrbtn>; 96 97 button@0 { 98 gpios = <&gpio0 5 GPIO_ACTIVE_LOW>; 99 linux,code = <KEY_POWER>; 100 label = "GPIO Key Power"; 101 linux,input-type = <1>; 102 gpio-key,wakeup = <1>; 103 debounce-interval = <100>; 104 }; 105 }; 106 107 rt5640-sound { 108 compatible = "simple-audio-card"; 109 simple-audio-card,format = "i2s"; 110 simple-audio-card,name = "rockchip,rt5640-codec"; 111 simple-audio-card,mclk-fs = <256>; 112 simple-audio-card,widgets = 113 "Microphone", "Mic Jack", 114 "Headphone", "Headphone Jack"; 115 simple-audio-card,routing = 116 "Mic Jack", "MICBIAS1", 117 "IN1P", "Mic Jack", 118 "Headphone Jack", "HPOL", 119 "Headphone Jack", "HPOR"; 120 simple-audio-card,cpu { 121 sound-dai = <&i2s1>; 122 }; 123 simple-audio-card,codec { 124 sound-dai = <&rt5640>; 125 }; 126 }; 127 128 hdmi_sound: hdmi-sound { 129 status = "disabled"; 130 compatible = "simple-audio-card"; 131 simple-audio-card,format = "i2s"; 132 simple-audio-card,mclk-fs = <256>; 133 simple-audio-card,name = "rockchip,hdmi"; 134 135 simple-audio-card,cpu { 136 sound-dai = <&i2s2>; 137 }; 138 simple-audio-card,codec { 139 sound-dai = <&dw_hdmi_audio>; 140 }; 141 }; 142 143 hdmi_codec: hdmi-codec { 144 compatible = "simple-audio-card"; 145 simple-audio-card,format = "i2s"; 146 simple-audio-card,mclk-fs = <256>; 147 simple-audio-card,name = "HDMI-CODEC"; 148 149 simple-audio-card,cpu { 150 sound-dai = <&i2s2>; 151 }; 152 153 simple-audio-card,codec { 154 sound-dai = <&hdmi>; 155 }; 156 }; 157 158 spdif-sound { 159 status = "okay"; 160 compatible = "simple-audio-card"; 161 simple-audio-card,name = "ROCKCHIP,SPDIF"; 162 simple-audio-card,mclk-fs = <128>; 163 simple-audio-card,cpu { 164 sound-dai = <&spdif>; 165 }; 166 simple-audio-card,codec { 167 sound-dai = <&spdif_out>; 168 }; 169 }; 170 171 spdif_out: spdif-out { 172 status = "okay"; 173 compatible = "linux,spdif-dit"; 174 #sound-dai-cells = <0>; 175 }; 176 177 sdio_pwrseq: sdio-pwrseq { 178 compatible = "mmc-pwrseq-simple"; 179 clocks = <&rk808 1>; 180 clock-names = "ext_clock"; 181 pinctrl-names = "default"; 182 pinctrl-0 = <&wifi_enable_h>; 183 184 /* 185 * On the module itself this is one of these (depending 186 * on the actual card populated): 187 * - SDIO_RESET_L_WL_REG_ON 188 * - PDN (power down when low) 189 */ 190 reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; /* GPIO0_B2 */ 191 }; 192 193 vcc3v3_pcie: vcc3v3-pcie-regulator { 194 compatible = "regulator-fixed"; 195 enable-active-high; 196 regulator-always-on; 197 regulator-boot-on; 198 gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 199 pinctrl-names = "default"; 200 pinctrl-0 = <&pcie_drv>; 201 regulator-name = "vcc3v3_pcie"; 202 }; 203 204 vcc3v3_sys: vcc3v3-sys { 205 compatible = "regulator-fixed"; 206 regulator-name = "vcc3v3_sys"; 207 regulator-always-on; 208 regulator-boot-on; 209 regulator-min-microvolt = <3300000>; 210 regulator-max-microvolt = <3300000>; 211 }; 212 213 vcc5v0_host: vcc5v0-host-regulator { 214 compatible = "regulator-fixed"; 215 enable-active-high; 216 gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; 217 pinctrl-names = "default"; 218 pinctrl-0 = <&host_vbus_drv>; 219 regulator-name = "vcc5v0_host"; 220 regulator-always-on; 221 }; 222 223 vcc5v0_sys: vcc5v0-sys { 224 compatible = "regulator-fixed"; 225 regulator-name = "vcc5v0_sys"; 226 regulator-always-on; 227 regulator-boot-on; 228 regulator-min-microvolt = <5000000>; 229 regulator-max-microvolt = <5000000>; 230 }; 231 232 vcc_phy: vcc-phy-regulator { 233 compatible = "regulator-fixed"; 234 regulator-name = "vcc_phy"; 235 regulator-always-on; 236 regulator-boot-on; 237 }; 238 239 vdd_log: vdd-log { 240 compatible = "pwm-regulator"; 241 pwms = <&pwm2 0 25000 1>; 242 regulator-name = "vdd_log"; 243 regulator-min-microvolt = <800000>; 244 /* 245 * the firefly hardware using 3.0 v as APIO2_VDD 246 * voltage, but the pwm divider resistance is designed 247 * based on hardware which the APIO2_VDD is 1.8v, so we 248 * need to change the regulator-max-microvolt from 1.4v 249 * to 1.0v, so the pwm can output 0.9v voltage. 250 */ 251 regulator-max-microvolt = <1000000>; 252 regulator-always-on; 253 regulator-boot-on; 254 255 /* for rockchip boot on */ 256 rockchip,pwm_id= <2>; 257 rockchip,pwm_voltage = <900000>; 258 }; 259 260 vccadc_ref: vccadc-ref { 261 compatible = "regulator-fixed"; 262 regulator-name = "vcc1v8_sys"; 263 regulator-always-on; 264 regulator-boot-on; 265 regulator-min-microvolt = <1800000>; 266 regulator-max-microvolt = <1800000>; 267 }; 268 269 vcc_lcd: vcc-lcd-regulator { 270 compatible = "regulator-fixed"; 271 regulator-always-on; 272 regulator-boot-on; 273 enable-active-high; 274 gpio = <&gpio1 1 GPIO_ACTIVE_HIGH>; 275 pinctrl-names = "default"; 276 pinctrl-0 = <&lcd_en>; 277 regulator-name = "vcc_lcd"; 278 }; 279 280 xin32k: xin32k { 281 compatible = "fixed-clock"; 282 clock-frequency = <32768>; 283 clock-output-names = "xin32k"; 284 #clock-cells = <0>; 285 }; 286 287 wireless-wlan { 288 compatible = "wlan-platdata"; 289 rockchip,grf = <&grf>; 290 wifi_chip_type = "ap6354"; 291 sdio_vref = <1800>; 292 WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */ 293 status = "okay"; 294 }; 295 296 wireless-bluetooth { 297 compatible = "bluetooth-platdata"; 298 //wifi-bt-power-toggle; 299 uart_rts_gpios = <&gpio2 19 GPIO_ACTIVE_LOW>; /* GPIO2_C3 */ 300 pinctrl-names = "default", "rts_gpio"; 301 pinctrl-0 = <&uart0_rts>; 302 pinctrl-1 = <&uart0_gpios>; 303 //BT,power_gpio = <&gpio3 19 GPIO_ACTIVE_HIGH>; /* GPIOx_xx */ 304 BT,reset_gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; /* GPIO0_B1 */ 305 BT,wake_gpio = <&gpio2 26 GPIO_ACTIVE_HIGH>; /* GPIO2_D2 */ 306 BT,wake_host_irq = <&gpio0 4 GPIO_ACTIVE_HIGH>; /* GPIO0_A4 */ 307 status = "okay"; 308 }; 309}; 310 311&cpu_l0 { 312 cpu-supply = <&vdd_cpu_l>; 313}; 314 315&cpu_l1 { 316 cpu-supply = <&vdd_cpu_l>; 317}; 318 319&cpu_l2 { 320 cpu-supply = <&vdd_cpu_l>; 321}; 322 323&cpu_l3 { 324 cpu-supply = <&vdd_cpu_l>; 325}; 326 327&cpu_b0 { 328 cpu-supply = <&vdd_cpu_b>; 329}; 330 331&cpu_b1 { 332 cpu-supply = <&vdd_cpu_b>; 333}; 334 335&display_subsystem { 336 status = "okay"; 337}; 338 339&edp { 340 status = "disabled"; 341 342 ports { 343 edp_out: port@1 { 344 reg = <1>; 345 #address-cells = <1>; 346 #size-cells = <0>; 347 348 edp_out_panel: endpoint@0 { 349 reg = <0>; 350 remote-endpoint = <&panel_in_edp>; 351 }; 352 }; 353 }; 354}; 355 356&emmc_phy { 357 status = "okay"; 358}; 359 360&gmac { 361 phy-supply = <&vcc_phy>; 362 phy-mode = "rgmii"; 363 clock_in_out = "input"; 364 snps,reset-gpio = <&gpio3 15 GPIO_ACTIVE_LOW>; 365 snps,reset-active-low; 366 snps,reset-delays-us = <0 10000 50000>; 367 assigned-clocks = <&cru SCLK_RMII_SRC>; 368 assigned-clock-parents = <&clkin_gmac>; 369 pinctrl-names = "default"; 370 pinctrl-0 = <&rgmii_pins>; 371 tx_delay = <0x28>; 372 rx_delay = <0x11>; 373 status = "okay"; 374}; 375 376&gpu { 377 status = "okay"; 378 mali-supply = <&vdd_gpu>; 379}; 380 381&hdmi { 382 #address-cells = <1>; 383 #size-cells = <0>; 384 #sound-dai-cells = <0>; 385 status = "okay"; 386}; 387 388&i2c0 { 389 status = "okay"; 390 i2c-scl-rising-time-ns = <168>; 391 i2c-scl-falling-time-ns = <4>; 392 clock-frequency = <400000>; 393 394 vdd_cpu_b: syr827@40 { 395 compatible = "silergy,syr827"; 396 reg = <0x40>; 397 vin-supply = <&vcc5v0_sys>; 398 regulator-compatible = "fan53555-reg"; 399 regulator-name = "vdd_cpu_b"; 400 regulator-min-microvolt = <712500>; 401 regulator-max-microvolt = <1500000>; 402 regulator-ramp-delay = <1000>; 403 vsel-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; 404 fcs,suspend-voltage-selector = <1>; 405 regulator-always-on; 406 regulator-boot-on; 407 regulator-initial-state = <3>; 408 regulator-state-mem { 409 regulator-off-in-suspend; 410 }; 411 }; 412 413 vdd_gpu: syr828@41 { 414 compatible = "silergy,syr828"; 415 reg = <0x41>; 416 vin-supply = <&vcc5v0_sys>; 417 regulator-compatible = "fan53555-reg"; 418 regulator-name = "vdd_gpu"; 419 regulator-min-microvolt = <712500>; 420 regulator-max-microvolt = <1500000>; 421 regulator-ramp-delay = <1000>; 422 fcs,suspend-voltage-selector = <1>; 423 regulator-always-on; 424 regulator-boot-on; 425 regulator-initial-state = <3>; 426 regulator-state-mem { 427 regulator-off-in-suspend; 428 }; 429 }; 430 431 rk808: pmic@1b { 432 compatible = "rockchip,rk808"; 433 reg = <0x1b>; 434 interrupt-parent = <&gpio1>; 435 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 436 pinctrl-names = "default"; 437 pinctrl-0 = <&pmic_int_l &pmic_dvs2>; 438 rockchip,system-power-controller; 439 wakeup-source; 440 #clock-cells = <1>; 441 clock-output-names = "rk808-clkout1", "rk808-clkout2"; 442 443 vcc1-supply = <&vcc3v3_sys>; 444 vcc2-supply = <&vcc3v3_sys>; 445 vcc3-supply = <&vcc3v3_sys>; 446 vcc4-supply = <&vcc3v3_sys>; 447 vcc6-supply = <&vcc3v3_sys>; 448 vcc7-supply = <&vcc3v3_sys>; 449 vcc8-supply = <&vcc3v3_sys>; 450 vcc9-supply = <&vcc3v3_sys>; 451 vcc10-supply = <&vcc3v3_sys>; 452 vcc11-supply = <&vcc3v3_sys>; 453 vcc12-supply = <&vcc3v3_sys>; 454 vddio-supply = <&vcc1v8_pmu>; 455 456 regulators { 457 vdd_center: DCDC_REG1 { 458 regulator-always-on; 459 regulator-boot-on; 460 regulator-min-microvolt = <750000>; 461 regulator-max-microvolt = <1350000>; 462 regulator-ramp-delay = <6001>; 463 regulator-name = "vdd_center"; 464 regulator-state-mem { 465 regulator-off-in-suspend; 466 }; 467 }; 468 469 vdd_cpu_l: DCDC_REG2 { 470 regulator-always-on; 471 regulator-boot-on; 472 regulator-min-microvolt = <750000>; 473 regulator-max-microvolt = <1350000>; 474 regulator-ramp-delay = <6001>; 475 regulator-name = "vdd_cpu_l"; 476 regulator-state-mem { 477 regulator-off-in-suspend; 478 }; 479 }; 480 481 vcc_ddr: DCDC_REG3 { 482 regulator-always-on; 483 regulator-boot-on; 484 regulator-name = "vcc_ddr"; 485 regulator-state-mem { 486 regulator-on-in-suspend; 487 }; 488 }; 489 490 vcc_1v8: DCDC_REG4 { 491 regulator-always-on; 492 regulator-boot-on; 493 regulator-min-microvolt = <1800000>; 494 regulator-max-microvolt = <1800000>; 495 regulator-name = "vcc_1v8"; 496 regulator-state-mem { 497 regulator-on-in-suspend; 498 regulator-suspend-microvolt = <1800000>; 499 }; 500 }; 501 502 vcc1v8_dvp: LDO_REG1 { 503 regulator-always-on; 504 regulator-boot-on; 505 regulator-min-microvolt = <1800000>; 506 regulator-max-microvolt = <1800000>; 507 regulator-name = "vcc1v8_dvp"; 508 regulator-state-mem { 509 regulator-off-in-suspend; 510 }; 511 }; 512 513 vcc3v0_tp: LDO_REG2 { 514 regulator-always-on; 515 regulator-boot-on; 516 regulator-min-microvolt = <3000000>; 517 regulator-max-microvolt = <3000000>; 518 regulator-name = "vcc3v0_tp"; 519 regulator-state-mem { 520 regulator-off-in-suspend; 521 }; 522 }; 523 524 vcc1v8_pmu: LDO_REG3 { 525 regulator-always-on; 526 regulator-boot-on; 527 regulator-min-microvolt = <1800000>; 528 regulator-max-microvolt = <1800000>; 529 regulator-name = "vcc1v8_pmu"; 530 regulator-state-mem { 531 regulator-on-in-suspend; 532 regulator-suspend-microvolt = <1800000>; 533 }; 534 }; 535 536 vcc_sd: LDO_REG4 { 537 regulator-always-on; 538 regulator-boot-on; 539 regulator-min-microvolt = <1800000>; 540 regulator-max-microvolt = <3000000>; 541 regulator-name = "vcc_sd"; 542 regulator-state-mem { 543 regulator-on-in-suspend; 544 regulator-suspend-microvolt = <3000000>; 545 }; 546 }; 547 548 vcca3v0_codec: LDO_REG5 { 549 regulator-always-on; 550 regulator-boot-on; 551 regulator-min-microvolt = <3000000>; 552 regulator-max-microvolt = <3000000>; 553 regulator-name = "vcca3v0_codec"; 554 regulator-state-mem { 555 regulator-off-in-suspend; 556 }; 557 }; 558 559 vcc_1v5: LDO_REG6 { 560 regulator-always-on; 561 regulator-boot-on; 562 regulator-min-microvolt = <1500000>; 563 regulator-max-microvolt = <1500000>; 564 regulator-name = "vcc_1v5"; 565 regulator-state-mem { 566 regulator-on-in-suspend; 567 regulator-suspend-microvolt = <1500000>; 568 }; 569 }; 570 571 vcca1v8_codec: LDO_REG7 { 572 regulator-always-on; 573 regulator-boot-on; 574 regulator-min-microvolt = <1800000>; 575 regulator-max-microvolt = <1800000>; 576 regulator-name = "vcca1v8_codec"; 577 regulator-state-mem { 578 regulator-off-in-suspend; 579 }; 580 }; 581 582 vcc_3v0: LDO_REG8 { 583 regulator-always-on; 584 regulator-boot-on; 585 regulator-min-microvolt = <3000000>; 586 regulator-max-microvolt = <3000000>; 587 regulator-name = "vcc_3v0"; 588 regulator-state-mem { 589 regulator-on-in-suspend; 590 regulator-suspend-microvolt = <3000000>; 591 }; 592 }; 593 594 vcc3v3_s3: SWITCH_REG1 { 595 regulator-always-on; 596 regulator-boot-on; 597 regulator-name = "vcc3v3_s3"; 598 regulator-state-mem { 599 regulator-off-in-suspend; 600 }; 601 }; 602 603 vcc3v3_s0: SWITCH_REG2 { 604 regulator-always-on; 605 regulator-boot-on; 606 regulator-name = "vcc3v3_s0"; 607 regulator-state-mem { 608 regulator-off-in-suspend; 609 }; 610 }; 611 }; 612 }; 613}; 614 615&i2c1 { 616 status = "okay"; 617 i2c-scl-rising-time-ns = <300>; 618 i2c-scl-falling-time-ns = <15>; 619 620 rt5640: rt5640@1c { 621 #sound-dai-cells = <0>; 622 compatible = "realtek,rt5640"; 623 reg = <0x1c>; 624 clocks = <&cru SCLK_I2S_8CH_OUT>; 625 clock-names = "mclk"; 626 realtek,in1-differential; 627 pinctrl-names = "default"; 628 pinctrl-0 = <&rt5640_hpcon &i2s_8ch_mclk>; 629 hp-con-gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 630 //hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>; 631 io-channels = <&saradc 4>; 632 hp-det-adc-value = <500>; 633 }; 634 635 camera0: ov13850@10 { 636 status = "okay"; 637 compatible = "omnivision,ov13850-v4l2-i2c-subdev"; 638 reg = < 0x10 >; 639 device_type = "v4l2-i2c-subdev"; 640 641 clocks = <&cru SCLK_CIF_OUT>; 642 clock-names = "clk_cif_out"; 643 644 pinctrl-names = "rockchip,camera_default", "rockchip,camera_sleep"; 645 pinctrl-0 = <&cam0_default_pins>; 646 pinctrl-1 = <&cam0_sleep_pins>; 647 648 rockchip,pd-gpio = <&gpio2 12 GPIO_ACTIVE_LOW>; 649 rockchip,pwr-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>; 650 rockchip,pwr-2nd-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>; 651 rockchip,rst-gpio = <&gpio0 8 GPIO_ACTIVE_LOW>; 652 653 rockchip,camera-module-mclk-name = "clk_cif_out"; 654 rockchip,camera-module-facing = "back"; 655 rockchip,camera-module-name = "cmk-cb0695-fv1"; 656 rockchip,camera-module-len-name = "lg9569a2"; 657 rockchip,camera-module-fov-h = "66.0"; 658 rockchip,camera-module-fov-v = "50.1"; 659 rockchip,camera-module-orientation = <0>; 660 rockchip,camera-module-iq-flip = <0>; 661 rockchip,camera-module-iq-mirror = <0>; 662 rockchip,camera-module-flip = <1>; 663 rockchip,camera-module-mirror = <0>; 664 665 rockchip,camera-module-defrect0 = <2112 1568 0 0 2112 1568>; 666 rockchip,camera-module-defrect1 = <4224 3136 0 0 4224 3136>; 667 rockchip,camera-module-defrect3 = <3264 2448 0 0 3264 2448>; 668 rockchip,camera-module-flash-support = <0>; 669 rockchip,camera-module-mipi-dphy-index = <0>; 670 }; 671}; 672 673&i2c3 { 674 status = "okay"; 675 i2c-scl-rising-time-ns = <450>; 676 i2c-scl-falling-time-ns = <15>; 677}; 678 679&i2c4 { 680 status = "okay"; 681 i2c-scl-rising-time-ns = <600>; 682 i2c-scl-falling-time-ns = <20>; 683 684 fusb0: fusb30x@22 { 685 compatible = "fairchild,fusb302"; 686 reg = <0x22>; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&fusb0_int>; 689 int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; 690 vbus-5v-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; 691 status = "okay"; 692 }; 693 694 gsl3680: gsl3680@41 { 695 status = "disabled"; 696 compatible = "gslX680-pad"; 697 reg = <0x41>; 698 screen_max_x = <1536>; 699 screen_max_y = <2048>; 700 touch-gpio = <&gpio1 20 IRQ_TYPE_LEVEL_LOW>; 701 reset-gpio = <&gpio0 12 GPIO_ACTIVE_HIGH>; 702 }; 703 704 mpu6050: mpu@68 { 705 status = "disabled"; 706 compatible = "invensense,mpu6050"; 707 reg = <0x68>; 708 mpu-int_config = <0x10>; 709 mpu-level_shifter = <0>; 710 mpu-orientation = <0 1 0 1 0 0 0 0 1>; 711 orientation-x= <1>; 712 orientation-y= <1>; 713 orientation-z= <1>; 714 irq-gpio = <&gpio1 4 IRQ_TYPE_LEVEL_LOW>; 715 mpu-debug = <1>; 716 }; 717}; 718 719&i2s0 { 720 status = "okay"; 721 rockchip,i2s-broken-burst-len; 722 rockchip,playback-channels = <8>; 723 rockchip,capture-channels = <8>; 724 #sound-dai-cells = <0>; 725}; 726 727&i2s1 { 728 status = "okay"; 729 rockchip,i2s-broken-burst-len; 730 rockchip,playback-channels = <2>; 731 rockchip,capture-channels = <2>; 732 #sound-dai-cells = <0>; 733}; 734 735&i2s2 { 736 #sound-dai-cells = <0>; 737 status = "okay"; 738}; 739 740&io_domains { 741 status = "okay"; 742 743 bt656-supply = <&vcc1v8_dvp>; /* bt656_gpio2ab_ms */ 744 audio-supply = <&vcca1v8_codec>; /* audio_gpio3d4a_ms */ 745 sdmmc-supply = <&vcc_sd>; /* sdmmc_gpio4b_ms */ 746 gpio1830-supply = <&vcc_3v0>; /* gpio1833_gpio4cd_ms */ 747}; 748 749&pcie_phy { 750 status = "okay"; 751}; 752 753&pcie0 { 754 ep-gpios = <&gpio4 25 GPIO_ACTIVE_HIGH>; 755 num-lanes = <4>; 756 pinctrl-names = "default"; 757 pinctrl-0 = <&pcie_clkreqn_cpm>; 758 status = "okay"; 759}; 760 761&pmu_io_domains { 762 status = "okay"; 763 pmu1830-supply = <&vcc_3v0>; 764}; 765 766&pinctrl { 767 buttons { 768 pwrbtn: pwrbtn { 769 rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>; 770 }; 771 }; 772 773 lcd-panel { 774 lcd_panel_reset: lcd-panel-reset { 775 rockchip,pins = <4 RK_PD5 RK_FUNC_GPIO &pcfg_pull_up>; 776 }; 777 778 lcd_en: lcd-en { 779 rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 780 }; 781 }; 782 783 pcie { 784 pcie_drv: pcie-drv { 785 rockchip,pins = 786 <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>; 787 }; 788 pcie_3g_drv: pcie-3g-drv { 789 rockchip,pins = 790 <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 791 }; 792 }; 793 794 pmic { 795 vsel1_gpio: vsel1-gpio { 796 rockchip,pins = 797 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; 798 }; 799 800 vsel2_gpio: vsel2-gpio { 801 rockchip,pins = 802 <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; 803 }; 804 }; 805 806 sdio-pwrseq { 807 wifi_enable_h: wifi-enable-h { 808 rockchip,pins = 809 <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; 810 }; 811 }; 812 813 wireless-bluetooth { 814 uart0_gpios: uart0-gpios { 815 rockchip,pins = 816 <2 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>; 817 }; 818 }; 819 820 rt5640 { 821 rt5640_hpcon: rt5640-hpcon { 822 rockchip,pins = <4 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; 823 }; 824 }; 825 826 pmic { 827 pmic_int_l: pmic-int-l { 828 rockchip,pins = 829 <1 RK_PC5 RK_FUNC_GPIO &pcfg_pull_up>; 830 }; 831 832 pmic_dvs2: pmic-dvs2 { 833 rockchip,pins = 834 <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>; 835 }; 836 }; 837 838 usb2 { 839 host_vbus_drv: host-vbus-drv { 840 rockchip,pins = 841 <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; 842 }; 843 }; 844 845 fusb30x { 846 fusb0_int: fusb0-int { 847 rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>; 848 }; 849 }; 850}; 851 852&pwm0 { 853 status = "okay"; 854}; 855 856&pwm2 { 857 status = "okay"; 858 pinctrl-names = "active"; 859 pinctrl-0 = <&pwm2_pin_pull_down>; 860}; 861 862&rockchip_suspend { 863 rockchip,power-ctrl = 864 <&gpio1 18 GPIO_ACTIVE_LOW>, 865 <&gpio1 14 GPIO_ACTIVE_HIGH>; 866}; 867 868&route_edp { 869 status = "disabled"; 870}; 871 872&saradc { 873 status = "okay"; 874 vref-supply = <&vccadc_ref>; 875}; 876 877&sdhci { 878 bus-width = <8>; 879 keep-power-in-suspend; 880 mmc-hs400-1_8v; 881 mmc-hs400-enhanced-strobe; 882 non-removable; 883 status = "okay"; 884 no-sdio; 885 no-sd; 886}; 887 888&sdmmc { 889 max-frequency = <150000000>; 890 no-sdio; 891 no-mmc; 892 bus-width = <4>; 893 cap-mmc-highspeed; 894 cap-sd-highspeed; 895 disable-wp; 896 num-slots = <1>; 897 vqmmc-supply = <&vcc_sd>; 898 pinctrl-names = "default"; 899 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 900 status = "okay"; 901}; 902 903&sdio0 { 904 max-frequency = <50000000>; 905 no-sd; 906 no-mmc; 907 bus-width = <4>; 908 disable-wp; 909 cap-sd-highspeed; 910 keep-power-in-suspend; 911 mmc-pwrseq = <&sdio_pwrseq>; 912 non-removable; 913 num-slots = <1>; 914 pinctrl-names = "default"; 915 pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; 916 sd-uhs-sdr104; 917 status = "okay"; 918}; 919 920&spdif { 921 status = "okay"; 922 pinctrl-0 = <&spdif_bus_1>; 923 i2c-scl-rising-time-ns = <450>; 924 i2c-scl-falling-time-ns = <15>; 925 #sound-dai-cells = <0>; 926}; 927 928&tcphy0 { 929 extcon = <&fusb0>; 930 status = "okay"; 931}; 932 933&tcphy1 { 934 status = "okay"; 935}; 936 937&tsadc { 938 /* tshut mode 0:CRU 1:GPIO */ 939 rockchip,hw-tshut-mode = <1>; 940 /* tshut polarity 0:LOW 1:HIGH */ 941 rockchip,hw-tshut-polarity = <1>; 942 status = "okay"; 943}; 944 945&u2phy0 { 946 status = "okay"; 947 extcon = <&fusb0>; 948 949 u2phy0_otg: otg-port { 950 status = "okay"; 951 }; 952 953 u2phy0_host: host-port { 954 phy-supply = <&vcc5v0_host>; 955 status = "okay"; 956 }; 957}; 958 959&u2phy1 { 960 status = "okay"; 961 962 u2phy1_otg: otg-port { 963 status = "okay"; 964 }; 965 966 u2phy1_host: host-port { 967 phy-supply = <&vcc5v0_host>; 968 status = "okay"; 969 }; 970}; 971 972&uart0 { 973 pinctrl-names = "default"; 974 pinctrl-0 = <&uart0_xfer &uart0_cts>; 975 status = "okay"; 976}; 977 978&uart2 { 979 status = "okay"; 980}; 981 982&usbdrd3_0 { 983 status = "okay"; 984}; 985 986&usbdrd3_1 { 987 status = "okay"; 988}; 989 990&usbdrd_dwc3_0 { 991 status = "okay"; 992 extcon = <&fusb0>; 993}; 994 995&usbdrd_dwc3_1 { 996 status = "okay"; 997 dr_mode = "host"; 998}; 999 1000&usb_host0_ehci { 1001 status = "okay"; 1002}; 1003 1004&usb_host0_ohci { 1005 status = "okay"; 1006}; 1007 1008&usb_host1_ehci { 1009 status = "okay"; 1010}; 1011 1012&usb_host1_ohci { 1013 status = "okay"; 1014}; 1015 1016&cif_isp0 { 1017 rockchip,camera-modules-attached = <&camera0>; 1018 status = "okay"; 1019}; 1020 1021&isp0_mmu { 1022 status = "okay"; 1023}; 1024 1025&vopb { 1026 status = "okay"; 1027}; 1028 1029&vopb_mmu { 1030 status = "okay"; 1031}; 1032 1033&vopl { 1034 status = "okay"; 1035}; 1036 1037&vopl_mmu { 1038 status = "okay"; 1039}; 1040