xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3368a-817-tablet.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
9*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
10*4882a593Smuzhiyun#include "rk3368.dtsi"
11*4882a593Smuzhiyun#include "rk3368-android.dtsi"
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Rockchip rk3368a tablet rk817 board";
14*4882a593Smuzhiyun	compatible = "rockchip,tablet", "rockchip,rk3368a", "rockchip,rk3368";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	adc_keys: adc-keys {
17*4882a593Smuzhiyun		compatible = "adc-keys";
18*4882a593Smuzhiyun		io-channels = <&saradc 1>;
19*4882a593Smuzhiyun		io-channel-names = "buttons";
20*4882a593Smuzhiyun		keyup-threshold-microvolt = <1024000>;
21*4882a593Smuzhiyun		poll-interval = <100>;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun		vol-up-key {
24*4882a593Smuzhiyun			label = "volume up";
25*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
26*4882a593Smuzhiyun			press-threshold-microvolt = <1000>;
27*4882a593Smuzhiyun		};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun		vol-down-key {
30*4882a593Smuzhiyun			label = "volume down";
31*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
32*4882a593Smuzhiyun			press-threshold-microvolt = <170000>;
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	backlight: backlight {
37*4882a593Smuzhiyun		compatible = "pwm-backlight";
38*4882a593Smuzhiyun		pwms = <&pwm0 0 25000 1>;
39*4882a593Smuzhiyun		brightness-levels = <
40*4882a593Smuzhiyun			 30  30  30  31  31  31  32  32
41*4882a593Smuzhiyun			 32  33  33  33  34  34  34  35
42*4882a593Smuzhiyun			 35  35  36  36  36  37  37  37
43*4882a593Smuzhiyun			 38  38  38  39  39  39  40  40
44*4882a593Smuzhiyun			 40  41  41  41  42  42  42  43
45*4882a593Smuzhiyun			 43  43  44  44  44  45  46  47
46*4882a593Smuzhiyun			 48  49  50  51  52  53  54  55
47*4882a593Smuzhiyun			 56  57  58  59  60  61  62  63
48*4882a593Smuzhiyun			 64  65  66  67  68  69  70  71
49*4882a593Smuzhiyun			 72  73  74  75  76  77  78  79
50*4882a593Smuzhiyun			 80  81  82  83  84  85  86  87
51*4882a593Smuzhiyun			 88  89  90  91  92  93  94  95
52*4882a593Smuzhiyun			 96  97  98  99 100 101 102 103
53*4882a593Smuzhiyun			104 105 106 107 108 109 110 111
54*4882a593Smuzhiyun			112 113 114 115 116 117 118 119
55*4882a593Smuzhiyun			120 121 122 123 124 125 126 127
56*4882a593Smuzhiyun			128 129 130 131 132 133 134 135
57*4882a593Smuzhiyun			136 137 138 139 140 141 142 143
58*4882a593Smuzhiyun			144 145 146 147 148 149 150 151
59*4882a593Smuzhiyun			152 153 154 155 156 157 158 159
60*4882a593Smuzhiyun			160 161 162 163 164 165 166 167
61*4882a593Smuzhiyun			168 169 170 171 172 173 174 175
62*4882a593Smuzhiyun			176 177 178 179 180 181 182 183
63*4882a593Smuzhiyun			184 185 186 187 188 189 190 191
64*4882a593Smuzhiyun			192 193 194 195 196 197 198 199
65*4882a593Smuzhiyun			200 201 202 203 204 205 206 207
66*4882a593Smuzhiyun			208 209 210 211 212 213 214 215
67*4882a593Smuzhiyun			216 217 218 219 220 221 222 223
68*4882a593Smuzhiyun			224 225 226 227 228 229 230 231
69*4882a593Smuzhiyun			232 232 232 233 233 233 234 234
70*4882a593Smuzhiyun			234 235 235 235 236 236 236 237
71*4882a593Smuzhiyun			237 238 238 239 239 240 240 240>;
72*4882a593Smuzhiyun		default-brightness-level = <200>;
73*4882a593Smuzhiyun		enable-gpios = <&gpio3 28 GPIO_ACTIVE_HIGH>;
74*4882a593Smuzhiyun	};
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun	charge-animation {
77*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
78*4882a593Smuzhiyun		rockchip,uboot-charge-on = <1>;
79*4882a593Smuzhiyun		rockchip,android-charge-on = <0>;
80*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <3400>;
81*4882a593Smuzhiyun		rockchip,screen-on-voltage = <3400>;
82*4882a593Smuzhiyun		status = "okay";
83*4882a593Smuzhiyun	};
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun	chosen: chosen {
86*4882a593Smuzhiyun		bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0";
87*4882a593Smuzhiyun	};
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun	rk817-sound {
90*4882a593Smuzhiyun		compatible = "simple-audio-card";
91*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
92*4882a593Smuzhiyun		simple-audio-card,name = "rockchip-rk817-codec";
93*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
94*4882a593Smuzhiyun		simple-audio-card,widgets =
95*4882a593Smuzhiyun			"Microphone", "Mic Jack",
96*4882a593Smuzhiyun			"Headphone", "Headphone Jack";
97*4882a593Smuzhiyun		simple-audio-card,routing =
98*4882a593Smuzhiyun			"Mic Jack", "MICBIAS1",
99*4882a593Smuzhiyun			"IN1P", "Mic Jack",
100*4882a593Smuzhiyun			"Headphone Jack", "HPOL",
101*4882a593Smuzhiyun			"Headphone Jack", "HPOR";
102*4882a593Smuzhiyun		simple-audio-card,cpu {
103*4882a593Smuzhiyun			sound-dai = <&i2s_8ch>;
104*4882a593Smuzhiyun		};
105*4882a593Smuzhiyun		simple-audio-card,codec {
106*4882a593Smuzhiyun			sound-dai = <&rk817_codec>;
107*4882a593Smuzhiyun		};
108*4882a593Smuzhiyun	};
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun	rk_headset: rk-headset {
111*4882a593Smuzhiyun		compatible = "rockchip_headset";
112*4882a593Smuzhiyun		headset_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
113*4882a593Smuzhiyun		pinctrl-names = "default";
114*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
115*4882a593Smuzhiyun		io-channels = <&saradc 2>;
116*4882a593Smuzhiyun	};
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
119*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
120*4882a593Smuzhiyun		pinctrl-names = "default";
121*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun		/*
124*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
125*4882a593Smuzhiyun		 * on the actual card populated):
126*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
127*4882a593Smuzhiyun		 * - PDN (power down when low)
128*4882a593Smuzhiyun		 */
129*4882a593Smuzhiyun		reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
130*4882a593Smuzhiyun	};
131*4882a593Smuzhiyun
132*4882a593Smuzhiyun	vccsys: vccsys {
133*4882a593Smuzhiyun		compatible = "regulator-fixed";
134*4882a593Smuzhiyun		regulator-name = "vcc3v8_sys";
135*4882a593Smuzhiyun		regulator-always-on;
136*4882a593Smuzhiyun		regulator-boot-on;
137*4882a593Smuzhiyun		regulator-min-microvolt = <3800000>;
138*4882a593Smuzhiyun		regulator-max-microvolt = <3800000>;
139*4882a593Smuzhiyun	};
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun	wireless-wlan {
142*4882a593Smuzhiyun		compatible = "wlan-platdata";
143*4882a593Smuzhiyun		/* wifi_chip_type - wifi chip define
144*4882a593Smuzhiyun		* ap6210, ap6330, ap6335
145*4882a593Smuzhiyun		* rtl8188eu, rtl8723bs, rtl8723bu
146*4882a593Smuzhiyun		* esp8089
147*4882a593Smuzhiyun		*/
148*4882a593Smuzhiyun		wifi_chip_type = "rtl8723bs";
149*4882a593Smuzhiyun		WIFI,vbat_gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>;
150*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>;
151*4882a593Smuzhiyun		status = "okay";
152*4882a593Smuzhiyun	};
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun	wireless-bluetooth {
155*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
156*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
157*4882a593Smuzhiyun		pinctrl-names = "default","rts_gpio";
158*4882a593Smuzhiyun		pinctrl-0 = <&uart0_rts>;
159*4882a593Smuzhiyun		pinctrl-1 = <&uart0_rts_gpio>;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun		//BT,power_gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
162*4882a593Smuzhiyun		BT,reset_gpio = <&gpio3 13 GPIO_ACTIVE_HIGH>;
163*4882a593Smuzhiyun		BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
164*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun		status = "okay";
167*4882a593Smuzhiyun	};
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun	vcc_sys: vcc-sys {
170*4882a593Smuzhiyun		compatible = "regulator-fixed";
171*4882a593Smuzhiyun		regulator-name = "vcc_sys";
172*4882a593Smuzhiyun		regulator-always-on;
173*4882a593Smuzhiyun		regulator-boot-on;
174*4882a593Smuzhiyun		regulator-min-microvolt = <3800000>;
175*4882a593Smuzhiyun		regulator-max-microvolt = <3800000>;
176*4882a593Smuzhiyun	};
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun	vcc_host: vcc-host {
179*4882a593Smuzhiyun		compatible = "regulator-fixed";
180*4882a593Smuzhiyun		enable-active-high;
181*4882a593Smuzhiyun		gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
182*4882a593Smuzhiyun		pinctrl-names = "default";
183*4882a593Smuzhiyun		pinctrl-0 = <&host_vbus_drv>;
184*4882a593Smuzhiyun		regulator-name = "vcc_host";
185*4882a593Smuzhiyun		regulator-always-on;
186*4882a593Smuzhiyun	};
187*4882a593Smuzhiyun
188*4882a593Smuzhiyun	xin32k: xin32k {
189*4882a593Smuzhiyun		compatible = "fixed-clock";
190*4882a593Smuzhiyun		clock-frequency = <32768>;
191*4882a593Smuzhiyun		clock-output-names = "xin32k";
192*4882a593Smuzhiyun		#clock-cells = <0>;
193*4882a593Smuzhiyun	};
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun};
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun&cif_clkout {
198*4882a593Smuzhiyun	/* cif_clkout */
199*4882a593Smuzhiyun	rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none_4ma>;
200*4882a593Smuzhiyun};
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun&cpu_l0 {
203*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
204*4882a593Smuzhiyun};
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun&cpu_l1 {
207*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
208*4882a593Smuzhiyun};
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun&cpu_l2 {
211*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
212*4882a593Smuzhiyun};
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun&cpu_l3 {
215*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
216*4882a593Smuzhiyun};
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun&cpu_b0 {
219*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
220*4882a593Smuzhiyun};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun&cpu_b1 {
223*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&cpu_b2 {
227*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
228*4882a593Smuzhiyun};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun&cpu_b3 {
231*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
232*4882a593Smuzhiyun};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun&gpu {
235*4882a593Smuzhiyun	logic-supply = <&vdd_logic>;
236*4882a593Smuzhiyun};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun&dsi {
239*4882a593Smuzhiyun	status = "okay";
240*4882a593Smuzhiyun	//rockchip,lane-rate = <500>;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun	panel:panel@0 {
243*4882a593Smuzhiyun		compatible = "simple-panel-dsi";
244*4882a593Smuzhiyun		reg = <0>;
245*4882a593Smuzhiyun		backlight = <&backlight>;
246*4882a593Smuzhiyun		enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
247*4882a593Smuzhiyun		prepare-delay-ms = <20>;
248*4882a593Smuzhiyun		reset-delay-ms = <20>;
249*4882a593Smuzhiyun		init-delay-ms = <20>;
250*4882a593Smuzhiyun		enable-delay-ms = <120>;
251*4882a593Smuzhiyun		disable-delay-ms = <20>;
252*4882a593Smuzhiyun		unprepare-delay-ms = <20>;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun		width-mm = <135>;
255*4882a593Smuzhiyun		height-mm = <216>;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
258*4882a593Smuzhiyun			      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
259*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
260*4882a593Smuzhiyun		dsi,lanes = <4>;
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun		panel-init-sequence = [
263*4882a593Smuzhiyun			39 00 04 FF 98 81 03
264*4882a593Smuzhiyun			15 00 02 01 00
265*4882a593Smuzhiyun			15 00 02 02 00
266*4882a593Smuzhiyun			15 00 02 03 53
267*4882a593Smuzhiyun			15 00 02 04 00
268*4882a593Smuzhiyun			15 00 02 05 00
269*4882a593Smuzhiyun			15 00 02 06 08
270*4882a593Smuzhiyun			15 00 02 07 00
271*4882a593Smuzhiyun			15 00 02 08 00
272*4882a593Smuzhiyun			15 00 02 09 00
273*4882a593Smuzhiyun			15 00 02 0A 00
274*4882a593Smuzhiyun			15 00 02 0B 00
275*4882a593Smuzhiyun			15 00 02 0C 00
276*4882a593Smuzhiyun			15 00 02 0D 00
277*4882a593Smuzhiyun			15 00 02 0E 00
278*4882a593Smuzhiyun			15 00 02 0F 26
279*4882a593Smuzhiyun			15 00 02 10 26
280*4882a593Smuzhiyun			15 00 02 11 00
281*4882a593Smuzhiyun			15 00 02 12 00
282*4882a593Smuzhiyun			15 00 02 13 00
283*4882a593Smuzhiyun			15 00 02 14 00
284*4882a593Smuzhiyun			15 00 02 15 00
285*4882a593Smuzhiyun			15 00 02 16 00
286*4882a593Smuzhiyun			15 00 02 17 00
287*4882a593Smuzhiyun			15 00 02 18 00
288*4882a593Smuzhiyun			15 00 02 19 00
289*4882a593Smuzhiyun			15 00 02 1A 00
290*4882a593Smuzhiyun			15 00 02 1B 00
291*4882a593Smuzhiyun			15 00 02 1C 00
292*4882a593Smuzhiyun			15 00 02 1D 00
293*4882a593Smuzhiyun			15 00 02 1E 40
294*4882a593Smuzhiyun			15 00 02 1F C0
295*4882a593Smuzhiyun			15 00 02 20 06
296*4882a593Smuzhiyun			15 00 02 21 01
297*4882a593Smuzhiyun			15 00 02 22 07
298*4882a593Smuzhiyun			15 00 02 23 00
299*4882a593Smuzhiyun			15 00 02 24 8A
300*4882a593Smuzhiyun			15 00 02 25 8A
301*4882a593Smuzhiyun			15 00 02 26 00
302*4882a593Smuzhiyun			15 00 02 27 00
303*4882a593Smuzhiyun			15 00 02 28 33
304*4882a593Smuzhiyun			15 00 02 29 33
305*4882a593Smuzhiyun			15 00 02 2A 00
306*4882a593Smuzhiyun			15 00 02 2B 00
307*4882a593Smuzhiyun			15 00 02 2C 08
308*4882a593Smuzhiyun			15 00 02 2D 08
309*4882a593Smuzhiyun			15 00 02 2E 0B
310*4882a593Smuzhiyun			15 00 02 2F 0B
311*4882a593Smuzhiyun			15 00 02 30 00
312*4882a593Smuzhiyun			15 00 02 31 00
313*4882a593Smuzhiyun			15 00 02 32 42
314*4882a593Smuzhiyun			15 00 02 33 00
315*4882a593Smuzhiyun			15 00 02 34 00
316*4882a593Smuzhiyun			15 00 02 35 0A
317*4882a593Smuzhiyun			15 00 02 36 00
318*4882a593Smuzhiyun			15 00 02 37 08
319*4882a593Smuzhiyun			15 00 02 38 3C
320*4882a593Smuzhiyun			15 00 02 39 00
321*4882a593Smuzhiyun			15 00 02 3A 00
322*4882a593Smuzhiyun			15 00 02 3B 00
323*4882a593Smuzhiyun			15 00 02 3C 00
324*4882a593Smuzhiyun			15 00 02 3D 00
325*4882a593Smuzhiyun			15 00 02 3E 00
326*4882a593Smuzhiyun			15 00 02 3F 00
327*4882a593Smuzhiyun			15 00 02 40 00
328*4882a593Smuzhiyun			15 00 02 41 00
329*4882a593Smuzhiyun			15 00 02 42 00
330*4882a593Smuzhiyun			15 00 02 43 08
331*4882a593Smuzhiyun			15 00 02 44 00
332*4882a593Smuzhiyun			15 00 02 50 01
333*4882a593Smuzhiyun			15 00 02 51 23
334*4882a593Smuzhiyun			15 00 02 52 45
335*4882a593Smuzhiyun			15 00 02 53 67
336*4882a593Smuzhiyun			15 00 02 54 89
337*4882a593Smuzhiyun			15 00 02 55 AB
338*4882a593Smuzhiyun			15 00 02 56 01
339*4882a593Smuzhiyun			15 00 02 57 23
340*4882a593Smuzhiyun			15 00 02 58 45
341*4882a593Smuzhiyun			15 00 02 59 67
342*4882a593Smuzhiyun			15 00 02 5A 89
343*4882a593Smuzhiyun			15 00 02 5B AB
344*4882a593Smuzhiyun			15 00 02 5C CD
345*4882a593Smuzhiyun			15 00 02 5D EF
346*4882a593Smuzhiyun			15 00 02 5E 00
347*4882a593Smuzhiyun			15 00 02 5F 01
348*4882a593Smuzhiyun			15 00 02 60 01
349*4882a593Smuzhiyun			15 00 02 61 06
350*4882a593Smuzhiyun			15 00 02 62 06
351*4882a593Smuzhiyun			15 00 02 63 06
352*4882a593Smuzhiyun			15 00 02 64 06
353*4882a593Smuzhiyun			15 00 02 65 00
354*4882a593Smuzhiyun			15 00 02 66 00
355*4882a593Smuzhiyun			15 00 02 67 17
356*4882a593Smuzhiyun			15 00 02 68 02
357*4882a593Smuzhiyun			15 00 02 69 16
358*4882a593Smuzhiyun			15 00 02 6A 16
359*4882a593Smuzhiyun			15 00 02 6B 02
360*4882a593Smuzhiyun			15 00 02 6C 0D
361*4882a593Smuzhiyun			15 00 02 6D 0D
362*4882a593Smuzhiyun			15 00 02 6E 0C
363*4882a593Smuzhiyun			15 00 02 6F 0C
364*4882a593Smuzhiyun			15 00 02 70 0F
365*4882a593Smuzhiyun			15 00 02 71 0F
366*4882a593Smuzhiyun			15 00 02 72 0E
367*4882a593Smuzhiyun			15 00 02 73 0E
368*4882a593Smuzhiyun			15 00 02 74 02
369*4882a593Smuzhiyun			15 00 02 75 01
370*4882a593Smuzhiyun			15 00 02 76 01
371*4882a593Smuzhiyun			15 00 02 77 06
372*4882a593Smuzhiyun			15 00 02 78 06
373*4882a593Smuzhiyun			15 00 02 79 06
374*4882a593Smuzhiyun			15 00 02 7A 06
375*4882a593Smuzhiyun			15 00 02 7B 00
376*4882a593Smuzhiyun			15 00 02 7C 00
377*4882a593Smuzhiyun			15 00 02 7D 17
378*4882a593Smuzhiyun			15 00 02 7E 02
379*4882a593Smuzhiyun			15 00 02 7F 16
380*4882a593Smuzhiyun			15 00 02 80 16
381*4882a593Smuzhiyun			15 00 02 81 02
382*4882a593Smuzhiyun			15 00 02 82 0D
383*4882a593Smuzhiyun			15 00 02 83 0D
384*4882a593Smuzhiyun			15 00 02 84 0C
385*4882a593Smuzhiyun			15 00 02 85 0C
386*4882a593Smuzhiyun			15 00 02 86 0F
387*4882a593Smuzhiyun			15 00 02 87 0F
388*4882a593Smuzhiyun			15 00 02 88 0E
389*4882a593Smuzhiyun			15 00 02 89 0E
390*4882a593Smuzhiyun			15 00 02 8A 02
391*4882a593Smuzhiyun			39 00 04 FF 98 81 04
392*4882a593Smuzhiyun			15 00 02 6E 2B
393*4882a593Smuzhiyun			15 00 02 6F 35
394*4882a593Smuzhiyun			15 00 02 3A A4
395*4882a593Smuzhiyun			15 00 02 8D 1A
396*4882a593Smuzhiyun			15 00 02 87 BA
397*4882a593Smuzhiyun			15 00 02 B2 D1
398*4882a593Smuzhiyun			15 00 02 88 0B
399*4882a593Smuzhiyun			15 00 02 38 01
400*4882a593Smuzhiyun			15 00 02 39 00
401*4882a593Smuzhiyun			15 00 02 B5 07
402*4882a593Smuzhiyun			15 00 02 31 75
403*4882a593Smuzhiyun			15 00 02 3B 98
404*4882a593Smuzhiyun			39 00 04 FF 98 81 01
405*4882a593Smuzhiyun			15 00 02 22 0A
406*4882a593Smuzhiyun			15 00 02 31 00
407*4882a593Smuzhiyun			15 00 02 53 40
408*4882a593Smuzhiyun			15 00 02 55 40
409*4882a593Smuzhiyun			15 00 02 50 95
410*4882a593Smuzhiyun			15 00 02 51 90
411*4882a593Smuzhiyun			15 00 02 60 22
412*4882a593Smuzhiyun			15 00 02 62 20
413*4882a593Smuzhiyun			15 00 02 A0 00
414*4882a593Smuzhiyun			15 00 02 A1 1B
415*4882a593Smuzhiyun			15 00 02 A2 2A
416*4882a593Smuzhiyun			15 00 02 A3 14
417*4882a593Smuzhiyun			15 00 02 A4 17
418*4882a593Smuzhiyun			15 00 02 A5 2B
419*4882a593Smuzhiyun			15 00 02 A6 1F
420*4882a593Smuzhiyun			15 00 02 A7 20
421*4882a593Smuzhiyun			15 00 02 A8 93
422*4882a593Smuzhiyun			15 00 02 A9 1E
423*4882a593Smuzhiyun			15 00 02 AA 2A
424*4882a593Smuzhiyun			15 00 02 AB 7E
425*4882a593Smuzhiyun			15 00 02 AC 1B
426*4882a593Smuzhiyun			15 00 02 AD 19
427*4882a593Smuzhiyun			15 00 02 AE 4C
428*4882a593Smuzhiyun			15 00 02 AF 22
429*4882a593Smuzhiyun			15 00 02 B0 28
430*4882a593Smuzhiyun			15 00 02 B1 4B
431*4882a593Smuzhiyun			15 00 02 B2 59
432*4882a593Smuzhiyun			15 00 02 B3 23
433*4882a593Smuzhiyun			15 00 02 C0 00
434*4882a593Smuzhiyun			15 00 02 C1 1B
435*4882a593Smuzhiyun			15 00 02 C2 2A
436*4882a593Smuzhiyun			15 00 02 C3 14
437*4882a593Smuzhiyun			15 00 02 C4 17
438*4882a593Smuzhiyun			15 00 02 C5 2B
439*4882a593Smuzhiyun			15 00 02 C6 1F
440*4882a593Smuzhiyun			15 00 02 C7 20
441*4882a593Smuzhiyun			15 00 02 C8 93
442*4882a593Smuzhiyun			15 00 02 C9 1E
443*4882a593Smuzhiyun			15 00 02 CA 2A
444*4882a593Smuzhiyun			15 00 02 CB 7E
445*4882a593Smuzhiyun			15 00 02 CC 1B
446*4882a593Smuzhiyun			15 00 02 CD 19
447*4882a593Smuzhiyun			15 00 02 CE 4C
448*4882a593Smuzhiyun			15 00 02 CF 22
449*4882a593Smuzhiyun			15 00 02 D0 28
450*4882a593Smuzhiyun			15 00 02 D1 4B
451*4882a593Smuzhiyun			15 00 02 D2 59
452*4882a593Smuzhiyun			15 00 02 D3 23
453*4882a593Smuzhiyun			//39 00 04 FF 98 81 04
454*4882a593Smuzhiyun			//05 00 02 2D 80
455*4882a593Smuzhiyun			//05 00 02 2F 31
456*4882a593Smuzhiyun			39 00 04 FF 98 81 00
457*4882a593Smuzhiyun			05 78 01 11
458*4882a593Smuzhiyun			05 14 01 29
459*4882a593Smuzhiyun			15 00 02 35 00
460*4882a593Smuzhiyun		];
461*4882a593Smuzhiyun
462*4882a593Smuzhiyun		panel-exit-sequence = [
463*4882a593Smuzhiyun			05 00 01 28
464*4882a593Smuzhiyun			05 00 01 10
465*4882a593Smuzhiyun		];
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun		display-timings {
468*4882a593Smuzhiyun			native-mode = <&timing0>;
469*4882a593Smuzhiyun
470*4882a593Smuzhiyun			timing0: timing0 {
471*4882a593Smuzhiyun				clock-frequency = <78000000>;
472*4882a593Smuzhiyun				hactive = <800>;
473*4882a593Smuzhiyun				vactive = <1280>;
474*4882a593Smuzhiyun				hfront-porch = <60>;//70 //16
475*4882a593Smuzhiyun				hsync-len = <30>; //20 //5
476*4882a593Smuzhiyun				hback-porch = <60>; //59
477*4882a593Smuzhiyun				vfront-porch = <20>; //16 //8
478*4882a593Smuzhiyun				vsync-len = <8>; //5
479*4882a593Smuzhiyun				vback-porch = <16>; //22 //3
480*4882a593Smuzhiyun				hsync-active = <0>;
481*4882a593Smuzhiyun				vsync-active = <0>;
482*4882a593Smuzhiyun				de-active = <0>;
483*4882a593Smuzhiyun				pixelclk-active = <0>;
484*4882a593Smuzhiyun			};
485*4882a593Smuzhiyun		};
486*4882a593Smuzhiyun	};
487*4882a593Smuzhiyun};
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun&dfi {
490*4882a593Smuzhiyun	status = "okay";
491*4882a593Smuzhiyun};
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun&dmc {
494*4882a593Smuzhiyun	status = "okay";
495*4882a593Smuzhiyun	center-supply = <&vdd_logic>;
496*4882a593Smuzhiyun	devfreq-events = <&dfi>;
497*4882a593Smuzhiyun	upthreshold = <60>;
498*4882a593Smuzhiyun	downdifferential = <20>;
499*4882a593Smuzhiyun	system-status-freq = <
500*4882a593Smuzhiyun		/*system status		freq(KHz)*/
501*4882a593Smuzhiyun		SYS_STATUS_NORMAL	600000
502*4882a593Smuzhiyun		SYS_STATUS_REBOOT	600000
503*4882a593Smuzhiyun		SYS_STATUS_SUSPEND	240000
504*4882a593Smuzhiyun		SYS_STATUS_VIDEO_1080P	396000
505*4882a593Smuzhiyun		SYS_STATUS_VIDEO_4K	600000
506*4882a593Smuzhiyun		SYS_STATUS_PERFORMANCE	600000
507*4882a593Smuzhiyun		SYS_STATUS_BOOST	396000
508*4882a593Smuzhiyun		SYS_STATUS_DUALVIEW	600000
509*4882a593Smuzhiyun		SYS_STATUS_ISP		528000
510*4882a593Smuzhiyun	>;
511*4882a593Smuzhiyun	vop-bw-dmc-freq = <
512*4882a593Smuzhiyun	/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
513*4882a593Smuzhiyun		0       582      240000
514*4882a593Smuzhiyun		583     99999    396000
515*4882a593Smuzhiyun	>;
516*4882a593Smuzhiyun	vop-dclk-mode = <1>;
517*4882a593Smuzhiyun	auto-min-freq = <240000>;
518*4882a593Smuzhiyun	auto-freq-en = <0>;
519*4882a593Smuzhiyun};
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun&emmc {
522*4882a593Smuzhiyun	bus-width = <8>;
523*4882a593Smuzhiyun	cap-mmc-highspeed;
524*4882a593Smuzhiyun	mmc-hs200-1_8v;
525*4882a593Smuzhiyun	no-sdio;
526*4882a593Smuzhiyun	no-sd;
527*4882a593Smuzhiyun	disable-wp;
528*4882a593Smuzhiyun	non-removable;
529*4882a593Smuzhiyun	num-slots = <1>;
530*4882a593Smuzhiyun	status = "okay";
531*4882a593Smuzhiyun};
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun&i2c0 {
534*4882a593Smuzhiyun	status = "okay";
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun	vdd_cpu: syr827@40 {
537*4882a593Smuzhiyun		compatible = "silergy,syr827";
538*4882a593Smuzhiyun		status = "okay";
539*4882a593Smuzhiyun		reg = <0x40>;
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
542*4882a593Smuzhiyun		regulator-name = "vdd_cpu";
543*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
544*4882a593Smuzhiyun		regulator-max-microvolt = <1500000>;
545*4882a593Smuzhiyun		regulator-ramp-delay = <1000>;
546*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
547*4882a593Smuzhiyun		pinctrl-0 = <&vsel_gpio>;
548*4882a593Smuzhiyun		vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
549*4882a593Smuzhiyun		regulator-always-on;
550*4882a593Smuzhiyun		regulator-boot-on;
551*4882a593Smuzhiyun		regulator-initial-state = <3>;
552*4882a593Smuzhiyun		regulator-state-mem {
553*4882a593Smuzhiyun			regulator-off-in-suspend;
554*4882a593Smuzhiyun		};
555*4882a593Smuzhiyun	};
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun	rk817: pmic@20 {
558*4882a593Smuzhiyun		compatible = "rockchip,rk817";
559*4882a593Smuzhiyun		reg = <0x20>;
560*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
561*4882a593Smuzhiyun		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
562*4882a593Smuzhiyun		pinctrl-names = "default", "pmic-sleep",
563*4882a593Smuzhiyun				"pmic-power-off", "pmic-reset";
564*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int>;
565*4882a593Smuzhiyun		pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
566*4882a593Smuzhiyun		pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>;
567*4882a593Smuzhiyun		pinctrl-3 = <&soc_slppin_slp>, <&rk817_slppin_slp>;
568*4882a593Smuzhiyun		rockchip,system-power-controller;
569*4882a593Smuzhiyun		wakeup-source;
570*4882a593Smuzhiyun		#clock-cells = <1>;
571*4882a593Smuzhiyun		clock-output-names = "rk808-clkout1", "rk808-clkout2";
572*4882a593Smuzhiyun		//fb-inner-reg-idxs = <2>;
573*4882a593Smuzhiyun		/* 1: rst regs (default in codes), 0: rst the pmic */
574*4882a593Smuzhiyun		pmic-reset-func = <1>;
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun		vcc1-supply = <&vccsys>;
577*4882a593Smuzhiyun		vcc2-supply = <&vccsys>;
578*4882a593Smuzhiyun		vcc3-supply = <&vccsys>;
579*4882a593Smuzhiyun		vcc4-supply = <&vccsys>;
580*4882a593Smuzhiyun		vcc5-supply = <&vccsys>;
581*4882a593Smuzhiyun		vcc6-supply = <&vccsys>;
582*4882a593Smuzhiyun		vcc7-supply = <&vcc_io>;
583*4882a593Smuzhiyun		vcc8-supply = <&vccsys>;
584*4882a593Smuzhiyun		vcc9-supply = <&dcdc_boost>;
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun		pwrkey {
587*4882a593Smuzhiyun			status = "okay";
588*4882a593Smuzhiyun		};
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun		pinctrl_rk8xx: pinctrl_rk8xx {
591*4882a593Smuzhiyun			gpio-controller;
592*4882a593Smuzhiyun			#gpio-cells = <2>;
593*4882a593Smuzhiyun
594*4882a593Smuzhiyun			rk817_ts_gpio1: rk817_ts_gpio1 {
595*4882a593Smuzhiyun				pins = "gpio_ts";
596*4882a593Smuzhiyun				function = "pin_fun1";
597*4882a593Smuzhiyun				/* output-low; */
598*4882a593Smuzhiyun				/* input-enable; */
599*4882a593Smuzhiyun			};
600*4882a593Smuzhiyun
601*4882a593Smuzhiyun			rk817_gt_gpio2: rk817_gt_gpio2 {
602*4882a593Smuzhiyun				pins = "gpio_gt";
603*4882a593Smuzhiyun				function = "pin_fun1";
604*4882a593Smuzhiyun			};
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun			rk817_pin_ts: rk817_pin_ts {
607*4882a593Smuzhiyun				pins = "gpio_ts";
608*4882a593Smuzhiyun				function = "pin_fun0";
609*4882a593Smuzhiyun			};
610*4882a593Smuzhiyun
611*4882a593Smuzhiyun			rk817_pin_gt: rk817_pin_gt {
612*4882a593Smuzhiyun				pins = "gpio_gt";
613*4882a593Smuzhiyun				function = "pin_fun0";
614*4882a593Smuzhiyun			};
615*4882a593Smuzhiyun
616*4882a593Smuzhiyun			rk817_slppin_null: rk817_slppin_null {
617*4882a593Smuzhiyun				pins = "gpio_slp";
618*4882a593Smuzhiyun				function = "pin_fun0";
619*4882a593Smuzhiyun			};
620*4882a593Smuzhiyun
621*4882a593Smuzhiyun			rk817_slppin_slp: rk817_slppin_slp {
622*4882a593Smuzhiyun				pins = "gpio_slp";
623*4882a593Smuzhiyun				function = "pin_fun1";
624*4882a593Smuzhiyun			};
625*4882a593Smuzhiyun
626*4882a593Smuzhiyun			rk817_slppin_pwrdn: rk817_slppin_pwrdn {
627*4882a593Smuzhiyun				pins = "gpio_slp";
628*4882a593Smuzhiyun				function = "pin_fun2";
629*4882a593Smuzhiyun			};
630*4882a593Smuzhiyun
631*4882a593Smuzhiyun			rk817_slppin_rst: rk817_slppin_rst {
632*4882a593Smuzhiyun				pins = "gpio_slp";
633*4882a593Smuzhiyun				function = "pin_fun3";
634*4882a593Smuzhiyun			};
635*4882a593Smuzhiyun		};
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun		regulators {
638*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
639*4882a593Smuzhiyun				regulator-always-on;
640*4882a593Smuzhiyun				regulator-boot-on;
641*4882a593Smuzhiyun				regulator-min-microvolt = <950000>;
642*4882a593Smuzhiyun				regulator-max-microvolt = <1350000>;
643*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
644*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
645*4882a593Smuzhiyun				regulator-name = "vdd_logic";
646*4882a593Smuzhiyun				regulator-state-mem {
647*4882a593Smuzhiyun					regulator-on-in-suspend;
648*4882a593Smuzhiyun					regulator-suspend-microvolt = <950000>;
649*4882a593Smuzhiyun				};
650*4882a593Smuzhiyun			};
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun			vcc_3v3: DCDC_REG2 {
653*4882a593Smuzhiyun				regulator-name = "vcc_3v3";
654*4882a593Smuzhiyun				regulator-always-on;
655*4882a593Smuzhiyun				regulator-boot-on;
656*4882a593Smuzhiyun				regulator-state-mem {
657*4882a593Smuzhiyun					regulator-on-in-suspend;
658*4882a593Smuzhiyun				};
659*4882a593Smuzhiyun			};
660*4882a593Smuzhiyun
661*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
662*4882a593Smuzhiyun				regulator-always-on;
663*4882a593Smuzhiyun				regulator-boot-on;
664*4882a593Smuzhiyun				regulator-initial-mode = <0x2>;
665*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
666*4882a593Smuzhiyun				regulator-state-mem {
667*4882a593Smuzhiyun					regulator-on-in-suspend;
668*4882a593Smuzhiyun				};
669*4882a593Smuzhiyun			};
670*4882a593Smuzhiyun
671*4882a593Smuzhiyun			vcc_io: DCDC_REG4 {
672*4882a593Smuzhiyun				regulator-always-on;
673*4882a593Smuzhiyun				regulator-boot-on;
674*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
675*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
676*4882a593Smuzhiyun				regulator-name = "vcc_io";
677*4882a593Smuzhiyun				regulator-state-mem {
678*4882a593Smuzhiyun					regulator-on-in-suspend;
679*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
680*4882a593Smuzhiyun				};
681*4882a593Smuzhiyun			};
682*4882a593Smuzhiyun
683*4882a593Smuzhiyun			vcc_1v0: LDO_REG1 {
684*4882a593Smuzhiyun				regulator-always-on;
685*4882a593Smuzhiyun				regulator-boot-on;
686*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
687*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
688*4882a593Smuzhiyun				regulator-name = "vcc_1v0";
689*4882a593Smuzhiyun				regulator-state-mem {
690*4882a593Smuzhiyun					regulator-on-in-suspend;
691*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
692*4882a593Smuzhiyun				};
693*4882a593Smuzhiyun			};
694*4882a593Smuzhiyun
695*4882a593Smuzhiyun			vcc1v8_soc: LDO_REG2 {
696*4882a593Smuzhiyun				regulator-always-on;
697*4882a593Smuzhiyun				regulator-boot-on;
698*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
699*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
700*4882a593Smuzhiyun
701*4882a593Smuzhiyun				regulator-name = "vcc1v8_soc";
702*4882a593Smuzhiyun				regulator-state-mem {
703*4882a593Smuzhiyun					regulator-on-in-suspend;
704*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
705*4882a593Smuzhiyun				};
706*4882a593Smuzhiyun			};
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun			vdd1v0_soc: LDO_REG3 {
709*4882a593Smuzhiyun				regulator-always-on;
710*4882a593Smuzhiyun				regulator-boot-on;
711*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
712*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun				regulator-name = "vcc1v0_soc";
715*4882a593Smuzhiyun				regulator-state-mem {
716*4882a593Smuzhiyun					regulator-on-in-suspend;
717*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
718*4882a593Smuzhiyun				};
719*4882a593Smuzhiyun			};
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun			vcc3v3_pmu: LDO_REG4 {
722*4882a593Smuzhiyun				regulator-always-on;
723*4882a593Smuzhiyun				regulator-boot-on;
724*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
725*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
726*4882a593Smuzhiyun
727*4882a593Smuzhiyun				regulator-name = "vcc3v3_pmu";
728*4882a593Smuzhiyun				regulator-state-mem {
729*4882a593Smuzhiyun					regulator-on-in-suspend;
730*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun				};
733*4882a593Smuzhiyun			};
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun			vccio_sd: LDO_REG5 {
736*4882a593Smuzhiyun				regulator-always-on;
737*4882a593Smuzhiyun				regulator-boot-on;
738*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
739*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
740*4882a593Smuzhiyun
741*4882a593Smuzhiyun				regulator-name = "vccio_sd";
742*4882a593Smuzhiyun				regulator-state-mem {
743*4882a593Smuzhiyun					regulator-on-in-suspend;
744*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
745*4882a593Smuzhiyun				};
746*4882a593Smuzhiyun			};
747*4882a593Smuzhiyun
748*4882a593Smuzhiyun			vcc_sd: LDO_REG6 {
749*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
750*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
751*4882a593Smuzhiyun
752*4882a593Smuzhiyun				regulator-name = "vcc_sd";
753*4882a593Smuzhiyun				regulator-state-mem {
754*4882a593Smuzhiyun					regulator-on-in-suspend;
755*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun				};
758*4882a593Smuzhiyun			};
759*4882a593Smuzhiyun
760*4882a593Smuzhiyun			vcc2v8_dvp: LDO_REG7 {
761*4882a593Smuzhiyun				regulator-boot-on;
762*4882a593Smuzhiyun				regulator-min-microvolt = <2800000>;
763*4882a593Smuzhiyun				regulator-max-microvolt = <2800000>;
764*4882a593Smuzhiyun
765*4882a593Smuzhiyun				regulator-name = "vcc2v8_dvp";
766*4882a593Smuzhiyun				regulator-state-mem {
767*4882a593Smuzhiyun					regulator-off-in-suspend;
768*4882a593Smuzhiyun					regulator-suspend-microvolt = <2800000>;
769*4882a593Smuzhiyun				};
770*4882a593Smuzhiyun			};
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun			vcc1v8_dvp: LDO_REG8 {
773*4882a593Smuzhiyun				regulator-boot-on;
774*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
775*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun				regulator-name = "vcc1v8_dvp";
778*4882a593Smuzhiyun				regulator-state-mem {
779*4882a593Smuzhiyun					regulator-off-in-suspend;
780*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
781*4882a593Smuzhiyun				};
782*4882a593Smuzhiyun			};
783*4882a593Smuzhiyun
784*4882a593Smuzhiyun			vdd1v5_dvp: LDO_REG9 {
785*4882a593Smuzhiyun				regulator-boot-on;
786*4882a593Smuzhiyun				regulator-min-microvolt = <1500000>;
787*4882a593Smuzhiyun				regulator-max-microvolt = <1500000>;
788*4882a593Smuzhiyun
789*4882a593Smuzhiyun				regulator-name = "vdd1v5_dvp";
790*4882a593Smuzhiyun				regulator-state-mem {
791*4882a593Smuzhiyun					regulator-off-in-suspend;
792*4882a593Smuzhiyun					regulator-suspend-microvolt = <1500000>;
793*4882a593Smuzhiyun				};
794*4882a593Smuzhiyun			};
795*4882a593Smuzhiyun
796*4882a593Smuzhiyun			dcdc_boost: BOOST {
797*4882a593Smuzhiyun				regulator-always-on;
798*4882a593Smuzhiyun				regulator-boot-on;
799*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
800*4882a593Smuzhiyun				regulator-max-microvolt = <5000000>;
801*4882a593Smuzhiyun				regulator-name = "boost";
802*4882a593Smuzhiyun			};
803*4882a593Smuzhiyun
804*4882a593Smuzhiyun			otg_switch: OTG_SWITCH {
805*4882a593Smuzhiyun				regulator-name = "otg_switch";
806*4882a593Smuzhiyun			};
807*4882a593Smuzhiyun		};
808*4882a593Smuzhiyun
809*4882a593Smuzhiyun		battery {
810*4882a593Smuzhiyun			compatible = "rk817,battery";
811*4882a593Smuzhiyun			ocv_table = <3500 3548 3592 3636 3687 3740 3780
812*4882a593Smuzhiyun				3806 3827 3846 3864 3889 3929 3964
813*4882a593Smuzhiyun				3993 4015 4030 4041 4056 4076 4148>;
814*4882a593Smuzhiyun			design_capacity = <5000>;
815*4882a593Smuzhiyun			design_qmax = <5500>;
816*4882a593Smuzhiyun			bat_res = <100>;
817*4882a593Smuzhiyun			sleep_enter_current = <150>;
818*4882a593Smuzhiyun			sleep_exit_current = <180>;
819*4882a593Smuzhiyun			sleep_filter_current = <100>;
820*4882a593Smuzhiyun			power_off_thresd = <3400>;
821*4882a593Smuzhiyun			zero_algorithm_vol = <3850>;
822*4882a593Smuzhiyun			max_soc_offset = <60>;
823*4882a593Smuzhiyun			monitor_sec = <5>;
824*4882a593Smuzhiyun			sample_res = <10>;
825*4882a593Smuzhiyun			virtual_power = <0>;
826*4882a593Smuzhiyun		};
827*4882a593Smuzhiyun
828*4882a593Smuzhiyun		charger {
829*4882a593Smuzhiyun			compatible = "rk817,charger";
830*4882a593Smuzhiyun			min_input_voltage = <4500>;
831*4882a593Smuzhiyun			max_input_current = <1500>;
832*4882a593Smuzhiyun			max_chrg_current = <2000>;
833*4882a593Smuzhiyun			max_chrg_voltage = <4200>;
834*4882a593Smuzhiyun			chrg_term_mode = <0>;
835*4882a593Smuzhiyun			chrg_finish_cur = <300>;
836*4882a593Smuzhiyun			virtual_power = <0>;
837*4882a593Smuzhiyun			dc_det_adc = <0>;
838*4882a593Smuzhiyun			extcon = <&u2phy>;
839*4882a593Smuzhiyun		};
840*4882a593Smuzhiyun
841*4882a593Smuzhiyun		rk817_codec: codec {
842*4882a593Smuzhiyun			#sound-dai-cells = <0>;
843*4882a593Smuzhiyun			compatible = "rockchip,rk817-codec";
844*4882a593Smuzhiyun			clocks = <&cru SCLK_I2S_8CH_OUT>;
845*4882a593Smuzhiyun			clock-names = "mclk";
846*4882a593Smuzhiyun			pinctrl-names = "default";
847*4882a593Smuzhiyun			pinctrl-0 = <&i2s_8ch_mclk>;
848*4882a593Smuzhiyun			hp-volume = <20>;
849*4882a593Smuzhiyun			spk-volume = <3>;
850*4882a593Smuzhiyun			mic-in-differential;
851*4882a593Smuzhiyun			out-l2spk-r2hp;
852*4882a593Smuzhiyun			spk-ctl-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
853*4882a593Smuzhiyun			status = "okay";
854*4882a593Smuzhiyun		};
855*4882a593Smuzhiyun	};
856*4882a593Smuzhiyun};
857*4882a593Smuzhiyun
858*4882a593Smuzhiyun&i2c2 {
859*4882a593Smuzhiyun	status = "okay";
860*4882a593Smuzhiyun
861*4882a593Smuzhiyun	ts@40 {
862*4882a593Smuzhiyun		status = "okay";
863*4882a593Smuzhiyun		compatible = "GSL,GSL_THZY";
864*4882a593Smuzhiyun		reg = <0x40>;
865*4882a593Smuzhiyun		irq_gpio_number = <&gpio0 RK_PB4 IRQ_TYPE_LEVEL_HIGH>;
866*4882a593Smuzhiyun		rst_gpio_number = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
867*4882a593Smuzhiyun	};
868*4882a593Smuzhiyun};
869*4882a593Smuzhiyun
870*4882a593Smuzhiyun&i2c3 {
871*4882a593Smuzhiyun	status = "okay";
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun	gc032a: gc032a@21 {
874*4882a593Smuzhiyun		status = "okay";
875*4882a593Smuzhiyun		compatible = "galaxycore,gc032a";
876*4882a593Smuzhiyun		reg = <0x21>;
877*4882a593Smuzhiyun		clocks = <&cru SCLK_VIP_OUT>;
878*4882a593Smuzhiyun		clock-names = "xvclk";
879*4882a593Smuzhiyun
880*4882a593Smuzhiyun		avdd-supply = <&vcc2v8_dvp>;
881*4882a593Smuzhiyun		dovdd-supply = <&vcc1v8_dvp>;
882*4882a593Smuzhiyun		dvdd-supply = <&vdd1v5_dvp>;
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
885*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
886*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
887*4882a593Smuzhiyun		rockchip,camera-module-name = "CameraKing";
888*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan";
889*4882a593Smuzhiyun		port {
890*4882a593Smuzhiyun			gc0312_out: endpoint {
891*4882a593Smuzhiyun				remote-endpoint = <&dvp_in_fcam>;
892*4882a593Smuzhiyun			};
893*4882a593Smuzhiyun		};
894*4882a593Smuzhiyun	};
895*4882a593Smuzhiyun
896*4882a593Smuzhiyun	gc2145: gc2145@3c {
897*4882a593Smuzhiyun		status = "okay";
898*4882a593Smuzhiyun		compatible = "galaxycore,gc2145";
899*4882a593Smuzhiyun		reg = <0x3c>;
900*4882a593Smuzhiyun		clocks = <&cru SCLK_VIP_OUT>;
901*4882a593Smuzhiyun		clock-names = "xvclk";
902*4882a593Smuzhiyun
903*4882a593Smuzhiyun		avdd-supply = <&vcc2v8_dvp>;
904*4882a593Smuzhiyun		dovdd-supply = <&vcc1v8_dvp>;
905*4882a593Smuzhiyun		dvdd-supply = <&vdd1v5_dvp>;
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
908*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
909*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
910*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
911*4882a593Smuzhiyun		rockchip,camera-module-name = "CameraKing";
912*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan";
913*4882a593Smuzhiyun		port {
914*4882a593Smuzhiyun			gc2145_mipi_out: endpoint {
915*4882a593Smuzhiyun				remote-endpoint = <&mipi_in_bcam>;
916*4882a593Smuzhiyun				data-lanes = <1>;
917*4882a593Smuzhiyun			};
918*4882a593Smuzhiyun		};
919*4882a593Smuzhiyun	};
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun	ov8858: ov8858@36 {
922*4882a593Smuzhiyun		status = "disabled";
923*4882a593Smuzhiyun		compatible = "ovti,ov8858";
924*4882a593Smuzhiyun		reg = <0x36>;
925*4882a593Smuzhiyun		clocks = <&cru SCLK_VIP_OUT>;
926*4882a593Smuzhiyun		clock-names = "xvclk";
927*4882a593Smuzhiyun
928*4882a593Smuzhiyun		avdd-supply = <&vcc2v8_dvp>;
929*4882a593Smuzhiyun		dovdd-supply = <&vcc1v8_dvp>;
930*4882a593Smuzhiyun		dvdd-supply = <&vdd1v5_dvp>;
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
933*4882a593Smuzhiyun		reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
934*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
935*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
936*4882a593Smuzhiyun		rockchip,camera-module-name = "CameraKing";
937*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan-9569A2";
938*4882a593Smuzhiyun		port {
939*4882a593Smuzhiyun			ov8858_out: endpoint {
940*4882a593Smuzhiyun				remote-endpoint = <&mipi_in>;
941*4882a593Smuzhiyun				data-lanes = <1 2>;
942*4882a593Smuzhiyun			};
943*4882a593Smuzhiyun		};
944*4882a593Smuzhiyun	};
945*4882a593Smuzhiyun};
946*4882a593Smuzhiyun
947*4882a593Smuzhiyun&i2c4 {
948*4882a593Smuzhiyun	status = "okay";
949*4882a593Smuzhiyun
950*4882a593Smuzhiyun	sensor@26 {
951*4882a593Smuzhiyun		compatible = "gs_da223";
952*4882a593Smuzhiyun		reg = <0x26>;
953*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
954*4882a593Smuzhiyun		irq_enable = <0>;
955*4882a593Smuzhiyun		poll_delay_ms = <10>;
956*4882a593Smuzhiyun		layout = <3>;
957*4882a593Smuzhiyun	};
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun	sensor@19 {
960*4882a593Smuzhiyun		compatible = "gs_sc7a20";
961*4882a593Smuzhiyun		reg = <0x19>;
962*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
963*4882a593Smuzhiyun		irq_enable = <0>;
964*4882a593Smuzhiyun		poll_delay_ms = <10>;
965*4882a593Smuzhiyun		layout = <1>;
966*4882a593Smuzhiyun	};
967*4882a593Smuzhiyun
968*4882a593Smuzhiyun	mpu6500@68 {
969*4882a593Smuzhiyun		status = "disabled";
970*4882a593Smuzhiyun		compatible = "invensense,mpu6500";
971*4882a593Smuzhiyun		pinctrl-names = "default";
972*4882a593Smuzhiyun		pinctrl-0 = <&mpu6500_irq_gpio>;
973*4882a593Smuzhiyun		reg = <0x68>;
974*4882a593Smuzhiyun		irq-gpio = <&gpio3 14 IRQ_TYPE_EDGE_RISING>;
975*4882a593Smuzhiyun		mpu-int_config = <0x10>;
976*4882a593Smuzhiyun		mpu-level_shifter = <0>;
977*4882a593Smuzhiyun		mpu-orientation = <1 0 0 0 1 0 0 0 1>;
978*4882a593Smuzhiyun		orientation-x= <1>;
979*4882a593Smuzhiyun		orientation-y= <0>;
980*4882a593Smuzhiyun		orientation-z= <1>;
981*4882a593Smuzhiyun		support-hw-poweroff = <1>;
982*4882a593Smuzhiyun		mpu-debug = <1>;
983*4882a593Smuzhiyun	};
984*4882a593Smuzhiyun
985*4882a593Smuzhiyun	sensor@4c {
986*4882a593Smuzhiyun		status = "disabled";
987*4882a593Smuzhiyun		compatible = "gs_mc3230";
988*4882a593Smuzhiyun		reg = <0x4c>;
989*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
990*4882a593Smuzhiyun		irq_enable = <0>;
991*4882a593Smuzhiyun		poll_delay_ms = <30>;
992*4882a593Smuzhiyun		layout = <9>;
993*4882a593Smuzhiyun		reprobe_en = <1>;
994*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PB6 IRQ_TYPE_LEVEL_LOW>;
995*4882a593Smuzhiyun	};
996*4882a593Smuzhiyun
997*4882a593Smuzhiyun	sensor@18 {
998*4882a593Smuzhiyun		status = "gs_mc3230";
999*4882a593Smuzhiyun		compatible = "gs_sc7a30";
1000*4882a593Smuzhiyun		reg = <0x18>;
1001*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
1002*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PB6 IRQ_TYPE_LEVEL_LOW>;
1003*4882a593Smuzhiyun		irq_enable = <0>;
1004*4882a593Smuzhiyun		poll_delay_ms = <30>;
1005*4882a593Smuzhiyun		layout = <6>;
1006*4882a593Smuzhiyun		reprobe_en = <1>;
1007*4882a593Smuzhiyun	};
1008*4882a593Smuzhiyun
1009*4882a593Smuzhiyun	sensor@10 {
1010*4882a593Smuzhiyun		status = "gs_mc3230";
1011*4882a593Smuzhiyun		compatible = "light_cm3218";
1012*4882a593Smuzhiyun		pinctrl-names = "default";
1013*4882a593Smuzhiyun		pinctrl-0 = <&cm3218_irq_gpio>;
1014*4882a593Smuzhiyun		reg = <0x10>;
1015*4882a593Smuzhiyun		type = <SENSOR_TYPE_LIGHT>;
1016*4882a593Smuzhiyun		irq-gpio = <&gpio3 15 IRQ_TYPE_EDGE_FALLING>;
1017*4882a593Smuzhiyun		irq_enable = <1>;
1018*4882a593Smuzhiyun		poll_delay_ms = <30>;
1019*4882a593Smuzhiyun	};
1020*4882a593Smuzhiyun};
1021*4882a593Smuzhiyun
1022*4882a593Smuzhiyun&i2s_8ch {
1023*4882a593Smuzhiyun	status = "okay";
1024*4882a593Smuzhiyun	rockchip,i2s-broken-burst-len;
1025*4882a593Smuzhiyun	rockchip,playback-channels = <8>;
1026*4882a593Smuzhiyun	rockchip,capture-channels = <2>;
1027*4882a593Smuzhiyun	#sound-dai-cells = <0>;
1028*4882a593Smuzhiyun};
1029*4882a593Smuzhiyun
1030*4882a593Smuzhiyun&io_domains {
1031*4882a593Smuzhiyun	status = "okay";
1032*4882a593Smuzhiyun
1033*4882a593Smuzhiyun	dvp-supply = <&vcc1v8_dvp>;
1034*4882a593Smuzhiyun	audio-supply = <&vcc_io>;
1035*4882a593Smuzhiyun	gpio30-supply = <&vcc_io>;
1036*4882a593Smuzhiyun	gpio1830-supply = <&vcc_io>;
1037*4882a593Smuzhiyun	sdcard-supply = <&vccio_sd>;
1038*4882a593Smuzhiyun	wifi-supply = <&vcc_3v3>;
1039*4882a593Smuzhiyun};
1040*4882a593Smuzhiyun
1041*4882a593Smuzhiyun&isp_dvp_d2d9 {
1042*4882a593Smuzhiyun	rockchip,pins =
1043*4882a593Smuzhiyun			/* cif_data4 ... cif_data9 */
1044*4882a593Smuzhiyun			<1 RK_PA2 1 &pcfg_pull_down>,
1045*4882a593Smuzhiyun			<1 RK_PA3 1 &pcfg_pull_down>,
1046*4882a593Smuzhiyun			<1 RK_PA4 1 &pcfg_pull_down>,
1047*4882a593Smuzhiyun			<1 RK_PA5 1 &pcfg_pull_down>,
1048*4882a593Smuzhiyun			<1 RK_PA6 1 &pcfg_pull_down>,
1049*4882a593Smuzhiyun			<1 RK_PA7 1 &pcfg_pull_down>,
1050*4882a593Smuzhiyun			/* cif_sync, cif_href */
1051*4882a593Smuzhiyun			<1 RK_PB0 1 &pcfg_pull_down>,
1052*4882a593Smuzhiyun			<1 RK_PB1 1 &pcfg_pull_down>,
1053*4882a593Smuzhiyun			/* cif_clkin */
1054*4882a593Smuzhiyun			<1 RK_PB2 1 &pcfg_pull_down>;
1055*4882a593Smuzhiyun};
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun&isp_dvp_d10d11 {
1058*4882a593Smuzhiyun	rockchip,pins =
1059*4882a593Smuzhiyun			/* cif_data10, cif_data11 */
1060*4882a593Smuzhiyun			<1 RK_PB6 1 &pcfg_pull_down>,
1061*4882a593Smuzhiyun			<1 RK_PB7 1 &pcfg_pull_down>;
1062*4882a593Smuzhiyun};
1063*4882a593Smuzhiyun
1064*4882a593Smuzhiyun&isp_mmu {
1065*4882a593Smuzhiyun	status = "okay";
1066*4882a593Smuzhiyun};
1067*4882a593Smuzhiyun
1068*4882a593Smuzhiyun&mipi_dphy_rx0 {
1069*4882a593Smuzhiyun	status = "okay";
1070*4882a593Smuzhiyun
1071*4882a593Smuzhiyun	ports {
1072*4882a593Smuzhiyun		#address-cells = <1>;
1073*4882a593Smuzhiyun		#size-cells = <0>;
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun		port@0 {
1076*4882a593Smuzhiyun			reg = <0>;
1077*4882a593Smuzhiyun			#address-cells = <1>;
1078*4882a593Smuzhiyun			#size-cells = <0>;
1079*4882a593Smuzhiyun			mipi_in_bcam: endpoint@0 {
1080*4882a593Smuzhiyun				reg = <0>;
1081*4882a593Smuzhiyun				remote-endpoint = <&gc2145_mipi_out>;
1082*4882a593Smuzhiyun				data-lanes = <1>;
1083*4882a593Smuzhiyun			};
1084*4882a593Smuzhiyun
1085*4882a593Smuzhiyun			mipi_in: endpoint@1 {
1086*4882a593Smuzhiyun				reg = <1>;
1087*4882a593Smuzhiyun				remote-endpoint = <&ov8858_out>;
1088*4882a593Smuzhiyun				data-lanes = <1 2>;
1089*4882a593Smuzhiyun			};
1090*4882a593Smuzhiyun		};
1091*4882a593Smuzhiyun
1092*4882a593Smuzhiyun		port@1 {
1093*4882a593Smuzhiyun			reg = <1>;
1094*4882a593Smuzhiyun			#address-cells = <1>;
1095*4882a593Smuzhiyun			#size-cells = <0>;
1096*4882a593Smuzhiyun
1097*4882a593Smuzhiyun			dphy_rx_out: endpoint@0 {
1098*4882a593Smuzhiyun				reg = <0>;
1099*4882a593Smuzhiyun				remote-endpoint = <&isp_mipi_in>;
1100*4882a593Smuzhiyun			};
1101*4882a593Smuzhiyun		};
1102*4882a593Smuzhiyun	};
1103*4882a593Smuzhiyun};
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun&nandc0 {
1106*4882a593Smuzhiyun	status = "okay";
1107*4882a593Smuzhiyun};
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun&pmu_io_domains {
1110*4882a593Smuzhiyun	status = "okay";
1111*4882a593Smuzhiyun
1112*4882a593Smuzhiyun	pmu-supply = <&vcc3v3_pmu>;
1113*4882a593Smuzhiyun	vop-supply = <&vcc3v3_pmu>;
1114*4882a593Smuzhiyun};
1115*4882a593Smuzhiyun
1116*4882a593Smuzhiyun&pwm0 {
1117*4882a593Smuzhiyun	status = "okay";
1118*4882a593Smuzhiyun};
1119*4882a593Smuzhiyun
1120*4882a593Smuzhiyun&pinctrl {
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun	headphone {
1123*4882a593Smuzhiyun		hp_det: hp-det {
1124*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
1125*4882a593Smuzhiyun		};
1126*4882a593Smuzhiyun	};
1127*4882a593Smuzhiyun
1128*4882a593Smuzhiyun	pmic {
1129*4882a593Smuzhiyun		pmic_int: pmic_int {
1130*4882a593Smuzhiyun			rockchip,pins =
1131*4882a593Smuzhiyun				<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
1132*4882a593Smuzhiyun		};
1133*4882a593Smuzhiyun
1134*4882a593Smuzhiyun		soc_slppin_gpio: soc_slppin_gpio {
1135*4882a593Smuzhiyun			rockchip,pins =
1136*4882a593Smuzhiyun				<0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>;
1137*4882a593Smuzhiyun		};
1138*4882a593Smuzhiyun
1139*4882a593Smuzhiyun		soc_slppin_slp: soc_slppin_slp {
1140*4882a593Smuzhiyun			rockchip,pins =
1141*4882a593Smuzhiyun				<0 RK_PA0 1 &pcfg_pull_none>;
1142*4882a593Smuzhiyun		};
1143*4882a593Smuzhiyun
1144*4882a593Smuzhiyun		soc_slppin_rst: soc_slppin_rst {
1145*4882a593Smuzhiyun			rockchip,pins =
1146*4882a593Smuzhiyun				<0 RK_PA0 2 &pcfg_pull_none>;
1147*4882a593Smuzhiyun		};
1148*4882a593Smuzhiyun
1149*4882a593Smuzhiyun		vsel_gpio: vsel-gpio {
1150*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
1151*4882a593Smuzhiyun		};
1152*4882a593Smuzhiyun	};
1153*4882a593Smuzhiyun
1154*4882a593Smuzhiyun	mpu6500 {
1155*4882a593Smuzhiyun		mpu6500_irq_gpio: mpu6500-irq-gpio {
1156*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
1157*4882a593Smuzhiyun		};
1158*4882a593Smuzhiyun	};
1159*4882a593Smuzhiyun
1160*4882a593Smuzhiyun	cm3218 {
1161*4882a593Smuzhiyun		cm3218_irq_gpio: cm3218-irq-gpio {
1162*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
1163*4882a593Smuzhiyun		};
1164*4882a593Smuzhiyun	};
1165*4882a593Smuzhiyun
1166*4882a593Smuzhiyun	dc_det {
1167*4882a593Smuzhiyun		dc_irq_gpio: dc-irq-gpio {
1168*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
1169*4882a593Smuzhiyun		};
1170*4882a593Smuzhiyun	};
1171*4882a593Smuzhiyun
1172*4882a593Smuzhiyun	pcfg_pull_none_4ma: pcfg-pull-none-4ma {
1173*4882a593Smuzhiyun		bias-disable;
1174*4882a593Smuzhiyun		drive-strength = <4>;
1175*4882a593Smuzhiyun	};
1176*4882a593Smuzhiyun
1177*4882a593Smuzhiyun	pcfg_pull_none_smt: pcfg-pull-none-smt {
1178*4882a593Smuzhiyun		bias-disable;
1179*4882a593Smuzhiyun		input-schmitt-enable;
1180*4882a593Smuzhiyun	};
1181*4882a593Smuzhiyun
1182*4882a593Smuzhiyun	pcfg_output_high: pcfg-output-high {
1183*4882a593Smuzhiyun		output-high;
1184*4882a593Smuzhiyun	};
1185*4882a593Smuzhiyun
1186*4882a593Smuzhiyun	pcfg_output_low: pcfg-output-low {
1187*4882a593Smuzhiyun		output-low;
1188*4882a593Smuzhiyun	};
1189*4882a593Smuzhiyun
1190*4882a593Smuzhiyun	pcfg_input_high: pcfg-input-high {
1191*4882a593Smuzhiyun		bias-pull-up;
1192*4882a593Smuzhiyun		input-enable;
1193*4882a593Smuzhiyun	};
1194*4882a593Smuzhiyun
1195*4882a593Smuzhiyun	pcfg_input: pcfg-input {
1196*4882a593Smuzhiyun		input-enable;
1197*4882a593Smuzhiyun	};
1198*4882a593Smuzhiyun
1199*4882a593Smuzhiyun	sdio-pwrseq {
1200*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
1201*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
1202*4882a593Smuzhiyun		};
1203*4882a593Smuzhiyun	};
1204*4882a593Smuzhiyun
1205*4882a593Smuzhiyun	usb2 {
1206*4882a593Smuzhiyun		host_vbus_drv: host-vbus-drv {
1207*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
1208*4882a593Smuzhiyun		};
1209*4882a593Smuzhiyun	};
1210*4882a593Smuzhiyun
1211*4882a593Smuzhiyun	wireless-bluetooth {
1212*4882a593Smuzhiyun		uart0_rts_gpio: uart0-rts-gpio {
1213*4882a593Smuzhiyun			rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
1214*4882a593Smuzhiyun		};
1215*4882a593Smuzhiyun	};
1216*4882a593Smuzhiyun};
1217*4882a593Smuzhiyun
1218*4882a593Smuzhiyun&rkisp1 {
1219*4882a593Smuzhiyun	status = "okay";
1220*4882a593Smuzhiyun	pinctrl-names = "default";
1221*4882a593Smuzhiyun	pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d10d11 &cif_clkout>;
1222*4882a593Smuzhiyun	port {
1223*4882a593Smuzhiyun		#address-cells = <1>;
1224*4882a593Smuzhiyun		#size-cells = <0>;
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun		dvp_in_fcam: endpoint@0 {
1227*4882a593Smuzhiyun			reg = <0>;
1228*4882a593Smuzhiyun			remote-endpoint = <&gc0312_out>;
1229*4882a593Smuzhiyun		};
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun		isp_mipi_in: endpoint@1 {
1232*4882a593Smuzhiyun			reg = <1>;
1233*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx_out>;
1234*4882a593Smuzhiyun		};
1235*4882a593Smuzhiyun	};
1236*4882a593Smuzhiyun};
1237*4882a593Smuzhiyun
1238*4882a593Smuzhiyun&route_dsi {
1239*4882a593Smuzhiyun	status = "okay";
1240*4882a593Smuzhiyun};
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun&rockchip_suspend {
1243*4882a593Smuzhiyun	status = "okay";
1244*4882a593Smuzhiyun	Rockchip,sleep-debug-en = <1>;
1245*4882a593Smuzhiyun	rockchip,sleep-mode-config = <
1246*4882a593Smuzhiyun		(0
1247*4882a593Smuzhiyun		| RKPM_SLP_ARMOFF
1248*4882a593Smuzhiyun		| RKPM_SLP_PMU_PLLS_PWRDN
1249*4882a593Smuzhiyun		| RKPM_SLP_PMU_PMUALIVE_32K
1250*4882a593Smuzhiyun		| RKPM_SLP_SFT_PLLS_DEEP
1251*4882a593Smuzhiyun		| RKPM_SLP_PMU_DIS_OSC
1252*4882a593Smuzhiyun		| RKPM_SLP_SFT_PD_NBSCUS
1253*4882a593Smuzhiyun		)
1254*4882a593Smuzhiyun	>;
1255*4882a593Smuzhiyun	rockchip,wakeup-config = <
1256*4882a593Smuzhiyun		(0
1257*4882a593Smuzhiyun		| RKPM_GPIO_WKUP_EN
1258*4882a593Smuzhiyun		| RKPM_USB_WKUP_EN
1259*4882a593Smuzhiyun		| RKPM_CLUSTER_L_WKUP_EN
1260*4882a593Smuzhiyun		)
1261*4882a593Smuzhiyun	>;
1262*4882a593Smuzhiyun};
1263*4882a593Smuzhiyun
1264*4882a593Smuzhiyun&saradc {
1265*4882a593Smuzhiyun	status = "okay";
1266*4882a593Smuzhiyun};
1267*4882a593Smuzhiyun
1268*4882a593Smuzhiyun&sdmmc {
1269*4882a593Smuzhiyun	clock-frequency = <37500000>;
1270*4882a593Smuzhiyun	clock-freq-min-max = <400000 37500000>;
1271*4882a593Smuzhiyun	no-sdio;
1272*4882a593Smuzhiyun	no-mmc;
1273*4882a593Smuzhiyun	cap-mmc-highspeed;
1274*4882a593Smuzhiyun	cap-sd-highspeed;
1275*4882a593Smuzhiyun	card-detect-delay = <200>;
1276*4882a593Smuzhiyun	disable-wp;
1277*4882a593Smuzhiyun	num-slots = <1>;
1278*4882a593Smuzhiyun	vmmc-supply = <&vcc_sd>;
1279*4882a593Smuzhiyun	pinctrl-names = "default";
1280*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
1281*4882a593Smuzhiyun	status = "disabled";
1282*4882a593Smuzhiyun};
1283*4882a593Smuzhiyun
1284*4882a593Smuzhiyun&sdio0 {
1285*4882a593Smuzhiyun	max-frequency = <50000000>;
1286*4882a593Smuzhiyun	no-sd;
1287*4882a593Smuzhiyun	no-mmc;
1288*4882a593Smuzhiyun	bus-width = <4>;
1289*4882a593Smuzhiyun	disable-wp;
1290*4882a593Smuzhiyun	cap-sd-highspeed;
1291*4882a593Smuzhiyun	cap-sdio-irq;
1292*4882a593Smuzhiyun	keep-power-in-suspend;
1293*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
1294*4882a593Smuzhiyun	non-removable;
1295*4882a593Smuzhiyun	num-slots = <1>;
1296*4882a593Smuzhiyun	pinctrl-names = "default";
1297*4882a593Smuzhiyun	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
1298*4882a593Smuzhiyun	rockchip,default-sample-phase = <90>;
1299*4882a593Smuzhiyun	status = "okay";
1300*4882a593Smuzhiyun};
1301*4882a593Smuzhiyun
1302*4882a593Smuzhiyun&tsadc {
1303*4882a593Smuzhiyun	tsadc-supply = <&vdd_cpu>;
1304*4882a593Smuzhiyun	status = "okay";
1305*4882a593Smuzhiyun};
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun&uart0 {
1308*4882a593Smuzhiyun	pinctrl-names = "default";
1309*4882a593Smuzhiyun	pinctrl-0 = <&uart0_xfer &uart0_cts>;
1310*4882a593Smuzhiyun	status = "okay";
1311*4882a593Smuzhiyun};
1312*4882a593Smuzhiyun
1313*4882a593Smuzhiyun&u2phy {
1314*4882a593Smuzhiyun	status = "okay";
1315*4882a593Smuzhiyun
1316*4882a593Smuzhiyun	u2phy_otg: otg-port {
1317*4882a593Smuzhiyun		status = "okay";
1318*4882a593Smuzhiyun	};
1319*4882a593Smuzhiyun
1320*4882a593Smuzhiyun	u2phy_host: host-port {
1321*4882a593Smuzhiyun		phy-supply = <&vcc_host>;
1322*4882a593Smuzhiyun		status = "okay";
1323*4882a593Smuzhiyun	};
1324*4882a593Smuzhiyun};
1325*4882a593Smuzhiyun
1326*4882a593Smuzhiyun&usb_host0_ehci {
1327*4882a593Smuzhiyun	status = "okay";
1328*4882a593Smuzhiyun};
1329*4882a593Smuzhiyun
1330*4882a593Smuzhiyun&usb_host0_ohci {
1331*4882a593Smuzhiyun	status = "okay";
1332*4882a593Smuzhiyun};
1333*4882a593Smuzhiyun
1334