1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2020 Rockchip Electronics Co., Ltd. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h> 9*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 10*4882a593Smuzhiyun#include "rk3368.dtsi" 11*4882a593Smuzhiyun#include "rk3368-android.dtsi" 12*4882a593Smuzhiyun/ { 13*4882a593Smuzhiyun model = "Rockchip rk3368a tablet rk817 board"; 14*4882a593Smuzhiyun compatible = "rockchip,tablet", "rockchip,rk3368a", "rockchip,rk3368"; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun adc_keys: adc-keys { 17*4882a593Smuzhiyun compatible = "adc-keys"; 18*4882a593Smuzhiyun io-channels = <&saradc 1>; 19*4882a593Smuzhiyun io-channel-names = "buttons"; 20*4882a593Smuzhiyun keyup-threshold-microvolt = <1024000>; 21*4882a593Smuzhiyun poll-interval = <100>; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun vol-up-key { 24*4882a593Smuzhiyun label = "volume up"; 25*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 26*4882a593Smuzhiyun press-threshold-microvolt = <1000>; 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun vol-down-key { 30*4882a593Smuzhiyun label = "volume down"; 31*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 32*4882a593Smuzhiyun press-threshold-microvolt = <170000>; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun backlight: backlight { 37*4882a593Smuzhiyun compatible = "pwm-backlight"; 38*4882a593Smuzhiyun pwms = <&pwm0 0 25000 1>; 39*4882a593Smuzhiyun brightness-levels = < 40*4882a593Smuzhiyun 10 10 10 11 12 13 14 15 41*4882a593Smuzhiyun 16 16 16 16 16 16 16 16 42*4882a593Smuzhiyun 17 17 17 17 17 17 17 17 43*4882a593Smuzhiyun 18 18 18 18 18 18 18 18 44*4882a593Smuzhiyun 19 19 19 19 19 19 19 19 45*4882a593Smuzhiyun 20 20 20 20 20 20 20 20 46*4882a593Smuzhiyun 21 21 21 21 21 21 21 21 47*4882a593Smuzhiyun 22 22 22 22 22 22 22 22 48*4882a593Smuzhiyun 23 23 23 23 23 23 23 23 49*4882a593Smuzhiyun 24 24 24 24 24 24 24 24 50*4882a593Smuzhiyun 25 25 25 25 25 25 25 25 51*4882a593Smuzhiyun 26 26 26 26 26 26 26 26 52*4882a593Smuzhiyun 27 27 27 27 27 27 27 27 53*4882a593Smuzhiyun 28 28 28 28 28 28 28 28 54*4882a593Smuzhiyun 27 27 27 27 27 27 27 27 55*4882a593Smuzhiyun 30 30 30 30 30 30 30 30 56*4882a593Smuzhiyun 31 31 31 31 31 31 31 31 57*4882a593Smuzhiyun 32 32 32 32 32 32 32 32 58*4882a593Smuzhiyun 33 33 33 33 33 33 33 33 59*4882a593Smuzhiyun 34 34 34 34 34 34 34 34 60*4882a593Smuzhiyun 35 35 35 35 35 35 35 35 61*4882a593Smuzhiyun 36 36 36 36 36 36 36 36 62*4882a593Smuzhiyun 37 37 37 37 37 37 37 37 63*4882a593Smuzhiyun 38 38 38 38 38 38 38 38 64*4882a593Smuzhiyun 38 38 38 38 38 38 38 38 65*4882a593Smuzhiyun 38 38 38 38 38 38 38 38 66*4882a593Smuzhiyun 38 38 38 38 38 38 38 38 67*4882a593Smuzhiyun 38 38 38 38 38 38 38 38 68*4882a593Smuzhiyun 38 38 38 38 38 38 38 38 69*4882a593Smuzhiyun 38 38 38 38 38 38 38 38 70*4882a593Smuzhiyun 38 38 38 38 38 38 38 38>; 71*4882a593Smuzhiyun default-brightness-level = <200>; 72*4882a593Smuzhiyun enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun charge-animation { 76*4882a593Smuzhiyun compatible = "rockchip,uboot-charge"; 77*4882a593Smuzhiyun rockchip,uboot-charge-on = <1>; 78*4882a593Smuzhiyun rockchip,android-charge-on = <0>; 79*4882a593Smuzhiyun rockchip,uboot-low-power-voltage = <3500>; 80*4882a593Smuzhiyun rockchip,screen-on-voltage = <3600>; 81*4882a593Smuzhiyun status = "okay"; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun chosen: chosen { 85*4882a593Smuzhiyun bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0"; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun rk817-sound { 89*4882a593Smuzhiyun compatible = "simple-audio-card"; 90*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 91*4882a593Smuzhiyun simple-audio-card,name = "rockchip-rk817-codec"; 92*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 93*4882a593Smuzhiyun simple-audio-card,widgets = 94*4882a593Smuzhiyun "Microphone", "Mic Jack", 95*4882a593Smuzhiyun "Headphone", "Headphone Jack"; 96*4882a593Smuzhiyun simple-audio-card,routing = 97*4882a593Smuzhiyun "Mic Jack", "MICBIAS1", 98*4882a593Smuzhiyun "IN1P", "Mic Jack", 99*4882a593Smuzhiyun "Headphone Jack", "HPOL", 100*4882a593Smuzhiyun "Headphone Jack", "HPOR"; 101*4882a593Smuzhiyun simple-audio-card,cpu { 102*4882a593Smuzhiyun sound-dai = <&i2s_8ch>; 103*4882a593Smuzhiyun }; 104*4882a593Smuzhiyun simple-audio-card,codec { 105*4882a593Smuzhiyun sound-dai = <&rk817_codec>; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun rk_headset: rk-headset { 110*4882a593Smuzhiyun compatible = "rockchip_headset"; 111*4882a593Smuzhiyun headset_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>; 112*4882a593Smuzhiyun pinctrl-names = "default"; 113*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 114*4882a593Smuzhiyun io-channels = <&saradc 2>; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 118*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 119*4882a593Smuzhiyun pinctrl-names = "default"; 120*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* 123*4882a593Smuzhiyun * On the module itself this is one of these (depending 124*4882a593Smuzhiyun * on the actual card populated): 125*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 126*4882a593Smuzhiyun * - PDN (power down when low) 127*4882a593Smuzhiyun */ 128*4882a593Smuzhiyun reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun vccsys: vccsys { 132*4882a593Smuzhiyun compatible = "regulator-fixed"; 133*4882a593Smuzhiyun regulator-name = "vcc3v8_sys"; 134*4882a593Smuzhiyun regulator-always-on; 135*4882a593Smuzhiyun regulator-boot-on; 136*4882a593Smuzhiyun regulator-min-microvolt = <3800000>; 137*4882a593Smuzhiyun regulator-max-microvolt = <3800000>; 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun wireless-wlan { 141*4882a593Smuzhiyun compatible = "wlan-platdata"; 142*4882a593Smuzhiyun /* wifi_chip_type - wifi chip define 143*4882a593Smuzhiyun * ap6210, ap6330, ap6335 144*4882a593Smuzhiyun * rtl8188eu, rtl8723bs, rtl8723bu 145*4882a593Smuzhiyun * esp8089 146*4882a593Smuzhiyun */ 147*4882a593Smuzhiyun wifi_chip_type = "ap6255"; 148*4882a593Smuzhiyun WIFI,vbat_gpio = <&gpio0 2 GPIO_ACTIVE_HIGH>; 149*4882a593Smuzhiyun WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>; 150*4882a593Smuzhiyun status = "okay"; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun wireless-bluetooth { 154*4882a593Smuzhiyun compatible = "bluetooth-platdata"; 155*4882a593Smuzhiyun uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; 156*4882a593Smuzhiyun pinctrl-names = "default","rts_gpio"; 157*4882a593Smuzhiyun pinctrl-0 = <&uart0_rts>; 158*4882a593Smuzhiyun pinctrl-1 = <&uart0_rts_gpio>; 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun //BT,power_gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; 161*4882a593Smuzhiyun BT,reset_gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; 162*4882a593Smuzhiyun BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>; 163*4882a593Smuzhiyun BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun status = "okay"; 166*4882a593Smuzhiyun }; 167*4882a593Smuzhiyun 168*4882a593Smuzhiyun vcc_sys: vcc-sys { 169*4882a593Smuzhiyun compatible = "regulator-fixed"; 170*4882a593Smuzhiyun regulator-name = "vcc_sys"; 171*4882a593Smuzhiyun regulator-always-on; 172*4882a593Smuzhiyun regulator-boot-on; 173*4882a593Smuzhiyun regulator-min-microvolt = <3800000>; 174*4882a593Smuzhiyun regulator-max-microvolt = <3800000>; 175*4882a593Smuzhiyun }; 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun vcc_host: vcc-host { 178*4882a593Smuzhiyun compatible = "regulator-fixed"; 179*4882a593Smuzhiyun enable-active-high; 180*4882a593Smuzhiyun gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>; 181*4882a593Smuzhiyun pinctrl-names = "default"; 182*4882a593Smuzhiyun pinctrl-0 = <&host_vbus_drv>; 183*4882a593Smuzhiyun regulator-name = "vcc_host"; 184*4882a593Smuzhiyun regulator-always-on; 185*4882a593Smuzhiyun }; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun xin32k: xin32k { 188*4882a593Smuzhiyun compatible = "fixed-clock"; 189*4882a593Smuzhiyun clock-frequency = <32768>; 190*4882a593Smuzhiyun clock-output-names = "xin32k"; 191*4882a593Smuzhiyun #clock-cells = <0>; 192*4882a593Smuzhiyun }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&cif_clkout { 197*4882a593Smuzhiyun /* cif_clkout */ 198*4882a593Smuzhiyun rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none_4ma>; 199*4882a593Smuzhiyun}; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun&cpu_l0 { 202*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 203*4882a593Smuzhiyun}; 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun&cpu_l1 { 206*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 207*4882a593Smuzhiyun}; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun&cpu_l2 { 210*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 211*4882a593Smuzhiyun}; 212*4882a593Smuzhiyun 213*4882a593Smuzhiyun&cpu_l3 { 214*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 215*4882a593Smuzhiyun}; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun&cpu_b0 { 218*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 219*4882a593Smuzhiyun}; 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun&cpu_b1 { 222*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 223*4882a593Smuzhiyun}; 224*4882a593Smuzhiyun 225*4882a593Smuzhiyun&cpu_b2 { 226*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 227*4882a593Smuzhiyun}; 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun&cpu_b3 { 230*4882a593Smuzhiyun cpu-supply = <&vdd_cpu>; 231*4882a593Smuzhiyun}; 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun&gpu { 234*4882a593Smuzhiyun logic-supply = <&vdd_logic>; 235*4882a593Smuzhiyun}; 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun&dfi { 238*4882a593Smuzhiyun status = "okay"; 239*4882a593Smuzhiyun}; 240*4882a593Smuzhiyun 241*4882a593Smuzhiyun&dmc { 242*4882a593Smuzhiyun status = "okay"; 243*4882a593Smuzhiyun center-supply = <&vdd_logic>; 244*4882a593Smuzhiyun devfreq-events = <&dfi>; 245*4882a593Smuzhiyun upthreshold = <60>; 246*4882a593Smuzhiyun downdifferential = <20>; 247*4882a593Smuzhiyun system-status-freq = < 248*4882a593Smuzhiyun /*system status freq(KHz)*/ 249*4882a593Smuzhiyun SYS_STATUS_NORMAL 600000 250*4882a593Smuzhiyun SYS_STATUS_REBOOT 600000 251*4882a593Smuzhiyun SYS_STATUS_SUSPEND 240000 252*4882a593Smuzhiyun SYS_STATUS_VIDEO_1080P 396000 253*4882a593Smuzhiyun SYS_STATUS_VIDEO_4K 600000 254*4882a593Smuzhiyun SYS_STATUS_PERFORMANCE 600000 255*4882a593Smuzhiyun SYS_STATUS_BOOST 396000 256*4882a593Smuzhiyun SYS_STATUS_DUALVIEW 600000 257*4882a593Smuzhiyun SYS_STATUS_ISP 528000 258*4882a593Smuzhiyun >; 259*4882a593Smuzhiyun vop-bw-dmc-freq = < 260*4882a593Smuzhiyun /* min_bw(MB/s) max_bw(MB/s) freq(KHz) */ 261*4882a593Smuzhiyun 0 582 240000 262*4882a593Smuzhiyun 583 99999 396000 263*4882a593Smuzhiyun >; 264*4882a593Smuzhiyun vop-dclk-mode = <1>; 265*4882a593Smuzhiyun auto-min-freq = <240000>; 266*4882a593Smuzhiyun auto-freq-en = <0>; 267*4882a593Smuzhiyun}; 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun&dsi { 270*4882a593Smuzhiyun status = "okay"; 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun panel@0 { 273*4882a593Smuzhiyun compatible = "simple-panel-dsi"; 274*4882a593Smuzhiyun reg = <0>; 275*4882a593Smuzhiyun backlight = <&backlight>; 276*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>; 277*4882a593Smuzhiyun /* back-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_HIGH>; */ 278*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>; 279*4882a593Smuzhiyun prepare-delay-ms = <8>; 280*4882a593Smuzhiyun enable-delay-ms = <3>; 281*4882a593Smuzhiyun reset-delay-ms = <50>; 282*4882a593Smuzhiyun init-delay-ms = <20>; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 285*4882a593Smuzhiyun MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>; 286*4882a593Smuzhiyun dsi,format = <MIPI_DSI_FMT_RGB888>; 287*4882a593Smuzhiyun dsi,lanes = <4>; 288*4882a593Smuzhiyun width-mm = <153>; 289*4882a593Smuzhiyun height-mm = <85>; 290*4882a593Smuzhiyun panel-init-sequence = [ 291*4882a593Smuzhiyun 05 1e 01 01 292*4882a593Smuzhiyun 15 00 02 80 47 293*4882a593Smuzhiyun 15 00 02 81 40 294*4882a593Smuzhiyun 15 00 02 82 04 295*4882a593Smuzhiyun 15 00 02 83 77 296*4882a593Smuzhiyun 15 00 02 84 0f 297*4882a593Smuzhiyun 15 00 02 85 70 298*4882a593Smuzhiyun 15 78 02 86 70 299*4882a593Smuzhiyun ]; 300*4882a593Smuzhiyun panel-exit-sequence = [ 301*4882a593Smuzhiyun 05 00 01 28 302*4882a593Smuzhiyun 05 00 01 10 303*4882a593Smuzhiyun ]; 304*4882a593Smuzhiyun 305*4882a593Smuzhiyun display-timings { 306*4882a593Smuzhiyun native-mode = <&timing0>; 307*4882a593Smuzhiyun 308*4882a593Smuzhiyun timing0: timing0 { 309*4882a593Smuzhiyun clock-frequency = <49500000>; 310*4882a593Smuzhiyun hactive = <1024>; 311*4882a593Smuzhiyun vactive = <600>; 312*4882a593Smuzhiyun hback-porch = <120>; 313*4882a593Smuzhiyun hfront-porch = <80>; 314*4882a593Smuzhiyun vback-porch = <14>; 315*4882a593Smuzhiyun vfront-porch = <14>; 316*4882a593Smuzhiyun hsync-len = <40>; 317*4882a593Smuzhiyun vsync-len = <4>; 318*4882a593Smuzhiyun hsync-active = <0>; 319*4882a593Smuzhiyun vsync-active = <0>; 320*4882a593Smuzhiyun de-active = <0>; 321*4882a593Smuzhiyun pixelclk-active = <0>; 322*4882a593Smuzhiyun }; 323*4882a593Smuzhiyun }; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun}; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun&emmc { 328*4882a593Smuzhiyun bus-width = <8>; 329*4882a593Smuzhiyun cap-mmc-highspeed; 330*4882a593Smuzhiyun mmc-hs200-1_8v; 331*4882a593Smuzhiyun no-sdio; 332*4882a593Smuzhiyun no-sd; 333*4882a593Smuzhiyun disable-wp; 334*4882a593Smuzhiyun non-removable; 335*4882a593Smuzhiyun num-slots = <1>; 336*4882a593Smuzhiyun status = "okay"; 337*4882a593Smuzhiyun}; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun&i2c0 { 340*4882a593Smuzhiyun status = "okay"; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun vdd_cpu: tcs4526@10 { 343*4882a593Smuzhiyun compatible = "tcs,tcs4526"; 344*4882a593Smuzhiyun reg = <0x10>; 345*4882a593Smuzhiyun regulator-compatible = "fan53555-reg"; 346*4882a593Smuzhiyun pinctrl-0 = <&vsel_gpio>; 347*4882a593Smuzhiyun vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>; 348*4882a593Smuzhiyun regulator-name = "vdd_cpu"; 349*4882a593Smuzhiyun regulator-min-microvolt = <712500>; 350*4882a593Smuzhiyun regulator-max-microvolt = <1390000>; 351*4882a593Smuzhiyun regulator-ramp-delay = <2300>; 352*4882a593Smuzhiyun fcs,suspend-voltage-selector = <1>; 353*4882a593Smuzhiyun regulator-boot-on; 354*4882a593Smuzhiyun regulator-always-on; 355*4882a593Smuzhiyun regulator-state-mem { 356*4882a593Smuzhiyun regulator-off-in-suspend; 357*4882a593Smuzhiyun }; 358*4882a593Smuzhiyun }; 359*4882a593Smuzhiyun rk817: pmic@20 { 360*4882a593Smuzhiyun compatible = "rockchip,rk817"; 361*4882a593Smuzhiyun reg = <0x20>; 362*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 363*4882a593Smuzhiyun interrupts = <1 IRQ_TYPE_LEVEL_LOW>; 364*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 365*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 366*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 367*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 368*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 369*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 370*4882a593Smuzhiyun rockchip,system-power-controller; 371*4882a593Smuzhiyun wakeup-source; 372*4882a593Smuzhiyun #clock-cells = <1>; 373*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 374*4882a593Smuzhiyun //fb-inner-reg-idxs = <2>; 375*4882a593Smuzhiyun /* 1: rst regs (default in codes), 0: rst the pmic */ 376*4882a593Smuzhiyun pmic-reset-func = <1>; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun vcc1-supply = <&vccsys>; 379*4882a593Smuzhiyun vcc2-supply = <&vccsys>; 380*4882a593Smuzhiyun vcc3-supply = <&vccsys>; 381*4882a593Smuzhiyun vcc4-supply = <&vccsys>; 382*4882a593Smuzhiyun vcc5-supply = <&vccsys>; 383*4882a593Smuzhiyun vcc6-supply = <&vccsys>; 384*4882a593Smuzhiyun vcc7-supply = <&vcc_io>; 385*4882a593Smuzhiyun vcc8-supply = <&vccsys>; 386*4882a593Smuzhiyun vcc9-supply = <&dcdc_boost>; 387*4882a593Smuzhiyun 388*4882a593Smuzhiyun pwrkey { 389*4882a593Smuzhiyun status = "okay"; 390*4882a593Smuzhiyun }; 391*4882a593Smuzhiyun 392*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 393*4882a593Smuzhiyun gpio-controller; 394*4882a593Smuzhiyun #gpio-cells = <2>; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun rk817_ts_gpio1: rk817_ts_gpio1 { 397*4882a593Smuzhiyun pins = "gpio_ts"; 398*4882a593Smuzhiyun function = "pin_fun1"; 399*4882a593Smuzhiyun /* output-low; */ 400*4882a593Smuzhiyun /* input-enable; */ 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun rk817_gt_gpio2: rk817_gt_gpio2 { 404*4882a593Smuzhiyun pins = "gpio_gt"; 405*4882a593Smuzhiyun function = "pin_fun1"; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun rk817_pin_ts: rk817_pin_ts { 409*4882a593Smuzhiyun pins = "gpio_ts"; 410*4882a593Smuzhiyun function = "pin_fun0"; 411*4882a593Smuzhiyun }; 412*4882a593Smuzhiyun 413*4882a593Smuzhiyun rk817_pin_gt: rk817_pin_gt { 414*4882a593Smuzhiyun pins = "gpio_gt"; 415*4882a593Smuzhiyun function = "pin_fun0"; 416*4882a593Smuzhiyun }; 417*4882a593Smuzhiyun 418*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 419*4882a593Smuzhiyun pins = "gpio_slp"; 420*4882a593Smuzhiyun function = "pin_fun0"; 421*4882a593Smuzhiyun }; 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 424*4882a593Smuzhiyun pins = "gpio_slp"; 425*4882a593Smuzhiyun function = "pin_fun1"; 426*4882a593Smuzhiyun }; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 429*4882a593Smuzhiyun pins = "gpio_slp"; 430*4882a593Smuzhiyun function = "pin_fun2"; 431*4882a593Smuzhiyun }; 432*4882a593Smuzhiyun 433*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 434*4882a593Smuzhiyun pins = "gpio_slp"; 435*4882a593Smuzhiyun function = "pin_fun3"; 436*4882a593Smuzhiyun }; 437*4882a593Smuzhiyun }; 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun regulators { 440*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 441*4882a593Smuzhiyun regulator-always-on; 442*4882a593Smuzhiyun regulator-boot-on; 443*4882a593Smuzhiyun regulator-min-microvolt = <950000>; 444*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 445*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 446*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 447*4882a593Smuzhiyun regulator-name = "vdd_logic"; 448*4882a593Smuzhiyun regulator-state-mem { 449*4882a593Smuzhiyun regulator-on-in-suspend; 450*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 451*4882a593Smuzhiyun }; 452*4882a593Smuzhiyun }; 453*4882a593Smuzhiyun 454*4882a593Smuzhiyun vcc_3v3: DCDC_REG2 { 455*4882a593Smuzhiyun regulator-name = "vcc_3v3"; 456*4882a593Smuzhiyun regulator-always-on; 457*4882a593Smuzhiyun regulator-boot-on; 458*4882a593Smuzhiyun regulator-state-mem { 459*4882a593Smuzhiyun regulator-on-in-suspend; 460*4882a593Smuzhiyun }; 461*4882a593Smuzhiyun }; 462*4882a593Smuzhiyun 463*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 464*4882a593Smuzhiyun regulator-always-on; 465*4882a593Smuzhiyun regulator-boot-on; 466*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 467*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 468*4882a593Smuzhiyun regulator-state-mem { 469*4882a593Smuzhiyun regulator-on-in-suspend; 470*4882a593Smuzhiyun }; 471*4882a593Smuzhiyun }; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun vcc_io: DCDC_REG4 { 474*4882a593Smuzhiyun regulator-always-on; 475*4882a593Smuzhiyun regulator-boot-on; 476*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 477*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 478*4882a593Smuzhiyun regulator-name = "vcc_io"; 479*4882a593Smuzhiyun regulator-state-mem { 480*4882a593Smuzhiyun regulator-off-in-suspend; 481*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 482*4882a593Smuzhiyun }; 483*4882a593Smuzhiyun }; 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun vcc_1v0: LDO_REG1 { 486*4882a593Smuzhiyun regulator-always-on; 487*4882a593Smuzhiyun regulator-boot-on; 488*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 489*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 490*4882a593Smuzhiyun regulator-name = "vcc_1v0"; 491*4882a593Smuzhiyun regulator-state-mem { 492*4882a593Smuzhiyun regulator-on-in-suspend; 493*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 494*4882a593Smuzhiyun }; 495*4882a593Smuzhiyun }; 496*4882a593Smuzhiyun 497*4882a593Smuzhiyun vcc1v8_soc: LDO_REG2 { 498*4882a593Smuzhiyun regulator-always-on; 499*4882a593Smuzhiyun regulator-boot-on; 500*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 501*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun regulator-name = "vcc1v8_soc"; 504*4882a593Smuzhiyun regulator-state-mem { 505*4882a593Smuzhiyun regulator-on-in-suspend; 506*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 507*4882a593Smuzhiyun }; 508*4882a593Smuzhiyun }; 509*4882a593Smuzhiyun 510*4882a593Smuzhiyun vdd1v0_soc: LDO_REG3 { 511*4882a593Smuzhiyun regulator-always-on; 512*4882a593Smuzhiyun regulator-boot-on; 513*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 514*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 515*4882a593Smuzhiyun 516*4882a593Smuzhiyun regulator-name = "vcc1v0_soc"; 517*4882a593Smuzhiyun regulator-state-mem { 518*4882a593Smuzhiyun regulator-on-in-suspend; 519*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 520*4882a593Smuzhiyun }; 521*4882a593Smuzhiyun }; 522*4882a593Smuzhiyun 523*4882a593Smuzhiyun vcc3v3_pmu: LDO_REG4 { 524*4882a593Smuzhiyun regulator-always-on; 525*4882a593Smuzhiyun regulator-boot-on; 526*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 527*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 528*4882a593Smuzhiyun 529*4882a593Smuzhiyun regulator-name = "vcc3v3_pmu"; 530*4882a593Smuzhiyun regulator-state-mem { 531*4882a593Smuzhiyun regulator-on-in-suspend; 532*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 533*4882a593Smuzhiyun 534*4882a593Smuzhiyun }; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 538*4882a593Smuzhiyun regulator-always-on; 539*4882a593Smuzhiyun regulator-boot-on; 540*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 541*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 542*4882a593Smuzhiyun 543*4882a593Smuzhiyun regulator-name = "vccio_sd"; 544*4882a593Smuzhiyun regulator-state-mem { 545*4882a593Smuzhiyun regulator-on-in-suspend; 546*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 547*4882a593Smuzhiyun }; 548*4882a593Smuzhiyun }; 549*4882a593Smuzhiyun 550*4882a593Smuzhiyun vcc_sd: LDO_REG6 { 551*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 552*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun regulator-name = "vcc_sd"; 555*4882a593Smuzhiyun regulator-state-mem { 556*4882a593Smuzhiyun regulator-on-in-suspend; 557*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun }; 560*4882a593Smuzhiyun }; 561*4882a593Smuzhiyun 562*4882a593Smuzhiyun vcc2v8_dvp: LDO_REG7 { 563*4882a593Smuzhiyun regulator-boot-on; 564*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 565*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 566*4882a593Smuzhiyun 567*4882a593Smuzhiyun regulator-name = "vcc2v8_dvp"; 568*4882a593Smuzhiyun regulator-state-mem { 569*4882a593Smuzhiyun regulator-off-in-suspend; 570*4882a593Smuzhiyun regulator-suspend-microvolt = <2800000>; 571*4882a593Smuzhiyun }; 572*4882a593Smuzhiyun }; 573*4882a593Smuzhiyun 574*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG8 { 575*4882a593Smuzhiyun regulator-boot-on; 576*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 577*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 580*4882a593Smuzhiyun regulator-state-mem { 581*4882a593Smuzhiyun regulator-off-in-suspend; 582*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 583*4882a593Smuzhiyun }; 584*4882a593Smuzhiyun }; 585*4882a593Smuzhiyun 586*4882a593Smuzhiyun vdd1v5_dvp: LDO_REG9 { 587*4882a593Smuzhiyun regulator-boot-on; 588*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 589*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun regulator-name = "vdd1v5_dvp"; 592*4882a593Smuzhiyun regulator-state-mem { 593*4882a593Smuzhiyun regulator-off-in-suspend; 594*4882a593Smuzhiyun regulator-suspend-microvolt = <1500000>; 595*4882a593Smuzhiyun }; 596*4882a593Smuzhiyun }; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun dcdc_boost: BOOST { 599*4882a593Smuzhiyun regulator-always-on; 600*4882a593Smuzhiyun regulator-boot-on; 601*4882a593Smuzhiyun regulator-min-microvolt = <5000000>; 602*4882a593Smuzhiyun regulator-max-microvolt = <5000000>; 603*4882a593Smuzhiyun regulator-name = "boost"; 604*4882a593Smuzhiyun }; 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun otg_switch: OTG_SWITCH { 607*4882a593Smuzhiyun regulator-name = "otg_switch"; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun }; 610*4882a593Smuzhiyun 611*4882a593Smuzhiyun battery { 612*4882a593Smuzhiyun compatible = "rk817,battery"; 613*4882a593Smuzhiyun ocv_table = <3500 3548 3592 3636 3687 3740 3780 614*4882a593Smuzhiyun 3806 3827 3846 3864 3889 3929 3964 615*4882a593Smuzhiyun 3993 4015 4030 4041 4056 4076 4148>; 616*4882a593Smuzhiyun design_capacity = <4000>; 617*4882a593Smuzhiyun design_qmax = <4200>; 618*4882a593Smuzhiyun bat_res = <100>; 619*4882a593Smuzhiyun sleep_enter_current = <150>; 620*4882a593Smuzhiyun sleep_exit_current = <180>; 621*4882a593Smuzhiyun sleep_filter_current = <100>; 622*4882a593Smuzhiyun power_off_thresd = <3500>; 623*4882a593Smuzhiyun zero_algorithm_vol = <3850>; 624*4882a593Smuzhiyun max_soc_offset = <60>; 625*4882a593Smuzhiyun monitor_sec = <5>; 626*4882a593Smuzhiyun sample_res = <10>; 627*4882a593Smuzhiyun virtual_power = <0>; 628*4882a593Smuzhiyun }; 629*4882a593Smuzhiyun 630*4882a593Smuzhiyun charger { 631*4882a593Smuzhiyun compatible = "rk817,charger"; 632*4882a593Smuzhiyun min_input_voltage = <4500>; 633*4882a593Smuzhiyun max_input_current = <1500>; 634*4882a593Smuzhiyun max_chrg_current = <2000>; 635*4882a593Smuzhiyun max_chrg_voltage = <4200>; 636*4882a593Smuzhiyun chrg_term_mode = <0>; 637*4882a593Smuzhiyun chrg_finish_cur = <300>; 638*4882a593Smuzhiyun virtual_power = <0>; 639*4882a593Smuzhiyun dc_det_adc = <0>; 640*4882a593Smuzhiyun extcon = <&u2phy>; 641*4882a593Smuzhiyun }; 642*4882a593Smuzhiyun 643*4882a593Smuzhiyun rk817_codec: codec { 644*4882a593Smuzhiyun #sound-dai-cells = <0>; 645*4882a593Smuzhiyun compatible = "rockchip,rk817-codec"; 646*4882a593Smuzhiyun clocks = <&cru SCLK_I2S_8CH_OUT>; 647*4882a593Smuzhiyun clock-names = "mclk"; 648*4882a593Smuzhiyun pinctrl-names = "default"; 649*4882a593Smuzhiyun pinctrl-0 = <&i2s_8ch_mclk>; 650*4882a593Smuzhiyun hp-volume = <20>; 651*4882a593Smuzhiyun spk-volume = <3>; 652*4882a593Smuzhiyun mic-in-differential; 653*4882a593Smuzhiyun status = "okay"; 654*4882a593Smuzhiyun }; 655*4882a593Smuzhiyun }; 656*4882a593Smuzhiyun}; 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun&i2c2 { 659*4882a593Smuzhiyun status = "okay"; 660*4882a593Smuzhiyun 661*4882a593Smuzhiyun ts@5a { 662*4882a593Smuzhiyun compatible = "cst2xxse"; 663*4882a593Smuzhiyun reg = <0x5a>; 664*4882a593Smuzhiyun irq-gpio = <&gpio0 RK_PB4 IRQ_TYPE_LEVEL_LOW>; 665*4882a593Smuzhiyun //touch-gpio = <&gpio1 GPIO_B0 IRQ_TYPE_LEVEL_LOW>; /* TP_INT == GPIO1_B0 */ 666*4882a593Smuzhiyun //reset-gpio = <&gpio0 GPIO_D1 GPIO_ACTIVE_LOW>; /* TP_RST == GPIO0_D1 */ 667*4882a593Smuzhiyun //power-gpio = <&gpio0 GPIO_C5 GPIO_ACTIVE_LOW>; 668*4882a593Smuzhiyun //max-x = <800>; 669*4882a593Smuzhiyun //max-y = <480>; 670*4882a593Smuzhiyun status = "okay"; 671*4882a593Smuzhiyun }; 672*4882a593Smuzhiyun}; 673*4882a593Smuzhiyun 674*4882a593Smuzhiyun&i2c3 { 675*4882a593Smuzhiyun status = "okay"; 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun gc0312: gc0312@21 { 678*4882a593Smuzhiyun status = "okay"; 679*4882a593Smuzhiyun compatible = "galaxycore,gc0312"; 680*4882a593Smuzhiyun reg = <0x21>; 681*4882a593Smuzhiyun clocks = <&cru SCLK_VIP_OUT>; 682*4882a593Smuzhiyun clock-names = "xvclk"; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun avdd-supply = <&vcc2v8_dvp>; 685*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dvp>; 686*4882a593Smuzhiyun dvdd-supply = <&vdd1v5_dvp>; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>; 689*4882a593Smuzhiyun 690*4882a593Smuzhiyun rockchip,camera-module-index = <1>; 691*4882a593Smuzhiyun rockchip,camera-module-facing = "front"; 692*4882a593Smuzhiyun rockchip,camera-module-name = "CameraKing"; 693*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan"; 694*4882a593Smuzhiyun port { 695*4882a593Smuzhiyun gc0312_out: endpoint { 696*4882a593Smuzhiyun remote-endpoint = <&dvp_in_fcam>; 697*4882a593Smuzhiyun }; 698*4882a593Smuzhiyun }; 699*4882a593Smuzhiyun }; 700*4882a593Smuzhiyun 701*4882a593Smuzhiyun gc2145: gc2145@3c { 702*4882a593Smuzhiyun status = "okay"; 703*4882a593Smuzhiyun compatible = "galaxycore,gc2145"; 704*4882a593Smuzhiyun reg = <0x3c>; 705*4882a593Smuzhiyun clocks = <&cru SCLK_VIP_OUT>; 706*4882a593Smuzhiyun clock-names = "xvclk"; 707*4882a593Smuzhiyun 708*4882a593Smuzhiyun avdd-supply = <&vcc2v8_dvp>; 709*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dvp>; 710*4882a593Smuzhiyun dvdd-supply = <&vdd1v5_dvp>; 711*4882a593Smuzhiyun 712*4882a593Smuzhiyun pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; 713*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 714*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 715*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 716*4882a593Smuzhiyun rockchip,camera-module-name = "CameraKing"; 717*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan"; 718*4882a593Smuzhiyun port { 719*4882a593Smuzhiyun gc2145_out: endpoint { 720*4882a593Smuzhiyun remote-endpoint = <&dvp_in_bcam>; 721*4882a593Smuzhiyun }; 722*4882a593Smuzhiyun }; 723*4882a593Smuzhiyun }; 724*4882a593Smuzhiyun 725*4882a593Smuzhiyun ov8858: ov8858@36 { 726*4882a593Smuzhiyun status = "disabled"; 727*4882a593Smuzhiyun compatible = "ovti,ov8858"; 728*4882a593Smuzhiyun reg = <0x36>; 729*4882a593Smuzhiyun clocks = <&cru SCLK_VIP_OUT>; 730*4882a593Smuzhiyun clock-names = "xvclk"; 731*4882a593Smuzhiyun 732*4882a593Smuzhiyun avdd-supply = <&vcc2v8_dvp>; 733*4882a593Smuzhiyun dovdd-supply = <&vcc1v8_dvp>; 734*4882a593Smuzhiyun dvdd-supply = <&vdd1v5_dvp>; 735*4882a593Smuzhiyun 736*4882a593Smuzhiyun pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>; 737*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>; 738*4882a593Smuzhiyun rockchip,camera-module-index = <0>; 739*4882a593Smuzhiyun rockchip,camera-module-facing = "back"; 740*4882a593Smuzhiyun rockchip,camera-module-name = "CameraKing"; 741*4882a593Smuzhiyun rockchip,camera-module-lens-name = "Largan-9569A2"; 742*4882a593Smuzhiyun port { 743*4882a593Smuzhiyun ov8858_out: endpoint { 744*4882a593Smuzhiyun remote-endpoint = <&mipi_in>; 745*4882a593Smuzhiyun data-lanes = <1 2>; 746*4882a593Smuzhiyun }; 747*4882a593Smuzhiyun }; 748*4882a593Smuzhiyun }; 749*4882a593Smuzhiyun}; 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun&i2c4 { 752*4882a593Smuzhiyun status = "okay"; 753*4882a593Smuzhiyun 754*4882a593Smuzhiyun sc7a30: sc7a30@18 { 755*4882a593Smuzhiyun status = "okay"; 756*4882a593Smuzhiyun compatible = "gs_sc7a30"; 757*4882a593Smuzhiyun reg = <0x18>; 758*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 759*4882a593Smuzhiyun pinctrl-names = "default"; 760*4882a593Smuzhiyun pinctrl-0 = <&sc7a30_irq_gpio>; 761*4882a593Smuzhiyun irq-gpio = <&gpio3 RK_PB6 IRQ_TYPE_LEVEL_LOW>; 762*4882a593Smuzhiyun irq_enable = <0>; 763*4882a593Smuzhiyun poll_delay_ms = <30>; 764*4882a593Smuzhiyun layout = <6>; 765*4882a593Smuzhiyun reprobe_en = <1>; 766*4882a593Smuzhiyun }; 767*4882a593Smuzhiyun 768*4882a593Smuzhiyun}; 769*4882a593Smuzhiyun 770*4882a593Smuzhiyun&i2s_8ch { 771*4882a593Smuzhiyun status = "okay"; 772*4882a593Smuzhiyun rockchip,i2s-broken-burst-len; 773*4882a593Smuzhiyun rockchip,playback-channels = <8>; 774*4882a593Smuzhiyun rockchip,capture-channels = <2>; 775*4882a593Smuzhiyun #sound-dai-cells = <0>; 776*4882a593Smuzhiyun}; 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun&io_domains { 779*4882a593Smuzhiyun status = "okay"; 780*4882a593Smuzhiyun 781*4882a593Smuzhiyun dvp-supply = <&vcc1v8_dvp>; 782*4882a593Smuzhiyun audio-supply = <&vcc_io>; 783*4882a593Smuzhiyun gpio30-supply = <&vcc_io>; 784*4882a593Smuzhiyun gpio1830-supply = <&vcc_io>; 785*4882a593Smuzhiyun sdcard-supply = <&vccio_sd>; 786*4882a593Smuzhiyun wifi-supply = <&vcc_3v3>; 787*4882a593Smuzhiyun}; 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun&isp_dvp_d2d9 { 790*4882a593Smuzhiyun rockchip,pins = 791*4882a593Smuzhiyun /* cif_data4 ... cif_data9 */ 792*4882a593Smuzhiyun <1 RK_PA2 1 &pcfg_pull_down>, 793*4882a593Smuzhiyun <1 RK_PA3 1 &pcfg_pull_down>, 794*4882a593Smuzhiyun <1 RK_PA4 1 &pcfg_pull_down>, 795*4882a593Smuzhiyun <1 RK_PA5 1 &pcfg_pull_down>, 796*4882a593Smuzhiyun <1 RK_PA6 1 &pcfg_pull_down>, 797*4882a593Smuzhiyun <1 RK_PA7 1 &pcfg_pull_down>, 798*4882a593Smuzhiyun /* cif_sync, cif_href */ 799*4882a593Smuzhiyun <1 RK_PB0 1 &pcfg_pull_down>, 800*4882a593Smuzhiyun <1 RK_PB1 1 &pcfg_pull_down>, 801*4882a593Smuzhiyun /* cif_clkin */ 802*4882a593Smuzhiyun <1 RK_PB2 1 &pcfg_pull_down>; 803*4882a593Smuzhiyun}; 804*4882a593Smuzhiyun 805*4882a593Smuzhiyun&isp_dvp_d10d11 { 806*4882a593Smuzhiyun rockchip,pins = 807*4882a593Smuzhiyun /* cif_data10, cif_data11 */ 808*4882a593Smuzhiyun <1 RK_PB6 1 &pcfg_pull_down>, 809*4882a593Smuzhiyun <1 RK_PB7 1 &pcfg_pull_down>; 810*4882a593Smuzhiyun}; 811*4882a593Smuzhiyun 812*4882a593Smuzhiyun&isp_mmu { 813*4882a593Smuzhiyun status = "okay"; 814*4882a593Smuzhiyun}; 815*4882a593Smuzhiyun 816*4882a593Smuzhiyun&mipi_dphy_rx0 { 817*4882a593Smuzhiyun status = "disabled"; 818*4882a593Smuzhiyun 819*4882a593Smuzhiyun ports { 820*4882a593Smuzhiyun #address-cells = <1>; 821*4882a593Smuzhiyun #size-cells = <0>; 822*4882a593Smuzhiyun 823*4882a593Smuzhiyun port@0 { 824*4882a593Smuzhiyun reg = <0>; 825*4882a593Smuzhiyun #address-cells = <1>; 826*4882a593Smuzhiyun #size-cells = <0>; 827*4882a593Smuzhiyun 828*4882a593Smuzhiyun mipi_in: endpoint@1 { 829*4882a593Smuzhiyun reg = <1>; 830*4882a593Smuzhiyun remote-endpoint = <&ov8858_out>; 831*4882a593Smuzhiyun data-lanes = <1 2>; 832*4882a593Smuzhiyun }; 833*4882a593Smuzhiyun }; 834*4882a593Smuzhiyun 835*4882a593Smuzhiyun port@1 { 836*4882a593Smuzhiyun reg = <1>; 837*4882a593Smuzhiyun #address-cells = <1>; 838*4882a593Smuzhiyun #size-cells = <0>; 839*4882a593Smuzhiyun 840*4882a593Smuzhiyun dphy_rx_out: endpoint@0 { 841*4882a593Smuzhiyun reg = <0>; 842*4882a593Smuzhiyun remote-endpoint = <&isp_mipi_in>; 843*4882a593Smuzhiyun }; 844*4882a593Smuzhiyun }; 845*4882a593Smuzhiyun }; 846*4882a593Smuzhiyun}; 847*4882a593Smuzhiyun 848*4882a593Smuzhiyun&nandc0 { 849*4882a593Smuzhiyun status = "okay"; 850*4882a593Smuzhiyun}; 851*4882a593Smuzhiyun 852*4882a593Smuzhiyun&pmu_io_domains { 853*4882a593Smuzhiyun status = "okay"; 854*4882a593Smuzhiyun 855*4882a593Smuzhiyun pmu-supply = <&vcc3v3_pmu>; 856*4882a593Smuzhiyun vop-supply = <&vcc3v3_pmu>; 857*4882a593Smuzhiyun}; 858*4882a593Smuzhiyun 859*4882a593Smuzhiyun&pwm0 { 860*4882a593Smuzhiyun status = "okay"; 861*4882a593Smuzhiyun}; 862*4882a593Smuzhiyun 863*4882a593Smuzhiyun&pinctrl { 864*4882a593Smuzhiyun 865*4882a593Smuzhiyun headphone { 866*4882a593Smuzhiyun hp_det: hp-det { 867*4882a593Smuzhiyun rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>; 868*4882a593Smuzhiyun }; 869*4882a593Smuzhiyun }; 870*4882a593Smuzhiyun 871*4882a593Smuzhiyun pmic { 872*4882a593Smuzhiyun pmic_int: pmic_int { 873*4882a593Smuzhiyun rockchip,pins = 874*4882a593Smuzhiyun <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>; 875*4882a593Smuzhiyun }; 876*4882a593Smuzhiyun 877*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 878*4882a593Smuzhiyun rockchip,pins = 879*4882a593Smuzhiyun <0 RK_PA0 RK_FUNC_GPIO &pcfg_output_low>; 880*4882a593Smuzhiyun }; 881*4882a593Smuzhiyun 882*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 883*4882a593Smuzhiyun rockchip,pins = 884*4882a593Smuzhiyun <0 RK_PA0 1 &pcfg_pull_none>; 885*4882a593Smuzhiyun }; 886*4882a593Smuzhiyun 887*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 888*4882a593Smuzhiyun rockchip,pins = 889*4882a593Smuzhiyun <0 RK_PA0 2 &pcfg_pull_none>; 890*4882a593Smuzhiyun }; 891*4882a593Smuzhiyun 892*4882a593Smuzhiyun vsel_gpio: vsel-gpio { 893*4882a593Smuzhiyun rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>; 894*4882a593Smuzhiyun }; 895*4882a593Smuzhiyun }; 896*4882a593Smuzhiyun 897*4882a593Smuzhiyun sc7a30 { 898*4882a593Smuzhiyun sc7a30_irq_gpio: sc7a30_irq_gpio { 899*4882a593Smuzhiyun rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>; 900*4882a593Smuzhiyun }; 901*4882a593Smuzhiyun }; 902*4882a593Smuzhiyun 903*4882a593Smuzhiyun dc_det { 904*4882a593Smuzhiyun dc_irq_gpio: dc-irq-gpio { 905*4882a593Smuzhiyun rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>; 906*4882a593Smuzhiyun }; 907*4882a593Smuzhiyun }; 908*4882a593Smuzhiyun 909*4882a593Smuzhiyun pcfg_pull_none_4ma: pcfg-pull-none-4ma { 910*4882a593Smuzhiyun bias-disable; 911*4882a593Smuzhiyun drive-strength = <4>; 912*4882a593Smuzhiyun }; 913*4882a593Smuzhiyun 914*4882a593Smuzhiyun pcfg_pull_none_smt: pcfg-pull-none-smt { 915*4882a593Smuzhiyun bias-disable; 916*4882a593Smuzhiyun input-schmitt-enable; 917*4882a593Smuzhiyun }; 918*4882a593Smuzhiyun 919*4882a593Smuzhiyun pcfg_output_high: pcfg-output-high { 920*4882a593Smuzhiyun output-high; 921*4882a593Smuzhiyun }; 922*4882a593Smuzhiyun 923*4882a593Smuzhiyun pcfg_output_low: pcfg-output-low { 924*4882a593Smuzhiyun output-low; 925*4882a593Smuzhiyun }; 926*4882a593Smuzhiyun 927*4882a593Smuzhiyun pcfg_input_high: pcfg-input-high { 928*4882a593Smuzhiyun bias-pull-up; 929*4882a593Smuzhiyun input-enable; 930*4882a593Smuzhiyun }; 931*4882a593Smuzhiyun 932*4882a593Smuzhiyun pcfg_input: pcfg-input { 933*4882a593Smuzhiyun input-enable; 934*4882a593Smuzhiyun }; 935*4882a593Smuzhiyun 936*4882a593Smuzhiyun sdio-pwrseq { 937*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 938*4882a593Smuzhiyun rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 939*4882a593Smuzhiyun }; 940*4882a593Smuzhiyun }; 941*4882a593Smuzhiyun 942*4882a593Smuzhiyun usb2 { 943*4882a593Smuzhiyun host_vbus_drv: host-vbus-drv { 944*4882a593Smuzhiyun rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>; 945*4882a593Smuzhiyun }; 946*4882a593Smuzhiyun }; 947*4882a593Smuzhiyun 948*4882a593Smuzhiyun wireless-bluetooth { 949*4882a593Smuzhiyun uart0_rts_gpio: uart0-rts-gpio { 950*4882a593Smuzhiyun rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; 951*4882a593Smuzhiyun }; 952*4882a593Smuzhiyun }; 953*4882a593Smuzhiyun}; 954*4882a593Smuzhiyun 955*4882a593Smuzhiyun&rkisp1 { 956*4882a593Smuzhiyun status = "okay"; 957*4882a593Smuzhiyun pinctrl-names = "default"; 958*4882a593Smuzhiyun pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d10d11 &cif_clkout>; 959*4882a593Smuzhiyun port { 960*4882a593Smuzhiyun #address-cells = <1>; 961*4882a593Smuzhiyun #size-cells = <0>; 962*4882a593Smuzhiyun 963*4882a593Smuzhiyun dvp_in_fcam: endpoint@0 { 964*4882a593Smuzhiyun reg = <0>; 965*4882a593Smuzhiyun remote-endpoint = <&gc0312_out>; 966*4882a593Smuzhiyun }; 967*4882a593Smuzhiyun 968*4882a593Smuzhiyun dvp_in_bcam: endpoint@1 { 969*4882a593Smuzhiyun reg = <1>; 970*4882a593Smuzhiyun remote-endpoint = <&gc2145_out>; 971*4882a593Smuzhiyun }; 972*4882a593Smuzhiyun 973*4882a593Smuzhiyun isp_mipi_in: endpoint@2 { 974*4882a593Smuzhiyun reg = <2>; 975*4882a593Smuzhiyun remote-endpoint = <&dphy_rx_out>; 976*4882a593Smuzhiyun }; 977*4882a593Smuzhiyun }; 978*4882a593Smuzhiyun}; 979*4882a593Smuzhiyun 980*4882a593Smuzhiyun&route_dsi { 981*4882a593Smuzhiyun status = "okay"; 982*4882a593Smuzhiyun}; 983*4882a593Smuzhiyun 984*4882a593Smuzhiyun&rockchip_suspend { 985*4882a593Smuzhiyun status = "okay"; 986*4882a593Smuzhiyun rockchip,sleep-mode-config = < 987*4882a593Smuzhiyun (0 988*4882a593Smuzhiyun | RKPM_SLP_ARMOFF 989*4882a593Smuzhiyun | RKPM_SLP_PMU_PLLS_PWRDN 990*4882a593Smuzhiyun | RKPM_SLP_PMU_PMUALIVE_32K 991*4882a593Smuzhiyun | RKPM_SLP_SFT_PLLS_DEEP 992*4882a593Smuzhiyun | RKPM_SLP_PMU_DIS_OSC 993*4882a593Smuzhiyun | RKPM_SLP_SFT_PD_NBSCUS 994*4882a593Smuzhiyun ) 995*4882a593Smuzhiyun >; 996*4882a593Smuzhiyun rockchip,wakeup-config = < 997*4882a593Smuzhiyun (0 998*4882a593Smuzhiyun | RKPM_GPIO_WKUP_EN 999*4882a593Smuzhiyun | RKPM_USB_WKUP_EN 1000*4882a593Smuzhiyun | RKPM_CLUSTER_L_WKUP_EN 1001*4882a593Smuzhiyun ) 1002*4882a593Smuzhiyun >; 1003*4882a593Smuzhiyun}; 1004*4882a593Smuzhiyun 1005*4882a593Smuzhiyun&saradc { 1006*4882a593Smuzhiyun status = "okay"; 1007*4882a593Smuzhiyun}; 1008*4882a593Smuzhiyun 1009*4882a593Smuzhiyun&sdmmc { 1010*4882a593Smuzhiyun clock-frequency = <37500000>; 1011*4882a593Smuzhiyun clock-freq-min-max = <400000 37500000>; 1012*4882a593Smuzhiyun no-sdio; 1013*4882a593Smuzhiyun no-mmc; 1014*4882a593Smuzhiyun cap-mmc-highspeed; 1015*4882a593Smuzhiyun cap-sd-highspeed; 1016*4882a593Smuzhiyun card-detect-delay = <200>; 1017*4882a593Smuzhiyun disable-wp; 1018*4882a593Smuzhiyun num-slots = <1>; 1019*4882a593Smuzhiyun pinctrl-names = "default"; 1020*4882a593Smuzhiyun pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>; 1021*4882a593Smuzhiyun vmmc-supply = <&vcc_sd>; 1022*4882a593Smuzhiyun status = "disabled"; 1023*4882a593Smuzhiyun}; 1024*4882a593Smuzhiyun 1025*4882a593Smuzhiyun&sdio0 { 1026*4882a593Smuzhiyun max-frequency = <50000000>; 1027*4882a593Smuzhiyun no-sd; 1028*4882a593Smuzhiyun no-mmc; 1029*4882a593Smuzhiyun bus-width = <4>; 1030*4882a593Smuzhiyun disable-wp; 1031*4882a593Smuzhiyun cap-sd-highspeed; 1032*4882a593Smuzhiyun cap-sdio-irq; 1033*4882a593Smuzhiyun keep-power-in-suspend; 1034*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 1035*4882a593Smuzhiyun non-removable; 1036*4882a593Smuzhiyun num-slots = <1>; 1037*4882a593Smuzhiyun pinctrl-names = "default"; 1038*4882a593Smuzhiyun pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>; 1039*4882a593Smuzhiyun rockchip,default-sample-phase = <90>; 1040*4882a593Smuzhiyun status = "okay"; 1041*4882a593Smuzhiyun}; 1042*4882a593Smuzhiyun 1043*4882a593Smuzhiyun&tsadc { 1044*4882a593Smuzhiyun tsadc-supply = <&vdd_cpu>; 1045*4882a593Smuzhiyun status = "okay"; 1046*4882a593Smuzhiyun}; 1047*4882a593Smuzhiyun 1048*4882a593Smuzhiyun&uart0 { 1049*4882a593Smuzhiyun pinctrl-names = "default"; 1050*4882a593Smuzhiyun pinctrl-0 = <&uart0_xfer &uart0_cts>; 1051*4882a593Smuzhiyun status = "okay"; 1052*4882a593Smuzhiyun}; 1053*4882a593Smuzhiyun 1054*4882a593Smuzhiyun&u2phy { 1055*4882a593Smuzhiyun status = "okay"; 1056*4882a593Smuzhiyun 1057*4882a593Smuzhiyun u2phy_otg: otg-port { 1058*4882a593Smuzhiyun status = "okay"; 1059*4882a593Smuzhiyun }; 1060*4882a593Smuzhiyun 1061*4882a593Smuzhiyun u2phy_host: host-port { 1062*4882a593Smuzhiyun phy-supply = <&vcc_host>; 1063*4882a593Smuzhiyun status = "okay"; 1064*4882a593Smuzhiyun }; 1065*4882a593Smuzhiyun}; 1066*4882a593Smuzhiyun 1067*4882a593Smuzhiyun&usb_host0_ehci { 1068*4882a593Smuzhiyun status = "okay"; 1069*4882a593Smuzhiyun}; 1070*4882a593Smuzhiyun 1071*4882a593Smuzhiyun&usb_host0_ohci { 1072*4882a593Smuzhiyun status = "okay"; 1073*4882a593Smuzhiyun}; 1074*4882a593Smuzhiyun 1075