1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2015 Heiko Stuebner <heiko@sntech.de> 4 */ 5 6#include <dt-bindings/clock/rk3368-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 compatible = "rockchip,rk3368"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 ethernet0 = &gmac; 22 gpio0 = &gpio0; 23 gpio1 = &gpio1; 24 gpio2 = &gpio2; 25 gpio3 = &gpio3; 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 serial0 = &uart0; 33 serial1 = &uart1; 34 serial2 = &uart2; 35 serial3 = &uart3; 36 serial4 = &uart4; 37 spi0 = &spi0; 38 spi1 = &spi1; 39 spi2 = &spi2; 40 }; 41 42 cpus { 43 #address-cells = <0x2>; 44 #size-cells = <0x0>; 45 46 cpu-map { 47 cluster0 { 48 core0 { 49 cpu = <&cpu_b0>; 50 }; 51 core1 { 52 cpu = <&cpu_b1>; 53 }; 54 core2 { 55 cpu = <&cpu_b2>; 56 }; 57 core3 { 58 cpu = <&cpu_b3>; 59 }; 60 }; 61 62 cluster1 { 63 core0 { 64 cpu = <&cpu_l0>; 65 }; 66 core1 { 67 cpu = <&cpu_l1>; 68 }; 69 core2 { 70 cpu = <&cpu_l2>; 71 }; 72 core3 { 73 cpu = <&cpu_l3>; 74 }; 75 }; 76 }; 77 78 cpu_l0: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x0>; 82 enable-method = "psci"; 83 #cooling-cells = <2>; /* min followed by max */ 84 }; 85 86 cpu_l1: cpu@1 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 reg = <0x0 0x1>; 90 enable-method = "psci"; 91 #cooling-cells = <2>; /* min followed by max */ 92 }; 93 94 cpu_l2: cpu@2 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a53"; 97 reg = <0x0 0x2>; 98 enable-method = "psci"; 99 #cooling-cells = <2>; /* min followed by max */ 100 }; 101 102 cpu_l3: cpu@3 { 103 device_type = "cpu"; 104 compatible = "arm,cortex-a53"; 105 reg = <0x0 0x3>; 106 enable-method = "psci"; 107 #cooling-cells = <2>; /* min followed by max */ 108 }; 109 110 cpu_b0: cpu@100 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a53"; 113 reg = <0x0 0x100>; 114 enable-method = "psci"; 115 #cooling-cells = <2>; /* min followed by max */ 116 }; 117 118 cpu_b1: cpu@101 { 119 device_type = "cpu"; 120 compatible = "arm,cortex-a53"; 121 reg = <0x0 0x101>; 122 enable-method = "psci"; 123 #cooling-cells = <2>; /* min followed by max */ 124 }; 125 126 cpu_b2: cpu@102 { 127 device_type = "cpu"; 128 compatible = "arm,cortex-a53"; 129 reg = <0x0 0x102>; 130 enable-method = "psci"; 131 #cooling-cells = <2>; /* min followed by max */ 132 }; 133 134 cpu_b3: cpu@103 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a53"; 137 reg = <0x0 0x103>; 138 enable-method = "psci"; 139 #cooling-cells = <2>; /* min followed by max */ 140 }; 141 }; 142 143 amba: bus { 144 compatible = "simple-bus"; 145 #address-cells = <2>; 146 #size-cells = <2>; 147 ranges; 148 149 dmac_peri: dma-controller@ff250000 { 150 compatible = "arm,pl330", "arm,primecell"; 151 reg = <0x0 0xff250000 0x0 0x4000>; 152 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 154 #dma-cells = <1>; 155 arm,pl330-broken-no-flushp; 156 arm,pl330-periph-burst; 157 clocks = <&cru ACLK_DMAC_PERI>; 158 clock-names = "apb_pclk"; 159 }; 160 161 dmac_bus: dma-controller@ff600000 { 162 compatible = "arm,pl330", "arm,primecell"; 163 reg = <0x0 0xff600000 0x0 0x4000>; 164 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 166 #dma-cells = <1>; 167 arm,pl330-broken-no-flushp; 168 arm,pl330-periph-burst; 169 clocks = <&cru ACLK_DMAC_BUS>; 170 clock-names = "apb_pclk"; 171 }; 172 }; 173 174 arm-pmu { 175 compatible = "arm,armv8-pmuv3"; 176 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 184 interrupt-affinity = <&cpu_l0>, <&cpu_l1>, <&cpu_l2>, 185 <&cpu_l3>, <&cpu_b0>, <&cpu_b1>, 186 <&cpu_b2>, <&cpu_b3>; 187 }; 188 189 psci { 190 compatible = "arm,psci-0.2"; 191 method = "smc"; 192 }; 193 194 timer { 195 compatible = "arm,armv8-timer"; 196 interrupts = <GIC_PPI 13 197 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 198 <GIC_PPI 14 199 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 200 <GIC_PPI 11 201 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>, 202 <GIC_PPI 10 203 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 204 }; 205 206 xin24m: oscillator { 207 compatible = "fixed-clock"; 208 clock-frequency = <24000000>; 209 clock-output-names = "xin24m"; 210 #clock-cells = <0>; 211 }; 212 213 sdmmc: mmc@ff0c0000 { 214 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 215 reg = <0x0 0xff0c0000 0x0 0x4000>; 216 max-frequency = <150000000>; 217 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 218 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 219 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 220 fifo-depth = <0x100>; 221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 222 resets = <&cru SRST_MMC0>; 223 reset-names = "reset"; 224 status = "disabled"; 225 }; 226 227 sdio0: mmc@ff0d0000 { 228 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 229 reg = <0x0 0xff0d0000 0x0 0x4000>; 230 max-frequency = <150000000>; 231 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>, 232 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>; 233 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 234 fifo-depth = <0x100>; 235 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 236 resets = <&cru SRST_SDIO0>; 237 reset-names = "reset"; 238 status = "disabled"; 239 }; 240 241 emmc: mmc@ff0f0000 { 242 compatible = "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc"; 243 reg = <0x0 0xff0f0000 0x0 0x4000>; 244 max-frequency = <150000000>; 245 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 246 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 247 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 248 fifo-depth = <0x100>; 249 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 250 resets = <&cru SRST_EMMC>; 251 reset-names = "reset"; 252 status = "disabled"; 253 }; 254 255 saradc: saradc@ff100000 { 256 compatible = "rockchip,saradc"; 257 reg = <0x0 0xff100000 0x0 0x100>; 258 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 259 #io-channel-cells = <1>; 260 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 261 clock-names = "saradc", "apb_pclk"; 262 resets = <&cru SRST_SARADC>; 263 reset-names = "saradc-apb"; 264 status = "disabled"; 265 }; 266 267 spi0: spi@ff110000 { 268 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 269 reg = <0x0 0xff110000 0x0 0x1000>; 270 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 271 clock-names = "spiclk", "apb_pclk"; 272 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>; 275 #address-cells = <1>; 276 #size-cells = <0>; 277 status = "disabled"; 278 }; 279 280 spi1: spi@ff120000 { 281 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 282 reg = <0x0 0xff120000 0x0 0x1000>; 283 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 284 clock-names = "spiclk", "apb_pclk"; 285 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>; 288 #address-cells = <1>; 289 #size-cells = <0>; 290 status = "disabled"; 291 }; 292 293 spi2: spi@ff130000 { 294 compatible = "rockchip,rk3368-spi", "rockchip,rk3066-spi"; 295 reg = <0x0 0xff130000 0x0 0x1000>; 296 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>; 297 clock-names = "spiclk", "apb_pclk"; 298 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 299 pinctrl-names = "default"; 300 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>; 301 #address-cells = <1>; 302 #size-cells = <0>; 303 status = "disabled"; 304 }; 305 306 i2c2: i2c@ff140000 { 307 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 308 reg = <0x0 0xff140000 0x0 0x1000>; 309 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 clock-names = "i2c"; 313 clocks = <&cru PCLK_I2C2>; 314 pinctrl-names = "default"; 315 pinctrl-0 = <&i2c2_xfer>; 316 status = "disabled"; 317 }; 318 319 i2c3: i2c@ff150000 { 320 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 321 reg = <0x0 0xff150000 0x0 0x1000>; 322 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 clock-names = "i2c"; 326 clocks = <&cru PCLK_I2C3>; 327 pinctrl-names = "default"; 328 pinctrl-0 = <&i2c3_xfer>; 329 status = "disabled"; 330 }; 331 332 i2c4: i2c@ff160000 { 333 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 334 reg = <0x0 0xff160000 0x0 0x1000>; 335 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 clock-names = "i2c"; 339 clocks = <&cru PCLK_I2C4>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&i2c4_xfer>; 342 status = "disabled"; 343 }; 344 345 i2c5: i2c@ff170000 { 346 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 347 reg = <0x0 0xff170000 0x0 0x1000>; 348 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 clock-names = "i2c"; 352 clocks = <&cru PCLK_I2C5>; 353 pinctrl-names = "default"; 354 pinctrl-0 = <&i2c5_xfer>; 355 status = "disabled"; 356 }; 357 358 uart0: serial@ff180000 { 359 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 360 reg = <0x0 0xff180000 0x0 0x100>; 361 clock-frequency = <24000000>; 362 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 363 clock-names = "baudclk", "apb_pclk"; 364 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 365 reg-shift = <2>; 366 reg-io-width = <4>; 367 status = "disabled"; 368 }; 369 370 uart1: serial@ff190000 { 371 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 372 reg = <0x0 0xff190000 0x0 0x100>; 373 clock-frequency = <24000000>; 374 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 375 clock-names = "baudclk", "apb_pclk"; 376 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 377 reg-shift = <2>; 378 reg-io-width = <4>; 379 status = "disabled"; 380 }; 381 382 uart3: serial@ff1b0000 { 383 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 384 reg = <0x0 0xff1b0000 0x0 0x100>; 385 clock-frequency = <24000000>; 386 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 387 clock-names = "baudclk", "apb_pclk"; 388 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 389 reg-shift = <2>; 390 reg-io-width = <4>; 391 status = "disabled"; 392 }; 393 394 uart4: serial@ff1c0000 { 395 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 396 reg = <0x0 0xff1c0000 0x0 0x100>; 397 clock-frequency = <24000000>; 398 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 399 clock-names = "baudclk", "apb_pclk"; 400 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 401 reg-shift = <2>; 402 reg-io-width = <4>; 403 status = "disabled"; 404 }; 405 406 thermal-zones { 407 cpu { 408 polling-delay-passive = <100>; /* milliseconds */ 409 polling-delay = <5000>; /* milliseconds */ 410 411 thermal-sensors = <&tsadc 0>; 412 413 trips { 414 cpu_alert0: cpu_alert0 { 415 temperature = <75000>; /* millicelsius */ 416 hysteresis = <2000>; /* millicelsius */ 417 type = "passive"; 418 }; 419 cpu_alert1: cpu_alert1 { 420 temperature = <80000>; /* millicelsius */ 421 hysteresis = <2000>; /* millicelsius */ 422 type = "passive"; 423 }; 424 cpu_crit: cpu_crit { 425 temperature = <95000>; /* millicelsius */ 426 hysteresis = <2000>; /* millicelsius */ 427 type = "critical"; 428 }; 429 }; 430 431 cooling-maps { 432 map0 { 433 trip = <&cpu_alert0>; 434 cooling-device = 435 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 436 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 437 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 438 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 439 }; 440 map1 { 441 trip = <&cpu_alert1>; 442 cooling-device = 443 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 444 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 445 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 446 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 447 }; 448 }; 449 }; 450 451 gpu { 452 polling-delay-passive = <100>; /* milliseconds */ 453 polling-delay = <5000>; /* milliseconds */ 454 455 thermal-sensors = <&tsadc 1>; 456 457 trips { 458 gpu_alert0: gpu_alert0 { 459 temperature = <80000>; /* millicelsius */ 460 hysteresis = <2000>; /* millicelsius */ 461 type = "passive"; 462 }; 463 gpu_crit: gpu_crit { 464 temperature = <115000>; /* millicelsius */ 465 hysteresis = <2000>; /* millicelsius */ 466 type = "critical"; 467 }; 468 }; 469 470 cooling-maps { 471 map0 { 472 trip = <&gpu_alert0>; 473 cooling-device = 474 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 475 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 476 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 477 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 478 }; 479 }; 480 }; 481 }; 482 483 tsadc: tsadc@ff280000 { 484 compatible = "rockchip,rk3368-tsadc"; 485 reg = <0x0 0xff280000 0x0 0x100>; 486 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 488 clock-names = "tsadc", "apb_pclk"; 489 resets = <&cru SRST_TSADC>; 490 reset-names = "tsadc-apb"; 491 pinctrl-names = "init", "default", "sleep"; 492 pinctrl-0 = <&otp_pin>; 493 pinctrl-1 = <&otp_out>; 494 pinctrl-2 = <&otp_pin>; 495 #thermal-sensor-cells = <1>; 496 rockchip,hw-tshut-temp = <95000>; 497 status = "disabled"; 498 }; 499 500 gmac: ethernet@ff290000 { 501 compatible = "rockchip,rk3368-gmac"; 502 reg = <0x0 0xff290000 0x0 0x10000>; 503 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 504 interrupt-names = "macirq"; 505 rockchip,grf = <&grf>; 506 clocks = <&cru SCLK_MAC>, 507 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>, 508 <&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>, 509 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>; 510 clock-names = "stmmaceth", 511 "mac_clk_rx", "mac_clk_tx", 512 "clk_mac_ref", "clk_mac_refout", 513 "aclk_mac", "pclk_mac"; 514 status = "disabled"; 515 }; 516 517 usb_host0_ehci: usb@ff500000 { 518 compatible = "generic-ehci"; 519 reg = <0x0 0xff500000 0x0 0x100>; 520 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&cru HCLK_HOST0>; 522 status = "disabled"; 523 }; 524 525 usb_otg: usb@ff580000 { 526 compatible = "rockchip,rk3368-usb", "rockchip,rk3066-usb", 527 "snps,dwc2"; 528 reg = <0x0 0xff580000 0x0 0x40000>; 529 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&cru HCLK_OTG0>; 531 clock-names = "otg"; 532 dr_mode = "otg"; 533 g-np-tx-fifo-size = <16>; 534 g-rx-fifo-size = <275>; 535 g-tx-fifo-size = <256 128 128 64 64 32>; 536 status = "disabled"; 537 }; 538 539 i2c0: i2c@ff650000 { 540 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 541 reg = <0x0 0xff650000 0x0 0x1000>; 542 clocks = <&cru PCLK_I2C0>; 543 clock-names = "i2c"; 544 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&i2c0_xfer>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 status = "disabled"; 550 }; 551 552 i2c1: i2c@ff660000 { 553 compatible = "rockchip,rk3368-i2c", "rockchip,rk3288-i2c"; 554 reg = <0x0 0xff660000 0x0 0x1000>; 555 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 clock-names = "i2c"; 559 clocks = <&cru PCLK_I2C1>; 560 pinctrl-names = "default"; 561 pinctrl-0 = <&i2c1_xfer>; 562 status = "disabled"; 563 }; 564 565 pwm0: pwm@ff680000 { 566 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 567 reg = <0x0 0xff680000 0x0 0x10>; 568 #pwm-cells = <3>; 569 pinctrl-names = "active"; 570 pinctrl-0 = <&pwm0_pin>; 571 clocks = <&cru PCLK_PWM1>; 572 clock-names = "pwm"; 573 status = "disabled"; 574 }; 575 576 pwm1: pwm@ff680010 { 577 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 578 reg = <0x0 0xff680010 0x0 0x10>; 579 #pwm-cells = <3>; 580 pinctrl-names = "active"; 581 pinctrl-0 = <&pwm1_pin>; 582 clocks = <&cru PCLK_PWM1>; 583 clock-names = "pwm"; 584 status = "disabled"; 585 }; 586 587 pwm2: pwm@ff680020 { 588 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 589 reg = <0x0 0xff680020 0x0 0x10>; 590 #pwm-cells = <3>; 591 clocks = <&cru PCLK_PWM1>; 592 clock-names = "pwm"; 593 status = "disabled"; 594 }; 595 596 pwm3: pwm@ff680030 { 597 compatible = "rockchip,rk3368-pwm", "rockchip,rk3288-pwm"; 598 reg = <0x0 0xff680030 0x0 0x10>; 599 #pwm-cells = <3>; 600 pinctrl-names = "active"; 601 pinctrl-0 = <&pwm3_pin>; 602 clocks = <&cru PCLK_PWM1>; 603 clock-names = "pwm"; 604 status = "disabled"; 605 }; 606 607 uart2: serial@ff690000 { 608 compatible = "rockchip,rk3368-uart", "snps,dw-apb-uart"; 609 reg = <0x0 0xff690000 0x0 0x100>; 610 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 611 clock-names = "baudclk", "apb_pclk"; 612 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 613 pinctrl-names = "default"; 614 pinctrl-0 = <&uart2_xfer>; 615 reg-shift = <2>; 616 reg-io-width = <4>; 617 status = "disabled"; 618 }; 619 620 mbox: mbox@ff6b0000 { 621 compatible = "rockchip,rk3368-mailbox"; 622 reg = <0x0 0xff6b0000 0x0 0x1000>; 623 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 624 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 625 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&cru PCLK_MAILBOX>; 628 clock-names = "pclk_mailbox"; 629 #mbox-cells = <1>; 630 status = "disabled"; 631 }; 632 633 pmugrf: syscon@ff738000 { 634 compatible = "rockchip,rk3368-pmugrf", "syscon", "simple-mfd"; 635 reg = <0x0 0xff738000 0x0 0x1000>; 636 637 pmu_io_domains: io-domains { 638 compatible = "rockchip,rk3368-pmu-io-voltage-domain"; 639 status = "disabled"; 640 }; 641 642 reboot-mode { 643 compatible = "syscon-reboot-mode"; 644 offset = <0x200>; 645 mode-normal = <BOOT_NORMAL>; 646 mode-recovery = <BOOT_RECOVERY>; 647 mode-bootloader = <BOOT_FASTBOOT>; 648 mode-loader = <BOOT_BL_DOWNLOAD>; 649 }; 650 }; 651 652 cru: clock-controller@ff760000 { 653 compatible = "rockchip,rk3368-cru"; 654 reg = <0x0 0xff760000 0x0 0x1000>; 655 rockchip,grf = <&grf>; 656 #clock-cells = <1>; 657 #reset-cells = <1>; 658 }; 659 660 grf: syscon@ff770000 { 661 compatible = "rockchip,rk3368-grf", "syscon", "simple-mfd"; 662 reg = <0x0 0xff770000 0x0 0x1000>; 663 664 io_domains: io-domains { 665 compatible = "rockchip,rk3368-io-voltage-domain"; 666 status = "disabled"; 667 }; 668 }; 669 670 wdt: watchdog@ff800000 { 671 compatible = "rockchip,rk3368-wdt", "snps,dw-wdt"; 672 reg = <0x0 0xff800000 0x0 0x100>; 673 clocks = <&cru PCLK_WDT>; 674 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 675 status = "disabled"; 676 }; 677 678 timer@ff810000 { 679 compatible = "rockchip,rk3368-timer", "rockchip,rk3288-timer"; 680 reg = <0x0 0xff810000 0x0 0x20>; 681 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 682 }; 683 684 spdif: spdif@ff880000 { 685 compatible = "rockchip,rk3368-spdif"; 686 reg = <0x0 0xff880000 0x0 0x1000>; 687 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>; 689 clock-names = "mclk", "hclk"; 690 dmas = <&dmac_bus 3>; 691 dma-names = "tx"; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&spdif_tx>; 694 status = "disabled"; 695 }; 696 697 i2s_2ch: i2s-2ch@ff890000 { 698 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; 699 reg = <0x0 0xff890000 0x0 0x1000>; 700 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 701 clock-names = "i2s_clk", "i2s_hclk"; 702 clocks = <&cru SCLK_I2S_2CH>, <&cru HCLK_I2S_2CH>; 703 dmas = <&dmac_bus 6>, <&dmac_bus 7>; 704 dma-names = "tx", "rx"; 705 status = "disabled"; 706 }; 707 708 i2s_8ch: i2s-8ch@ff898000 { 709 compatible = "rockchip,rk3368-i2s", "rockchip,rk3066-i2s"; 710 reg = <0x0 0xff898000 0x0 0x1000>; 711 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 712 clock-names = "i2s_clk", "i2s_hclk"; 713 clocks = <&cru SCLK_I2S_8CH>, <&cru HCLK_I2S_8CH>; 714 dmas = <&dmac_bus 0>, <&dmac_bus 1>; 715 dma-names = "tx", "rx"; 716 pinctrl-names = "default"; 717 pinctrl-0 = <&i2s_8ch_bus>; 718 status = "disabled"; 719 }; 720 721 iep_mmu: iommu@ff900800 { 722 compatible = "rockchip,iommu"; 723 reg = <0x0 0xff900800 0x0 0x100>; 724 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 725 interrupt-names = "iep_mmu"; 726 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>; 727 clock-names = "aclk", "iface"; 728 #iommu-cells = <0>; 729 status = "disabled"; 730 }; 731 732 isp_mmu: iommu@ff914000 { 733 compatible = "rockchip,iommu"; 734 reg = <0x0 0xff914000 0x0 0x100>, 735 <0x0 0xff915000 0x0 0x100>; 736 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 737 interrupt-names = "isp_mmu"; 738 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>; 739 clock-names = "aclk", "iface"; 740 #iommu-cells = <0>; 741 rockchip,disable-mmu-reset; 742 status = "disabled"; 743 }; 744 745 vop_mmu: iommu@ff930300 { 746 compatible = "rockchip,iommu"; 747 reg = <0x0 0xff930300 0x0 0x100>; 748 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 749 interrupt-names = "vop_mmu"; 750 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; 751 clock-names = "aclk", "iface"; 752 #iommu-cells = <0>; 753 status = "disabled"; 754 }; 755 756 hevc_mmu: iommu@ff9a0440 { 757 compatible = "rockchip,iommu"; 758 reg = <0x0 0xff9a0440 0x0 0x40>, 759 <0x0 0xff9a0480 0x0 0x40>; 760 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 761 interrupt-names = "hevc_mmu"; 762 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; 763 clock-names = "aclk", "iface"; 764 #iommu-cells = <0>; 765 status = "disabled"; 766 }; 767 768 vpu_mmu: iommu@ff9a0800 { 769 compatible = "rockchip,iommu"; 770 reg = <0x0 0xff9a0800 0x0 0x100>; 771 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 773 interrupt-names = "vepu_mmu", "vdpu_mmu"; 774 clocks = <&cru ACLK_VIDEO>, <&cru HCLK_VIDEO>; 775 clock-names = "aclk", "iface"; 776 #iommu-cells = <0>; 777 status = "disabled"; 778 }; 779 780 efuse256: efuse@ffb00000 { 781 compatible = "rockchip,rk3368-efuse"; 782 reg = <0x0 0xffb00000 0x0 0x20>; 783 #address-cells = <1>; 784 #size-cells = <1>; 785 clocks = <&cru PCLK_EFUSE256>; 786 clock-names = "pclk_efuse"; 787 788 cpu_leakage: cpu-leakage@17 { 789 reg = <0x17 0x1>; 790 }; 791 temp_adjust: temp-adjust@1f { 792 reg = <0x1f 0x1>; 793 }; 794 }; 795 796 gic: interrupt-controller@ffb71000 { 797 compatible = "arm,gic-400"; 798 interrupt-controller; 799 #interrupt-cells = <3>; 800 #address-cells = <0>; 801 802 reg = <0x0 0xffb71000 0x0 0x1000>, 803 <0x0 0xffb72000 0x0 0x2000>, 804 <0x0 0xffb74000 0x0 0x2000>, 805 <0x0 0xffb76000 0x0 0x2000>; 806 interrupts = <GIC_PPI 9 807 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 808 }; 809 810 pinctrl: pinctrl { 811 compatible = "rockchip,rk3368-pinctrl"; 812 rockchip,grf = <&grf>; 813 rockchip,pmu = <&pmugrf>; 814 #address-cells = <0x2>; 815 #size-cells = <0x2>; 816 ranges; 817 818 gpio0: gpio0@ff750000 { 819 compatible = "rockchip,gpio-bank"; 820 reg = <0x0 0xff750000 0x0 0x100>; 821 clocks = <&cru PCLK_GPIO0>; 822 interrupts = <GIC_SPI 0x51 IRQ_TYPE_LEVEL_HIGH>; 823 824 gpio-controller; 825 #gpio-cells = <0x2>; 826 827 interrupt-controller; 828 #interrupt-cells = <0x2>; 829 }; 830 831 gpio1: gpio1@ff780000 { 832 compatible = "rockchip,gpio-bank"; 833 reg = <0x0 0xff780000 0x0 0x100>; 834 clocks = <&cru PCLK_GPIO1>; 835 interrupts = <GIC_SPI 0x52 IRQ_TYPE_LEVEL_HIGH>; 836 837 gpio-controller; 838 #gpio-cells = <0x2>; 839 840 interrupt-controller; 841 #interrupt-cells = <0x2>; 842 }; 843 844 gpio2: gpio2@ff790000 { 845 compatible = "rockchip,gpio-bank"; 846 reg = <0x0 0xff790000 0x0 0x100>; 847 clocks = <&cru PCLK_GPIO2>; 848 interrupts = <GIC_SPI 0x53 IRQ_TYPE_LEVEL_HIGH>; 849 850 gpio-controller; 851 #gpio-cells = <0x2>; 852 853 interrupt-controller; 854 #interrupt-cells = <0x2>; 855 }; 856 857 gpio3: gpio3@ff7a0000 { 858 compatible = "rockchip,gpio-bank"; 859 reg = <0x0 0xff7a0000 0x0 0x100>; 860 clocks = <&cru PCLK_GPIO3>; 861 interrupts = <GIC_SPI 0x54 IRQ_TYPE_LEVEL_HIGH>; 862 863 gpio-controller; 864 #gpio-cells = <0x2>; 865 866 interrupt-controller; 867 #interrupt-cells = <0x2>; 868 }; 869 870 pcfg_pull_up: pcfg-pull-up { 871 bias-pull-up; 872 }; 873 874 pcfg_pull_down: pcfg-pull-down { 875 bias-pull-down; 876 }; 877 878 pcfg_pull_none: pcfg-pull-none { 879 bias-disable; 880 }; 881 882 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 883 bias-disable; 884 drive-strength = <12>; 885 }; 886 887 emmc { 888 emmc_clk: emmc-clk { 889 rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>; 890 }; 891 892 emmc_cmd: emmc-cmd { 893 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>; 894 }; 895 896 emmc_pwr: emmc-pwr { 897 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>; 898 }; 899 900 emmc_bus1: emmc-bus1 { 901 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>; 902 }; 903 904 emmc_bus4: emmc-bus4 { 905 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 906 <1 RK_PC3 2 &pcfg_pull_up>, 907 <1 RK_PC4 2 &pcfg_pull_up>, 908 <1 RK_PC5 2 &pcfg_pull_up>; 909 }; 910 911 emmc_bus8: emmc-bus8 { 912 rockchip,pins = <1 RK_PC2 2 &pcfg_pull_up>, 913 <1 RK_PC3 2 &pcfg_pull_up>, 914 <1 RK_PC4 2 &pcfg_pull_up>, 915 <1 RK_PC5 2 &pcfg_pull_up>, 916 <1 RK_PC6 2 &pcfg_pull_up>, 917 <1 RK_PC7 2 &pcfg_pull_up>, 918 <1 RK_PD0 2 &pcfg_pull_up>, 919 <1 RK_PD1 2 &pcfg_pull_up>; 920 }; 921 }; 922 923 gmac { 924 rgmii_pins: rgmii-pins { 925 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, 926 <3 RK_PD0 1 &pcfg_pull_none>, 927 <3 RK_PC3 1 &pcfg_pull_none>, 928 <3 RK_PB0 1 &pcfg_pull_none_12ma>, 929 <3 RK_PB1 1 &pcfg_pull_none_12ma>, 930 <3 RK_PB2 1 &pcfg_pull_none_12ma>, 931 <3 RK_PB6 1 &pcfg_pull_none_12ma>, 932 <3 RK_PD4 1 &pcfg_pull_none_12ma>, 933 <3 RK_PB5 1 &pcfg_pull_none_12ma>, 934 <3 RK_PB7 1 &pcfg_pull_none>, 935 <3 RK_PC0 1 &pcfg_pull_none>, 936 <3 RK_PC1 1 &pcfg_pull_none>, 937 <3 RK_PC2 1 &pcfg_pull_none>, 938 <3 RK_PD1 1 &pcfg_pull_none>, 939 <3 RK_PC4 1 &pcfg_pull_none>; 940 }; 941 942 rmii_pins: rmii-pins { 943 rockchip,pins = <3 RK_PC6 1 &pcfg_pull_none>, 944 <3 RK_PD0 1 &pcfg_pull_none>, 945 <3 RK_PC3 1 &pcfg_pull_none>, 946 <3 RK_PB0 1 &pcfg_pull_none_12ma>, 947 <3 RK_PB1 1 &pcfg_pull_none_12ma>, 948 <3 RK_PB5 1 &pcfg_pull_none_12ma>, 949 <3 RK_PB7 1 &pcfg_pull_none>, 950 <3 RK_PC0 1 &pcfg_pull_none>, 951 <3 RK_PC4 1 &pcfg_pull_none>, 952 <3 RK_PC5 1 &pcfg_pull_none>; 953 }; 954 }; 955 956 i2c0 { 957 i2c0_xfer: i2c0-xfer { 958 rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, 959 <0 RK_PA7 1 &pcfg_pull_none>; 960 }; 961 }; 962 963 i2c1 { 964 i2c1_xfer: i2c1-xfer { 965 rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>, 966 <2 RK_PC6 1 &pcfg_pull_none>; 967 }; 968 }; 969 970 i2c2 { 971 i2c2_xfer: i2c2-xfer { 972 rockchip,pins = <0 RK_PB1 2 &pcfg_pull_none>, 973 <3 RK_PD7 2 &pcfg_pull_none>; 974 }; 975 }; 976 977 i2c3 { 978 i2c3_xfer: i2c3-xfer { 979 rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>, 980 <1 RK_PC1 1 &pcfg_pull_none>; 981 }; 982 }; 983 984 i2c4 { 985 i2c4_xfer: i2c4-xfer { 986 rockchip,pins = <3 RK_PD0 2 &pcfg_pull_none>, 987 <3 RK_PD1 2 &pcfg_pull_none>; 988 }; 989 }; 990 991 i2c5 { 992 i2c5_xfer: i2c5-xfer { 993 rockchip,pins = <3 RK_PD2 2 &pcfg_pull_none>, 994 <3 RK_PD3 2 &pcfg_pull_none>; 995 }; 996 }; 997 998 i2s { 999 i2s_8ch_bus: i2s-8ch-bus { 1000 rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, 1001 <2 RK_PB5 1 &pcfg_pull_none>, 1002 <2 RK_PB6 1 &pcfg_pull_none>, 1003 <2 RK_PB7 1 &pcfg_pull_none>, 1004 <2 RK_PC0 1 &pcfg_pull_none>, 1005 <2 RK_PC1 1 &pcfg_pull_none>, 1006 <2 RK_PC2 1 &pcfg_pull_none>, 1007 <2 RK_PC3 1 &pcfg_pull_none>, 1008 <2 RK_PC4 1 &pcfg_pull_none>; 1009 }; 1010 }; 1011 1012 pwm0 { 1013 pwm0_pin: pwm0-pin { 1014 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_none>; 1015 }; 1016 1017 pwm0_pin_pull_down: pwm0-pin-pull-down { 1018 rockchip,pins = <3 RK_PB0 2 &pcfg_pull_down>; 1019 }; 1020 1021 vop_pwm_pin: vop-pwm { 1022 rockchip,pins = <3 RK_PB0 3 &pcfg_pull_none>; 1023 }; 1024 }; 1025 1026 pwm1 { 1027 pwm1_pin: pwm1-pin { 1028 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>; 1029 }; 1030 1031 pwm1_pin_pull_down: pwm1-pin-pull-down { 1032 rockchip,pins = <0 RK_PB0 2 &pcfg_pull_down>; 1033 }; 1034 }; 1035 1036 pwm3 { 1037 pwm3_pin: pwm3-pin { 1038 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_none>; 1039 }; 1040 1041 pwm3_pin_pull_down: pwm3-pin-pull-down { 1042 rockchip,pins = <3 RK_PD6 3 &pcfg_pull_down>; 1043 }; 1044 }; 1045 1046 sdio0 { 1047 sdio0_bus1: sdio0-bus1 { 1048 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>; 1049 }; 1050 1051 sdio0_bus4: sdio0-bus4 { 1052 rockchip,pins = <2 RK_PD4 1 &pcfg_pull_up>, 1053 <2 RK_PD5 1 &pcfg_pull_up>, 1054 <2 RK_PD6 1 &pcfg_pull_up>, 1055 <2 RK_PD7 1 &pcfg_pull_up>; 1056 }; 1057 1058 sdio0_cmd: sdio0-cmd { 1059 rockchip,pins = <3 RK_PA0 1 &pcfg_pull_up>; 1060 }; 1061 1062 sdio0_clk: sdio0-clk { 1063 rockchip,pins = <3 RK_PA1 1 &pcfg_pull_none>; 1064 }; 1065 1066 sdio0_cd: sdio0-cd { 1067 rockchip,pins = <3 RK_PA2 1 &pcfg_pull_up>; 1068 }; 1069 1070 sdio0_wp: sdio0-wp { 1071 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_up>; 1072 }; 1073 1074 sdio0_pwr: sdio0-pwr { 1075 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_up>; 1076 }; 1077 1078 sdio0_bkpwr: sdio0-bkpwr { 1079 rockchip,pins = <3 RK_PA5 1 &pcfg_pull_up>; 1080 }; 1081 1082 sdio0_int: sdio0-int { 1083 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>; 1084 }; 1085 }; 1086 1087 sdmmc { 1088 sdmmc_clk: sdmmc-clk { 1089 rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; 1090 }; 1091 1092 sdmmc_cmd: sdmmc-cmd { 1093 rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>; 1094 }; 1095 1096 sdmmc_cd: sdmmc-cd { 1097 rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>; 1098 }; 1099 1100 sdmmc_bus1: sdmmc-bus1 { 1101 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>; 1102 }; 1103 1104 sdmmc_bus4: sdmmc-bus4 { 1105 rockchip,pins = <2 RK_PA5 1 &pcfg_pull_up>, 1106 <2 RK_PA6 1 &pcfg_pull_up>, 1107 <2 RK_PA7 1 &pcfg_pull_up>, 1108 <2 RK_PB0 1 &pcfg_pull_up>; 1109 }; 1110 }; 1111 1112 spdif { 1113 spdif_tx: spdif-tx { 1114 rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>; 1115 }; 1116 }; 1117 1118 spi0 { 1119 spi0_clk: spi0-clk { 1120 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_up>; 1121 }; 1122 spi0_cs0: spi0-cs0 { 1123 rockchip,pins = <1 RK_PD0 3 &pcfg_pull_up>; 1124 }; 1125 spi0_cs1: spi0-cs1 { 1126 rockchip,pins = <1 RK_PD1 3 &pcfg_pull_up>; 1127 }; 1128 spi0_tx: spi0-tx { 1129 rockchip,pins = <1 RK_PC7 3 &pcfg_pull_up>; 1130 }; 1131 spi0_rx: spi0-rx { 1132 rockchip,pins = <1 RK_PC6 3 &pcfg_pull_up>; 1133 }; 1134 }; 1135 1136 spi1 { 1137 spi1_clk: spi1-clk { 1138 rockchip,pins = <1 RK_PB6 2 &pcfg_pull_up>; 1139 }; 1140 spi1_cs0: spi1-cs0 { 1141 rockchip,pins = <1 RK_PB7 2 &pcfg_pull_up>; 1142 }; 1143 spi1_cs1: spi1-cs1 { 1144 rockchip,pins = <3 RK_PD4 2 &pcfg_pull_up>; 1145 }; 1146 spi1_rx: spi1-rx { 1147 rockchip,pins = <1 RK_PC0 2 &pcfg_pull_up>; 1148 }; 1149 spi1_tx: spi1-tx { 1150 rockchip,pins = <1 RK_PC1 2 &pcfg_pull_up>; 1151 }; 1152 }; 1153 1154 spi2 { 1155 spi2_clk: spi2-clk { 1156 rockchip,pins = <0 RK_PB4 2 &pcfg_pull_up>; 1157 }; 1158 spi2_cs0: spi2-cs0 { 1159 rockchip,pins = <0 RK_PB5 2 &pcfg_pull_up>; 1160 }; 1161 spi2_rx: spi2-rx { 1162 rockchip,pins = <0 RK_PB2 2 &pcfg_pull_up>; 1163 }; 1164 spi2_tx: spi2-tx { 1165 rockchip,pins = <0 RK_PB3 2 &pcfg_pull_up>; 1166 }; 1167 }; 1168 1169 tsadc { 1170 otp_pin: otp-pin { 1171 rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 1172 }; 1173 1174 otp_out: otp-out { 1175 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>; 1176 }; 1177 }; 1178 1179 uart0 { 1180 uart0_xfer: uart0-xfer { 1181 rockchip,pins = <2 RK_PD0 1 &pcfg_pull_up>, 1182 <2 RK_PD1 1 &pcfg_pull_none>; 1183 }; 1184 1185 uart0_cts: uart0-cts { 1186 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_none>; 1187 }; 1188 1189 uart0_rts: uart0-rts { 1190 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_none>; 1191 }; 1192 }; 1193 1194 uart1 { 1195 uart1_xfer: uart1-xfer { 1196 rockchip,pins = <0 RK_PC4 3 &pcfg_pull_up>, 1197 <0 RK_PC5 3 &pcfg_pull_none>; 1198 }; 1199 1200 uart1_cts: uart1-cts { 1201 rockchip,pins = <0 RK_PC6 3 &pcfg_pull_none>; 1202 }; 1203 1204 uart1_rts: uart1-rts { 1205 rockchip,pins = <0 RK_PC7 3 &pcfg_pull_none>; 1206 }; 1207 }; 1208 1209 uart2 { 1210 uart2_xfer: uart2-xfer { 1211 rockchip,pins = <2 RK_PA6 2 &pcfg_pull_up>, 1212 <2 RK_PA5 2 &pcfg_pull_none>; 1213 }; 1214 /* no rts / cts for uart2 */ 1215 }; 1216 1217 uart3 { 1218 uart3_xfer: uart3-xfer { 1219 rockchip,pins = <3 RK_PD5 2 &pcfg_pull_up>, 1220 <3 RK_PD6 3 &pcfg_pull_none>; 1221 }; 1222 1223 uart3_cts: uart3-cts { 1224 rockchip,pins = <3 RK_PC0 2 &pcfg_pull_none>; 1225 }; 1226 1227 uart3_rts: uart3-rts { 1228 rockchip,pins = <3 RK_PC1 2 &pcfg_pull_none>; 1229 }; 1230 }; 1231 1232 uart4 { 1233 uart4_xfer: uart4-xfer { 1234 rockchip,pins = <0 RK_PD3 3 &pcfg_pull_up>, 1235 <0 RK_PD2 3 &pcfg_pull_none>; 1236 }; 1237 1238 uart4_cts: uart4-cts { 1239 rockchip,pins = <0 RK_PD0 3 &pcfg_pull_none>; 1240 }; 1241 1242 uart4_rts: uart4-rts { 1243 rockchip,pins = <0 RK_PD1 3 &pcfg_pull_none>; 1244 }; 1245 }; 1246 }; 1247}; 1248