xref: /OK3568_Linux_fs/kernel/scripts/dtc/include-prefixes/arm64/rockchip/rk3368-tablet.dts (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2*4882a593Smuzhiyun/*
3*4882a593Smuzhiyun * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun/dts-v1/;
7*4882a593Smuzhiyun#include <dt-bindings/input/input.h>
8*4882a593Smuzhiyun#include <dt-bindings/pwm/pwm.h>
9*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h>
10*4882a593Smuzhiyun#include "rk3368.dtsi"
11*4882a593Smuzhiyun#include "rk3368-android.dtsi"
12*4882a593Smuzhiyun/ {
13*4882a593Smuzhiyun	model = "Rockchip rk3368 tablet board";
14*4882a593Smuzhiyun	compatible = "rockchip,tablet", "rockchip,rk3368";
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun	adc_keys: adc-keys {
17*4882a593Smuzhiyun		compatible = "adc-keys";
18*4882a593Smuzhiyun		io-channels = <&saradc 1>;
19*4882a593Smuzhiyun		io-channel-names = "buttons";
20*4882a593Smuzhiyun		keyup-threshold-microvolt = <1024000>;
21*4882a593Smuzhiyun		poll-interval = <100>;
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun		vol-up-key {
24*4882a593Smuzhiyun			label = "volume up";
25*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEUP>;
26*4882a593Smuzhiyun			press-threshold-microvolt = <1000>;
27*4882a593Smuzhiyun		};
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun		vol-down-key {
30*4882a593Smuzhiyun			label = "volume down";
31*4882a593Smuzhiyun			linux,code = <KEY_VOLUMEDOWN>;
32*4882a593Smuzhiyun			press-threshold-microvolt = <170000>;
33*4882a593Smuzhiyun		};
34*4882a593Smuzhiyun	};
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun	vcc_camera: vcc-camera-regulator {
37*4882a593Smuzhiyun		compatible = "regulator-fixed";
38*4882a593Smuzhiyun		gpio = <&gpio0 RK_PD0 GPIO_ACTIVE_HIGH>;
39*4882a593Smuzhiyun		pinctrl-names = "default";
40*4882a593Smuzhiyun		pinctrl-0 = <&camera_pwr>;
41*4882a593Smuzhiyun		regulator-name = "vcc_camera";
42*4882a593Smuzhiyun		enable-active-high;
43*4882a593Smuzhiyun		regulator-always-on;
44*4882a593Smuzhiyun		regulator-boot-on;
45*4882a593Smuzhiyun	};
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun	backlight: backlight {
48*4882a593Smuzhiyun		compatible = "pwm-backlight";
49*4882a593Smuzhiyun		pwms = <&pwm0 0 25000 1>;
50*4882a593Smuzhiyun		brightness-levels = <
51*4882a593Smuzhiyun			 0   1   2   3   4   5   6   7
52*4882a593Smuzhiyun			 8   9  10  11  12  13  14  15
53*4882a593Smuzhiyun			16  16  16  16  16  16  16  16
54*4882a593Smuzhiyun			17  17  17  17  17  17  17  17
55*4882a593Smuzhiyun			18  18  18  18  18  18  18  18
56*4882a593Smuzhiyun			19  19  19  19  19  19  19  19
57*4882a593Smuzhiyun			20  20  20  20  20  20  20  20
58*4882a593Smuzhiyun			21  21  21  21  21  21  21  21
59*4882a593Smuzhiyun			22  22  22  22  22  22  22  22
60*4882a593Smuzhiyun			23  23  23  23	23  23  23  23
61*4882a593Smuzhiyun			24  24  24  24  24  24  24  24
62*4882a593Smuzhiyun			25  25  25  25  25  25  25  25
63*4882a593Smuzhiyun			26  26  26  26  26  26  26  26
64*4882a593Smuzhiyun			27  27  27  27  27  27  27  27
65*4882a593Smuzhiyun			28  28  28  28  28  28  28  28
66*4882a593Smuzhiyun			27  27  27  27  27  27  27  27
67*4882a593Smuzhiyun			30  30  30  30  30  30  30  30
68*4882a593Smuzhiyun			31  31  31  31  31  31  31  31
69*4882a593Smuzhiyun			32  32  32  32  32  32  32  32
70*4882a593Smuzhiyun			33  33  33  33  33  33  33  33
71*4882a593Smuzhiyun			34  34  34  34  34  34  34  34
72*4882a593Smuzhiyun			35  35  35  35  35  35  35  35
73*4882a593Smuzhiyun			36  36  36  36  36  36  36  36
74*4882a593Smuzhiyun			37  37  37  37  37  37  37  37
75*4882a593Smuzhiyun			38  38  38  38  38  38  38  38
76*4882a593Smuzhiyun			38  38  38  38  38  38  38  38
77*4882a593Smuzhiyun			38  38  38  38  38  38  38  38
78*4882a593Smuzhiyun			38  38  38  38  38  38  38  38
79*4882a593Smuzhiyun			38  38  38  38  38  38  38  38
80*4882a593Smuzhiyun			38  38  38  38  38  38  38  38
81*4882a593Smuzhiyun			38  38  38  38  38  38  38  38
82*4882a593Smuzhiyun			38  38  38  38  38  38  38  38>;
83*4882a593Smuzhiyun		default-brightness-level = <200>;
84*4882a593Smuzhiyun		enable-gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>;
85*4882a593Smuzhiyun	};
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun	charge-animation {
88*4882a593Smuzhiyun		compatible = "rockchip,uboot-charge";
89*4882a593Smuzhiyun		rockchip,uboot-charge-on = <1>;
90*4882a593Smuzhiyun		rockchip,android-charge-on = <0>;
91*4882a593Smuzhiyun		rockchip,uboot-low-power-voltage = <3500>;
92*4882a593Smuzhiyun		rockchip,screen-on-voltage = <3600>;
93*4882a593Smuzhiyun		status = "okay";
94*4882a593Smuzhiyun	};
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun	chosen: chosen {
97*4882a593Smuzhiyun		bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 androidboot.baseband=N/A androidboot.veritymode=enforcing androidboot.hardware=rk30board androidboot.console=ttyFIQ0 init=/init kpti=0";
98*4882a593Smuzhiyun	};
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun	es8316-sound {
101*4882a593Smuzhiyun		compatible = "simple-audio-card";
102*4882a593Smuzhiyun		simple-audio-card,format = "i2s";
103*4882a593Smuzhiyun		simple-audio-card,name = "rockchip,es8316-codec";
104*4882a593Smuzhiyun		simple-audio-card,mclk-fs = <256>;
105*4882a593Smuzhiyun		simple-audio-card,widgets =
106*4882a593Smuzhiyun			"Microphone", "Mic Jack",
107*4882a593Smuzhiyun			"Headphone", "Headphone Jack";
108*4882a593Smuzhiyun		simple-audio-card,routing =
109*4882a593Smuzhiyun			"Mic Jack", "MICBIAS1",
110*4882a593Smuzhiyun			"IN1P", "Mic Jack",
111*4882a593Smuzhiyun			"Headphone Jack", "HPOL",
112*4882a593Smuzhiyun			"Headphone Jack", "HPOR";
113*4882a593Smuzhiyun		simple-audio-card,cpu {
114*4882a593Smuzhiyun			sound-dai = <&i2s_8ch>;
115*4882a593Smuzhiyun			system-clock-frequency = <11289600>;
116*4882a593Smuzhiyun		};
117*4882a593Smuzhiyun		simple-audio-card,codec {
118*4882a593Smuzhiyun			sound-dai = <&es8316>;
119*4882a593Smuzhiyun			system-clock-frequency = <11289600>;
120*4882a593Smuzhiyun		};
121*4882a593Smuzhiyun	};
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun	rk_headset: rk-headset {
124*4882a593Smuzhiyun		compatible = "rockchip_headset";
125*4882a593Smuzhiyun		headset_gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
126*4882a593Smuzhiyun		pinctrl-names = "default";
127*4882a593Smuzhiyun		pinctrl-0 = <&hp_det>;
128*4882a593Smuzhiyun		io-channels = <&saradc 2>;
129*4882a593Smuzhiyun	};
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun	sdio_pwrseq: sdio-pwrseq {
132*4882a593Smuzhiyun		compatible = "mmc-pwrseq-simple";
133*4882a593Smuzhiyun		clocks = <&rk818 1>;
134*4882a593Smuzhiyun		clock-names = "ext_clock";
135*4882a593Smuzhiyun		pinctrl-names = "default";
136*4882a593Smuzhiyun		pinctrl-0 = <&wifi_enable_h>;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun		/*
139*4882a593Smuzhiyun		 * On the module itself this is one of these (depending
140*4882a593Smuzhiyun		 * on the actual card populated):
141*4882a593Smuzhiyun		 * - SDIO_RESET_L_WL_REG_ON
142*4882a593Smuzhiyun		 * - PDN (power down when low)
143*4882a593Smuzhiyun		 */
144*4882a593Smuzhiyun		reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */
145*4882a593Smuzhiyun	};
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun	gpio_keys: gpio-keys {
148*4882a593Smuzhiyun		compatible = "gpio-keys";
149*4882a593Smuzhiyun		autorepeat;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun		power {
152*4882a593Smuzhiyun			debounce-interval = <100>;
153*4882a593Smuzhiyun			gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
154*4882a593Smuzhiyun			label = "GPIO Key Power";
155*4882a593Smuzhiyun			linux,code = <KEY_POWER>;
156*4882a593Smuzhiyun			wakeup-source;
157*4882a593Smuzhiyun		};
158*4882a593Smuzhiyun	};
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun	wireless-wlan {
161*4882a593Smuzhiyun		compatible = "wlan-platdata";
162*4882a593Smuzhiyun		/* wifi_chip_type - wifi chip define
163*4882a593Smuzhiyun		* ap6210, ap6330, ap6335
164*4882a593Smuzhiyun		* rtl8188eu, rtl8723bs, rtl8723bu
165*4882a593Smuzhiyun		* esp8089
166*4882a593Smuzhiyun		*/
167*4882a593Smuzhiyun		wifi_chip_type = "ap6255";
168*4882a593Smuzhiyun		WIFI,host_wake_irq = <&gpio3 6 GPIO_ACTIVE_HIGH>;
169*4882a593Smuzhiyun		status = "okay";
170*4882a593Smuzhiyun	};
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun	wireless-bluetooth {
173*4882a593Smuzhiyun		compatible = "bluetooth-platdata";
174*4882a593Smuzhiyun		clocks = <&rk818 1>;
175*4882a593Smuzhiyun		clock-names = "ext_clock";
176*4882a593Smuzhiyun		uart_rts_gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
177*4882a593Smuzhiyun		pinctrl-names = "default","rts_gpio";
178*4882a593Smuzhiyun		pinctrl-0 = <&uart0_rts>;
179*4882a593Smuzhiyun		pinctrl-1 = <&uart0_rts_gpio>;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun		//BT,power_gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>;
182*4882a593Smuzhiyun		BT,reset_gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>;
183*4882a593Smuzhiyun		BT,wake_gpio = <&gpio3 2 GPIO_ACTIVE_HIGH>;
184*4882a593Smuzhiyun		BT,wake_host_irq = <&gpio3 7 GPIO_ACTIVE_HIGH>;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun		status = "okay";
187*4882a593Smuzhiyun	};
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun	vcc_sys: vcc-sys {
190*4882a593Smuzhiyun		compatible = "regulator-fixed";
191*4882a593Smuzhiyun		regulator-name = "vcc_sys";
192*4882a593Smuzhiyun		regulator-always-on;
193*4882a593Smuzhiyun		regulator-boot-on;
194*4882a593Smuzhiyun		regulator-min-microvolt = <3800000>;
195*4882a593Smuzhiyun		regulator-max-microvolt = <3800000>;
196*4882a593Smuzhiyun	};
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun	vcc_host: vcc-host {
199*4882a593Smuzhiyun		compatible = "regulator-fixed";
200*4882a593Smuzhiyun		enable-active-high;
201*4882a593Smuzhiyun		gpio = <&gpio0 4 GPIO_ACTIVE_HIGH>;
202*4882a593Smuzhiyun		pinctrl-names = "default";
203*4882a593Smuzhiyun		pinctrl-0 = <&host_vbus_drv>;
204*4882a593Smuzhiyun		regulator-name = "vcc_host";
205*4882a593Smuzhiyun		regulator-always-on;
206*4882a593Smuzhiyun	};
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun	xin32k: xin32k {
209*4882a593Smuzhiyun		compatible = "fixed-clock";
210*4882a593Smuzhiyun		clock-frequency = <32768>;
211*4882a593Smuzhiyun		clock-output-names = "xin32k";
212*4882a593Smuzhiyun		#clock-cells = <0>;
213*4882a593Smuzhiyun	};
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun};
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun&cif_clkout {
218*4882a593Smuzhiyun	/* cif_clkout */
219*4882a593Smuzhiyun	rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none_4ma>;
220*4882a593Smuzhiyun};
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun&cpu_l0 {
223*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
224*4882a593Smuzhiyun};
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun&cpu_l1 {
227*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
228*4882a593Smuzhiyun};
229*4882a593Smuzhiyun
230*4882a593Smuzhiyun&cpu_l2 {
231*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
232*4882a593Smuzhiyun};
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun&cpu_l3 {
235*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
236*4882a593Smuzhiyun};
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun&cpu_b0 {
239*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
240*4882a593Smuzhiyun};
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun&cpu_b1 {
243*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
244*4882a593Smuzhiyun};
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun&cpu_b2 {
247*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
248*4882a593Smuzhiyun};
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun&cpu_b3 {
251*4882a593Smuzhiyun	cpu-supply = <&vdd_cpu>;
252*4882a593Smuzhiyun};
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun&gpu {
255*4882a593Smuzhiyun	logic-supply = <&vdd_logic>;
256*4882a593Smuzhiyun};
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun&dfi {
259*4882a593Smuzhiyun	status = "okay";
260*4882a593Smuzhiyun};
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun&dmc {
263*4882a593Smuzhiyun	status = "okay";
264*4882a593Smuzhiyun	center-supply = <&vdd_logic>;
265*4882a593Smuzhiyun	devfreq-events = <&dfi>;
266*4882a593Smuzhiyun	upthreshold = <60>;
267*4882a593Smuzhiyun	downdifferential = <20>;
268*4882a593Smuzhiyun	system-status-freq = <
269*4882a593Smuzhiyun		/*system status		freq(KHz)*/
270*4882a593Smuzhiyun		SYS_STATUS_NORMAL	600000
271*4882a593Smuzhiyun		SYS_STATUS_REBOOT	600000
272*4882a593Smuzhiyun		SYS_STATUS_SUSPEND	240000
273*4882a593Smuzhiyun		SYS_STATUS_VIDEO_1080P	396000
274*4882a593Smuzhiyun		SYS_STATUS_VIDEO_4K	600000
275*4882a593Smuzhiyun		SYS_STATUS_PERFORMANCE	600000
276*4882a593Smuzhiyun		SYS_STATUS_BOOST	396000
277*4882a593Smuzhiyun		SYS_STATUS_DUALVIEW	600000
278*4882a593Smuzhiyun		SYS_STATUS_ISP		528000
279*4882a593Smuzhiyun	>;
280*4882a593Smuzhiyun	vop-bw-dmc-freq = <
281*4882a593Smuzhiyun	/* min_bw(MB/s) max_bw(MB/s) freq(KHz) */
282*4882a593Smuzhiyun		0       582      240000
283*4882a593Smuzhiyun		583     99999    396000
284*4882a593Smuzhiyun	>;
285*4882a593Smuzhiyun	auto-min-freq = <240000>;
286*4882a593Smuzhiyun	auto-freq-en = <1>;
287*4882a593Smuzhiyun};
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun&dsi {
290*4882a593Smuzhiyun	status = "okay";
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun	panel@0 {
293*4882a593Smuzhiyun		compatible = "simple-panel-dsi";
294*4882a593Smuzhiyun		reg = <0>;
295*4882a593Smuzhiyun		backlight = <&backlight>;
296*4882a593Smuzhiyun		enable-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
297*4882a593Smuzhiyun		back-gpios = <&gpio2 RK_PC3 GPIO_ACTIVE_HIGH>;
298*4882a593Smuzhiyun		reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_LOW>;
299*4882a593Smuzhiyun		prepare-delay-ms = <8>;
300*4882a593Smuzhiyun		enable-delay-ms = <3>;
301*4882a593Smuzhiyun		reset-delay-ms = <50>;
302*4882a593Smuzhiyun		init-delay-ms = <20>;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun		dsi,flags = <(MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
305*4882a593Smuzhiyun			      MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_EOT_PACKET)>;
306*4882a593Smuzhiyun		dsi,format = <MIPI_DSI_FMT_RGB888>;
307*4882a593Smuzhiyun		dsi,lanes = <4>;
308*4882a593Smuzhiyun		width-mm = <153>;
309*4882a593Smuzhiyun		height-mm = <85>;
310*4882a593Smuzhiyun		panel-init-sequence = [
311*4882a593Smuzhiyun			05 1e 01 01
312*4882a593Smuzhiyun			15 00 02 80 47
313*4882a593Smuzhiyun			15 00 02 81 40
314*4882a593Smuzhiyun			15 00 02 82 04
315*4882a593Smuzhiyun			15 00 02 83 77
316*4882a593Smuzhiyun			15 00 02 84 0f
317*4882a593Smuzhiyun			15 00 02 85 70
318*4882a593Smuzhiyun			15 78 02 86 70
319*4882a593Smuzhiyun		];
320*4882a593Smuzhiyun		panel-exit-sequence = [
321*4882a593Smuzhiyun			05 00 01 28
322*4882a593Smuzhiyun			05 00 01 10
323*4882a593Smuzhiyun		];
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun		display-timings {
326*4882a593Smuzhiyun			native-mode = <&timing0>;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun			timing0: timing0 {
329*4882a593Smuzhiyun				clock-frequency = <49500000>;
330*4882a593Smuzhiyun				hactive = <1024>;
331*4882a593Smuzhiyun				vactive = <600>;
332*4882a593Smuzhiyun				hback-porch = <120>;
333*4882a593Smuzhiyun				hfront-porch = <80>;
334*4882a593Smuzhiyun				vback-porch = <14>;
335*4882a593Smuzhiyun				vfront-porch = <14>;
336*4882a593Smuzhiyun				hsync-len = <40>;
337*4882a593Smuzhiyun				vsync-len = <4>;
338*4882a593Smuzhiyun				hsync-active = <0>;
339*4882a593Smuzhiyun				vsync-active = <0>;
340*4882a593Smuzhiyun				de-active = <0>;
341*4882a593Smuzhiyun				pixelclk-active = <0>;
342*4882a593Smuzhiyun			};
343*4882a593Smuzhiyun		};
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun		ports {
346*4882a593Smuzhiyun			#address-cells = <1>;
347*4882a593Smuzhiyun			#size-cells = <0>;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun			port@0 {
350*4882a593Smuzhiyun				reg = <0>;
351*4882a593Smuzhiyun				panel_in_dsi: endpoint {
352*4882a593Smuzhiyun					remote-endpoint = <&dsi_out_panel>;
353*4882a593Smuzhiyun				};
354*4882a593Smuzhiyun			};
355*4882a593Smuzhiyun		};
356*4882a593Smuzhiyun	};
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun	ports {
359*4882a593Smuzhiyun		#address-cells = <1>;
360*4882a593Smuzhiyun		#size-cells = <0>;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun		port@1 {
363*4882a593Smuzhiyun			reg = <1>;
364*4882a593Smuzhiyun			dsi_out_panel: endpoint {
365*4882a593Smuzhiyun				remote-endpoint = <&panel_in_dsi>;
366*4882a593Smuzhiyun			};
367*4882a593Smuzhiyun		};
368*4882a593Smuzhiyun	};
369*4882a593Smuzhiyun};
370*4882a593Smuzhiyun
371*4882a593Smuzhiyun&emmc {
372*4882a593Smuzhiyun	bus-width = <8>;
373*4882a593Smuzhiyun	cap-mmc-highspeed;
374*4882a593Smuzhiyun	mmc-hs200-1_8v;
375*4882a593Smuzhiyun	no-sdio;
376*4882a593Smuzhiyun	no-sd;
377*4882a593Smuzhiyun	disable-wp;
378*4882a593Smuzhiyun	non-removable;
379*4882a593Smuzhiyun	num-slots = <1>;
380*4882a593Smuzhiyun	status = "okay";
381*4882a593Smuzhiyun};
382*4882a593Smuzhiyun
383*4882a593Smuzhiyun&i2c0 {
384*4882a593Smuzhiyun	status = "okay";
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun		vdd_cpu: tcs4526@10 {
387*4882a593Smuzhiyun		compatible = "tcs,tcs4526";
388*4882a593Smuzhiyun		reg = <0x10>;
389*4882a593Smuzhiyun		regulator-compatible = "fan53555-reg";
390*4882a593Smuzhiyun		pinctrl-0 = <&vsel_gpio>;
391*4882a593Smuzhiyun		vsel-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
392*4882a593Smuzhiyun		regulator-name = "vdd_cpu";
393*4882a593Smuzhiyun		regulator-min-microvolt = <712500>;
394*4882a593Smuzhiyun		regulator-max-microvolt = <1390000>;
395*4882a593Smuzhiyun		regulator-ramp-delay = <2300>;
396*4882a593Smuzhiyun		fcs,suspend-voltage-selector = <1>;
397*4882a593Smuzhiyun		regulator-boot-on;
398*4882a593Smuzhiyun		regulator-always-on;
399*4882a593Smuzhiyun		regulator-state-mem {
400*4882a593Smuzhiyun			regulator-off-in-suspend;
401*4882a593Smuzhiyun		};
402*4882a593Smuzhiyun	};
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun	rk818: pmic@1c {
405*4882a593Smuzhiyun		compatible = "rockchip,rk818";
406*4882a593Smuzhiyun		status = "okay";
407*4882a593Smuzhiyun		reg = <0x1c>;
408*4882a593Smuzhiyun		clock-output-names = "rk818-clkout1", "wifibt_32kin";
409*4882a593Smuzhiyun		interrupt-parent = <&gpio0>;
410*4882a593Smuzhiyun		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
411*4882a593Smuzhiyun		pinctrl-names = "default";
412*4882a593Smuzhiyun		pinctrl-0 = <&pmic_int_l>;
413*4882a593Smuzhiyun		rockchip,system-power-controller;
414*4882a593Smuzhiyun		wakeup-source;
415*4882a593Smuzhiyun		extcon = <&u2phy>;
416*4882a593Smuzhiyun		#clock-cells = <1>;
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun		vcc1-supply = <&vcc_sys>;
419*4882a593Smuzhiyun		vcc2-supply = <&vcc_sys>;
420*4882a593Smuzhiyun		vcc3-supply = <&vcc_sys>;
421*4882a593Smuzhiyun		vcc4-supply = <&vcc_sys>;
422*4882a593Smuzhiyun		vcc6-supply = <&vcc_sys>;
423*4882a593Smuzhiyun		vcc7-supply = <&vcc_sys>;
424*4882a593Smuzhiyun		vcc8-supply = <&vcc_sys>;
425*4882a593Smuzhiyun		vcc9-supply = <&vcc_io>;
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun		regulators {
428*4882a593Smuzhiyun			vdd_logic: DCDC_REG1 {
429*4882a593Smuzhiyun				regulator-name = "vdd_logic";
430*4882a593Smuzhiyun				regulator-always-on;
431*4882a593Smuzhiyun				regulator-boot-on;
432*4882a593Smuzhiyun				regulator-min-microvolt = <750000>;
433*4882a593Smuzhiyun				regulator-max-microvolt = <1450000>;
434*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
435*4882a593Smuzhiyun				regulator-state-mem {
436*4882a593Smuzhiyun					regulator-on-in-suspend;
437*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
438*4882a593Smuzhiyun				};
439*4882a593Smuzhiyun			};
440*4882a593Smuzhiyun
441*4882a593Smuzhiyun			vdd_gpu: DCDC_REG2 {
442*4882a593Smuzhiyun				regulator-name = "vdd_gpu";
443*4882a593Smuzhiyun				regulator-always-on;
444*4882a593Smuzhiyun				regulator-boot-on;
445*4882a593Smuzhiyun				regulator-min-microvolt = <800000>;
446*4882a593Smuzhiyun				regulator-max-microvolt = <1250000>;
447*4882a593Smuzhiyun				regulator-ramp-delay = <6001>;
448*4882a593Smuzhiyun				regulator-state-mem {
449*4882a593Smuzhiyun					regulator-on-in-suspend;
450*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
451*4882a593Smuzhiyun				};
452*4882a593Smuzhiyun			};
453*4882a593Smuzhiyun
454*4882a593Smuzhiyun			vcc_ddr: DCDC_REG3 {
455*4882a593Smuzhiyun				regulator-always-on;
456*4882a593Smuzhiyun				regulator-boot-on;
457*4882a593Smuzhiyun				regulator-name = "vcc_ddr";
458*4882a593Smuzhiyun				regulator-state-mem {
459*4882a593Smuzhiyun					regulator-on-in-suspend;
460*4882a593Smuzhiyun				};
461*4882a593Smuzhiyun			};
462*4882a593Smuzhiyun
463*4882a593Smuzhiyun			vcc_io: DCDC_REG4 {
464*4882a593Smuzhiyun				regulator-always-on;
465*4882a593Smuzhiyun				regulator-boot-on;
466*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
467*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
468*4882a593Smuzhiyun				regulator-name = "vcc_io";
469*4882a593Smuzhiyun				regulator-state-mem {
470*4882a593Smuzhiyun					regulator-on-in-suspend;
471*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
472*4882a593Smuzhiyun				};
473*4882a593Smuzhiyun			};
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun			vcca_codec: LDO_REG1 {
476*4882a593Smuzhiyun				regulator-always-on;
477*4882a593Smuzhiyun				regulator-boot-on;
478*4882a593Smuzhiyun				regulator-min-microvolt = <3300000>;
479*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
480*4882a593Smuzhiyun				regulator-name = "vcca_codec";
481*4882a593Smuzhiyun				regulator-state-mem {
482*4882a593Smuzhiyun					regulator-on-in-suspend;
483*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
484*4882a593Smuzhiyun				};
485*4882a593Smuzhiyun			};
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun			vcc_tp: LDO_REG2 {
488*4882a593Smuzhiyun				regulator-boot-on;
489*4882a593Smuzhiyun				regulator-min-microvolt = <3000000>;
490*4882a593Smuzhiyun				regulator-max-microvolt = <3000000>;
491*4882a593Smuzhiyun				regulator-name = "vcc_tp";
492*4882a593Smuzhiyun				regulator-state-mem {
493*4882a593Smuzhiyun					regulator-off-in-suspend;
494*4882a593Smuzhiyun				};
495*4882a593Smuzhiyun			};
496*4882a593Smuzhiyun
497*4882a593Smuzhiyun			vdd_10: LDO_REG3 {
498*4882a593Smuzhiyun				regulator-always-on;
499*4882a593Smuzhiyun				regulator-boot-on;
500*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
501*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
502*4882a593Smuzhiyun				regulator-name = "vdd_10";
503*4882a593Smuzhiyun				regulator-state-mem {
504*4882a593Smuzhiyun					regulator-on-in-suspend;
505*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
506*4882a593Smuzhiyun				};
507*4882a593Smuzhiyun			};
508*4882a593Smuzhiyun
509*4882a593Smuzhiyun			vcc18_lcd: LDO_REG4 {
510*4882a593Smuzhiyun				regulator-always-on;
511*4882a593Smuzhiyun				regulator-boot-on;
512*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
513*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
514*4882a593Smuzhiyun				regulator-name = "vcc18_lcd";
515*4882a593Smuzhiyun				regulator-state-mem {
516*4882a593Smuzhiyun					regulator-on-in-suspend;
517*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
518*4882a593Smuzhiyun				};
519*4882a593Smuzhiyun			};
520*4882a593Smuzhiyun
521*4882a593Smuzhiyun			vccio_pmu: LDO_REG5 {
522*4882a593Smuzhiyun				regulator-always-on;
523*4882a593Smuzhiyun				regulator-boot-on;
524*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
525*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
526*4882a593Smuzhiyun				regulator-name = "vccio_pmu";
527*4882a593Smuzhiyun				regulator-state-mem {
528*4882a593Smuzhiyun					regulator-on-in-suspend;
529*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
530*4882a593Smuzhiyun				};
531*4882a593Smuzhiyun			};
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun			vdd10_lcd: LDO_REG6 {
534*4882a593Smuzhiyun				regulator-always-on;
535*4882a593Smuzhiyun				regulator-boot-on;
536*4882a593Smuzhiyun				regulator-min-microvolt = <1000000>;
537*4882a593Smuzhiyun				regulator-max-microvolt = <1000000>;
538*4882a593Smuzhiyun				regulator-name = "vdd10_lcd";
539*4882a593Smuzhiyun				regulator-state-mem {
540*4882a593Smuzhiyun					regulator-on-in-suspend;
541*4882a593Smuzhiyun					regulator-suspend-microvolt = <1000000>;
542*4882a593Smuzhiyun				};
543*4882a593Smuzhiyun			};
544*4882a593Smuzhiyun
545*4882a593Smuzhiyun			vcc_18: LDO_REG7 {
546*4882a593Smuzhiyun				regulator-always-on;
547*4882a593Smuzhiyun				regulator-boot-on;
548*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
549*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
550*4882a593Smuzhiyun				regulator-name = "vcc_18";
551*4882a593Smuzhiyun				regulator-state-mem {
552*4882a593Smuzhiyun					regulator-on-in-suspend;
553*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
554*4882a593Smuzhiyun				};
555*4882a593Smuzhiyun			};
556*4882a593Smuzhiyun
557*4882a593Smuzhiyun			vccio_wl: LDO_REG8 {
558*4882a593Smuzhiyun				regulator-always-on;
559*4882a593Smuzhiyun				regulator-boot-on;
560*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
561*4882a593Smuzhiyun				regulator-max-microvolt = <1800000>;
562*4882a593Smuzhiyun				regulator-name = "vccio_wl";
563*4882a593Smuzhiyun				regulator-state-mem {
564*4882a593Smuzhiyun					regulator-on-in-suspend;
565*4882a593Smuzhiyun					regulator-suspend-microvolt = <1800000>;
566*4882a593Smuzhiyun				};
567*4882a593Smuzhiyun			};
568*4882a593Smuzhiyun
569*4882a593Smuzhiyun			vccio_sd: LDO_REG9 {
570*4882a593Smuzhiyun				regulator-always-on;
571*4882a593Smuzhiyun				regulator-boot-on;
572*4882a593Smuzhiyun				regulator-min-microvolt = <1800000>;
573*4882a593Smuzhiyun				regulator-max-microvolt = <3300000>;
574*4882a593Smuzhiyun				regulator-name = "vccio_sd";
575*4882a593Smuzhiyun				regulator-state-mem {
576*4882a593Smuzhiyun					regulator-on-in-suspend;
577*4882a593Smuzhiyun					regulator-suspend-microvolt = <3300000>;
578*4882a593Smuzhiyun				};
579*4882a593Smuzhiyun			};
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun			vcc_sd: SWITCH_REG {
582*4882a593Smuzhiyun				regulator-always-on;
583*4882a593Smuzhiyun				regulator-boot-on;
584*4882a593Smuzhiyun				regulator-name = "vcc_sd";
585*4882a593Smuzhiyun				regulator-state-mem {
586*4882a593Smuzhiyun					regulator-on-in-suspend;
587*4882a593Smuzhiyun				};
588*4882a593Smuzhiyun			};
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun			boost_otg: DCDC_BOOST {
591*4882a593Smuzhiyun				regulator-name = "boost_otg";
592*4882a593Smuzhiyun				regulator-always-on;
593*4882a593Smuzhiyun				regulator-boot-on;
594*4882a593Smuzhiyun				regulator-min-microvolt = <5000000>;
595*4882a593Smuzhiyun				regulator-max-microvolt = <5000000>;
596*4882a593Smuzhiyun				regulator-state-mem {
597*4882a593Smuzhiyun					regulator-on-in-suspend;
598*4882a593Smuzhiyun					regulator-suspend-microvolt = <5000000>;
599*4882a593Smuzhiyun				};
600*4882a593Smuzhiyun			};
601*4882a593Smuzhiyun
602*4882a593Smuzhiyun			otg_switch: OTG_SWITCH {
603*4882a593Smuzhiyun				regulator-name = "otg_switch";
604*4882a593Smuzhiyun			};
605*4882a593Smuzhiyun		};
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun		battery {
608*4882a593Smuzhiyun			compatible = "rk818-battery";
609*4882a593Smuzhiyun			pinctrl-names = "default";
610*4882a593Smuzhiyun			pinctrl-0 = <&dc_irq_gpio>;
611*4882a593Smuzhiyun			ocv_table = <
612*4882a593Smuzhiyun				3400 3652 3680 3707 3730 3747 3764
613*4882a593Smuzhiyun				3772 3781 3792 3807 3828 3861 3899
614*4882a593Smuzhiyun				3929 3958 3987 4038 4079 4127 4186>;
615*4882a593Smuzhiyun			design_capacity = <7536>;
616*4882a593Smuzhiyun			design_qmax = <8290>;
617*4882a593Smuzhiyun			bat_res = <100>;
618*4882a593Smuzhiyun			max_input_current = <1750>;
619*4882a593Smuzhiyun			max_chrg_current = <2000>;
620*4882a593Smuzhiyun			max_chrg_voltage = <4200>;
621*4882a593Smuzhiyun			sleep_enter_current = <600>;
622*4882a593Smuzhiyun			sleep_exit_current = <600>;
623*4882a593Smuzhiyun			power_off_thresd = <3400>;
624*4882a593Smuzhiyun			zero_algorithm_vol = <3850>;
625*4882a593Smuzhiyun			fb_temperature = <115>;
626*4882a593Smuzhiyun			sample_res = <20>;
627*4882a593Smuzhiyun			max_soc_offset = <60>;
628*4882a593Smuzhiyun			energy_mode = <0>;
629*4882a593Smuzhiyun			monitor_sec = <5>;
630*4882a593Smuzhiyun			virtual_power = <0>;
631*4882a593Smuzhiyun			power_dc2otg = <0>;
632*4882a593Smuzhiyun			support_usb_adp = <1>;
633*4882a593Smuzhiyun			support_dc_adp = <1>;
634*4882a593Smuzhiyun			dc_det_gpio = <&gpio0 17 GPIO_ACTIVE_LOW>;
635*4882a593Smuzhiyun		};
636*4882a593Smuzhiyun	};
637*4882a593Smuzhiyun};
638*4882a593Smuzhiyun
639*4882a593Smuzhiyun&i2c1 {
640*4882a593Smuzhiyun	status = "okay";
641*4882a593Smuzhiyun
642*4882a593Smuzhiyun	es8316: es8316@10 {
643*4882a593Smuzhiyun		status = "okay";
644*4882a593Smuzhiyun		#sound-dai-cells = <0>;
645*4882a593Smuzhiyun		compatible = "everest,es8316";
646*4882a593Smuzhiyun		reg = <0x10>;
647*4882a593Smuzhiyun		clocks = <&cru SCLK_I2S_8CH_OUT>;
648*4882a593Smuzhiyun		clock-names = "mclk";
649*4882a593Smuzhiyun		spk-con-gpio = <&gpio0 27 GPIO_ACTIVE_HIGH>;
650*4882a593Smuzhiyun		hp-det-gpio = <&gpio0 23 GPIO_ACTIVE_HIGH>;
651*4882a593Smuzhiyun		pinctrl-names = "default";
652*4882a593Smuzhiyun		pinctrl-0 = <&i2s_8ch_mclk>;
653*4882a593Smuzhiyun		extcon = <&rk_headset>;
654*4882a593Smuzhiyun	};
655*4882a593Smuzhiyun};
656*4882a593Smuzhiyun
657*4882a593Smuzhiyun&i2c2 {
658*4882a593Smuzhiyun	status = "okay";
659*4882a593Smuzhiyun
660*4882a593Smuzhiyun	ts@5a {
661*4882a593Smuzhiyun		compatible = "cst2xxse";
662*4882a593Smuzhiyun		reg = <0x5a>;
663*4882a593Smuzhiyun		irq-gpio = <&gpio0 RK_PB4 IRQ_TYPE_LEVEL_LOW>;
664*4882a593Smuzhiyun		//touch-gpio = <&gpio1 GPIO_B0 IRQ_TYPE_LEVEL_LOW>;       /* TP_INT == GPIO1_B0 */
665*4882a593Smuzhiyun		//reset-gpio = <&gpio0 GPIO_D1 GPIO_ACTIVE_LOW>;          /* TP_RST == GPIO0_D1 */
666*4882a593Smuzhiyun		//power-gpio = <&gpio0 GPIO_C5 GPIO_ACTIVE_LOW>;
667*4882a593Smuzhiyun		//max-x = <800>;
668*4882a593Smuzhiyun		//max-y = <480>;
669*4882a593Smuzhiyun		status = "okay";
670*4882a593Smuzhiyun	};
671*4882a593Smuzhiyun
672*4882a593Smuzhiyun};
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun&i2c3 {
675*4882a593Smuzhiyun	status = "okay";
676*4882a593Smuzhiyun
677*4882a593Smuzhiyun	gc0312: gc0312@21 {
678*4882a593Smuzhiyun		status = "okay";
679*4882a593Smuzhiyun		compatible = "galaxycore,gc0312";
680*4882a593Smuzhiyun		reg = <0x21>;
681*4882a593Smuzhiyun		clocks = <&cru SCLK_VIP_OUT>;
682*4882a593Smuzhiyun		clock-names = "xvclk";
683*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
684*4882a593Smuzhiyun
685*4882a593Smuzhiyun		rockchip,camera-module-index = <1>;
686*4882a593Smuzhiyun		rockchip,camera-module-facing = "front";
687*4882a593Smuzhiyun		rockchip,camera-module-name = "CameraKing";
688*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan";
689*4882a593Smuzhiyun		port {
690*4882a593Smuzhiyun			gc0312_out: endpoint {
691*4882a593Smuzhiyun				remote-endpoint = <&dvp_in_fcam>;
692*4882a593Smuzhiyun			};
693*4882a593Smuzhiyun		};
694*4882a593Smuzhiyun	};
695*4882a593Smuzhiyun
696*4882a593Smuzhiyun	gc2145: gc2145@3c {
697*4882a593Smuzhiyun		status = "okay";
698*4882a593Smuzhiyun		compatible = "galaxycore,gc2145";
699*4882a593Smuzhiyun		reg = <0x3c>;
700*4882a593Smuzhiyun		clocks = <&cru SCLK_VIP_OUT>;
701*4882a593Smuzhiyun		clock-names = "xvclk";
702*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
703*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
704*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
705*4882a593Smuzhiyun		rockchip,camera-module-name = "CameraKing";
706*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan";
707*4882a593Smuzhiyun		port {
708*4882a593Smuzhiyun			gc2145_out: endpoint {
709*4882a593Smuzhiyun				remote-endpoint = <&dvp_in_bcam>;
710*4882a593Smuzhiyun			};
711*4882a593Smuzhiyun		};
712*4882a593Smuzhiyun	};
713*4882a593Smuzhiyun
714*4882a593Smuzhiyun	ov8858: ov8858@36 {
715*4882a593Smuzhiyun		status = "disabled";
716*4882a593Smuzhiyun		compatible = "ovti,ov8858";
717*4882a593Smuzhiyun		reg = <0x36>;
718*4882a593Smuzhiyun		clocks = <&cru SCLK_VIP_OUT>;
719*4882a593Smuzhiyun		clock-names = "xvclk";
720*4882a593Smuzhiyun
721*4882a593Smuzhiyun		rockchip,camera-module-index = <0>;
722*4882a593Smuzhiyun		rockchip,camera-module-facing = "back";
723*4882a593Smuzhiyun		rockchip,camera-module-name = "CameraKing";
724*4882a593Smuzhiyun		rockchip,camera-module-lens-name = "Largan-9569A2";
725*4882a593Smuzhiyun		power-gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
726*4882a593Smuzhiyun		pwdn-gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_HIGH>;
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun		port {
729*4882a593Smuzhiyun			ov8858_out: endpoint {
730*4882a593Smuzhiyun				remote-endpoint = <&mipi_in>;
731*4882a593Smuzhiyun				data-lanes = <1 2>;
732*4882a593Smuzhiyun			};
733*4882a593Smuzhiyun		};
734*4882a593Smuzhiyun	};
735*4882a593Smuzhiyun};
736*4882a593Smuzhiyun
737*4882a593Smuzhiyun&i2c4 {
738*4882a593Smuzhiyun	status = "okay";
739*4882a593Smuzhiyun
740*4882a593Smuzhiyun	mpu6500@68 {
741*4882a593Smuzhiyun		status = "disabled";
742*4882a593Smuzhiyun		compatible = "invensense,mpu6500";
743*4882a593Smuzhiyun		pinctrl-names = "default";
744*4882a593Smuzhiyun		pinctrl-0 = <&mpu6500_irq_gpio>;
745*4882a593Smuzhiyun		reg = <0x68>;
746*4882a593Smuzhiyun		irq-gpio = <&gpio3 14 IRQ_TYPE_EDGE_RISING>;
747*4882a593Smuzhiyun		mpu-int_config = <0x10>;
748*4882a593Smuzhiyun		mpu-level_shifter = <0>;
749*4882a593Smuzhiyun		mpu-orientation = <1 0 0 0 1 0 0 0 1>;
750*4882a593Smuzhiyun		orientation-x= <1>;
751*4882a593Smuzhiyun		orientation-y= <0>;
752*4882a593Smuzhiyun		orientation-z= <1>;
753*4882a593Smuzhiyun		support-hw-poweroff = <1>;
754*4882a593Smuzhiyun		mpu-debug = <1>;
755*4882a593Smuzhiyun	};
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun	sensor@4c {
758*4882a593Smuzhiyun		status = "okay";
759*4882a593Smuzhiyun		compatible = "gs_mc3230";
760*4882a593Smuzhiyun		reg = <0x4c>;
761*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
762*4882a593Smuzhiyun		irq_enable = <0>;
763*4882a593Smuzhiyun		poll_delay_ms = <30>;
764*4882a593Smuzhiyun		layout = <9>;
765*4882a593Smuzhiyun		reprobe_en = <1>;
766*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PB6 IRQ_TYPE_LEVEL_LOW>;
767*4882a593Smuzhiyun	};
768*4882a593Smuzhiyun
769*4882a593Smuzhiyun	sensor@18 {
770*4882a593Smuzhiyun		status = "okay";
771*4882a593Smuzhiyun		compatible = "gs_sc7a30";
772*4882a593Smuzhiyun		reg = <0x18>;
773*4882a593Smuzhiyun		type = <SENSOR_TYPE_ACCEL>;
774*4882a593Smuzhiyun		irq-gpio = <&gpio3 RK_PB6 IRQ_TYPE_LEVEL_LOW>;
775*4882a593Smuzhiyun		irq_enable = <0>;
776*4882a593Smuzhiyun		poll_delay_ms = <30>;
777*4882a593Smuzhiyun		layout = <6>;
778*4882a593Smuzhiyun		reprobe_en = <1>;
779*4882a593Smuzhiyun	};
780*4882a593Smuzhiyun
781*4882a593Smuzhiyun	sensor@10 {
782*4882a593Smuzhiyun		status = "okay";
783*4882a593Smuzhiyun		compatible = "light_cm3218";
784*4882a593Smuzhiyun		pinctrl-names = "default";
785*4882a593Smuzhiyun		pinctrl-0 = <&cm3218_irq_gpio>;
786*4882a593Smuzhiyun		reg = <0x10>;
787*4882a593Smuzhiyun		type = <SENSOR_TYPE_LIGHT>;
788*4882a593Smuzhiyun		irq-gpio = <&gpio3 15 IRQ_TYPE_EDGE_FALLING>;
789*4882a593Smuzhiyun		irq_enable = <1>;
790*4882a593Smuzhiyun		poll_delay_ms = <30>;
791*4882a593Smuzhiyun	};
792*4882a593Smuzhiyun};
793*4882a593Smuzhiyun
794*4882a593Smuzhiyun&i2s_8ch {
795*4882a593Smuzhiyun	status = "okay";
796*4882a593Smuzhiyun	rockchip,i2s-broken-burst-len;
797*4882a593Smuzhiyun	rockchip,playback-channels = <8>;
798*4882a593Smuzhiyun	rockchip,capture-channels = <2>;
799*4882a593Smuzhiyun	#sound-dai-cells = <0>;
800*4882a593Smuzhiyun};
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun&io_domains {
803*4882a593Smuzhiyun	status = "okay";
804*4882a593Smuzhiyun
805*4882a593Smuzhiyun	dvp-supply = <&vcc_18>;
806*4882a593Smuzhiyun	audio-supply = <&vcc_io>;
807*4882a593Smuzhiyun	gpio30-supply = <&vcc_io>;
808*4882a593Smuzhiyun	gpio1830-supply = <&vcc_io>;
809*4882a593Smuzhiyun	sdcard-supply = <&vccio_sd>;
810*4882a593Smuzhiyun	wifi-supply = <&vccio_wl>;
811*4882a593Smuzhiyun};
812*4882a593Smuzhiyun
813*4882a593Smuzhiyun&isp_dvp_d2d9 {
814*4882a593Smuzhiyun	rockchip,pins =
815*4882a593Smuzhiyun			/* cif_data4 ... cif_data9 */
816*4882a593Smuzhiyun			<1 RK_PA2 1 &pcfg_pull_down>,
817*4882a593Smuzhiyun			<1 RK_PA3 1 &pcfg_pull_down>,
818*4882a593Smuzhiyun			<1 RK_PA4 1 &pcfg_pull_down>,
819*4882a593Smuzhiyun			<1 RK_PA5 1 &pcfg_pull_down>,
820*4882a593Smuzhiyun			<1 RK_PA6 1 &pcfg_pull_down>,
821*4882a593Smuzhiyun			<1 RK_PA7 1 &pcfg_pull_down>,
822*4882a593Smuzhiyun			/* cif_sync, cif_href */
823*4882a593Smuzhiyun			<1 RK_PB0 1 &pcfg_pull_down>,
824*4882a593Smuzhiyun			<1 RK_PB1 1 &pcfg_pull_down>,
825*4882a593Smuzhiyun			/* cif_clkin */
826*4882a593Smuzhiyun			<1 RK_PB2 1 &pcfg_pull_down>;
827*4882a593Smuzhiyun};
828*4882a593Smuzhiyun
829*4882a593Smuzhiyun&isp_dvp_d10d11 {
830*4882a593Smuzhiyun	rockchip,pins =
831*4882a593Smuzhiyun			/* cif_data10, cif_data11 */
832*4882a593Smuzhiyun			<1 RK_PB6 1 &pcfg_pull_down>,
833*4882a593Smuzhiyun			<1 RK_PB7 1 &pcfg_pull_down>;
834*4882a593Smuzhiyun};
835*4882a593Smuzhiyun
836*4882a593Smuzhiyun&isp_mmu {
837*4882a593Smuzhiyun	status = "okay";
838*4882a593Smuzhiyun};
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun&mipi_dphy_rx0 {
841*4882a593Smuzhiyun	status = "disabled";
842*4882a593Smuzhiyun
843*4882a593Smuzhiyun	ports {
844*4882a593Smuzhiyun		#address-cells = <1>;
845*4882a593Smuzhiyun		#size-cells = <0>;
846*4882a593Smuzhiyun
847*4882a593Smuzhiyun		port@0 {
848*4882a593Smuzhiyun			reg = <0>;
849*4882a593Smuzhiyun			#address-cells = <1>;
850*4882a593Smuzhiyun			#size-cells = <0>;
851*4882a593Smuzhiyun
852*4882a593Smuzhiyun			mipi_in: endpoint@1 {
853*4882a593Smuzhiyun				reg = <1>;
854*4882a593Smuzhiyun				remote-endpoint = <&ov8858_out>;
855*4882a593Smuzhiyun				data-lanes = <1 2>;
856*4882a593Smuzhiyun			};
857*4882a593Smuzhiyun		};
858*4882a593Smuzhiyun
859*4882a593Smuzhiyun		port@1 {
860*4882a593Smuzhiyun			reg = <1>;
861*4882a593Smuzhiyun			#address-cells = <1>;
862*4882a593Smuzhiyun			#size-cells = <0>;
863*4882a593Smuzhiyun
864*4882a593Smuzhiyun			dphy_rx_out: endpoint@0 {
865*4882a593Smuzhiyun				reg = <0>;
866*4882a593Smuzhiyun				remote-endpoint = <&isp_mipi_in>;
867*4882a593Smuzhiyun			};
868*4882a593Smuzhiyun		};
869*4882a593Smuzhiyun	};
870*4882a593Smuzhiyun};
871*4882a593Smuzhiyun
872*4882a593Smuzhiyun&nandc0 {
873*4882a593Smuzhiyun	status = "okay";
874*4882a593Smuzhiyun};
875*4882a593Smuzhiyun
876*4882a593Smuzhiyun&pmu_io_domains {
877*4882a593Smuzhiyun	status = "okay";
878*4882a593Smuzhiyun
879*4882a593Smuzhiyun	pmu-supply = <&vccio_pmu>;
880*4882a593Smuzhiyun	vop-supply = <&vccio_pmu>;
881*4882a593Smuzhiyun};
882*4882a593Smuzhiyun
883*4882a593Smuzhiyun&pwm0 {
884*4882a593Smuzhiyun	status = "okay";
885*4882a593Smuzhiyun};
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun&pinctrl {
888*4882a593Smuzhiyun	camera {
889*4882a593Smuzhiyun		camera_pwr: camera-pwr {
890*4882a593Smuzhiyun			rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
891*4882a593Smuzhiyun		};
892*4882a593Smuzhiyun	};
893*4882a593Smuzhiyun
894*4882a593Smuzhiyun	headphone {
895*4882a593Smuzhiyun		hp_det: hp-det {
896*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_up>;
897*4882a593Smuzhiyun		};
898*4882a593Smuzhiyun	};
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun	pmic {
901*4882a593Smuzhiyun		pmic_int_l: pmic-int-l {
902*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
903*4882a593Smuzhiyun		};
904*4882a593Smuzhiyun		vsel_gpio: vsel-gpio {
905*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_down>;
906*4882a593Smuzhiyun		};
907*4882a593Smuzhiyun	};
908*4882a593Smuzhiyun
909*4882a593Smuzhiyun	mpu6500 {
910*4882a593Smuzhiyun		mpu6500_irq_gpio: mpu6500-irq-gpio {
911*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
912*4882a593Smuzhiyun		};
913*4882a593Smuzhiyun	};
914*4882a593Smuzhiyun
915*4882a593Smuzhiyun	cm3218 {
916*4882a593Smuzhiyun		cm3218_irq_gpio: cm3218-irq-gpio {
917*4882a593Smuzhiyun			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
918*4882a593Smuzhiyun		};
919*4882a593Smuzhiyun	};
920*4882a593Smuzhiyun
921*4882a593Smuzhiyun	dc_det {
922*4882a593Smuzhiyun		dc_irq_gpio: dc-irq-gpio {
923*4882a593Smuzhiyun			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_up>;
924*4882a593Smuzhiyun		};
925*4882a593Smuzhiyun	};
926*4882a593Smuzhiyun
927*4882a593Smuzhiyun	pcfg_pull_none_4ma: pcfg-pull-none-4ma {
928*4882a593Smuzhiyun		bias-disable;
929*4882a593Smuzhiyun		drive-strength = <4>;
930*4882a593Smuzhiyun	};
931*4882a593Smuzhiyun
932*4882a593Smuzhiyun	sdio-pwrseq {
933*4882a593Smuzhiyun		wifi_enable_h: wifi-enable-h {
934*4882a593Smuzhiyun			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
935*4882a593Smuzhiyun		};
936*4882a593Smuzhiyun	};
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun	usb2 {
939*4882a593Smuzhiyun		host_vbus_drv: host-vbus-drv {
940*4882a593Smuzhiyun			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
941*4882a593Smuzhiyun		};
942*4882a593Smuzhiyun	};
943*4882a593Smuzhiyun
944*4882a593Smuzhiyun	wireless-bluetooth {
945*4882a593Smuzhiyun		uart0_rts_gpio: uart0-rts-gpio {
946*4882a593Smuzhiyun			rockchip,pins = <2 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
947*4882a593Smuzhiyun		};
948*4882a593Smuzhiyun	};
949*4882a593Smuzhiyun};
950*4882a593Smuzhiyun
951*4882a593Smuzhiyun&rkisp1 {
952*4882a593Smuzhiyun	status = "okay";
953*4882a593Smuzhiyun	pinctrl-names = "default";
954*4882a593Smuzhiyun	pinctrl-0 = <&isp_dvp_d2d9 &isp_dvp_d10d11 &cif_clkout>;
955*4882a593Smuzhiyun	port {
956*4882a593Smuzhiyun		#address-cells = <1>;
957*4882a593Smuzhiyun		#size-cells = <0>;
958*4882a593Smuzhiyun
959*4882a593Smuzhiyun		dvp_in_fcam: endpoint@0 {
960*4882a593Smuzhiyun			reg = <0>;
961*4882a593Smuzhiyun			remote-endpoint = <&gc0312_out>;
962*4882a593Smuzhiyun		};
963*4882a593Smuzhiyun
964*4882a593Smuzhiyun		dvp_in_bcam: endpoint@1 {
965*4882a593Smuzhiyun			reg = <1>;
966*4882a593Smuzhiyun			remote-endpoint = <&gc2145_out>;
967*4882a593Smuzhiyun		};
968*4882a593Smuzhiyun
969*4882a593Smuzhiyun		isp_mipi_in: endpoint@2 {
970*4882a593Smuzhiyun			reg = <2>;
971*4882a593Smuzhiyun			remote-endpoint = <&dphy_rx_out>;
972*4882a593Smuzhiyun		};
973*4882a593Smuzhiyun	};
974*4882a593Smuzhiyun};
975*4882a593Smuzhiyun
976*4882a593Smuzhiyun&route_dsi {
977*4882a593Smuzhiyun	status = "okay";
978*4882a593Smuzhiyun};
979*4882a593Smuzhiyun
980*4882a593Smuzhiyun&rockchip_suspend {
981*4882a593Smuzhiyun	status = "okay";
982*4882a593Smuzhiyun	rockchip,sleep-mode-config = <
983*4882a593Smuzhiyun		(0
984*4882a593Smuzhiyun		| RKPM_SLP_ARMOFF
985*4882a593Smuzhiyun		| RKPM_SLP_PMU_PLLS_PWRDN
986*4882a593Smuzhiyun		| RKPM_SLP_PMU_PMUALIVE_32K
987*4882a593Smuzhiyun		| RKPM_SLP_SFT_PLLS_DEEP
988*4882a593Smuzhiyun		| RKPM_SLP_PMU_DIS_OSC
989*4882a593Smuzhiyun		| RKPM_SLP_SFT_PD_NBSCUS
990*4882a593Smuzhiyun		)
991*4882a593Smuzhiyun	>;
992*4882a593Smuzhiyun	rockchip,wakeup-config = <
993*4882a593Smuzhiyun		(0
994*4882a593Smuzhiyun		| RKPM_GPIO_WKUP_EN
995*4882a593Smuzhiyun		| RKPM_USB_WKUP_EN
996*4882a593Smuzhiyun		| RKPM_CLUSTER_L_WKUP_EN
997*4882a593Smuzhiyun		)
998*4882a593Smuzhiyun	>;
999*4882a593Smuzhiyun};
1000*4882a593Smuzhiyun
1001*4882a593Smuzhiyun&saradc {
1002*4882a593Smuzhiyun	status = "okay";
1003*4882a593Smuzhiyun};
1004*4882a593Smuzhiyun
1005*4882a593Smuzhiyun&sdmmc {
1006*4882a593Smuzhiyun	clock-frequency = <37500000>;
1007*4882a593Smuzhiyun	clock-freq-min-max = <400000 37500000>;
1008*4882a593Smuzhiyun	no-sdio;
1009*4882a593Smuzhiyun	no-mmc;
1010*4882a593Smuzhiyun	cap-mmc-highspeed;
1011*4882a593Smuzhiyun	cap-sd-highspeed;
1012*4882a593Smuzhiyun	card-detect-delay = <200>;
1013*4882a593Smuzhiyun	disable-wp;
1014*4882a593Smuzhiyun	num-slots = <1>;
1015*4882a593Smuzhiyun	pinctrl-names = "default";
1016*4882a593Smuzhiyun	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
1017*4882a593Smuzhiyun	status = "disabled";
1018*4882a593Smuzhiyun};
1019*4882a593Smuzhiyun
1020*4882a593Smuzhiyun&sdio0 {
1021*4882a593Smuzhiyun	max-frequency = <100000000>;
1022*4882a593Smuzhiyun	no-sd;
1023*4882a593Smuzhiyun	no-mmc;
1024*4882a593Smuzhiyun	bus-width = <4>;
1025*4882a593Smuzhiyun	disable-wp;
1026*4882a593Smuzhiyun	cap-sd-highspeed;
1027*4882a593Smuzhiyun	cap-sdio-irq;
1028*4882a593Smuzhiyun	keep-power-in-suspend;
1029*4882a593Smuzhiyun	mmc-pwrseq = <&sdio_pwrseq>;
1030*4882a593Smuzhiyun	non-removable;
1031*4882a593Smuzhiyun	num-slots = <1>;
1032*4882a593Smuzhiyun	pinctrl-names = "default";
1033*4882a593Smuzhiyun	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
1034*4882a593Smuzhiyun	rockchip,default-sample-phase = <90>;
1035*4882a593Smuzhiyun	sd-uhs-sdr104;
1036*4882a593Smuzhiyun	status = "okay";
1037*4882a593Smuzhiyun};
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun&tsadc {
1040*4882a593Smuzhiyun	tsadc-supply = <&vdd_cpu>;
1041*4882a593Smuzhiyun	status = "okay";
1042*4882a593Smuzhiyun};
1043*4882a593Smuzhiyun
1044*4882a593Smuzhiyun&uart0 {
1045*4882a593Smuzhiyun	pinctrl-names = "default";
1046*4882a593Smuzhiyun	pinctrl-0 = <&uart0_xfer &uart0_cts>;
1047*4882a593Smuzhiyun	status = "okay";
1048*4882a593Smuzhiyun};
1049*4882a593Smuzhiyun
1050*4882a593Smuzhiyun&u2phy {
1051*4882a593Smuzhiyun	status = "okay";
1052*4882a593Smuzhiyun
1053*4882a593Smuzhiyun	u2phy_otg: otg-port {
1054*4882a593Smuzhiyun		status = "okay";
1055*4882a593Smuzhiyun	};
1056*4882a593Smuzhiyun
1057*4882a593Smuzhiyun	u2phy_host: host-port {
1058*4882a593Smuzhiyun		phy-supply = <&vcc_host>;
1059*4882a593Smuzhiyun		status = "okay";
1060*4882a593Smuzhiyun	};
1061*4882a593Smuzhiyun};
1062*4882a593Smuzhiyun
1063*4882a593Smuzhiyun&usb_host0_ehci {
1064*4882a593Smuzhiyun	status = "okay";
1065*4882a593Smuzhiyun};
1066*4882a593Smuzhiyun
1067*4882a593Smuzhiyun&usb_host0_ohci {
1068*4882a593Smuzhiyun	status = "okay";
1069*4882a593Smuzhiyun};
1070*4882a593Smuzhiyun
1071