1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6/dts-v1/; 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/pinctrl/rockchip.h> 9#include <dt-bindings/input/input.h> 10#include "px30-robot-no-gpu.dtsi" 11 12/ { 13 model = "Rockchip rk3326 evb lpddr3 v10 board for robot linux"; 14 compatible = "rockchip,rk3326-evb-lp3-v10-robot-linux", "rockchip,rk3326"; 15 16 adc-keys { 17 compatible = "adc-keys"; 18 io-channels = <&saradc 2>; 19 io-channel-names = "buttons"; 20 poll-interval = <100>; 21 keyup-threshold-microvolt = <1800000>; 22 23 esc-key { 24 linux,code = <KEY_ESC>; 25 label = "esc"; 26 press-threshold-microvolt = <1310000>; 27 }; 28 29 home-key { 30 linux,code = <KEY_HOME>; 31 label = "home"; 32 press-threshold-microvolt = <624000>; 33 }; 34 35 menu-key { 36 linux,code = <KEY_MENU>; 37 label = "menu"; 38 press-threshold-microvolt = <987000>; 39 }; 40 41 vol-down-key { 42 linux,code = <KEY_VOLUMEDOWN>; 43 label = "volume down"; 44 press-threshold-microvolt = <300000>; 45 }; 46 47 vol-up-key { 48 linux,code = <KEY_VOLUMEUP>; 49 label = "volume up"; 50 press-threshold-microvolt = <17000>; 51 }; 52 }; 53 54 rk817-sound { 55 compatible = "simple-audio-card"; 56 simple-audio-card,format = "i2s"; 57 simple-audio-card,name = "rockchip,rk817-codec"; 58 simple-audio-card,mclk-fs = <256>; 59 simple-audio-card,cpu { 60 sound-dai = <&i2s1_2ch>; 61 }; 62 simple-audio-card,codec { 63 sound-dai = <&rk817_codec>; 64 }; 65 }; 66 67 sdio_pwrseq: sdio-pwrseq { 68 compatible = "mmc-pwrseq-simple"; 69 /*clocks = <&rk817 1>;*/ 70 /*clock-names = "ext_clock";*/ 71 pinctrl-names = "default"; 72 pinctrl-0 = <&wifi_enable_h>; 73 74 /* 75 * On the module itself this is one of these (depending 76 * on the actual card populated): 77 * - SDIO_RESET_L_WL_REG_ON 78 * - PDN (power down when low) 79 */ 80 reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ 81 }; 82 83 vccsys: vccsys { 84 compatible = "regulator-fixed"; 85 regulator-name = "vcc3v8_sys"; 86 regulator-always-on; 87 regulator-boot-on; 88 regulator-min-microvolt = <3800000>; 89 regulator-max-microvolt = <3800000>; 90 }; 91 92 wireless-wlan { 93 compatible = "wlan-platdata"; 94 wifi_chip_type = "AP6210"; 95 WIFI,host_wake_irq = <&gpio0 RK_PB2 GPIO_ACTIVE_HIGH>; 96 status = "okay"; 97 }; 98}; 99 100&bus_apll { 101 bus-supply = <&vdd_logic>; 102 status = "okay"; 103}; 104 105&cif_new { 106 status = "okay"; 107 108 port { 109 cif_in: endpoint { 110 remote-endpoint = <&gc2155_out>; 111 vsync-active = <0>; 112 hsync-active = <1>; 113 }; 114 }; 115}; 116 117&cpu0 { 118 cpu-supply = <&vdd_arm>; 119}; 120 121&dfi { 122 status = "okay"; 123}; 124 125&dmc { 126 center-supply = <&vdd_logic>; 127 status = "okay"; 128}; 129 130&emmc { 131 bus-width = <8>; 132 cap-mmc-highspeed; 133 mmc-hs200-1_8v; 134 no-sdio; 135 no-sd; 136 disable-wp; 137 non-removable; 138 num-slots = <1>; 139 status = "okay"; 140}; 141 142&i2c0 { 143 status = "okay"; 144 clock-frequency = <400000>; 145 i2c-scl-rising-time-ns = <280>; 146 i2c-scl-falling-time-ns = <16>; 147 148 rk817: pmic@20 { 149 compatible = "rockchip,rk817"; 150 reg = <0x20>; 151 interrupt-parent = <&gpio0>; 152 interrupts = <7 IRQ_TYPE_LEVEL_LOW>; 153 pinctrl-names = "default", "pmic-sleep", 154 "pmic-power-off", "pmic-reset"; 155 pinctrl-0 = <&pmic_int>; 156 pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 157 pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 158 pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 159 rockchip,system-power-controller; 160 wakeup-source; 161 #clock-cells = <1>; 162 clock-output-names = "rk808-clkout1", "rk808-clkout2"; 163 //fb-inner-reg-idxs = <2>; 164 /* 1: rst regs (default in codes), 0: rst the pmic */ 165 pmic-reset-func = <1>; 166 167 vcc1-supply = <&vccsys>; 168 vcc2-supply = <&vccsys>; 169 vcc3-supply = <&vccsys>; 170 vcc4-supply = <&vccsys>; 171 vcc5-supply = <&vccsys>; 172 vcc6-supply = <&vccsys>; 173 vcc7-supply = <&vcc_3v0>; 174 vcc8-supply = <&vccsys>; 175 vcc9-supply = <&dcdc_boost>; 176 177 pwrkey { 178 status = "okay"; 179 }; 180 181 pinctrl_rk8xx: pinctrl_rk8xx { 182 gpio-controller; 183 #gpio-cells = <2>; 184 185 rk817_ts_gpio1: rk817_ts_gpio1 { 186 pins = "gpio_ts"; 187 function = "pin_fun1"; 188 /* output-low; */ 189 /* input-enable; */ 190 }; 191 192 rk817_gt_gpio2: rk817_gt_gpio2 { 193 pins = "gpio_gt"; 194 function = "pin_fun1"; 195 }; 196 197 rk817_pin_ts: rk817_pin_ts { 198 pins = "gpio_ts"; 199 function = "pin_fun0"; 200 }; 201 202 rk817_pin_gt: rk817_pin_gt { 203 pins = "gpio_gt"; 204 function = "pin_fun0"; 205 }; 206 207 rk817_slppin_null: rk817_slppin_null { 208 pins = "gpio_slp"; 209 function = "pin_fun0"; 210 }; 211 212 rk817_slppin_slp: rk817_slppin_slp { 213 pins = "gpio_slp"; 214 function = "pin_fun1"; 215 }; 216 217 rk817_slppin_pwrdn: rk817_slppin_pwrdn { 218 pins = "gpio_slp"; 219 function = "pin_fun2"; 220 }; 221 222 rk817_slppin_rst: rk817_slppin_rst { 223 pins = "gpio_slp"; 224 function = "pin_fun3"; 225 }; 226 }; 227 228 regulators { 229 vdd_logic: DCDC_REG1 { 230 regulator-always-on; 231 regulator-boot-on; 232 regulator-min-microvolt = <850000>; 233 regulator-max-microvolt = <1350000>; 234 regulator-ramp-delay = <6001>; 235 regulator-initial-mode = <0x2>; 236 regulator-name = "vdd_logic"; 237 regulator-state-mem { 238 regulator-on-in-suspend; 239 regulator-suspend-microvolt = <950000>; 240 }; 241 }; 242 243 vdd_arm: DCDC_REG2 { 244 regulator-always-on; 245 regulator-boot-on; 246 regulator-min-microvolt = <850000>; 247 regulator-max-microvolt = <1350000>; 248 regulator-ramp-delay = <6001>; 249 regulator-initial-mode = <0x2>; 250 regulator-name = "vdd_arm"; 251 regulator-state-mem { 252 regulator-off-in-suspend; 253 regulator-suspend-microvolt = <950000>; 254 }; 255 }; 256 257 vcc_ddr: DCDC_REG3 { 258 regulator-always-on; 259 regulator-boot-on; 260 regulator-initial-mode = <0x2>; 261 regulator-name = "vcc_ddr"; 262 regulator-state-mem { 263 regulator-on-in-suspend; 264 }; 265 }; 266 267 vcc_3v0: DCDC_REG4 { 268 regulator-always-on; 269 regulator-boot-on; 270 regulator-min-microvolt = <3000000>; 271 regulator-max-microvolt = <3000000>; 272 regulator-initial-mode = <0x2>; 273 regulator-name = "vcc_3v0"; 274 regulator-state-mem { 275 regulator-off-in-suspend; 276 regulator-suspend-microvolt = <3000000>; 277 }; 278 }; 279 280 vcc_1v0: LDO_REG1 { 281 regulator-always-on; 282 regulator-boot-on; 283 regulator-min-microvolt = <1000000>; 284 regulator-max-microvolt = <1000000>; 285 regulator-name = "vcc_1v0"; 286 regulator-state-mem { 287 regulator-on-in-suspend; 288 regulator-suspend-microvolt = <1000000>; 289 }; 290 }; 291 292 vcc1v8_soc: LDO_REG2 { 293 regulator-always-on; 294 regulator-boot-on; 295 regulator-min-microvolt = <1800000>; 296 regulator-max-microvolt = <1800000>; 297 298 regulator-name = "vcc1v8_soc"; 299 regulator-state-mem { 300 regulator-on-in-suspend; 301 regulator-suspend-microvolt = <1800000>; 302 }; 303 }; 304 305 vdd1v0_soc: LDO_REG3 { 306 regulator-always-on; 307 regulator-boot-on; 308 regulator-min-microvolt = <1000000>; 309 regulator-max-microvolt = <1000000>; 310 311 regulator-name = "vcc1v0_soc"; 312 regulator-state-mem { 313 regulator-on-in-suspend; 314 regulator-suspend-microvolt = <1000000>; 315 }; 316 }; 317 318 vcc3v0_pmu: LDO_REG4 { 319 regulator-always-on; 320 regulator-boot-on; 321 regulator-min-microvolt = <3000000>; 322 regulator-max-microvolt = <3000000>; 323 324 regulator-name = "vcc3v0_pmu"; 325 regulator-state-mem { 326 regulator-on-in-suspend; 327 regulator-suspend-microvolt = <3000000>; 328 329 }; 330 }; 331 332 vccio_sd: LDO_REG5 { 333 regulator-always-on; 334 regulator-boot-on; 335 regulator-min-microvolt = <1800000>; 336 regulator-max-microvolt = <3300000>; 337 338 regulator-name = "vccio_sd"; 339 regulator-state-mem { 340 regulator-on-in-suspend; 341 regulator-suspend-microvolt = <3300000>; 342 }; 343 }; 344 345 vcc_sd: LDO_REG6 { 346 regulator-min-microvolt = <3300000>; 347 regulator-max-microvolt = <3300000>; 348 349 regulator-name = "vcc_sd"; 350 regulator-state-mem { 351 regulator-on-in-suspend; 352 regulator-suspend-microvolt = <3300000>; 353 354 }; 355 }; 356 357 vcc2v8_dvp: LDO_REG7 { 358 regulator-min-microvolt = <2800000>; 359 regulator-max-microvolt = <2800000>; 360 361 regulator-name = "vcc2v8_dvp"; 362 regulator-state-mem { 363 regulator-off-in-suspend; 364 regulator-suspend-microvolt = <2800000>; 365 }; 366 }; 367 368 vcc1v8_dvp: LDO_REG8 { 369 regulator-min-microvolt = <1800000>; 370 regulator-max-microvolt = <1800000>; 371 372 regulator-name = "vcc1v8_dvp"; 373 regulator-state-mem { 374 regulator-on-in-suspend; 375 regulator-suspend-microvolt = <1800000>; 376 }; 377 }; 378 379 vdd1v5_dvp: LDO_REG9 { 380 regulator-min-microvolt = <1500000>; 381 regulator-max-microvolt = <1500000>; 382 383 regulator-name = "vdd1v5_dvp"; 384 regulator-state-mem { 385 regulator-off-in-suspend; 386 regulator-suspend-microvolt = <1500000>; 387 }; 388 }; 389 390 dcdc_boost: BOOST { 391 regulator-always-on; 392 regulator-boot-on; 393 regulator-min-microvolt = <4700000>; 394 regulator-max-microvolt = <5400000>; 395 regulator-name = "boost"; 396 }; 397 398 otg_switch: OTG_SWITCH { 399 regulator-name = "otg_switch"; 400 }; 401 }; 402 403 battery { 404 compatible = "rk817,battery"; 405 ocv_table = <3500 3625 3685 3697 3718 3735 3748 406 3760 3774 3788 3802 3816 3834 3853 407 3877 3908 3946 3975 4018 4071 4106>; 408 design_capacity = <2500>; 409 design_qmax = <2750>; 410 bat_res = <100>; 411 sleep_enter_current = <300>; 412 sleep_exit_current = <300>; 413 sleep_filter_current = <100>; 414 power_off_thresd = <3500>; 415 zero_algorithm_vol = <3850>; 416 max_soc_offset = <60>; 417 monitor_sec = <5>; 418 sample_res = <10>; 419 virtual_power = <1>; 420 }; 421 422 charger { 423 compatible = "rk817,charger"; 424 min_input_voltage = <4500>; 425 max_input_current = <1500>; 426 max_chrg_current = <2000>; 427 max_chrg_voltage = <4200>; 428 chrg_term_mode = <0>; 429 chrg_finish_cur = <300>; 430 virtual_power = <0>; 431 dc_det_adc = <0>; 432 extcon = <&u2phy>; 433 }; 434 435 rk817_codec: codec { 436 #sound-dai-cells = <0>; 437 compatible = "rockchip,rk817-codec"; 438 clocks = <&cru SCLK_I2S1_OUT>; 439 clock-names = "mclk"; 440 pinctrl-names = "default"; 441 pinctrl-0 = <&i2s1_2ch_mclk>; 442 hp-volume = <20>; 443 spk-volume = <3>; 444 status = "okay"; 445 }; 446 }; 447}; 448 449&i2c2 { 450 status = "okay"; 451 clock-frequency = <400000>; 452 453 /* 24M mclk is shared for multiple cameras */ 454 pinctrl-0 = <&i2c2_xfer &cif_clkout_m0>; 455 456 /* These are relatively safe rise/fall times; TODO: measure */ 457 i2c-scl-falling-time-ns = <50>; 458 i2c-scl-rising-time-ns = <300>; 459 460 gc2155: gc2155@3c { 461 compatible = "gc,gc2155"; 462 reg = <0x3c>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&cif_pin_m0>; 465 466 clocks = <&cru SCLK_CIF_OUT>; 467 clock-names = "xvclk"; 468 469 avdd-supply = <&vcc2v8_dvp>; 470 dovdd-supply = <&vcc1v8_dvp>; 471 dvdd-supply = <&vcc1v8_dvp>; 472 473 /* hw changed the pwdn to gpio2_b5 */ 474 pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; 475 476 port { 477 gc2155_out: endpoint { 478 remote-endpoint = <&cif_in>; 479 }; 480 }; 481 }; 482 483 ov5695: ov5695@36 { 484 compatible = "ovti,ov5695"; 485 reg = <0x36>; 486 487 clocks = <&cru SCLK_CIF_OUT>; 488 clock-names = "xvclk"; 489 490 avdd-supply = <&vcc2v8_dvp>; 491 dovdd-supply = <&vcc1v8_dvp>; 492 dvdd-supply = <&vcc1v8_dvp>; 493 494 /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ 495 pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; 496 497 port { 498 ucam_out: endpoint { 499 remote-endpoint = <&mipi_in_ucam>; 500 data-lanes = <1 2>; 501 }; 502 }; 503 }; 504}; 505 506&i2s1_2ch { 507 status = "okay"; 508 #sound-dai-cells = <0>; 509}; 510 511&io_domains { 512 status = "okay"; 513 514 vccio1-supply = <&vcc1v8_soc>; 515 vccio2-supply = <&vccio_sd>; 516 vccio3-supply = <&vcc1v8_dvp>; 517 vccio4-supply = <&vcc_3v0>; 518 vccio5-supply = <&vcc_3v0>; 519}; 520 521&isp_mmu { 522 status = "okay"; 523}; 524 525&mipi_dphy_rx0 { 526 status = "okay"; 527 528 ports { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 532 port@0 { 533 reg = <0>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 537 mipi_in_ucam: endpoint@1 { 538 reg = <1>; 539 remote-endpoint = <&ucam_out>; 540 data-lanes = <1 2>; 541 }; 542 }; 543 544 port@1 { 545 reg = <1>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 549 dphy_rx0_out: endpoint@0 { 550 reg = <0>; 551 remote-endpoint = <&isp0_mipi_in>; 552 }; 553 }; 554 }; 555}; 556 557&nandc0 { 558 status = "okay"; 559}; 560 561&rkisp1 { 562 status = "okay"; 563 564 port { 565 #address-cells = <1>; 566 #size-cells = <0>; 567 568 isp0_mipi_in: endpoint@0 { 569 reg = <0>; 570 remote-endpoint = <&dphy_rx0_out>; 571 }; 572 }; 573}; 574 575&pmu_io_domains { 576 status = "okay"; 577 578 pmuio1-supply = <&vcc3v0_pmu>; 579 pmuio2-supply = <&vcc3v0_pmu>; 580}; 581 582&rk_rga { 583 status = "okay"; 584}; 585 586&saradc { 587 status = "okay"; 588 vref-supply = <&vcc1v8_soc>; 589}; 590 591&sdmmc { 592 bus-width = <4>; 593 cap-mmc-highspeed; 594 cap-sd-highspeed; 595 no-sdio; 596 no-mmc; 597 card-detect-delay = <800>; 598 ignore-pm-notify; 599 /*cd-gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; [> CD GPIO <]*/ 600 sd-uhs-sdr12; 601 sd-uhs-sdr25; 602 sd-uhs-sdr50; 603 sd-uhs-sdr104; 604 vqmmc-supply = <&vccio_sd>; 605 vmmc-supply = <&vcc_sd>; 606 status = "disabled"; 607}; 608 609&sdio { 610 bus-width = <4>; 611 cap-sd-highspeed; 612 no-sd; 613 no-mmc; 614 ignore-pm-notify; 615 keep-power-in-suspend; 616 non-removable; 617 mmc-pwrseq = <&sdio_pwrseq>; 618 sd-uhs-sdr104; 619 status = "okay"; 620}; 621 622&tsadc { 623 pinctrl-names = "init", "default"; 624 pinctrl-0 = <&tsadc_otp_gpio>; 625 pinctrl-1 = <&tsadc_otp_out>; 626 status = "okay"; 627}; 628 629&u2phy { 630 status = "okay"; 631 632 u2phy_host: host-port { 633 status = "okay"; 634 }; 635 636 u2phy_otg: otg-port { 637 status = "okay"; 638 }; 639}; 640 641&usb20_otg { 642 status = "okay"; 643}; 644 645&uart1 { 646 pinctrl-names = "default"; 647 pinctrl-0 = <&uart1_xfer &uart1_cts>; 648 status = "okay"; 649}; 650 651&vip_mmu { 652 status = "okay"; 653}; 654 655&mpp_srv { 656 status = "okay"; 657}; 658 659&vdpu { 660 status = "okay"; 661}; 662 663&vepu { 664 status = "okay"; 665}; 666 667&vpu_mmu { 668 status = "okay"; 669}; 670 671&hevc { 672 status = "okay"; 673}; 674 675&hevc_mmu { 676 status = "okay"; 677}; 678 679&pinctrl { 680 cif-pin-m0 { 681 cif_pin_m0: cif-pin-m0 { 682 rockchip,pins = 683 <2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */ 684 <2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */ 685 <2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */ 686 <2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */ 687 <2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */ 688 <2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */ 689 <2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */ 690 <2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */ 691 <2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */ 692 <2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */ 693 <2 RK_PB2 1 &pcfg_pull_none>;/* cif_clkin */ 694 }; 695 }; 696 697 pmic { 698 pmic_int: pmic_int { 699 rockchip,pins = 700 <0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>; 701 }; 702 703 soc_slppin_gpio: soc_slppin_gpio { 704 rockchip,pins = 705 <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 706 }; 707 708 soc_slppin_slp: soc_slppin_slp { 709 rockchip,pins = 710 <0 RK_PA4 1 &pcfg_pull_none>; 711 }; 712 713 soc_slppin_rst: soc_slppin_rst { 714 rockchip,pins = 715 <0 RK_PA4 2 &pcfg_pull_none>; 716 }; 717 }; 718 719 sdio-pwrseq { 720 wifi_enable_h: wifi-enable-h { 721 rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 722 }; 723 }; 724}; 725 726/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 727/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 728/* DON'T PUT ANYTHING BELOW HERE. PUT IT ABOVE PINCTRL */ 729