1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6/dts-v1/; 7#include "rk3326.dtsi" 8#include "rk3326-linux.dtsi" 9#include "rk3326-evb-lp3-v10.dtsi" 10 11/ { 12 model = "Rockchip rk3326 evb lpddr3 v10 board for linux"; 13 compatible = "rockchip,rk3326-evb-lp3-v10-linux", "rockchip,rk3326"; 14 15 chosen { 16 bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait"; 17 }; 18 19 /delete-node/ test-power; 20}; 21 22&cif_new { 23 status = "okay"; 24 25 port { 26 cif_in: endpoint { 27 remote-endpoint = <&gc2155_out>; 28 vsync-active = <0>; 29 hsync-active = <1>; 30 }; 31 }; 32}; 33 34&i2c2 { 35 status = "okay"; 36 clock-frequency = <400000>; 37 38 /* 24M mclk is shared for multiple cameras */ 39 pinctrl-0 = <&i2c2_xfer &cif_clkout_m0>; 40 41 /* These are relatively safe rise/fall times; TODO: measure */ 42 i2c-scl-falling-time-ns = <50>; 43 i2c-scl-rising-time-ns = <300>; 44 45 gc2155: gc2155@3c { 46 compatible = "gc,gc2155"; 47 reg = <0x3c>; 48 pinctrl-names = "default"; 49 pinctrl-0 = <&cif_pin_m0>; 50 51 clocks = <&cru SCLK_CIF_OUT>; 52 clock-names = "xvclk"; 53 54 avdd-supply = <&vcc2v8_dvp>; 55 dovdd-supply = <&vcc1v8_dvp>; 56 dvdd-supply = <&vcc1v8_dvp>; 57 58 /* hw changed the pwdn to gpio2_b5 */ 59 pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; 60 61 port { 62 gc2155_out: endpoint { 63 remote-endpoint = <&cif_in>; 64 }; 65 }; 66 }; 67 68 ov5695: ov5695@36 { 69 compatible = "ovti,ov5695"; 70 reg = <0x36>; 71 72 clocks = <&cru SCLK_CIF_OUT>; 73 clock-names = "xvclk"; 74 75 avdd-supply = <&vcc2v8_dvp>; 76 dovdd-supply = <&vcc1v8_dvp>; 77 dvdd-supply = <&vdd1v5_dvp>; 78 79 /*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/ 80 pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; 81 82 rockchip,camera-module-index = <0>; 83 rockchip,camera-module-facing = "back"; 84 rockchip,camera-module-name = "TongJu"; 85 rockchip,camera-module-lens-name = "CHT842-MD"; 86 87 port { 88 ucam_out: endpoint { 89 remote-endpoint = <&mipi_in_ucam>; 90 data-lanes = <1 2>; 91 }; 92 }; 93 }; 94}; 95 96&mipi_dphy_rx0 { 97 status = "okay"; 98 99 ports { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 103 port@0 { 104 reg = <0>; 105 #address-cells = <1>; 106 #size-cells = <0>; 107 108 mipi_in_ucam: endpoint@1 { 109 reg = <1>; 110 remote-endpoint = <&ucam_out>; 111 data-lanes = <1 2>; 112 }; 113 }; 114 115 port@1 { 116 reg = <1>; 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 dphy_rx0_out: endpoint@0 { 121 reg = <0>; 122 remote-endpoint = <&isp0_mipi_in>; 123 }; 124 }; 125 }; 126}; 127 128&pinctrl { 129 cif-pin-m0 { 130 cif_pin_m0: cif-pin-m0 { 131 rockchip,pins = 132 <2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */ 133 <2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */ 134 <2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */ 135 <2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */ 136 <2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */ 137 <2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */ 138 <2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */ 139 <2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */ 140 <2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */ 141 <2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */ 142 <2 RK_PB2 1 &pcfg_pull_none>;/* cif_clkin */ 143 }; 144 }; 145}; 146 147&rkisp1 { 148 status = "okay"; 149 150 port { 151 #address-cells = <1>; 152 #size-cells = <0>; 153 154 isp0_mipi_in: endpoint@0 { 155 reg = <0>; 156 remote-endpoint = <&dphy_rx0_out>; 157 }; 158 }; 159}; 160 161&vip_mmu { 162 status = "okay"; 163}; 164