1*4882a593Smuzhiyun// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*4882a593Smuzhiyun/* 3*4882a593Smuzhiyun * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun/dts-v1/; 7*4882a593Smuzhiyun#include <dt-bindings/display/drm_mipi_dsi.h> 8*4882a593Smuzhiyun#include <dt-bindings/gpio/gpio.h> 9*4882a593Smuzhiyun#include <dt-bindings/input/input.h> 10*4882a593Smuzhiyun#include <dt-bindings/pinctrl/rockchip.h> 11*4882a593Smuzhiyun#include <dt-bindings/sensor-dev.h> 12*4882a593Smuzhiyun#include "rk3326.dtsi" 13*4882a593Smuzhiyun#include "rk3326-863-cif-sensor.dtsi" 14*4882a593Smuzhiyun#include "px30-android.dtsi" 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun/ { 17*4882a593Smuzhiyun model = "Rockchip rk3326 86v board"; 18*4882a593Smuzhiyun compatible = "rockchip,rk3326-86v-v10", "rockchip,rk3326"; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun adc-keys { 21*4882a593Smuzhiyun compatible = "adc-keys"; 22*4882a593Smuzhiyun io-channels = <&saradc 2>; 23*4882a593Smuzhiyun io-channel-names = "buttons"; 24*4882a593Smuzhiyun poll-interval = <100>; 25*4882a593Smuzhiyun keyup-threshold-microvolt = <617000>; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun vol-down-key { 28*4882a593Smuzhiyun linux,code = <KEY_VOLUMEDOWN>; 29*4882a593Smuzhiyun label = "volume down"; 30*4882a593Smuzhiyun press-threshold-microvolt = <300000>; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun vol-up-key { 34*4882a593Smuzhiyun linux,code = <KEY_VOLUMEUP>; 35*4882a593Smuzhiyun label = "volume up"; 36*4882a593Smuzhiyun press-threshold-microvolt = <17000>; 37*4882a593Smuzhiyun }; 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun backlight: backlight { 41*4882a593Smuzhiyun compatible = "pwm-backlight"; 42*4882a593Smuzhiyun pwms = <&pwm1 0 25000 0>; 43*4882a593Smuzhiyun brightness-levels = < 44*4882a593Smuzhiyun 0 10 10 11 11 12 12 13 45*4882a593Smuzhiyun 13 14 14 15 15 16 16 17 46*4882a593Smuzhiyun 17 18 18 19 20 21 22 23 47*4882a593Smuzhiyun 24 25 26 27 28 29 30 31 48*4882a593Smuzhiyun 32 33 34 35 36 37 38 39 49*4882a593Smuzhiyun 40 41 42 43 44 45 46 47 50*4882a593Smuzhiyun 48 49 50 51 52 53 54 55 51*4882a593Smuzhiyun 56 57 58 59 60 61 62 63 52*4882a593Smuzhiyun 64 65 66 67 68 69 70 71 53*4882a593Smuzhiyun 72 73 74 75 76 77 78 79 54*4882a593Smuzhiyun 80 81 82 83 84 85 86 87 55*4882a593Smuzhiyun 88 89 90 91 92 93 94 95 56*4882a593Smuzhiyun 96 97 98 99 100 101 102 103 57*4882a593Smuzhiyun 104 105 106 107 108 109 110 111 58*4882a593Smuzhiyun 112 113 114 115 116 117 118 119 59*4882a593Smuzhiyun 120 121 122 123 124 125 126 127 60*4882a593Smuzhiyun 128 129 130 131 132 133 134 135 61*4882a593Smuzhiyun 136 137 138 139 140 141 142 143 62*4882a593Smuzhiyun 144 145 146 147 148 149 150 151 63*4882a593Smuzhiyun 152 153 154 155 156 157 158 159 64*4882a593Smuzhiyun 160 161 162 163 164 165 166 167 65*4882a593Smuzhiyun 168 169 170 171 172 173 174 175 66*4882a593Smuzhiyun 176 177 178 179 180 181 182 183 67*4882a593Smuzhiyun 184 185 186 187 188 189 190 191 68*4882a593Smuzhiyun 192 193 194 195 196 197 198 199 69*4882a593Smuzhiyun 200 201 202 203 204 205 206 207 70*4882a593Smuzhiyun 208 209 210 211 212 213 214 215 71*4882a593Smuzhiyun 216 217 218 219 220 221 222 223 72*4882a593Smuzhiyun 224 225 226 227 228 229 230 231 73*4882a593Smuzhiyun 232 233 234 235 236 237 238 239 74*4882a593Smuzhiyun 240 241 242 243 244 245 246 247 75*4882a593Smuzhiyun 248 249 250 251 252 253 254 255>; 76*4882a593Smuzhiyun default-brightness-level = <200>; 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun charge-animation { 80*4882a593Smuzhiyun compatible = "rockchip,uboot-charge"; 81*4882a593Smuzhiyun rockchip,uboot-charge-on = <0>; 82*4882a593Smuzhiyun rockchip,android-charge-on = <0>; 83*4882a593Smuzhiyun rockchip,uboot-low-power-voltage = <3500>; 84*4882a593Smuzhiyun rockchip,screen-on-voltage = <3600>; 85*4882a593Smuzhiyun status = "okay"; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun panel { 89*4882a593Smuzhiyun compatible ="simple-panel"; 90*4882a593Smuzhiyun enable-gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_LOW>; 91*4882a593Smuzhiyun reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>; 92*4882a593Smuzhiyun bus-format = <MEDIA_BUS_FMT_RGB666_1X18>; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun display-timings { 95*4882a593Smuzhiyun native-mode = <&timing0>; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun timing0: timing0 { 98*4882a593Smuzhiyun clock-frequency = <51200000>; 99*4882a593Smuzhiyun hactive = <1024>; 100*4882a593Smuzhiyun vactive = <600>; 101*4882a593Smuzhiyun hback-porch = <100>; 102*4882a593Smuzhiyun hfront-porch = <120>; 103*4882a593Smuzhiyun vback-porch = <10>; 104*4882a593Smuzhiyun vfront-porch = <15>; 105*4882a593Smuzhiyun hsync-len = <100>; 106*4882a593Smuzhiyun vsync-len = <10>; 107*4882a593Smuzhiyun hsync-active = <0>; 108*4882a593Smuzhiyun vsync-active = <0>; 109*4882a593Smuzhiyun de-active = <0>; 110*4882a593Smuzhiyun pixelclk-active = <0>; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun }; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun port { 115*4882a593Smuzhiyun panel_in_rgb: endpoint { 116*4882a593Smuzhiyun remote-endpoint = <&rgb_out_panel>; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun rk817-sound { 122*4882a593Smuzhiyun compatible = "simple-audio-card"; 123*4882a593Smuzhiyun simple-audio-card,format = "i2s"; 124*4882a593Smuzhiyun simple-audio-card,name = "rockchip,rk817-codec"; 125*4882a593Smuzhiyun simple-audio-card,mclk-fs = <256>; 126*4882a593Smuzhiyun simple-audio-card,widgets = 127*4882a593Smuzhiyun "Microphone", "Mic Jack", 128*4882a593Smuzhiyun "Headphone", "Headphone Jack"; 129*4882a593Smuzhiyun simple-audio-card,routing = 130*4882a593Smuzhiyun "Mic Jack", "MICBIAS1", 131*4882a593Smuzhiyun "IN1P", "Mic Jack", 132*4882a593Smuzhiyun "Headphone Jack", "HPOL", 133*4882a593Smuzhiyun "Headphone Jack", "HPOR"; 134*4882a593Smuzhiyun simple-audio-card,cpu { 135*4882a593Smuzhiyun sound-dai = <&i2s1_2ch>; 136*4882a593Smuzhiyun }; 137*4882a593Smuzhiyun simple-audio-card,codec { 138*4882a593Smuzhiyun sound-dai = <&rk817_codec>; 139*4882a593Smuzhiyun }; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun rk_headset: rk-headset { 143*4882a593Smuzhiyun compatible = "rockchip_headset"; 144*4882a593Smuzhiyun headset_gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_LOW>; 145*4882a593Smuzhiyun pinctrl-names = "default"; 146*4882a593Smuzhiyun pinctrl-0 = <&hp_det>; 147*4882a593Smuzhiyun }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun sdio_pwrseq: sdio-pwrseq { 150*4882a593Smuzhiyun compatible = "mmc-pwrseq-simple"; 151*4882a593Smuzhiyun clocks = <&cru SCLK_WIFI_PMU>; 152*4882a593Smuzhiyun clock-names = "clk_wifi_pmu"; 153*4882a593Smuzhiyun pinctrl-names = "default"; 154*4882a593Smuzhiyun pinctrl-0 = <&wifi_enable_h>; 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun /* 157*4882a593Smuzhiyun * On the module itself this is one of these (depending 158*4882a593Smuzhiyun * on the actual card populated): 159*4882a593Smuzhiyun * - SDIO_RESET_L_WL_REG_ON 160*4882a593Smuzhiyun * - PDN (power down when low) 161*4882a593Smuzhiyun */ 162*4882a593Smuzhiyun reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>; /* GPIO3_A4 */ 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun vccsys: vccsys { 166*4882a593Smuzhiyun compatible = "regulator-fixed"; 167*4882a593Smuzhiyun regulator-name = "vcc3v8_sys"; 168*4882a593Smuzhiyun regulator-always-on; 169*4882a593Smuzhiyun regulator-boot-on; 170*4882a593Smuzhiyun regulator-min-microvolt = <3800000>; 171*4882a593Smuzhiyun regulator-max-microvolt = <3800000>; 172*4882a593Smuzhiyun }; 173*4882a593Smuzhiyun}; 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun&cif { 176*4882a593Smuzhiyun status = "okay"; 177*4882a593Smuzhiyun}; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun&cif_sensor { 180*4882a593Smuzhiyun status = "okay"; 181*4882a593Smuzhiyun}; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun&display_subsystem { 184*4882a593Smuzhiyun status = "okay"; 185*4882a593Smuzhiyun}; 186*4882a593Smuzhiyun 187*4882a593Smuzhiyun&bus_apll { 188*4882a593Smuzhiyun bus-supply = <&vdd_logic>; 189*4882a593Smuzhiyun status = "okay"; 190*4882a593Smuzhiyun}; 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun&cpu0 { 193*4882a593Smuzhiyun cpu-supply = <&vdd_arm>; 194*4882a593Smuzhiyun}; 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun&cpu0_opp_table { 197*4882a593Smuzhiyun /* 198*4882a593Smuzhiyun * max IR-drop values on different freq condition for this board! 199*4882a593Smuzhiyun */ 200*4882a593Smuzhiyun rockchip,board-irdrop = < 201*4882a593Smuzhiyun /*MHz MHz uV */ 202*4882a593Smuzhiyun 0 815 75000 203*4882a593Smuzhiyun 816 1119 75000 204*4882a593Smuzhiyun 1200 1512 75000 205*4882a593Smuzhiyun >; 206*4882a593Smuzhiyun}; 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun&dmc_opp_table { 209*4882a593Smuzhiyun /* 210*4882a593Smuzhiyun * max IR-drop values on different freq condition for this board! 211*4882a593Smuzhiyun */ 212*4882a593Smuzhiyun rockchip,board-irdrop = < 213*4882a593Smuzhiyun /*MHz MHz uV */ 214*4882a593Smuzhiyun 451 800 75000 215*4882a593Smuzhiyun >; 216*4882a593Smuzhiyun}; 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun&dfi { 219*4882a593Smuzhiyun status = "okay"; 220*4882a593Smuzhiyun}; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun&dmc { 223*4882a593Smuzhiyun center-supply = <&vdd_logic>; 224*4882a593Smuzhiyun status = "disabled"; 225*4882a593Smuzhiyun}; 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun&emmc { 228*4882a593Smuzhiyun bus-width = <8>; 229*4882a593Smuzhiyun cap-mmc-highspeed; 230*4882a593Smuzhiyun /*mmc-hs200-1_8v;*/ 231*4882a593Smuzhiyun no-sdio; 232*4882a593Smuzhiyun no-sd; 233*4882a593Smuzhiyun disable-wp; 234*4882a593Smuzhiyun non-removable; 235*4882a593Smuzhiyun num-slots = <1>; 236*4882a593Smuzhiyun status = "okay"; 237*4882a593Smuzhiyun}; 238*4882a593Smuzhiyun 239*4882a593Smuzhiyun&gpu { 240*4882a593Smuzhiyun mali-supply = <&vdd_logic>; 241*4882a593Smuzhiyun status = "okay"; 242*4882a593Smuzhiyun}; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun&i2c0 { 245*4882a593Smuzhiyun status = "okay"; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun rk817: pmic@20 { 248*4882a593Smuzhiyun compatible = "rockchip,rk817"; 249*4882a593Smuzhiyun reg = <0x20>; 250*4882a593Smuzhiyun interrupt-parent = <&gpio0>; 251*4882a593Smuzhiyun interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 252*4882a593Smuzhiyun pinctrl-names = "default", "pmic-sleep", 253*4882a593Smuzhiyun "pmic-power-off", "pmic-reset"; 254*4882a593Smuzhiyun pinctrl-0 = <&pmic_int>; 255*4882a593Smuzhiyun pinctrl-1 = <&soc_slppin_slp>, <&rk817_slppin_slp>; 256*4882a593Smuzhiyun pinctrl-2 = <&soc_slppin_gpio>, <&rk817_slppin_pwrdn>; 257*4882a593Smuzhiyun pinctrl-3 = <&soc_slppin_rst>, <&rk817_slppin_rst>; 258*4882a593Smuzhiyun rockchip,system-power-controller; 259*4882a593Smuzhiyun wakeup-source; 260*4882a593Smuzhiyun #clock-cells = <1>; 261*4882a593Smuzhiyun clock-output-names = "rk808-clkout1", "rk808-clkout2"; 262*4882a593Smuzhiyun //fb-inner-reg-idxs = <2>; 263*4882a593Smuzhiyun /* 1: rst regs (default in codes), 0: rst the pmic */ 264*4882a593Smuzhiyun pmic-reset-func = <1>; 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun vcc1-supply = <&vccsys>; 267*4882a593Smuzhiyun vcc2-supply = <&vccsys>; 268*4882a593Smuzhiyun vcc3-supply = <&vccsys>; 269*4882a593Smuzhiyun vcc4-supply = <&vccsys>; 270*4882a593Smuzhiyun vcc5-supply = <&vccsys>; 271*4882a593Smuzhiyun vcc6-supply = <&vccsys>; 272*4882a593Smuzhiyun vcc7-supply = <&vcc_3v0>; 273*4882a593Smuzhiyun vcc8-supply = <&vccsys>; 274*4882a593Smuzhiyun vcc9-supply = <&dcdc_boost>; 275*4882a593Smuzhiyun 276*4882a593Smuzhiyun pwrkey { 277*4882a593Smuzhiyun status = "okay"; 278*4882a593Smuzhiyun }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun pinctrl_rk8xx: pinctrl_rk8xx { 281*4882a593Smuzhiyun gpio-controller; 282*4882a593Smuzhiyun #gpio-cells = <2>; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun rk817_ts_gpio1: rk817_ts_gpio1 { 285*4882a593Smuzhiyun pins = "gpio_ts"; 286*4882a593Smuzhiyun function = "pin_fun1"; 287*4882a593Smuzhiyun /* output-low; */ 288*4882a593Smuzhiyun /* input-enable; */ 289*4882a593Smuzhiyun }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun rk817_gt_gpio2: rk817_gt_gpio2 { 292*4882a593Smuzhiyun pins = "gpio_gt"; 293*4882a593Smuzhiyun function = "pin_fun1"; 294*4882a593Smuzhiyun }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun rk817_pin_ts: rk817_pin_ts { 297*4882a593Smuzhiyun pins = "gpio_ts"; 298*4882a593Smuzhiyun function = "pin_fun0"; 299*4882a593Smuzhiyun }; 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun rk817_pin_gt: rk817_pin_gt { 302*4882a593Smuzhiyun pins = "gpio_gt"; 303*4882a593Smuzhiyun function = "pin_fun0"; 304*4882a593Smuzhiyun }; 305*4882a593Smuzhiyun 306*4882a593Smuzhiyun rk817_slppin_null: rk817_slppin_null { 307*4882a593Smuzhiyun pins = "gpio_slp"; 308*4882a593Smuzhiyun function = "pin_fun0"; 309*4882a593Smuzhiyun }; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun rk817_slppin_slp: rk817_slppin_slp { 312*4882a593Smuzhiyun pins = "gpio_slp"; 313*4882a593Smuzhiyun function = "pin_fun1"; 314*4882a593Smuzhiyun }; 315*4882a593Smuzhiyun 316*4882a593Smuzhiyun rk817_slppin_pwrdn: rk817_slppin_pwrdn { 317*4882a593Smuzhiyun pins = "gpio_slp"; 318*4882a593Smuzhiyun function = "pin_fun2"; 319*4882a593Smuzhiyun }; 320*4882a593Smuzhiyun 321*4882a593Smuzhiyun rk817_slppin_rst: rk817_slppin_rst { 322*4882a593Smuzhiyun pins = "gpio_slp"; 323*4882a593Smuzhiyun function = "pin_fun3"; 324*4882a593Smuzhiyun }; 325*4882a593Smuzhiyun }; 326*4882a593Smuzhiyun 327*4882a593Smuzhiyun regulators { 328*4882a593Smuzhiyun vdd_logic: DCDC_REG1 { 329*4882a593Smuzhiyun regulator-always-on; 330*4882a593Smuzhiyun regulator-boot-on; 331*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 332*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 333*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 334*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 335*4882a593Smuzhiyun regulator-name = "vdd_logic"; 336*4882a593Smuzhiyun regulator-state-mem { 337*4882a593Smuzhiyun regulator-on-in-suspend; 338*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 339*4882a593Smuzhiyun }; 340*4882a593Smuzhiyun }; 341*4882a593Smuzhiyun 342*4882a593Smuzhiyun vdd_arm: DCDC_REG2 { 343*4882a593Smuzhiyun regulator-always-on; 344*4882a593Smuzhiyun regulator-boot-on; 345*4882a593Smuzhiyun regulator-min-microvolt = <850000>; 346*4882a593Smuzhiyun regulator-max-microvolt = <1350000>; 347*4882a593Smuzhiyun regulator-ramp-delay = <6001>; 348*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 349*4882a593Smuzhiyun regulator-name = "vdd_arm"; 350*4882a593Smuzhiyun regulator-state-mem { 351*4882a593Smuzhiyun regulator-off-in-suspend; 352*4882a593Smuzhiyun regulator-suspend-microvolt = <950000>; 353*4882a593Smuzhiyun }; 354*4882a593Smuzhiyun }; 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun vcc_ddr: DCDC_REG3 { 357*4882a593Smuzhiyun regulator-always-on; 358*4882a593Smuzhiyun regulator-boot-on; 359*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 360*4882a593Smuzhiyun regulator-name = "vcc_ddr"; 361*4882a593Smuzhiyun regulator-state-mem { 362*4882a593Smuzhiyun regulator-on-in-suspend; 363*4882a593Smuzhiyun }; 364*4882a593Smuzhiyun }; 365*4882a593Smuzhiyun 366*4882a593Smuzhiyun vcc_3v0: DCDC_REG4 { 367*4882a593Smuzhiyun regulator-always-on; 368*4882a593Smuzhiyun regulator-boot-on; 369*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 370*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 371*4882a593Smuzhiyun regulator-initial-mode = <0x2>; 372*4882a593Smuzhiyun regulator-name = "vcc_3v0"; 373*4882a593Smuzhiyun regulator-state-mem { 374*4882a593Smuzhiyun regulator-on-in-suspend; 375*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 376*4882a593Smuzhiyun }; 377*4882a593Smuzhiyun }; 378*4882a593Smuzhiyun 379*4882a593Smuzhiyun vcc_1v0: LDO_REG1 { 380*4882a593Smuzhiyun regulator-always-on; 381*4882a593Smuzhiyun regulator-boot-on; 382*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 383*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 384*4882a593Smuzhiyun regulator-name = "vcc_1v0"; 385*4882a593Smuzhiyun regulator-state-mem { 386*4882a593Smuzhiyun regulator-on-in-suspend; 387*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 388*4882a593Smuzhiyun }; 389*4882a593Smuzhiyun }; 390*4882a593Smuzhiyun 391*4882a593Smuzhiyun vcc1v8_soc: LDO_REG2 { 392*4882a593Smuzhiyun regulator-always-on; 393*4882a593Smuzhiyun regulator-boot-on; 394*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 395*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 396*4882a593Smuzhiyun 397*4882a593Smuzhiyun regulator-name = "vcc1v8_soc"; 398*4882a593Smuzhiyun regulator-state-mem { 399*4882a593Smuzhiyun regulator-on-in-suspend; 400*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun }; 403*4882a593Smuzhiyun 404*4882a593Smuzhiyun vdd1v0_soc: LDO_REG3 { 405*4882a593Smuzhiyun regulator-always-on; 406*4882a593Smuzhiyun regulator-boot-on; 407*4882a593Smuzhiyun regulator-min-microvolt = <1000000>; 408*4882a593Smuzhiyun regulator-max-microvolt = <1000000>; 409*4882a593Smuzhiyun 410*4882a593Smuzhiyun regulator-name = "vcc1v0_soc"; 411*4882a593Smuzhiyun regulator-state-mem { 412*4882a593Smuzhiyun regulator-on-in-suspend; 413*4882a593Smuzhiyun regulator-suspend-microvolt = <1000000>; 414*4882a593Smuzhiyun }; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun vcc3v0_pmu: LDO_REG4 { 418*4882a593Smuzhiyun regulator-always-on; 419*4882a593Smuzhiyun regulator-boot-on; 420*4882a593Smuzhiyun regulator-min-microvolt = <3000000>; 421*4882a593Smuzhiyun regulator-max-microvolt = <3000000>; 422*4882a593Smuzhiyun 423*4882a593Smuzhiyun regulator-name = "vcc3v0_pmu"; 424*4882a593Smuzhiyun regulator-state-mem { 425*4882a593Smuzhiyun regulator-on-in-suspend; 426*4882a593Smuzhiyun regulator-suspend-microvolt = <3000000>; 427*4882a593Smuzhiyun 428*4882a593Smuzhiyun }; 429*4882a593Smuzhiyun }; 430*4882a593Smuzhiyun 431*4882a593Smuzhiyun vccio_sd: LDO_REG5 { 432*4882a593Smuzhiyun regulator-always-on; 433*4882a593Smuzhiyun regulator-boot-on; 434*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 435*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun regulator-name = "vccio_sd"; 438*4882a593Smuzhiyun regulator-state-mem { 439*4882a593Smuzhiyun regulator-on-in-suspend; 440*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 441*4882a593Smuzhiyun }; 442*4882a593Smuzhiyun }; 443*4882a593Smuzhiyun 444*4882a593Smuzhiyun vcc_sd: LDO_REG6 { 445*4882a593Smuzhiyun regulator-min-microvolt = <3300000>; 446*4882a593Smuzhiyun regulator-max-microvolt = <3300000>; 447*4882a593Smuzhiyun 448*4882a593Smuzhiyun regulator-name = "vcc_sd"; 449*4882a593Smuzhiyun regulator-state-mem { 450*4882a593Smuzhiyun regulator-on-in-suspend; 451*4882a593Smuzhiyun regulator-suspend-microvolt = <3300000>; 452*4882a593Smuzhiyun 453*4882a593Smuzhiyun }; 454*4882a593Smuzhiyun }; 455*4882a593Smuzhiyun 456*4882a593Smuzhiyun vcc2v8_dvp: LDO_REG7 { 457*4882a593Smuzhiyun regulator-boot-on; 458*4882a593Smuzhiyun regulator-min-microvolt = <2800000>; 459*4882a593Smuzhiyun regulator-max-microvolt = <2800000>; 460*4882a593Smuzhiyun 461*4882a593Smuzhiyun regulator-name = "vcc2v8_dvp"; 462*4882a593Smuzhiyun regulator-state-mem { 463*4882a593Smuzhiyun regulator-off-in-suspend; 464*4882a593Smuzhiyun regulator-suspend-microvolt = <2800000>; 465*4882a593Smuzhiyun }; 466*4882a593Smuzhiyun }; 467*4882a593Smuzhiyun 468*4882a593Smuzhiyun vcc1v8_dvp: LDO_REG8 { 469*4882a593Smuzhiyun regulator-boot-on; 470*4882a593Smuzhiyun regulator-min-microvolt = <1800000>; 471*4882a593Smuzhiyun regulator-max-microvolt = <1800000>; 472*4882a593Smuzhiyun 473*4882a593Smuzhiyun regulator-name = "vcc1v8_dvp"; 474*4882a593Smuzhiyun regulator-state-mem { 475*4882a593Smuzhiyun regulator-off-in-suspend; 476*4882a593Smuzhiyun regulator-suspend-microvolt = <1800000>; 477*4882a593Smuzhiyun }; 478*4882a593Smuzhiyun }; 479*4882a593Smuzhiyun 480*4882a593Smuzhiyun vdd1v5_dvp: LDO_REG9 { 481*4882a593Smuzhiyun regulator-boot-on; 482*4882a593Smuzhiyun regulator-min-microvolt = <1500000>; 483*4882a593Smuzhiyun regulator-max-microvolt = <1500000>; 484*4882a593Smuzhiyun 485*4882a593Smuzhiyun regulator-name = "vdd1v5_dvp"; 486*4882a593Smuzhiyun regulator-state-mem { 487*4882a593Smuzhiyun regulator-off-in-suspend; 488*4882a593Smuzhiyun regulator-suspend-microvolt = <1500000>; 489*4882a593Smuzhiyun }; 490*4882a593Smuzhiyun }; 491*4882a593Smuzhiyun 492*4882a593Smuzhiyun dcdc_boost: BOOST { 493*4882a593Smuzhiyun regulator-always-on; 494*4882a593Smuzhiyun regulator-boot-on; 495*4882a593Smuzhiyun regulator-min-microvolt = <4700000>; 496*4882a593Smuzhiyun regulator-max-microvolt = <5400000>; 497*4882a593Smuzhiyun regulator-name = "boost"; 498*4882a593Smuzhiyun }; 499*4882a593Smuzhiyun 500*4882a593Smuzhiyun otg_switch: OTG_SWITCH { 501*4882a593Smuzhiyun regulator-name = "otg_switch"; 502*4882a593Smuzhiyun }; 503*4882a593Smuzhiyun }; 504*4882a593Smuzhiyun 505*4882a593Smuzhiyun battery { 506*4882a593Smuzhiyun compatible = "rk817,battery"; 507*4882a593Smuzhiyun ocv_table = <3500 3548 3592 3636 3687 3740 3780 508*4882a593Smuzhiyun 3806 3827 3846 3864 3889 3929 3964 509*4882a593Smuzhiyun 3993 4015 4030 4041 4056 4076 4148>; 510*4882a593Smuzhiyun design_capacity = <4000>; 511*4882a593Smuzhiyun design_qmax = <4200>; 512*4882a593Smuzhiyun bat_res = <100>; 513*4882a593Smuzhiyun sleep_enter_current = <150>; 514*4882a593Smuzhiyun sleep_exit_current = <180>; 515*4882a593Smuzhiyun sleep_filter_current = <100>; 516*4882a593Smuzhiyun power_off_thresd = <3500>; 517*4882a593Smuzhiyun zero_algorithm_vol = <3850>; 518*4882a593Smuzhiyun max_soc_offset = <60>; 519*4882a593Smuzhiyun monitor_sec = <5>; 520*4882a593Smuzhiyun sample_res = <10>; 521*4882a593Smuzhiyun virtual_power = <0>; 522*4882a593Smuzhiyun }; 523*4882a593Smuzhiyun 524*4882a593Smuzhiyun charger { 525*4882a593Smuzhiyun compatible = "rk817,charger"; 526*4882a593Smuzhiyun min_input_voltage = <4500>; 527*4882a593Smuzhiyun max_input_current = <1500>; 528*4882a593Smuzhiyun max_chrg_current = <2000>; 529*4882a593Smuzhiyun max_chrg_voltage = <4200>; 530*4882a593Smuzhiyun chrg_term_mode = <0>; 531*4882a593Smuzhiyun chrg_finish_cur = <300>; 532*4882a593Smuzhiyun virtual_power = <0>; 533*4882a593Smuzhiyun dc_det_adc = <0>; 534*4882a593Smuzhiyun extcon = <&u2phy>; 535*4882a593Smuzhiyun }; 536*4882a593Smuzhiyun 537*4882a593Smuzhiyun rk817_codec: codec { 538*4882a593Smuzhiyun #sound-dai-cells = <0>; 539*4882a593Smuzhiyun compatible = "rockchip,rk817-codec"; 540*4882a593Smuzhiyun clocks = <&cru SCLK_I2S1_OUT>; 541*4882a593Smuzhiyun clock-names = "mclk"; 542*4882a593Smuzhiyun pinctrl-names = "default"; 543*4882a593Smuzhiyun pinctrl-0 = <&i2s1_2ch_mclk>; 544*4882a593Smuzhiyun hp-volume = <20>; 545*4882a593Smuzhiyun spk-volume = <3>; 546*4882a593Smuzhiyun mic-in-differential; 547*4882a593Smuzhiyun status = "okay"; 548*4882a593Smuzhiyun }; 549*4882a593Smuzhiyun }; 550*4882a593Smuzhiyun}; 551*4882a593Smuzhiyun 552*4882a593Smuzhiyun&i2c1 { 553*4882a593Smuzhiyun status = "okay"; 554*4882a593Smuzhiyun 555*4882a593Smuzhiyun ts@40 { 556*4882a593Smuzhiyun compatible = "gslX680-d708"; 557*4882a593Smuzhiyun reg = <0x40>; 558*4882a593Smuzhiyun touch-gpio = <&gpio0 RK_PB3 IRQ_TYPE_LEVEL_LOW>; 559*4882a593Smuzhiyun wake-gpio = <&gpio0 RK_PC1 IRQ_TYPE_LEVEL_LOW>; 560*4882a593Smuzhiyun screen_max_x = <1024>; 561*4882a593Smuzhiyun screen_max_y = <600>; 562*4882a593Smuzhiyun revert_x = <1>; 563*4882a593Smuzhiyun status = "okay"; 564*4882a593Smuzhiyun }; 565*4882a593Smuzhiyun 566*4882a593Smuzhiyun sensor@1d { 567*4882a593Smuzhiyun status = "okay"; 568*4882a593Smuzhiyun compatible = "gs_lsm303d"; 569*4882a593Smuzhiyun reg = <0x1d>; 570*4882a593Smuzhiyun type = <SENSOR_TYPE_ACCEL>; 571*4882a593Smuzhiyun irq-gpio = <&gpio0 RK_PA1 IRQ_TYPE_LEVEL_LOW>; 572*4882a593Smuzhiyun irq_enable = <0>; 573*4882a593Smuzhiyun poll_delay_ms = <30>; 574*4882a593Smuzhiyun layout = <5>; 575*4882a593Smuzhiyun reprobe_en = <1>; 576*4882a593Smuzhiyun }; 577*4882a593Smuzhiyun}; 578*4882a593Smuzhiyun 579*4882a593Smuzhiyun&i2c2 { 580*4882a593Smuzhiyun status = "okay"; 581*4882a593Smuzhiyun}; 582*4882a593Smuzhiyun 583*4882a593Smuzhiyun&i2s1_2ch { 584*4882a593Smuzhiyun status = "okay"; 585*4882a593Smuzhiyun #sound-dai-cells = <0>; 586*4882a593Smuzhiyun}; 587*4882a593Smuzhiyun 588*4882a593Smuzhiyun&io_domains { 589*4882a593Smuzhiyun status = "okay"; 590*4882a593Smuzhiyun 591*4882a593Smuzhiyun vccio1-supply = <&vcc_3v0>; 592*4882a593Smuzhiyun vccio2-supply = <&vccio_sd>; 593*4882a593Smuzhiyun vccio3-supply = <&vcc2v8_dvp>; 594*4882a593Smuzhiyun vccio4-supply = <&vcc_3v0>; 595*4882a593Smuzhiyun vccio5-supply = <&vcc_3v0>; 596*4882a593Smuzhiyun}; 597*4882a593Smuzhiyun 598*4882a593Smuzhiyun&rgb { 599*4882a593Smuzhiyun status = "okay"; 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun ports { 602*4882a593Smuzhiyun port@1 { 603*4882a593Smuzhiyun reg = <1>; 604*4882a593Smuzhiyun 605*4882a593Smuzhiyun rgb_out_panel: endpoint { 606*4882a593Smuzhiyun remote-endpoint = <&panel_in_rgb>; 607*4882a593Smuzhiyun }; 608*4882a593Smuzhiyun }; 609*4882a593Smuzhiyun }; 610*4882a593Smuzhiyun}; 611*4882a593Smuzhiyun 612*4882a593Smuzhiyun&nandc0 { 613*4882a593Smuzhiyun status = "okay"; 614*4882a593Smuzhiyun}; 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun&pinctrl { 617*4882a593Smuzhiyun headphone { 618*4882a593Smuzhiyun hp_det: hp-det { 619*4882a593Smuzhiyun rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_up>; 620*4882a593Smuzhiyun }; 621*4882a593Smuzhiyun }; 622*4882a593Smuzhiyun 623*4882a593Smuzhiyun lcdc { 624*4882a593Smuzhiyun lcdc_m1_rgb_pins: lcdc-m1-rgb-pins { 625*4882a593Smuzhiyun rockchip,pins = 626*4882a593Smuzhiyun <3 RK_PA0 1 &pcfg_pull_none>, /* LCDC_DCLK */ 627*4882a593Smuzhiyun <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* LCDC_D0 */ 628*4882a593Smuzhiyun <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* LCDC_D2 */ 629*4882a593Smuzhiyun <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* LCDC_D6 */ 630*4882a593Smuzhiyun <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* LCDC_D7 */ 631*4882a593Smuzhiyun <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* LCDC_D9 */ 632*4882a593Smuzhiyun <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* LCDC_D12 */ 633*4882a593Smuzhiyun <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* LCDC_D13 */ 634*4882a593Smuzhiyun <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* LCDC_D14 */ 635*4882a593Smuzhiyun <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* LCDC_D15 */ 636*4882a593Smuzhiyun <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* LCDC_D16 */ 637*4882a593Smuzhiyun <3 RK_PC5 1 &pcfg_pull_none_8ma>; /* LCDC_D17 */ 638*4882a593Smuzhiyun }; 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun lcdc_m1_sleep_pins: lcdc-m1-sleep-pins { 641*4882a593Smuzhiyun rockchip,pins = 642*4882a593Smuzhiyun <3 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_DCLK */ 643*4882a593Smuzhiyun <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D0 */ 644*4882a593Smuzhiyun <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D2 */ 645*4882a593Smuzhiyun <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D6 */ 646*4882a593Smuzhiyun <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D7 */ 647*4882a593Smuzhiyun <3 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D9 */ 648*4882a593Smuzhiyun <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D12 */ 649*4882a593Smuzhiyun <3 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D13 */ 650*4882a593Smuzhiyun <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D14 */ 651*4882a593Smuzhiyun <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D15 */ 652*4882a593Smuzhiyun <3 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>, /* LCDC_D16 */ 653*4882a593Smuzhiyun <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>; /* LCDC_D17 */ 654*4882a593Smuzhiyun }; 655*4882a593Smuzhiyun }; 656*4882a593Smuzhiyun 657*4882a593Smuzhiyun pmic { 658*4882a593Smuzhiyun pmic_int: pmic_int { 659*4882a593Smuzhiyun rockchip,pins = 660*4882a593Smuzhiyun <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; 661*4882a593Smuzhiyun }; 662*4882a593Smuzhiyun 663*4882a593Smuzhiyun soc_slppin_gpio: soc_slppin_gpio { 664*4882a593Smuzhiyun rockchip,pins = 665*4882a593Smuzhiyun <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>; 666*4882a593Smuzhiyun }; 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun soc_slppin_slp: soc_slppin_slp { 669*4882a593Smuzhiyun rockchip,pins = 670*4882a593Smuzhiyun <0 RK_PA4 1 &pcfg_pull_none>; 671*4882a593Smuzhiyun }; 672*4882a593Smuzhiyun 673*4882a593Smuzhiyun soc_slppin_rst: soc_slppin_rst { 674*4882a593Smuzhiyun rockchip,pins = 675*4882a593Smuzhiyun <0 RK_PA4 2 &pcfg_pull_none>; 676*4882a593Smuzhiyun }; 677*4882a593Smuzhiyun }; 678*4882a593Smuzhiyun 679*4882a593Smuzhiyun sdio-pwrseq { 680*4882a593Smuzhiyun wifi_enable_h: wifi-enable-h { 681*4882a593Smuzhiyun rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; 682*4882a593Smuzhiyun }; 683*4882a593Smuzhiyun }; 684*4882a593Smuzhiyun}; 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun&pmu_io_domains { 687*4882a593Smuzhiyun status = "okay"; 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun pmuio1-supply = <&vcc3v0_pmu>; 690*4882a593Smuzhiyun pmuio2-supply = <&vcc3v0_pmu>; 691*4882a593Smuzhiyun}; 692*4882a593Smuzhiyun 693*4882a593Smuzhiyun&pwm1 { 694*4882a593Smuzhiyun status = "okay"; 695*4882a593Smuzhiyun}; 696*4882a593Smuzhiyun 697*4882a593Smuzhiyun&rk_rga { 698*4882a593Smuzhiyun status = "okay"; 699*4882a593Smuzhiyun}; 700*4882a593Smuzhiyun 701*4882a593Smuzhiyun&rockchip_suspend { 702*4882a593Smuzhiyun status = "okay"; 703*4882a593Smuzhiyun rockchip,sleep-debug-en = <1>; 704*4882a593Smuzhiyun}; 705*4882a593Smuzhiyun 706*4882a593Smuzhiyun&route_rgb { 707*4882a593Smuzhiyun connect = <&vopb_out_rgb>; 708*4882a593Smuzhiyun status = "okay"; 709*4882a593Smuzhiyun}; 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun&saradc { 712*4882a593Smuzhiyun status = "okay"; 713*4882a593Smuzhiyun vref-supply = <&vcc1v8_soc>; 714*4882a593Smuzhiyun}; 715*4882a593Smuzhiyun 716*4882a593Smuzhiyun&sdmmc { 717*4882a593Smuzhiyun bus-width = <4>; 718*4882a593Smuzhiyun cap-mmc-highspeed; 719*4882a593Smuzhiyun cap-sd-highspeed; 720*4882a593Smuzhiyun no-sdio; 721*4882a593Smuzhiyun no-mmc; 722*4882a593Smuzhiyun card-detect-delay = <800>; 723*4882a593Smuzhiyun ignore-pm-notify; 724*4882a593Smuzhiyun sd-uhs-sdr12; 725*4882a593Smuzhiyun sd-uhs-sdr25; 726*4882a593Smuzhiyun sd-uhs-sdr50; 727*4882a593Smuzhiyun sd-uhs-sdr104; 728*4882a593Smuzhiyun vqmmc-supply = <&vccio_sd>; 729*4882a593Smuzhiyun vmmc-supply = <&vcc_sd>; 730*4882a593Smuzhiyun status = "disabled"; 731*4882a593Smuzhiyun}; 732*4882a593Smuzhiyun 733*4882a593Smuzhiyun&sdio { 734*4882a593Smuzhiyun bus-width = <4>; 735*4882a593Smuzhiyun cap-sd-highspeed; 736*4882a593Smuzhiyun no-sd; 737*4882a593Smuzhiyun no-mmc; 738*4882a593Smuzhiyun ignore-pm-notify; 739*4882a593Smuzhiyun keep-power-in-suspend; 740*4882a593Smuzhiyun non-removable; 741*4882a593Smuzhiyun mmc-pwrseq = <&sdio_pwrseq>; 742*4882a593Smuzhiyun sd-uhs-sdr104; 743*4882a593Smuzhiyun status = "disabled"; 744*4882a593Smuzhiyun}; 745*4882a593Smuzhiyun 746*4882a593Smuzhiyun&tsadc { 747*4882a593Smuzhiyun pinctrl-names = "gpio", "otpout"; 748*4882a593Smuzhiyun pinctrl-0 = <&tsadc_otp_gpio>; 749*4882a593Smuzhiyun pinctrl-1 = <&tsadc_otp_out>; 750*4882a593Smuzhiyun status = "okay"; 751*4882a593Smuzhiyun}; 752*4882a593Smuzhiyun 753*4882a593Smuzhiyun&u2phy { 754*4882a593Smuzhiyun status = "okay"; 755*4882a593Smuzhiyun 756*4882a593Smuzhiyun u2phy_host: host-port { 757*4882a593Smuzhiyun rockchip,low-power-mode; 758*4882a593Smuzhiyun status = "okay"; 759*4882a593Smuzhiyun }; 760*4882a593Smuzhiyun 761*4882a593Smuzhiyun u2phy_otg: otg-port { 762*4882a593Smuzhiyun rockchip,low-power-mode; 763*4882a593Smuzhiyun status = "okay"; 764*4882a593Smuzhiyun }; 765*4882a593Smuzhiyun}; 766*4882a593Smuzhiyun 767*4882a593Smuzhiyun&usb20_otg { 768*4882a593Smuzhiyun status = "okay"; 769*4882a593Smuzhiyun}; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun&uart1 { 772*4882a593Smuzhiyun pinctrl-names = "default"; 773*4882a593Smuzhiyun pinctrl-0 = <&uart1_xfer &uart1_cts>; 774*4882a593Smuzhiyun status = "okay"; 775*4882a593Smuzhiyun}; 776*4882a593Smuzhiyun 777*4882a593Smuzhiyun&vip_mmu { 778*4882a593Smuzhiyun status = "okay"; 779*4882a593Smuzhiyun}; 780*4882a593Smuzhiyun 781*4882a593Smuzhiyun&vopb { 782*4882a593Smuzhiyun status = "okay"; 783*4882a593Smuzhiyun}; 784*4882a593Smuzhiyun 785*4882a593Smuzhiyun&vopb_mmu { 786*4882a593Smuzhiyun status = "okay"; 787*4882a593Smuzhiyun}; 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun&vopl { 790*4882a593Smuzhiyun status = "okay"; 791*4882a593Smuzhiyun}; 792*4882a593Smuzhiyun 793*4882a593Smuzhiyun&vopl_mmu { 794*4882a593Smuzhiyun status = "okay"; 795*4882a593Smuzhiyun}; 796*4882a593Smuzhiyun 797*4882a593Smuzhiyun&mpp_srv { 798*4882a593Smuzhiyun status = "okay"; 799*4882a593Smuzhiyun}; 800*4882a593Smuzhiyun 801*4882a593Smuzhiyun&vdpu { 802*4882a593Smuzhiyun status = "okay"; 803*4882a593Smuzhiyun}; 804*4882a593Smuzhiyun 805*4882a593Smuzhiyun&vepu { 806*4882a593Smuzhiyun status = "okay"; 807*4882a593Smuzhiyun}; 808*4882a593Smuzhiyun 809*4882a593Smuzhiyun&vpu_mmu { 810*4882a593Smuzhiyun status = "okay"; 811*4882a593Smuzhiyun}; 812*4882a593Smuzhiyun 813*4882a593Smuzhiyun&hevc { 814*4882a593Smuzhiyun status = "okay"; 815*4882a593Smuzhiyun}; 816*4882a593Smuzhiyun 817*4882a593Smuzhiyun&hevc_mmu { 818*4882a593Smuzhiyun status = "okay"; 819*4882a593Smuzhiyun}; 820*4882a593Smuzhiyun 821*4882a593Smuzhiyun&firmware_android { 822*4882a593Smuzhiyun compatible = "android,firmware"; 823*4882a593Smuzhiyun fstab { 824*4882a593Smuzhiyun compatible = "android,fstab"; 825*4882a593Smuzhiyun system { 826*4882a593Smuzhiyun compatible = "android,system"; 827*4882a593Smuzhiyun dev = "/dev/block/by-name/system"; 828*4882a593Smuzhiyun type = "ext4"; 829*4882a593Smuzhiyun mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 830*4882a593Smuzhiyun fsmgr_flags = "wait"; 831*4882a593Smuzhiyun }; 832*4882a593Smuzhiyun vendor { 833*4882a593Smuzhiyun compatible = "android,vendor"; 834*4882a593Smuzhiyun dev = "/dev/block/by-name/vendor"; 835*4882a593Smuzhiyun type = "ext4"; 836*4882a593Smuzhiyun mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; 837*4882a593Smuzhiyun fsmgr_flags = "wait"; 838*4882a593Smuzhiyun }; 839*4882a593Smuzhiyun }; 840*4882a593Smuzhiyun}; 841